Power semiconductor module and method for producing a power semiconductor module
Patent Information
- Application Number
- PCT/EP2025/055546
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-09-03
Smart Images
Figure EP2025055546_03092026_PF_FP_ABST
Abstract
Description
[0001] P2024,1161 WO E / P240219WO01 February 28, 2025
[0002] Description
[0003] POWER SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING A POWER SEMICONDUCTOR MODULE
[0004] The present disclosure relates to a power semiconductor module and a method for producing a power semiconductor module.
[0005] The next generation of e-mobility power semiconductor modules targeting passenger electric vehicles, EVs, and especially for urban air mobility, UAM, sectors, have challenging requirements in terms of high power density and high reliability.
[0006] Embodiments of the disclosure relate to a power semiconductor module which enables high power density, compactness, optimized electro -magnetics, e.g. low stray inductances and balanced couplings, and ease of assembly. Further embodiments relate to a method for producing such a power semiconductor module.
[0007] This is achieved by the subject-matter of the independent claims. Further embodiments are evident from the dependent claims and the following description.
[0008] A power semiconductor module is described. The term "power" here and in the following refers, for example, to power semiconductor modules and / or power semiconductor chips included in the power semiconductor module that are adapted for processing voltages and currents of more than 100 VP2024,1161 WO E / P240219WO01 February 28, 2025
[0009] and / or more than 10 A, exemplarily voltages of up to 10 kV and electrical currents of up to 10 kA.
[0010] According to an embodiment, the power semiconductor module comprises a substrate. The substrate extends within a main extension plane defining in particular lateral directions. For example, the substrate comprises a top metallization, an electrically insulating layer and a bottom metallization, in particular stacked along a stacking direction above one another. The stacking direction extends, for example, along a vertical direction being perpendicular to the lateral directions.
[0011] According to the embodiment, the power semiconductor module comprises at least one power semiconductor chip arranged on the substrate in a first side region. Exemplarily, the power semiconductor chip has a main extension plane extending along lateral directions. For example, a height in the vertical direction of the power semiconductor chip is smaller compared to a size in the lateral direction of the power semiconductor chip.
[0012] The power semiconductor chip comprises, for example, a semiconductor material such as at least one of silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). The power semiconductor chip is, for example, a power diode and / or a power metal insulating semiconductor field- effect transistor, power MISFET for short. The term MISFET shall also include MOSFETs, which have an oxide as an insulating material at a gate. The power semiconductor chip may also be an insulated-gate bipolar transistor, IGBT, or a high electron mobility transistor, HEMT.P2024,1161 WO E / P240219WO01 February 28, 2025
[0013] Exemplarily, the first side region is a high side region of the power semiconductor module.
[0014] Exemplarily, at least one sensor device is arranged on the substrate. In particular, the sensor device does not overlap with the power semiconductor chip in plan view, i. e. along the vertical direction.
[0015] According to the embodiment, the power semiconductor module comprises a first topside connection element. For example, the first topside connection element has a main extension plane extending along lateral directions. Exemplarily, the at least one power semiconductor chip arranged on the substrate in the first side region overlaps in plan view, i. e. along the vertical direction, with the first topside connection element in lateral directions. Exemplarily, the substrate, the power semiconductor chip arranged on the substrate in the first side region and the first topside connection element are stacked above one another in the vertical direction, particularly in the order indicated.
[0016] The first topside connection element comprises, for example, a first electrically conductive material, e.g. comprising a metal. The first electrically conductive material can comprise or consist of copper, aluminum, molybdenum, or a combination thereof or an alloy thereof.
[0017] For example, at least one surface of the first topside connection element can be covered with a first coating, being in particular electrically conductive. The first coating can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof, e.g. AlCu. For example, a bottom surface of the first topsideP2024,1161 WO E / P240219WO01 February 28, 2025
[0018] 4
[0019] connection element facing the substrate can be regionally or completely covered with the first coating. Alternatively or additionally, a top surface of the first topside connection element facing away from the substrate can be regionally or completely covered with the first coating.
[0020] According to the embodiment, the power semiconductor module comprises a first main terminal and a further first topside connection element which are directly electrically conductively connected to one another. For example, the first main terminal is a first power main terminal. This means that the first main terminal is configured to be electrically conductively contactable externally for providing power to the power semiconductor chip arranged on the substrate in the first side region. For example, the first main terminal is an anode terminal, depending on a type of the power semiconductor module. Exemplarily, the first main terminal is an AC terminal of the power semiconductor module.
[0021] For example, the further first topside connection element has a main extension plane extending along lateral directions. Exemplarily, the at least one power semiconductor chip arranged on the substrate in the first side region overlaps in plan view with the further first topside connection element in lateral directions. Exemplarily, the substrate, the power semiconductor chip arranged on the substrate in the first side region and the further first topside connection element are stacked above one another in the vertical direction, particularly in the order indicated.
[0022] In particular, the first topside connection element does not overlap in plan view with the further first topside connection element in lateral directions. The main extensionP2024,1161 WO E / P240219WO01 February 28, 2025
[0023] planes, in particular the top surfaces and / or the bottom surfaces, of the first topside connection element and the further first topside connection element are arranged within a common plane extending in lateral directions.
[0024] The first main terminal and the further first topside connection element comprise, for example, a further first electrically conductive material, e.g. comprising a metal. The further first electrically conductive material can comprise or consist of copper, aluminum, molybdenum, or a combination thereof or an alloy thereof.
[0025] Exemplarily, the first main terminal and the further first topside connection element are formed integrally with one another.
[0026] For example, at least one surface of the further first topside connection element can be covered with a further first coating, being in particular electrically conductive. The further first coating can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof, e.g. AlCu. For example, a bottom surface of the further first topside connection element facing the substrate can be regionally or completely covered with the further first coating. Alternatively or additionally, a top surface of the further first topside connection element facing away from the substrate can be regionally or completely covered with the further first coating. For example, the first coating and the further first coating can comprise the same material or comprise different materials.P2024,1161 WO E / P240219WO01 February 28, 2025
[0027] 6
[0028] In particular, the first main terminal and the further first topside connection element form a high current electrode of the power semiconductor module, and the first topside connection element forms a control electrode of the power semiconductor module in the first side region.
[0029] According to the embodiment of the power semiconductor module, the at least one power semiconductor chip comprises at least one control contact region and at least one first power contact region at a top surface facing away from the substrate. Exemplarily, the power semiconductor chip has a bottom surface and the top surface being connected to one another with at least one side surface. The bottom surface and the top surface both extend in lateral directions and are spaced apart from one another in the vertical direction by the at least one side surface. In particular, the bottom surface faces the substrate and the top surface faces away from the substrate; particularly, the top surface faces the first topside connection element and the further first topside connection element. Exemplarily, the bottom surface of the power semiconductor chip is connected to the substrate, particularly the top metallization. The control contact region and the first power contact region are arranged at the top surface of the power semiconductor chip, particularly facing the first topside connection element and the further first topside connection element.
[0030] If the power semiconductor chip comprises more than one first power contact region, the control contact region and the first power contact regions are arranged on virtual grid points of a virtual regular grid extending in lateral directions. The virtual regular grid can be a polygonal grid, like a triangular or quadrangular grid. Exemplarily, the atP2024,1161 WO E / P240219WO01 February 28, 2025
[0031] 7
[0032] least one power semiconductor chip comprises one control contact region and three first power contact regions. The control contact region and the first power contact regions are arranged for example on the virtual grid points of a virtual regular grid being the quadrangular grid.
[0033] Exemplarily, the control contact region overlaps in plan view, i.e. along the vertical direction, with the first topside connection element in lateral directions.
[0034] Exemplarily, the first power contact region, in particular all of the first power contact regions, overlap (s) in plan view, i. e. along the vertical direction, with the further first topside connection element in lateral directions.
[0035] Exemplarily, the control contact region comprises or consists of a gate contact region. Exemplarily, the first power contact region comprises or consists of a source contact region, an emitter contact region, or a cathode contact region.
[0036] According to the embodiment of the power semiconductor module, the first topside connection element is directly electrically conductively connected to the control contact region of the power semiconductor chip in the first side region. Exemplarily, the first topside connection element is directly electrically conductively connected to the control contact region by a dry contact, a sintering contact, a soldering contact, a welding contact, such as e.g. ultrasonic welding, laser welding, friction welding, or a glue contact.
[0037] For example, the dry contact is characteristic of a nonpermanent physical connection between the first topsideP2024,1161 WO E / P240219WO01 February 28, 2025
[0038] 8
[0039] connection element and the control contact region without using adhesives, solder, or welding.
[0040] Exemplarily, the term "directly electrically conductively connected" described herein means that dependent on a connection type, two elements are directly electrically connected to one another without an intermediate layer or with an intermediate layer comprising a solder material, a sinter material or a glue material.
[0041] According to the embodiment of the power semiconductor module, the further first topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the first side region. Exemplarily, the further first topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the first side region by a dry contact, a sintering contact, a soldering contact, a welding contact, such as e.g. ultrasonic welding, laser welding, friction welding, or a glue contact.
[0042] In particular, that the first topside connection element is directly electrically conductively connected to the control contact region of the power semiconductor chip in the first side region and that the further first topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the first side region means that the respective connections comprise no wire bonds.
[0043] Exemplarily, at least one further sensor device is arranged on one of the topside connection elements. In particular, theP2024,1161 WO E / P240219WO01 February 28, 2025
[0044] 9
[0045] further sensor device overlaps with the power semiconductor chip in plan view, i. e. along the vertical direction.
[0046] Achieving high power density in terms of both gravimetric and volumetric densities can be typically difficult to achieve. Exemplarily, achieving this requires extracting high current densities from the power semiconductor chips; however, the conventional wire bonds and die- top systems are typically not able to handle high current densities. In addition, high current densities in combination with a compact module design can lead to high magnetic fields that can interfere with gate signals and lead to instabilities. Furthermore, in conventional module design a significant portion of the conventional substrate is dedicated to the routing of signals and current paths as well as a landing area for terminals, which increases an overall footprint and reduces power density.
[0047] Advantageously, the power semiconductor module described herein enables the development of high-power density, compact, lightweight and reliable power semiconductor modules that are suited for the future generation of EV as well as urban air mobility and electric aircraft applications. In particular, using the topside connection elements - each connecting a respective contact region at the top surface -advantageously maximizes the performance, reduces the number of components and improves reliability.
[0048] According to a further embodiment, the power semiconductor module further comprises at least one power semiconductor chip arranged on the substrate in a second side region. The second side region is, for example, spaced apart from the first side region in lateral directions.P2024,1161 WO E / P240219WO01 February 28, 2025
[0049] - 10 -
[0050] Exemplarily, the second side region is a low side region of the power semiconductor module.
[0051] According to a further embodiment, the power semiconductor module further comprises a second topside connection element. For example, the second topside connection element has a main extension plane extending along lateral directions. The main extension plane of the first topside connection element and the main extension plane of the second topside connection element extend, for example, in a common plane.
[0052] Exemplarily, the at least one power semiconductor chip arranged on the substrate in the second side region overlaps in plan view, i. e. along the vertical direction, with the second topside connection element in lateral directions.
[0053] Exemplarily, the substrate, the power semiconductor chip arranged on the substrate in the second side region and the second topside connection element are stacked above one another in the vertical direction, particularly in the order indicated.
[0054] The second topside connection element comprises, for example, a second electrically conductive material, e.g. comprising a metal. The second electrically conductive material can comprise or consist of copper, aluminum, molybdenum, or a combination thereof or an alloy thereof. Exemplarily, the first electrically conductive material is equal to or different from the second electrically conductive material.
[0055] For example, at least one surface of the second topside connection element can be covered with a second coating, being in particular electrically conductive. The secondP2024, 1161 WO E / P240219WO01 February 28, 2025
[0056] coating can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof, e.g. AlCu. For example, a bottom surface of the second topside connection element facing the substrate can be regionally or completely covered with the second coating. Alternatively or additionally, a top surface of the second topside connection element facing away from the substrate can be regionally or completely covered with the second coating. Exemplarily, the first coating is equal to or different from the second coating.
[0057] According to a further embodiment, the power semiconductor module further comprises a second main terminal with a further second topside connection element which are directly electrically conductively connected to one another. For example, the second main terminal is a second power main terminal. This means that the second main terminal is configured to be electrically conductively contactable externally for providing power to the power semiconductor chip arranged on the substrate in the second side region. Exemplarily, the second main terminal is a DC- terminal of the power semiconductor module.
[0058] For example, the further second topside connection element has a main extension plane extending along lateral directions. The main extension plane of the further first topside connection element and the main extension plane of the further second topside connection element extend, for example, in a common plane. Exemplarily, the main extension planes of the first topside connection element, the second topside connection element, the further first topside connection element and the further second topside connection element extend in the common plane in lateral directions.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0059] - 12 -
[0060] Exemplarily, the at least one power semiconductor chip arranged on the substrate in the second side region overlaps in plan view with the further second topside connection element in lateral directions. Exemplarily, the substrate, the power semiconductor chip arranged on the substrate in the second side region and the further second topside connection element are stacked above one another in the vertical direction, particularly in the order indicated.
[0061] In particular, the second topside connection element does not overlap in plan view with the further second topside connection element in lateral directions. The main extension planes, in particular the top surfaces and / or the bottom surfaces, of the second topside connection element and the further second topside connection element are arranged within a common plane extending in lateral directions.
[0062] The second main terminal and the further second topside connection element comprise, for example, a further second electrically conductive material, e.g. comprising a metal. The further second electrically conductive material can comprise or consist of copper, aluminum, molybdenum, or a combination thereof or an alloy thereof. Exemplarily, the further first electrically conductive material is equal to or different from the further second electrically conductive material.
[0063] Exemplarily, the second main terminal and the further second topside connection element are formed integrally with one another.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0064] - 13 -
[0065] For example, at least one surface of the further second topside connection element can be covered with a further second coating, being in particular electrically conductive. The further second coating can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof, e.g. AlCu. For example, a bottom surface of the further second topside connection element facing the substrate can be regionally or completely covered with the further second coating. Alternatively or additionally, a top surface of the further second topside connection element facing away from the substrate can be regionally or completely covered with the further second coating. For example, the second coating and the further second coating can comprise the same material or comprise different materials.
[0066] In particular, the second main terminal and the further second topside connection element form a high current electrode of the power semiconductor module, and the second topside connection element forms a control electrode of the power semiconductor module in the second side region.
[0067] According to a further embodiment, the power semiconductor module further comprises a third main terminal. For example, the third main terminal is a third power main terminal. This means that the third main terminal is configured to be electrically conductively contactable externally for providing power to the power semiconductor chip arranged on the substrate in the first side region. Exemplarily, the third main terminal is a DC+ terminal of the power semiconductor module.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0068] - 14 -
[0069] In particular, the third main terminal forms a high current electrode of the power semiconductor module.
[0070] According to a further embodiment of the power semiconductor module, the second topside connection element is directly electrically conductively connected to the control contact region of the power semiconductor chip in the second side region. Exemplarily, the second topside connection element is directly electrically conductively connected to the control contact region of the power semiconductor chip in the second side region by a dry contact, a sintering contact, a soldering contact, a welding contact, such as e.g. ultrasonic welding, laser welding, friction welding, or a glue contact.
[0071] According to a further embodiment of the power semiconductor module, the further second topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the second side region. Exemplarily, the further second topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the second side region by a dry contact, a sintering contact, a soldering contact, a welding contact, such as e.g. ultrasonic welding, laser welding, friction welding, or a glue contact.
[0072] In particular, that the second topside connection element is directly electrically conductively connected to the control contact region of the power semiconductor chip in the second side region and that the further second topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductorP2024, 1161 WO E / P240219WO01 February 28, 2025
[0073] - 15 -
[0074] chip in the second side region means that the respective connections comprise no wire bonds.
[0075] According to a further embodiment of the power semiconductor module, the first topside connection element is surrounded in lateral directions by the further first topside connection element. Exemplarily, the further first topside connection element completely surrounds the first topside connection element in lateral directions.
[0076] According to a further embodiment of the power semiconductor module, the second topside connection element is surrounded in lateral directions by the further second topside connection element. Exemplarily, the further second topside connection element completely surrounds the second topside connection element in lateral directions.
[0077] According to a further embodiment of the power semiconductor module, the first topside connection element is electrically insulated from the further first topside connection element. In particular, the first topside connection element is spaced apart in lateral directions from the further first topside connection element.
[0078] According to a further embodiment of the power semiconductor module, the second topside connection element is electrically insulated from the further second topside connection element. In particular, the second topside connection element is spaced apart in lateral directions from the further second topside connection element.
[0079] According to a further embodiment of the power semiconductor module, each power semiconductor chip comprises a secondP2024, 1161 WO E / P240219WO01 February 28, 2025
[0080] - 16 -
[0081] power contact region at a bottom surface facing the substrate. Exemplarily, the second power contact region is arranged opposite the first power contact region and the control contact region at the bottom surface of the power semiconductor chip, particularly facing the substrate, in particular facing the top metallization.
[0082] Exemplarily, the second power contact region comprises or consists of a drain contact region, a collector contact region, or an anode contact region.
[0083] According to a further embodiment of the power semiconductor module, the further first topside connection element is electrically conductively connected to the second power contact region of the power semiconductor chip in the second side region. Exemplarily, the further first topside connection element is electrically conductively connected to the substrate, particularly the top metallization, in the second side region.
[0084] According to a further embodiment of the power semiconductor module, the third main terminal is electrically conductively connected to the second power contact region of the power semiconductor chip in the first side region. Exemplarily, the third main terminal is electrically conductively connected to the substrate, particularly the top metallization, in the first side region.
[0085] According to a further embodiment of the power semiconductor module, the substrate comprises the top metallization.
[0086] According to a further embodiment of the power semiconductor module, the top metallization comprises a first portion and aP2024, 1161 WO E / P240219WO01 February 28, 2025
[0087] - 17 -
[0088] second portion being spaced apart from one another in lateral directions. In particular, the first portion and the second portion are not in direct electrical contact with one another.
[0089] According to a further embodiment of the power semiconductor module, the first portion is located in the first side region, and the second portion is located in the second side region. Exemplarily, the further first topside connection element is electrically conductively connected to the second portion. Exemplarily, the third main terminal is electrically conductively connected to the first portion.
[0090] For example, the second power contact region of the power semiconductor chip in the first side region is directly electrically conductively connected to the first portion. Exemplarily, the second power contact region of the power semiconductor chip in the second side region is directly electrically conductively connected to the second portion.
[0091] According to a further embodiment of the power semiconductor module, the further first topside connection element comprises an interconnection.
[0092] Exemplarily, the third main terminal comprises a further interconnection.
[0093] According to a further embodiment of the power semiconductor module, the interconnection is directly electrically conductively connected to the second portion.
[0094] Exemplarily, the further interconnection is directly electrically conductively connected to the first portion.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0095] - 18 -
[0096] According to a further embodiment of the power semiconductor module, the interconnection comprises at least two sections. Each section is formed of a metallic band extending from the further first topside connection element to the second portion.
[0097] For example, the further interconnection comprises at least two further sections. Each further section is exemplarily formed of a metallic band extending from the third main terminal to the first portion.
[0098] According to a further embodiment of the power semiconductor module, the first main terminal, the second main terminal and the third main terminal are connected to the power semiconductor chip at the first side region and the power semiconductor chip at the second side region for forming a half bridge topology.
[0099] According to a further embodiment of the power semiconductor module, the further first topside connection element comprises a main portion extending in lateral directions and at least one connection structure extending in the vertical direction for connecting the first power region to the main portion. In particular, the main portion of the further first topside connection element defines the main extension plane of the further first topside connection element. Exemplarily, the main portion of the further first topside connection element and the connection structure of the further first topside connection element are formed integrally with one another.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0100] - 19 -
[0101] The connection structure of the further first topside connection element is, for example, a pillar. The pillar has, for example a round shape, an elliptical shape or polygonal shape in a cross section along the lateral directions.
[0102] For example, the further first main terminal can have cutouts. The cutouts are advantageously configured to release stress and / or to provide elasticity and / or flexibility.
[0103] According to a further embodiment of the power semiconductor module, the further second topside connection element comprises a main portion extending in lateral directions and at least one connection structure extending in the vertical direction for connecting the first power region to the main portion. In particular, the main portion of the further second topside connection element defines the main extension plane of the further second topside connection element.
[0104] Exemplarily, the main portion of the further second topside connection element and the connection structure of the further second topside connection element are formed integrally with one another.
[0105] The connection structure of the further second topside connection element is, for example, a pillar. The pillar has, for example, a round shape, an elliptical shape or polygonal shape in a cross section along the lateral directions.
[0106] For example, the further second main terminal can have further cutouts. The further cutouts are advantageously configured to release stress and / or to provide elasticity and / or flexibility.P2024, 1161 WO E / P240219WO01 February 28, 2025
[0107] - 20 -
[0108] According to a further embodiment of the power semiconductor module, at least two power semiconductor chips are arranged on the substrate in the first side region.
[0109] According to a further embodiment of the power semiconductor module, at least two power semiconductor chips are arranged on the substrate in the second side region.
[0110] If more than one power semiconductor chip are arranged in a corresponding side region, the power semiconductor chips are arranged on further virtual grid points of a virtual regular grid extending in lateral directions. The further virtual regular grid can be a polygonal grid, like a triangular or quadrangular grid. Exemplarily, if four power semiconductor chips are arranged on a corresponding side region, the power semiconductor chips are arranged for example on the further virtual grid points of a further virtual regular grid being the quadrangular grid, particularly a rectangular grid.
[0111] According to a further embodiment of the power semiconductor module, the first topside connection element is directly electrically conductively connected to the at least two control contact regions of the at least two power semiconductor chips in the first side region.
[0112] According to a further embodiment of the power semiconductor module, the second topside connection element is directly electrically conductively connected to the at least two control contact regions of the at least two power semiconductor chips in the second side region.
[0113] Advantageously, the control contact regions, particularly the gates, of the power semiconductor chips of a correspondingP2024,1161 WO E / P240219WO01 February 28, 2025
[0114] - 21 -
[0115] side region can be all contacted in parallel by a single topside connection element.
[0116] According to a further embodiment of the power semiconductor module, the control contact regions of the power semiconductor chips in the first side region face one another.
[0117] According to a further embodiment of the power semiconductor module, the control contact regions of the power semiconductor chips in the second side region face one another.
[0118] For example, distances of the control contact regions of the power semiconductor chips in the first side region and / or the second side region to a center of the first topside connection element and / or the second topside connection element are equal to one another, respectively.
[0119] Exemplarily, the first topside connection element and / or the second topside connection element each comprises at least two electrically conductive parts, wherein each electrically conductive part connects the respective control contact region to the center of the first topside connection element and / or the second topside connection element, respectively. In particular, the electrically conductive parts each have a length, being equal to one another.
[0120] The center of the first topside connection element and / or the second topside connection element is, respectively, in particular characteristic for a geometric center of the first topside connection element and / or the second topsideP2024,1161 WO E / P240219WO01 February 28, 2025
[0121] - 22 -
[0122] connection element in lateral directions and / or a center of mass.
[0123] Advantageously, due to such an orientation of the power semiconductor chips, distances between control contact regions are minimized to achieve low gate inductances and a balanced current sharing between the power semiconductor chips.
[0124] According to a further embodiment of the power semiconductor module, the first topside connection element and the second topside connection element each comprise a main portion extending in lateral directions and a connection structure extending in the vertical direction.
[0125] In particular, the main portion of the first topside connection element defines the main extension plane of the first topside connection element. In particular, the main portion of the second topside connection element defines the main extension plane of the second topside connection element. Exemplarily, the main portion of the first topside connection element and the connection structure of the first topside connection element are formed integrally with one another. Exemplarily, the main portion of the second topside connection element and the connection structure of the second topside connection element are formed integrally with one another.
[0126] The connection structure of the first topside connection element and / or the connection structure of the second topside connection element is / are, for example, a pillar. The pillar has, for example a round shape, an elliptical shape orP2024,1161 WO E / P240219WO01 February 28, 2025
[0127] - 23 -
[0128] polygonal shape in a cross section along the lateral directions.
[0129] According to a further embodiment of the power semiconductor module, each connection structure of the first topside connection element and the second topside connection element connects one of the control contact regions to the main portion. In particular, the connection structure of the first topside is directly electrically conductively connected to the control contact region of the power semiconductor chip in the first side region. In particular, the connection structure of the second topside is directly electrically conductively connected to the control contact region of the power semiconductor chip in the second side region.
[0130] According to a further embodiment of the power semiconductor module, the main portion of the further first topside connection element has a first recess. For example, the first recess completely penetrates the main portion of the further first topside connection element in the vertical direction.
[0131] According to a further embodiment of the power semiconductor module, the main portion of the first topside connection element is arranged in the first recess. Exemplarily, a side surface of the first recess delimited by the main portion of the further first topside connection element in lateral directions completely surrounds the first topside connection element.
[0132] Exemplarily, the top surfaces and / or bottom surfaces of the main portions of the first topside connection element and the further first topside connection element extend within a common plane in lateral directions.P2024,1161 WO E / P240219WO01 February 28, 2025
[0133] - 24 -
[0134] According to a further embodiment of the power semiconductor module, the main portion of the further second topside connection element has a second recess. For example, the second recess completely penetrates the main portion of the further second topside connection element in the vertical direction.
[0135] According to a further embodiment of the power semiconductor module, the main portion of the second topside connection element is arranged in the second recess. Exemplarily, a side surface of the second recess delimited by the main portion of the further second topside connection element in lateral directions completely surrounds the second topside connection element.
[0136] Exemplarily, top surfaces and / or bottom surfaces of the main portions of the second topside connection element and the further second topside connection element extend within a common plane in lateral directions.
[0137] According to a further embodiment, the power semiconductor module comprises a package body, wherein the package body completely encapsulates the power semiconductor chip, particularly the power semiconductor chips in the first side region and the second side region. Exemplarily, the package body, the substrate and the topside connection element encapsulate the power semiconductor chip, particularly the power semiconductor chips in the first side region and the second side region, particularly completely in a three-dimensional manner.P2024,1161 WO E / P240219WO01 February 28, 2025
[0138] - 25 -
[0139] According to a further embodiment of the power semiconductor module, the package body at least partly encapsulates the further first topside connection element and the further second topside connection element. This means that the top surfaces of the further first topside connection element and the further second topside connection element can be partially free of the package body for being configured to be electrically conductively contactable externally.
[0140] According to a further embodiment of the power semiconductor module, the first main terminal, the second main terminal and the third main terminal each protrude beyond the package body in lateral directions. This means that the protruding parts of the first main terminal, the second main terminal and the third main terminal are free of the package body for being configured to be electrically conductively contactable externally.
[0141] According to a further embodiment of the power semiconductor module, the package body at least partly encapsulates the first topside connection element and the second topside connection element. This means that the top surfaces of the first topside connection element and the second topside connection element can be partially free of the package body for being configured to be electrically conductively contactable externally.
[0142] According to a further embodiment of the power semiconductor module, the package body has at least one recess extending in the vertical direction through the package body in the first side region for exposing the first topside connection element.P2024,1161 WO E / P240219WO01 February 28, 2025
[0143] - 26 -
[0144] According to a further embodiment of the power semiconductor module, the package body has at least one recess extending in the vertical direction through the package body in the second side region for exposing the second topside connection element.
[0145] The at least one recess in the package body has at least one side surface delimited by the package body. The at least one side surface of the recess is, for example, covered by a third coating, which can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof.
[0146] According to a further embodiment of the power semiconductor module, the substrate comprises the bottom metallization.
[0147] According to a further embodiment of the power semiconductor module, the bottom metallization comprises or consists of a common portion. The common portion is, for example, formed as a metallization plate, e.g. being simply connected.
[0148] According to a further embodiment of the power semiconductor module, the package body has an opening extending in the vertical direction through the package body in the first side region and in the second side region for exposing the common portion.
[0149] For example, the exposed common portion is configured to be coupled to a mechanical support, a heat sink and / or a cooler.
[0150] According to a further embodiment of the power semiconductor module, the package body has at least one further recess extending in the vertical direction through the package bodyP2024,1161 WO E / P240219WO01 February 28, 2025
[0151] - 27 -
[0152] in the first side region for exposing the further first topside connection element.
[0153] According to a further embodiment of the power semiconductor module, the package body has at least one further recess extending in the vertical direction through the package body in the second side region for exposing the further second topside connection element.
[0154] The at least one further recess in the package body has at least one further side surface delimited by the package body. The at least one further side surface of the recess is, for example, covered by a further third coating, which can comprise or consist of at least one of the materials of silver, gold, nickel, aluminum, copper, or alloys thereof. For example, the third coating and the further third coating can comprise the same material or comprise different materials.
[0155] In particular, the third coating and / or the further third coating advantageously allow making a dry contact using spring loaded contacts.
[0156] The recess and / or the further recess advantageously reduce (s) a thermomechanical stress on the package body.
[0157] According to a further embodiment of the power semiconductor module, a contact arrangement with at least one contact is arranged in the respective recess for directly electrically conductively connecting the respective topside connection element.P2024,1161 WO E / P240219WO01 February 28, 2025
[0158] - 28 -
[0159] According to a further embodiment of the power semiconductor module, the contact arrangement with at least one further contact is arranged in the respective further recess for directly electrically conductively connecting the respective main terminal.
[0160] Exemplarily, the contact arrangement is formed of at least one bayonet connector, BNC, at least one radio frequency, RF, connector, for example a standard RF terminal, at least one spring loaded contact, at least one pogo pin, or at least one pin terminal.
[0161] Advantageously, the contact in the recess and / or the further recess provides an electrical connection to an external circuit, for example by spring loaded contacts.
[0162] A further embodiment relates to a method for producing a power semiconductor module, in particular the power semiconductor module as described herein above. Therefore, the features as described in connection with the method are also applicable to the power semiconductor module and vice versa.
[0163] According to the embodiment of the method, a substrate is provided.
[0164] According to the embodiment of the method, at least one power semiconductor chip is arranged on the substrate in a first side region.
[0165] According to the embodiment of the method, at least one power semiconductor chip is arranged on the substrate in a second side region.P2024,1161 WO E / P240219WO01 February 28, 2025
[0166] - 29 -
[0167] According to the embodiment of the method, a first topside connection element is connected to the power semiconductor chip in the first side region.
[0168] According to the embodiment of the method, a second topside connection element is connected to the power semiconductor chip in the second side region.
[0169] According to the embodiment of the method, a first main terminal and a further first topside connection element which are directly electrically conductively connected to one another are connected to the power semiconductor chip in the first side region.
[0170] According to the embodiment of the method, a second main terminal and a further second topside connection element which are directly electrically conductively connected to one another are connected to the power semiconductor chip in the second side region.
[0171] According to the embodiment of the method, a third main terminal is connected to the power semiconductor chip in the first side region.
[0172] According to the embodiment of the method, the power semiconductor chip in the first side region comprises at least one control contact region and at least one first power contact region at a top surface facing away from the substrate.
[0173] According to the embodiment of the method, the first topside connection element is directly electrically conductivelyP2024,1161 WO E / P240219WO01 February 28, 2025
[0174] - 30 -
[0175] connected to the control contact region of the power semiconductor chip in the first side region.
[0176] According to the embodiment of the method, the further first topside connection element is directly electrically conductively connected to the first power contact region of the power semiconductor chip in the first side region.
[0177] According to the embodiment of the method, the further first topside connection element is directly electrically conductively connected to the first power contact region by welding, sintering or soldering.
[0178] According to the embodiment of the method, the first topside connection element is directly electrically conductively connected to the control contact region by welding, sintering or soldering.
[0179] For directly electrically conductively connecting at least some or all the topside connection elements on the corresponding regions, exemplarily, at least some or all the topside connection elements are arranged on the corresponding regions. After at least some or all the topside connection elements are arranged on the corresponding regions, for example, a final sintering or a final soldering process is applied to form the direct electrically conductively connections between the topside connection elements and the corresponding regions. Advantageously, this step can eliminate the need for using multiple bonding methods or multiple sintering steps.
[0180] The accompanying figures are included to provide a further understanding. In the figures, elements of the same structureP2024,1161 WO E / P240219WO01 February 28, 2025
[0181] 31
[0182] and / or functionality may be referenced by the same reference signs. It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
[0183] Figures 1 and 2 each show a schematic view of parts of a power semiconductor module according to an exemplary embodiment as shown in Figure 3.
[0184] Figures 4, 5, 6, 7 and 8 each show a schematic view of a power semiconductor module according to an exemplary embodiment.
[0185] The power semiconductor module 1 according to Figures 1, 2 and 3 comprises a substrate 16 according to Figure 1. The substrate 16 comprises a top metallization 17 arranged on an insulating layer 20. The substrate 16 further comprises a bottom metallization 21, which is not shown in the Figures. The top metallization 17 comprises a first portion 18 and a second portion 19 being spaced apart from one another in lateral directions, and thus being electrically insulated from one another on the insulating layer 20. The first portion 18 is located in a first side region 13, and the second portion 19 is located in a second side region 14. Particularly, the first side region 13 is a high side region of the power semiconductor module 1 and the second side region 14 is a low side region of the power semiconductor module 1.
[0186] The substrate 16 extends in a main extension plane extending in lateral directions.P2024,1161 WO E / P240219WO01 February 28, 2025
[0187] 32
[0188] On the first portion 18, four power semiconductor chips 2 are arranged in the first side region 13. Further, on the second portion 19, four power semiconductor chips 2 are arranged in the second side region 14. Each power semiconductor chip 2 comprises one control contact region 8, particularly a gate contact region, and three first power contact regions 7, particularly source contact regions, at a top surface 6 facing away from the substrate 16. The power semiconductor chips 2 in one respective side region are arranged such that the control contact regions 8 face one another.
[0189] A first topside connection element 3 is directly electrically conductively connected to the control contact regions 8, particularly to all control contact regions 8, of the power semiconductor chips 2 in the first side region 13. The first topside connection element 3 comprises a main portion 30 extending in lateral directions and four connection structures 31 extending in the vertical direction, perpendicular to the lateral directions. Each connection structure 31 of the first topside connection element 3 is directly electrically conductively connected to one of the control contact regions 8 of the power semiconductor chips 2 in the first side region 13.
[0190] A second topside connection element 9 is directly electrically conductively connected to the control contact regions 8, particularly to all control contact regions 8, of the power semiconductor chips 2 in the second side region 14. The second topside connection element 9 comprises a main portion 30 extending in lateral directions and four connection structures 31 extending in the vertical direction, perpendicular to the lateral directions. Each connection structure 31 of the second topside connection element 9 isP2024,1161 WO E / P240219WO01 February 28, 2025
[0191] directly electrically conductively connected to one of the control contact regions 8 of the power semiconductor chips 2 in the second side region 14.
[0192] The view in Figure 1 is directed to top surfaces 6 of the first and the second topside connection elements 3, 9.
[0193] Advantageously, an orientation of the power semiconductor chips 2 is symmetrical such that distances between control contact regions 8 are minimized to achieve low gate inductances and a balanced current sharing between the power semiconductor chips 2. Advantageously, the first topside connection element 3 and / or the second topside connection element 9 is / are formed of a butterfly- shaped gate runner that can connect the respective control contact regions 8 of the respective power semiconductor chips 2 in parallel.
[0194] Further, the power semiconductor chips 2 are arranged to form a half bridge configuration with four power semiconductor chips 2 per switch position.
[0195] In particular, the topside connection elements advantageously provide electrical connections to the power semiconductor chips 2 to form the desired circuit configuration, which here is a half bridge. As a result, the layout design of the substrate 16 is particularly simple as only two portions, namely the first portion 18 and the second portion 19, of the top metallization 17 are needed for the attachment of high side region and low side region devices.
[0196] This can significantly improve the reliability of the power semiconductor module 1 with respect to power cycling stresses and reduces a chance of formation of partial discharges sinceP2024,1161 WO E / P240219WO01 February 28, 2025
[0197] it reduces the length of triple points, e.g. locations at edges between the packet body shown in Figure 4, the top metallization 17, and the insulating layer 20, e.g. being a substrate ceramic. In addition, having the topside connection elements formed as described in connection with Figures 1 to 3, a size of the substrate 16 is advantageously comparatively small because no additional space is needed for a routing of signals or current paths on the substrate 16. Therefore, the power semiconductor module 1 is advantageously compact, lightweight and reliable, e.g. at comparatively high operating temperatures because an overall thermomechanical stress resulting from thermal expansions is comparatively reduced.
[0198] The power semiconductor module 1 according to Figures 1, 2 and 3 further comprises a first main terminal 4, a second main terminal 10 and a third main terminal 12 according to Figure 2, as well as a further first topside connection element 5 and a further second topside connection element 11. Unlike in Figure 1, the view in Figure 2 is directed to bottom surfaces of the first and the second topside connection elements 3 and 9.
[0199] The first main terminal 4 is directly electrically conductively connected to the further first topside connection element 5. Further, the second main terminal 10 is directly electrically conductively connected to the further second topside connection element 11.
[0200] The further first topside connection element 5 is directly electrically conductively connected to the first power contact regions 7, particularly to all first power contact regions 7, of the power semiconductor chips 2 in the firstP2024,1161 WO E / P240219WO01 February 28, 2025
[0201] 35
[0202] side region 13. The further first topside connection element 5 comprises a main portion 30 extending in lateral directions and twelve connection structures 31 extending in the vertical direction, perpendicular to the lateral directions. Each connection structure 31 of the further first topside connection element 5 is directly electrically conductively connected to one of the first power contact regions 7 of the power semiconductor chips 2 in the first side region 13.
[0203] The further second topside connection element 11 is directly electrically conductively connected to the second power contact regions 15, particularly to all second power contact regions 15, of the power semiconductor chips 2 in the second side region 14. The further second topside connection element 11 comprises a main portion 30 extending in lateral directions and twelve connection structures 31 extending in the vertical direction, perpendicular to the lateral directions. Each connection structure 31 of the further second topside connection element 11 is directly electrically conductively connected to one of the second power contact regions 15 of the power semiconductor chips 2 in the second side region 14.
[0204] The main portion 30 of the further first topside connection element 5 has a first recess, wherein the main portion 30 of the first topside connection element 3 is arranged in the first recess. Further, the main portion 30 of the further second topside connection element 11 has a second recess, wherein the main portion 30 of the second topside connection element 9 is arranged in the second recess.
[0205] For example, the further first main terminal 4 can have cutouts 32 as further described in connection with Figure 3P2024,1161 WO E / P240219WO01 February 28, 2025
[0206] 36
[0207] for releasing stress and / or to provide elasticity and / or flexibility. The cutouts 32 are particularly arranged directly adjacent to the main portion 30 of the first main terminal 4.
[0208] For example, the second main terminal 10 can have cutouts 32 as further described in connection with Figure 3 for releasing stress and / or to provide elasticity and / or flexibility. The cutouts 32 are particularly arranged directly adjacent to the main portion 30 of the second main terminal 10.
[0209] The first main terminal 4 comprises an interconnection 27, and the third main terminal 12 comprises a further interconnection 28, which is further described in connection with Figure 3.
[0210] The power semiconductor module 1 according to Figure 3 comprises the elements described in connection with Figures 1 and 2, wherein the view in Figure 3 is directed to top surfaces 6 of the first and the second topside connection elements 3, 9.
[0211] For example, each power semiconductor chip 2 comprises a second power contact region 15 at a bottom surface facing the substrate 16, which is not explicitly shown in the Figures. The second power contact of the power semiconductor chip 2 in the first side region 13 is directly electrically conductively connected to the first portion 18, and the second power contact of the power semiconductor chip 2 in the second side region 14 is directly electrically conductively connected to the second portion 19. Exemplarily, the second power contact regions 15 are drain contact regions.P2024,1161 WO E / P240219WO01 February 28, 2025
[0212] - 37 -
[0213] The further first topside connection element 5 is electrically conductively connected to the second portion 19 by the interconnection 27. Further, the third main terminal 12 is electrically conductively connected to the first portion 18 by the further interconnection 28. The interconnection 27 and the further interconnection 28 each comprise a plurality of sections 29, each section 29 being formed as a metallic band.
[0214] The main terminals are advantageously integrated with the topside connection elements, which reduces a current path length and stray inductances significantly. Further, such topside connection elements further advantageously eliminate the need for a conventional die top system since the bonding of the power semiconductor chips 2 to the topside connection elements is achieved via the connection structures 31, e.g. formed of extruded pillars. Exemplarily, the connection structures 31 are sintered to the power semiconductor chips 2 using pressure - assisted or pressure - less sintering, soldering or welding, e.g. laser welding.
[0215] Advantageously, an attachment of topside connection elements to the substrate 16, e.g. the respective portions, can be made using the same process as used for the attachment of the power semiconductor chips 2 or in a separate process such as welding, e.g. ultrasonic welding, laser welding, sintering or soldering.
[0216] Preferably, the attachment of the power semiconductor chips 2 to the topside connection elements is made by pressure-assisted sintering and / or the attachment of topside connection elements to the substrate 16 by ultrasonicP2024,1161 WO E / P240219WO01 February 28, 2025
[0217] welding. Alternatively, also pressure - less sintering or soldering can achieve good results.
[0218] The power semiconductor module 1 according to Figures 4, 5 and 6 comprises, in contrast to the power semiconductor module 1 according to Figure 3, a package body 23. The view in Figure 4 is directed to top surfaces 6 of the first and the second topside connection elements 3, 9.
[0219] The package body 23 completely encapsulates the power semiconductor chip 2. Further, the first main terminal 4, the second main terminal 10 and the third main terminal 12 each protrude beyond the package body 23 in lateral directions.
[0220] The package body 23 has recesses 24 extending in the vertical direction through the package body 23 in the first side region 13 for exposing the first topside connection element 3, and the package body 23 has recesses 24 extending in the vertical direction through the package body 23 in the second side region 14 for exposing the second topside connection element 9.
[0221] The package body 23 additionally has further recesses 25 extending in the vertical direction through the package body 23 in the first side region 13 for exposing the further first topside connection element 5, and the package body 23 has at least one further recess 25 extending in the vertical direction through the package body 23 in the second side region 14 for exposing the further second topside connection element 11.
[0222] The view in Figure 5 is directed to bottom surfaces of the first and the second topside connection elements 3, 9, i. e.P2024,1161 WO E / P240219WO01 February 28, 2025
[0223] the view is rotated by 180° in Figure 5 with respect to Figure 4. Exemplarily, the substrate 16 comprises a bottom metallization 21, which is not shown in the Figures. The bottom metallization 21 comprises a common portion 22, extending in an opening 26 in the package body 23 in the first side region 13 and in the second side region 14 for exposing the common portion 22.
[0224] The view in Figure 6 shows a plan view, i. e. along the vertical direction, towards the top surfaces 6.
[0225] The power semiconductor module 1 according to Figures 7 and 8 each additionally comprises a contact arrangement 33 with a connector 34 and contacts 35. The contacts 35 are arranged in the respective recesses 24 for directly electrically conductively connecting the respective topside connection element.
[0226] Each contact arrangement 33 in Figure 7 has a connector 34 which is an RF connector 34, and the contacts 35 of the RF connector 34 are arranged in the recesses 24 for contacting the first and the second topside connection element 3, 9, respectively.
[0227] Further, the contact arrangement 33 in Figure 8 comprises a printed circuit board, PCB, with contacts 35 and further contacts 35, wherein the further contacts 35 are arranged in the respective further recesses 25 for directly electrically conductively connecting the respective main terminal.
[0228] Advantageously, the package body 23 of the power semiconductor module 1 is formed in such a way that the package body 23 covers the elements of the powerP2024,1161 WO E / P240219WO01 February 28, 2025
[0229] 40
[0230] semiconductor module 1 except the main terminals, a bottom metallization 21 of the substrate 16, and wherein the package body 23 having recesses 24 and further recesses 25 to provide access to the topside connection elements for gate and auxiliary connections.
[0231] The positions of the recesses 24 and further recesses 25 for the gate and auxiliary sources are defined to obtain the best electromagnetic performance, i. e. balanced low gate inductances and negative low mutual couplings. The recesses 24 and further recesses 25 also advantageously allow the attachment of RF connectors 34 such as SMA or BNC with coaxial cables for the best protection from the potential interferences on gate signals. The recesses 24 and further recesses 25 can further accommodate contacts 35 from a gate driver circuit comprised by the PCB using pin terminals, e.g. being soldered, screwed or press fitted, or spring - loaded contacts. The power semiconductor module 1 advantageously combines both possibilities to provide more flexibility for a user to make a choice based on the application requirements and optimizations.
[0232] The exemplary embodiments, in particular features of the exemplary embodiments, of the Figures can be combined with one another.P2024,1161 WO E / P240219WO01 February 28, 2025
[0233] Reference Signs
[0234] 1 power semiconductor module
[0235] 2 power semiconductor chip
[0236] 3 first topside connection element
[0237] 4 first main terminal
[0238] 5 further first topside connection element 6 top surface
[0239] 7 first power contact region
[0240] 8 control contact region
[0241] 9 second topside connection element
[0242] 10 second main terminal
[0243] 11 further second topside connection element 12 third main terminal
[0244] 13 first side region
[0245] 14 second side region
[0246] 15 second power contact region
[0247] 16 substrate
[0248] 17 top metallization
[0249] 18 first portion
[0250] 19 second portion
[0251] 20 insulating layer
[0252] 21 bottom metallization
[0253] 22 common portion
[0254] 23 package body
[0255] 24 recess
[0256] 25 further recess
[0257] 26 opening
[0258] 27 interconnection
[0259] 28 further interconnection
[0260] 29 section
[0261] 30 main portion
[0262] 31 connection structureP2024,1161 WO E / P240219WO01 February 28, 2025
[0263] - 42 -
[0264] 32 cutouts
[0265] 33 contact arrangement 34 connector
[0266] 35 contact
Claims
P2024,1161 WO E / P240219WO01 February 28, 2025- 43 -Claims1. Power semiconductor module (1), comprising- a substrate (16),- at least one power semiconductor chip (2) arranged on the substrate (16) in a first side region (13 ),- a first topside connection element (3 ), and- a first main terminal (4) and a further first topside connection element (5) which are directly electrically conductively connected to one another, wherein- the at least one power semiconductor chip (2) comprises at least one control contact region (8) and at least one first power contact region (7) at a top surface (6) facing away from the substrate (16),- the first topside connection element (3 ) is directly electrically conductively connected to the control contact region (8) of the power semiconductor chip (2) in the first side region (13 ), and- the further first topside connection element (5) is directly electrically conductively connected to the first power contact region (7) of the power semiconductor chip (2) in the first side region (13 ).
2. Power semiconductor module (1) according to claim 1, further comprising- at least one power semiconductor chip (2) arranged on the substrate (16) in a second side region (14),- a second topside connection element (9 ), and- a second main terminal (10) with a further second topside connection element (11) which are directly electrically conductively connected to one another, and a third main terminal (12), whereinP2024,1161 WO E / P240219WO01 February 28, 202544- the second topside connection element (9 ) is directly electrically conductively connected to the control contact region (8) of the power semiconductor chip (2) in the second side region (14), and- the further second topside connection element (11 ) is directly electrically conductively connected to the first power contact region (7) of the power semiconductor chip (2) in the second side region (14).
3. Power semiconductor module (1) according to claim 1 or 2, wherein- the first topside connection element (3 ) is surrounded in lateral directions by the further first topside connection element (5), and- the first topside connection element (3 ) is electrically insulated from the further first topside connection element (5).
4. Power semiconductor module (1) according to claim 2 or 3, wherein- the second topside connection element (9 ) is surrounded in lateral directions by the further second topside connection element (11), and- the second topside connection element (9 ) is electrically insulated from the further second topside connection element (11).
5. Power semiconductor module (1) according to claim 2 to 4, wherein- each power semiconductor chip (2) comprises a second power contact region (15) at a bottom surface facing the substrateP2024,1161 WO E / P240219WO01 February 28, 2025- 45 -- the further first topside connection element (5) is electrically conductively connected to the second power contact region (15) of the power semiconductor chip (2) in the second side region (14), and- the third main terminal (12) is electrically conductively connected to the second power contact region (15) of the power semiconductor chip (2) in the first side region (13 ).
6. Power semiconductor module (1) according to any one of claims 2 to 5, wherein- the substrate (16) comprises a top metallization (17), - the top metallization (17) comprises a first portion (18) and a second portion (19 ) being spaced apart from one another in lateral directions, and- the first portion (18) is located in the first side region (13 ), and- the second portion (19 ) is located in the second side region ( 14 ).
7. Power semiconductor module (1) according to claim 6, wherein- the further first topside connection element (5) comprises an interconnection (27), and- the interconnection (27) is directly electrically conductively connected to the second portion (19 ).
8. Power semiconductor module (1) according to claim 7, wherein- the interconnection (27) comprises at least two sections (29 ).
9. Power semiconductor module (1) according to any one of claims 2 to 8, whereinP2024,1161 WO E / P240219WO01 February 28, 2025- the first main terminal (4), the second main terminal (10) and the third main terminal (12) are connected to the power semiconductor chip (2) at the first side region (13 ) and the power semiconductor chip (2) at the second side region (14) for forming a half bridge topology.
10. Power semiconductor module (1) according to any one of claims 2 to 9, wherein- the further first topside connection element (5) comprises a main portion (30) extending in lateral directions and at least one connection structure (31) extending in a vertical direction for connecting the first power region to the main portion (30), and- the further second topside connection element (11 ) comprises a main portion (30) extending in lateral directions and at least one connection structure (31) extending in the vertical direction for connecting the first power region to the main portion (30).
11. Power semiconductor module (1) according to any one of claims 2 to 10, wherein- at least two power semiconductor chips (2) are arranged on the substrate (16) in the first side region (13),- at least two power semiconductor chips (2) are arranged on the substrate (16) in the second side region (14),- the first topside connection element (3 ) is directly electrically conductively connected to the at least two control contact regions (8) of the at least two power semiconductor chips (2) in the first side region (13), and - the second topside connection element (9 ) is directly electrically conductively connected to the at least two control contact regions (8) of the at least two power semiconductor chips (2) in the second side region ( 14).P2024,1161 WO E / P240219WO01 February 28, 202512. Power semiconductor module (1) according to claim 11, wherein- the control contact regions (8) of the power semiconductor chips (2) in the first side region (13 ) face one another, and - the control contact regions (8) of the power semiconductor chips (2) in the second side region (14) face one another.
13. Power semiconductor module (1) according to claim 11 or 12, wherein- the first topside connection element (3 ) and the second topside connection element (9 ) each comprise a main portion (30) extending in lateral directions and a connection structure (31) extending in the vertical direction, and- each connection structure (31) of the first topside connection element (3 ) and the second topside connection element (9 ) connects one of the control contact regions (8) to the main portion (30).
14. Power semiconductor module (1) according to claims 10 and 13, wherein- the main portion (30) of the further first topside connection element (5) has a first recess,- the main portion (30) of the first topside connection element (3 ) is arranged in the first recess,- the main portion (30) of the further second topside connection element (11) has a second recess,- the main portion (30) of the second topside connection element (9 ) is arranged in the second recess.
15. Power semiconductor module (1) according to any one of claims 2 to 14, further comprisinga package body (23 ), whereinP2024,1161 WO E / P240219WO01 February 28, 2025- the package body (23 ) completely encapsulates the power semiconductor chip (2),- the package body (23 ) at least partly encapsulates the further first topside connection element (5) and the further second topside connection element (11),- the first main terminal (4), the second main terminal (10) and the third main terminal (12) each protrude beyond the package body (23 ) in lateral directions, and- the package body (23 ) at least partly encapsulates the first topside connection element (3 ) and the second topside connection element (9 ).
16. Power semiconductor module (1) according to claim 15, wherein- the package body (23 ) has at least one recess (24 ) extending in the vertical direction through the package body (23 ) in the first side region (13 ) for exposing the first topside connection element (3 ), and- the package body (23 ) has at least one recess (24 ) extending in the vertical direction through the package body (23 ) in the second side region (14) for exposing the second topside connection element (9 ).
17. Power semiconductor module (1) according claim 15 to 16, wherein- the substrate (16) comprises a bottom metallization (21), - the bottom metallization (21) comprises or consists of a common portion (22), and- the package body (23 ) has an opening (26) extending in the vertical direction through the package body (23) in the first side region (13 ) and in the second side region (14) for exposing the common portion (22).P2024,1161 WO E / P240219WO01 February 28, 2025- 49 -18. Power semiconductor module (1) according to any one of claims 15 to 17, wherein- the package body (23 ) has at least one further recess (25) extending in the vertical direction through the package body (23 ) in the first side region (13 ) for exposing the further first topside connection element (5), and- the package body (23 ) has at least one further recess (25) extending in the vertical direction through the package body (23 ) in the second side region (14) for exposing the further second topside connection element (11).
19. Power semiconductor module (1) according to claims 16 and 18, wherein- a contact arrangement (33 ) with at least one contact (35) is arranged in the respective recess (24) for directly electrically conductively connecting the respective topside connection element, and / or- the contact arrangement (33 ) with at least one further contact (35) is arranged in the respective further recess (25) for directly electrically conductively connecting the respective main terminal.
20. Method for producing a power semiconductor module (1), comprising:- providing a substrate (16),- arranging at least one power semiconductor chip (2) on the substrate (16) in a first side region (13 ),- connecting a first topside connection element (3 ) to the power semiconductor chip (2) in the first side region (13 ), - connecting a first main terminal (4) and a further first topside connection element (5) which are directly electrically conductively connected to one another to theP2024,1161 WO E / P240219WO01 February 28, 202550power semiconductor chip (2) in the first side region (13 ), wherein- the power semiconductor chip (2) in the first side region (13 ) comprises at least one control contact region (8) and at least one first power contact region (7) at a top surface (6) facing away from the substrate (16),- the first topside connection element (3 ) is directly electrically conductively connected to the control contact region (8) of the power semiconductor chip (2) in the first side region (13 ),- the further first topside connection element (5) is directly electrically conductively connected to the first power contact region (7) of the power semiconductor chip (2) in the first side region (13 ).