Compensation of switching losses in multiple chips and multiple modules
Patent Information
- Application Number
- PCT/EP2026/054497
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-26
- Filing Date
- 2026-02-19
- Publication Date
- 2026-09-03
Smart Images
Figure EP2026054497_03092026_PF_FP_ABST
Abstract
Description
[0001] R.412786
[0002] - 1 -
[0003] Description
[0004] title
[0005] Compensation for switching losses across multiple chips and modules
[0006] State of the art
[0007] The present invention relates to a gate driver for compensating switching losses of at least one power module by determining a gate current profile for a switch-on process and a switch-off process of a logic switch.
[0008] The demand for high-power inverters is increasing in the automotive industry. To achieve high power output, current technology involves connecting power semiconductors and power modules in parallel to increase the phase current at the same DC link voltage. The design of the power module's electrical architecture and the selection of semiconductor chips are determined by the desired power increase. This power increase is achieved by reducing switching and conduction losses within a logic switch in a single or multiple parallel-connected modules. While the total switching losses of a logic switch are important, the loss distribution between individual microchips or parallel-connected modules should not be neglected and can be crucial for a product's reliability and lifespan.
[0009] State-of-the-art techniques include optimizing the power module layout and using intelligent gate drivers to mitigate current imbalance. For example, power modules with a symmetrical layout are designed for this purpose. Another method for balancing dynamic current in an asymmetrical layout involves nonlinear optimization and the application of RSM (response surfaceR.412786).
[0010] -2 -
[0011] methodology) with respect to the parasitic inductances of the power module. Passive switching loss compensation using an inductor and a resistor in the gate path is also possible. More recently, active switching loss compensation using a smart gate driver has been employed, which involves introducing a time delay into the gate driver circuit to reduce current imbalance and prevent thermal breakdown. Other industry best practices for reducing current imbalance include binning the chips in a logic switch based on the threshold voltage Vth, the plateau voltage Vth. plateau or the drain-source resistance R DS,ON can be based on.
[0012] An asymmetrical module layout or microchips with mismatched parameters leads to differences in switching losses between the SiC MOSFET chips in a multi-chip logic switch, which in turn leads to differences in junction temperature. These junction temperature differences increase the difference in the threshold and plateau voltages of the SiC MOSFET chips, further increasing the switching losses. Particularly in high-frequency, hard-switching applications, this can lead to thermal breakdown of the SiC MOSFET chips due to positive feedback. This reduces the reliability and lifetime of the SiC MOSFET chips. The same problem occurs with parallel modules, each containing a logic switch.The previously mentioned methods for compensating switching losses aim to balance the switching energy by aligning the current edges during current commutation in the case of a hard switching operation. However, this method cannot completely compensate for the switching energy, as a difference in switching energy always remains during voltage commutation. Furthermore, there is no algorithm for compensating switching losses between SiC MOSFET chips that considers the different operating conditions (junction temperatures, phase currents, and battery voltages) and the dependence of the threshold and plateau voltages on these conditions. Operating-point-based optimization is necessary, however, to achieve optimal gate driver performance under all operating conditions. R.412786.
[0013] - 3 -
[0014] Disclosure of the invention
[0015] The gate driver according to the invention is designed to compensate for switching losses of at least one power module and comprises a memory unit, at least one temperature sensor, and a processing unit. The processing unit is configured to determine the node temperatures of at least two SiC MOSFET chips using the temperature sensor. Based on the node temperatures, the processing unit can access at least one parameter from each of two parameter groups in the memory unit to calculate a switching profile. A first parameter group comprises temperature-dependent, predefined drain-source resistances, and a second parameter group comprises temperature-dependent, predefined gate charges. The processing unit is further configured to determine a gate current profile for a turn-on or turn-off process and to set a gate current to generate the signals corresponding to the gate current profile.The storage unit is designed to provide at least two temperature-dependent predefined parameter groups from the at least two SiC MOSFET chips as a basis for determining the gate current profile.
[0016] The gate current profile can be algorithmically adjusted to account for the various operating points and their dependence on the static parameters of the SiC MOSFET chips at these operating points. Regardless of the different parameters of the SiC MOSFET chips, the switching energies at each operating point can be balanced, thus increasing the reliability of the SiC MOSFET chips. Due to the different characteristics of the chips, more space per microchip would have been required on the circuit board without compensating for switching losses. It is also preferable to provide additional parameter groups for a more precise determination of the gate current profile, which can be accessed by a processing unit. A parameter group with equivalent switch capacitances is advantageous in this respect.
[0017] Furthermore, it is advantageous to have a gate current profile for a number n of interconnected SiC MOSFET chips, both for the turn-on process and for R.412786
[0018] - 4 -
[0019] The shutdown process is created using a processing unit. Furthermore, multiple power modules can be connected in an inverter via a logic switch in a half-bridge circuit. The SiC MOSFET chips are arranged in a common-gate configuration. The processing unit can be configured to incorporate the logic switch of the half-bridge circuit into a gate current profile, similar to a microchip, for more precise compensation of switching losses.
[0020] The dependent claims describe preferred embodiments of the invention.
[0021] Preferably, the processing unit is configured to determine, during a switch-on process, a first section of the gate current profile for each of the two SiC MOSFET chips from a quotient of the initial gate charge of the respective SiC MOSFET chip and a first time interval, to set a first gate current according to the first section of the gate current profile, and to define the first time interval from the first point in time when a gate-source voltage begins charging from a level of a gate-source voltage in the off-state of a gate, until a second point in time when the gate-source voltage reaches a turn-on threshold voltage, in order to better account for the conditions of the gate driver after the initiation of the switch-on process. The first time interval should be set to the smallest possible value or a minimum to reduce the dead time between a turn-off process and a turn-on process.In the off state of a gate, the gate-source voltage is preferably 0 volts. The first time interval, as well as all subsequent time intervals, are of the same length for the at least two SiC MOSFET chips and are constant due to their predefined nature.
[0022] The processing unit is preferably configured to determine, for the switch-on process of the switch, a second section of the gate current profile for each of the two SiC MOSFET chips from a quotient of a second gate charge of the respective SiC MOSFET chip and a second time interval. Furthermore, the processing unit is preferably configured to set a second gate current according to the second section of the gate current profile and to determine the second time interval from a second point in time at which the gate-source R.412786
[0023] -5 -
[0024] The second time interval is set to define a threshold voltage, from when the voltage reaches a turn-on threshold voltage until a third time point, at which a drain-source current from one of the SiC MOSFET chips first reaches a turn-on drain-source current. This allows the gate driver's characteristics after the first time interval have elapsed to be better taken into account. The second time interval is specifically set to minimize overall switching losses and ensure that the gate currents reach their target values as determined in the first interval.
[0025] Furthermore, the processing unit is preferably configured to determine a third section of the gate current profile for each of the two SiC MOSFET chips for the switch-on process. This third section is derived from the quotient of a third gate charge of the respective SiC MOSFET chip and a third time interval. The processing unit is also configured to set a third gate current corresponding to the third section of the gate current profile and to define the third time interval from the third time point at which a drain-source current from one of the SiC MOSFET chips first reaches a switch-on drain-source current, until a fourth time point at which the gate-source voltage reaches a switch-on start plateau voltage. This allows the conditions of the gate driver after completion of the second time interval to be better taken into account.The third time interval can be set for optimal reduction of switching losses based on the MOSFET's body diode characteristic for a given phase current. To determine the gate charge for the third section, the first gate charge can first be subtracted from the second gate charge and then multiplied by a factor. This factor represents the slope adjustment of the drain-source current in the reverse recovery region. This current arises due to reverse recovery peak currents on the body diode on the passive side and must therefore be taken into account. The product can then be divided by the second time interval and subsequently multiplied by the third time interval to obtain the third gate charge. All of these steps can be performed by the processing unit.
[0026] The computing unit is preferably designed to provide a fourth section of the gate current profile for each of the R.412786 for the switching process of the switch.
[0027] - 6 -
[0028] The gate current of both SiC MOSFET chips is determined from a quotient of a fourth gate charge of the respective SiC MOSFET chip and a fourth time interval. The processing unit is also preferably configured to set a fourth gate current according to the fourth section of the gate current profile and to define the fourth time interval from the fourth time point at which the gate-source voltage reaches a turn-on start plateau voltage to the fifth time point at which the gate-source voltage reaches a turn-on end plateau voltage. This allows the conditions of the gate driver after completion of the third time interval to be better taken into account. The fourth time interval can be reduced to a minimum by means of the gate current to minimize losses during the turn-on process. This time interval can be determined by the desired voltage slope during voltage commutation.
[0029] Preferably, the processing unit is configured to determine, for the switch-on process of the switch, a fifth section of the gate current profile for each of the two SiC MOSFET chips from a quotient of a fifth gate charge of the respective SiC MOSFET chip and a fifth time interval. The processing unit is also configured to set a fifth gate current corresponding to the fifth section of the gate current profile and to define the fifth time interval from a fifth time point at which the gate-source voltage reaches a turn-on end-plateau voltage, to a sixth time point at which the gate-source voltage reaches a turn-on voltage, also called the end-gate-source voltage. The turn-on voltage is, in particular, a voltage at which complete switching has occurred. This allows the conditions of the gate driver after completion of the fourth time interval to be better taken into account.
[0030] Furthermore, the computing unit is preferably configured to determine, for the switch-off process of the switch, a sixth section of the gate current profile for each of the two SiC MOSFET chips from a quotient of a sixth gate charge of the respective SiC MOSFET chip and a sixth time interval. In addition, the computing unit is preferably configured to set a sixth gate current corresponding to the sixth section of the gate current profile and to determine the sixth time interval from a seventh point in time at which the gate-source voltage changes from the R.412786
[0031] - 7 -
[0032] The turn-on voltage begins to discharge until an eighth point in time, at which a gate-source voltage reaches a turn-off start plateau voltage. This allows the characteristics of the gate driver after the fifth time interval has elapsed to be better taken into account.
[0033] Furthermore, the processing unit is preferably configured to determine, for the switch-off process of the switch, a seventh section of the gate current profile for each of the two SiC MOSFET chips from a quotient of a seventh gate charge of the respective SiC MOSFET chip and a seventh time interval. The processing unit is also preferably configured to set a seventh gate current corresponding to the seventh section of the gate current profile and to define the seventh time interval from an eighth time point at which a gate-source voltage reaches a turn-off start plateau voltage, to a ninth time point at which a gate-source voltage reaches a turn-off end plateau voltage. This allows the conditions of the gate driver after the initiation of the turn-off process to be better taken into account.
[0034] Additionally, the processing unit is preferably configured to determine, for the switch-off process of the switch, an eighth section of the gate current profile for each of the two SiC MOSFET chips from a quotient of an eighth gate charge of the respective SiC MOSFET chip and an eighth time interval. The processing unit is also preferably configured to set an eighth gate current corresponding to the eighth section of the gate current profile and to define the eighth time interval from a ninth time point at which a gate-source voltage reaches a turn-off end plateau voltage, to a tenth time point at which a gate-source voltage reaches a turn-off threshold voltage. This allows the conditions of the gate driver after completion of the seventh time interval to be better taken into account.To determine the eighth gate charge, a product of the second gate charge and a percentage determined by the proportion of the drain-source current that charges an equivalent output capacitance of the respective SiC MOSFET chip can be subtracted from the second gate charge. The eighth gate charge thus determined is the gate charge required to drive a switching current determined by the difference between the respective drain-source current and the product of the corresponding drain-source current and a percentage (R.412786).
[0035] - 8 -
[0036] to commutate the drain-source current, which charges an equivalent output capacitance of the respective SiC MOSFET chip, to a value of 0A.
[0037] The processing unit is preferably configured to determine a ninth section of the gate current profile for each of the two SiC MOSFET chips for the switch-off process. This determination is based on the quotient of a ninth gate charge of the respective SiC MOSFET chip and a ninth time interval. The processing unit is also preferably configured to set a ninth gate current corresponding to the ninth section of the gate current profile and to define the ninth time interval from the tenth time point at which a gate-source voltage reaches a turn-off threshold voltage, to the eleventh time point at which a gate-source voltage reaches a level corresponding to the gate-source voltage in the off-state of a gate. This allows the conditions of the gate driver after the eighth time interval has elapsed to be better taken into account.The ninth time interval can be minimized by maximizing the gate current of the slower SiC MOSFET chip and reducing the gate current of the faster SiC MOSFET chip. This ensures that both the faster and slower microchips reach the gate-source voltage simultaneously when a gate is off. This lower value can be determined by the processing unit. The faster microchip during the turn-off process is the one that exhibits the lower gate-source voltage after the preceding time interval has elapsed.
[0038] The processing unit is preferably further configured to determine the drain-source current of a first SiC MOSFET chip as the product of a phase current and the quotient of the first drain-source resistance of the first SiC MOSFET chip and the sum of the first drain-source resistance of the first SiC MOSFET chip and the second drain-source resistance of a second SiC MOSFET chip. The second, seventh, and eighth time intervals can also be determined using the drain-source current. To determine the second time interval using the drain-source current, a quotient of the drain-source current and a desired time derivative of the drain-source current is calculated. The quotient with the smallest absolute value determines the length of the R.412786.
[0039] - 9 -
[0040] The second time interval. This allows the overall switching losses to be reduced while simultaneously achieving the current values from the first part of the turn-on process. To determine the seventh time interval using the drain-source current, a product of the drain-source current itself and a percentage determined by the drain-source current that charges an equivalent output capacitance of the respective SiC MOSFET chip is subtracted from the respective drain-source current. The result of the subtraction is then divided by the aforementioned equivalent output capacitance. By determining the quotient of the DC link voltage and the result of the preceding calculation, the seventh time interval can now be determined.To determine the eighth time interval using the drain-source current, a product of the drain-source current itself and a percentage determined by the drain-source current that charges an equivalent output capacitance of the respective SiC MOSFET chip is subtracted from the respective drain-source current. The result of this subtraction is then divided by a desired time derivative of the respective drain-source current. The eighth time interval can be determined by the result of this division.
[0041] Analogous to the gate current profile, profiles can also be created for a gate voltage, a drain-source voltage, instantaneous power, and the switching energy of a power module. For example, a slower microchip requires more switching energy during the current commutation phase of a turn-on process, but less switching energy during the voltage commutation phase. This relationship is reversed for a faster microchip compared to a slower microchip during a turn-on process. By compensating for the differences in the switching energies of both SiC MOSFET chips during the turn-on process, the total switching energy remains the same for both SiC MOSFET chips. The current commutation phase during the turn-on process can be defined temporally from the second to the fourth time point.The voltage commutation phase in the switch-on process can be defined temporally from the third point in time to the fourth point in time.
[0042] During the turn-off process, the equivalent capacitances can be balanced during the voltage commutation phase. R.412786
[0043] - 10 -
[0044] Furthermore, the drain-source currents during the current commutation phase of the turn-off process can also be balanced by matching the gate current profiles of a faster SiC MOSFET chip and a slower SiC MOSFET chip. This ensures the same active turn-off energy for both SiC MOSFET chips. The voltage commutation phase can be defined from the eighth to the ninth time point during the turn-off process. The current commutation phase can be defined from the ninth to the tenth time point during the turn-off process.
[0045] The invention further relates to a method comprising providing at least two temperature-dependent predefined parameter groups from the at least two SiC MOSFET chips as a basis for determining the gate current profile. The method according to the invention also includes determining the node temperatures of at least two SiC MOSFET chips using the temperature sensor. Based on the node temperatures, at least one parameter from two parameter groups in the storage unit is accessed to calculate a gate current profile using the processing unit, wherein a first parameter group comprises temperature-dependent predefined drain-source resistances and a second parameter group comprises temperature-dependent predefined gate charges.
[0046] Subsequently, a gate current profile for a switch-on or switch-off process is determined using the processing unit, and the gate current is set to realize the signals corresponding to the gate current profile.
[0047] Brief description of the drawings
[0048] Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawings. The drawing shows:
[0049] Figure 1 shows a block diagram of a circuit arrangement.
[0050] Figure 2 shows a gate current profile of a switch-on process, and
[0051] Figure 3 shows a gate current profile of a shutdown process.
[0052] Embodiments of the invention R.412786
[0053] - 11 -
[0054] Preferably, all identical components, elements and / or units in all figures are provided with the same reference numerals.
[0055] Figure 1 shows a gate driver 1 configured to compensate for switching losses of at least one power module 2 and comprising a memory unit 3, at least one temperature sensor 4, and a processing unit 5. The processing unit 5 is configured to determine node temperatures of at least two SiC MOSFET chips 6, 7 using the temperature sensor 4, and, based on these node temperatures, to access at least one parameter from each of two parameter groups in the memory unit 3 to calculate a gate current profile 8 (see Figures 2 and 3), wherein a first parameter group comprises temperature-dependent predefined drain-source resistances and a second parameter group comprises temperature-dependent predefined gate charges. The gate current profile 8 is then used for a turn-on process 9 (see Figure 2) or a turn-off process 15 (see Figure 3).3) to determine and set a gate current to realize the signals corresponding to the gate current profile 8, wherein the memory unit 3 is configured to provide at least two temperature-dependent predefined parameter groups from the at least two SiC MOSFET chips 6, 7 as a basis for determining the gate current profile 8. In this case, a drain-source current of a first SiC MOSFET chip 6 is determined by means of the processing unit 5 as a product of a phase current and a quotient of a first drain-source resistance of a first SiC MOSFET chip 6 and a sum of a first drain-source resistance of the first SiC MOSFET chip 6 and the second drain-source resistance of a second SiC MOSFET chip 7.
[0056] Figure 2 shows a gate current profile 8 with a gate current IG of a switch-on process 9 and associated gate voltages VGS. The respective microchip 6, 7 is switched from a switch-off voltage VGS, OFF TO a switch-on voltage VGS, ON.
[0057] For example, the first microchip 6 switches faster than the second microchip 7. The chip current IDS, or drain-source current, flowing through the first microchip 6 in steady-state operation is therefore calculated as follows:
[0058] , > ( ^DS, ON, slow \,
[0059] IDS, almost I in I * Iphase
[0060]
[0061] \ K DS, ON, slow " I" K DS, ON,fast / R.412786
[0062] - 12 -
[0063] Here, RDS, ON, almost is the drain-source resistance of the first SiC MOSFET chip 6, RDS, ON, slow is the drain-source resistance of the second SiC MOSFET chip 7, and Iphase is the phase current. Similarly, the chip current IDS, slow, flowing through the second microchip 7 is calculated as follows:
[0064] r > ( ^DS, ON, fast \ f
[0065] WS, slow I 77 | n I * Iphase
[0066]
[0067] \ K DS, ON, slow " I" K DS, ON, almost J
[0068] For a switch-on operation 9 of a switch, the processing unit 5 determines a first section 10 of the gate current profile 8 for each of the two SiC MOSFET chips from a quotient of a first gate charge of the respective SiC MOSFET chip 6, 7 and a first time interval. Furthermore, the processing unit 5 sets a first gate current according to the first section 10 of the gate current profile 8 and defines the first time interval from a first time point t0 of the start of charging of a gate-source voltage from a level of a gate-source voltage in the off-state of a gate, i.e., the turn-off voltage VGS OFF, until a second time point h at which the gate-source voltage VGS reaches a turn-on threshold voltage Vth.
[0069] The first time point tO is therefore a time point when VGS begins to diverge from VGS.OFF. The gate current IG,ON, of the first SiC MOSFET chip 6 and the gate current IG,ON, SThe IOW of the second SiC MOSFET chip 7 are therefore determined for the first time interval as follows:
[0070] . _ QGS, V fast
[0071] 'G, ON, almost 7 7
[0072] H C 0
[0073] I _ QGS, V slow
[0074] 'G, ON, slow 7 7
[0075]
[0076] H C 0
[0077] Here, Qcs.vth is the gate charge upon reaching the turn-on threshold voltage Vth, for the first microchip 6 (with the suffix "fast") and the second microchip (with the suffix "slow"). The first time interval is chosen to be as small as possible in order to minimize dead times between turn-off processes 9 and turn-on processes 15.
[0078] Furthermore, the computing unit 5 determines a second section 11 of the gate current profile 8 for each of the two R.412786 for the switching-on process 9 of the switch.
[0079] - 13 -
[0080] SiC MOSFET chips 6, 7 are determined by a quotient of a second gate charge of the respective SiC MOSFET chip and a second time interval. The processing unit 5 sets a second gate current according to the second section 11 of the gate current profile 8 and sets the second time interval from the second time h to a third time t2, at which a drain-source current IDS from one of the SiC MOSFET chips first reaches a turn-on drain-source current that corresponds to the chip current I determined above. DS ,almost or I DS ,slow corresponds to fixed. The gate current IG, ON, fast of the first SiC MOSFET chip 6 and the gate current IG, ON, slow of the second SiC MOSFET chip 7 are therefore determined for the second time interval as follows:
[0081] - ® GS 'go, almost
[0082] 'G, ON, fast
[0083] l 2
[0084] . _ QGS, I DS slow
[0085] 'G, ON, slow 7 7
[0086]
[0087] l 2
[0088] The second time interval is specifically chosen to optimize the total switching losses on one side and to allow the chip currents to reach the current values defined in step 1. Specifically, the second time interval is the smaller one from Atf. ast and Atsiow, where:
[0089] IDS, almost
[0090] ^Ifast
[0091] desired (^ON, fast^
[0092] IDS, slow
[0093] Zislow
[0094] desired (-^ON,slow)
[0095]
[0096] Furthermore, for the switch-on process 9 of the switch, the processing unit 5 determines a third section 12 of the gate current profile 8 for each of the two SiC MOSFET chips 6, 7 from a quotient of a third gate charge of the respective SiC MOSFET chip and a third time interval. The processing unit 5 sets a third gate current according to the third section 12 of the gate current profile 8 and applies a switch-on start plateau voltage Vp to the gate-source voltage VGS for the third time interval from the third time t2 to a fourth time ts. st The gate current IG, ON, of the first SiC MOSFET chip 6 and the gate current IG, ON, SIOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows: R.412786
[0097] - 14 -
[0098] ^GS, IQS, max, almost
[0099] 'G, ON, fast ~L ~L
[0100] l 3 l 2
[0101] . _ QGS, IDS, slow
[0102] 'G, ON, slow 7 7
[0103]
[0104] l 3 l 2
[0105] This includes:
[0106] Q GS, IDS, max, fast ^fast (^3 ^2)
[0107] Sfast (QGS, IDS, fast th, fast)'
[0108] ™fast 7 7
[0109] l 2
[0110] QGS, IDS, max, slow ^'Slow (^3 ^2)
[0111] Sslow (. QGS, IDS, slow Q GS, V th, slow)
[0112] m s iow 7 7
[0113]
[0114] l 2
[0115] Sfast represents the slope adjustment of the drain-source current for the first microchip 6 to control the maximum drain-source current of the first SiC MOSFET chip 6 that occurs due to the reverse recovery peak current of the diode on the passive side.
[0116] Ssiow represents the slope adjustment of the drain-source current for the second microchip 7 to control the maximum drain-source current of the second SiC MOSFET chip 7 that occurs due to the reverse recovery peak current of the diode on the passive side.
[0117] The third time interval is selected specifically based on the body diode behavior of the MOSFETs, i.e., the first SiC MOSFET chip 6 and the second SiC MOSFET chip 7, for a given phase current.
[0118] For the switch-on process 9 of the switch, the processing unit 5 determines a fourth section 13 of the gate current profile 8 for each of the two SiC MOSFET chips 6, 7 from a quotient of a fourth gate charge of the respective SiC MOSFET chip (6, 7) and a fourth time interval. The processing unit 5 sets a fourth gate current according to the fourth section 13 of the gate current profile 8 and sets the fourth time interval from the fourth time ta to a fifth time t4, at which the gate-source voltage VGS reaches a switch-on end plateau voltage Vp. en d reached, fixed. The gate current IG, ON, almost of the first SiC MOSFET chip 6 and the gate current IG, ON, SIOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows: R.412786
[0119] - 15 -
[0120] QcD, almost
[0121] 'G, ON, fast “7 7
[0122] c 4 C3
[0123] . _ QGD, SIOW
[0124] G, ON, slow ~ 7
[0125] c 4 C3
[0126] QGD is the charge of the gate-drain capacity.
[0127] The fourth time interval can be derived, in particular, from the desired voltage rise during voltage commutation. This time interval should be kept to a minimum to reduce overall turn-on losses.
[0128] Finally, for the switch-on process 9 of the switch, the processing unit 5 determines a fifth section 14 of the gate current profile for each of the two SiC MOSFET chips 6, 7 from a quotient of a fifth gate charge of the respective SiC MOSFET chip and a fifth time interval. The processing unit 5 sets a fifth gate current according to the fifth section 14 of the gate current profile 8 and defines the fifth time interval from the fifth time point until a sixth time point ts, at which the gate-source voltage VGS reaches the turn-on voltage VGS.ON. The gate current IG,ON,almost of the first SiC MOSFET chip 6 and the gate current IG,ON,SIOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows:
[0129] Qdrive, almost
[0130] 'G, ON, almost 7 7
[0131] c 5 — C4
[0132] . _ Qdrive,slow
[0133] 1G, ON, slow 7 7
[0134]
[0135] c 5 — C4
[0136] Here, Qdrive is the charge that gate driver 1 must provide for the gate transition. The fifth time interval is preferably set to the minimum value to quickly bring the MOSFETs, i.e., the SiC MOSFET chips 6 and 7, to VGS.ON and thus reduce conduction losses. This can be achieved, for example, by adjusting the gate currents of SiC MOSFET chips 6 and 7 so that the gate voltages of both the faster first SiC MOSFET chip 6 and the slower second SiC MOSFET chip 7 reach VGS.ON simultaneously. R.412786
[0137] - 16 -
[0138] Figure 3 shows a gate current profile 8 with a gate current IG of a turn-off process 15 and associated gate voltages VGS. The respective microchip 6, 7 is switched from a turn-on voltage VGS, ON to a turn-off voltage VGS, OFF. Again, it is provided, for example, that the first microchip 6 switches faster than the second microchip 7.
[0139] For the switch-off process 15 of the switch, the processing unit 5 determines a sixth section 16 of the gate current profile for each of the two SiC MOSFET chips from a quotient of a sixth gate charge of the respective SiC MOSFET chip and a sixth time interval. The processing unit 5 sets a sixth gate current according to the sixth section 16 of the gate current profile 8 and sets the sixth time interval from a seventh time te, at which the gate-source voltage VGS begins to discharge from the turn-on voltage VGS,ON, to an eighth time tz, at which a gate-source voltage reaches a turn-off start plateau voltage Vp, st Art reached, fixed. The gate current IG, OFF, almost of the first SiC MOSFET chip 6 and the gate current IG, OFF, S The IOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows:
[0140] Qdrive, almost
[0141] 'G, OFF, almost 7 7
[0142] l 7 l 6
[0143] . _ Qdrive,slow
[0144] ^G, OFF, slow 7 7
[0145]
[0146] l 7 l 6
[0147] Furthermore, for the switch-off process 15 of the switch, the processing unit 5 determines a seventh section 17 of the gate current profile for each of the two SiC MOSFET chips from a quotient of a seventh gate charge of the respective SiC MOSFET chip and a seventh time interval. The processing unit 5 sets a seventh gate current according to the seventh section 17 of the gate current profile 8 and sets the seventh time interval from the eighth time t? to a ninth time ts, at which a gate-source voltage VGS reaches a turn-off end plateau voltage Vp. end reached, fixed. The gate current IG, OFF, almost of the first SiC MOSFET chip 6 and the gate current IG, OFF, SIOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows:
[0148] QcD, almost
[0149] 'G, ON, fast “
[0150] c 7 7
[0151] 7 C8R.412786
[0152] - 17 -
[0153] . _ QGD, slow
[0154] G, ON, slow ~ 7
[0155] l 7 l 8
[0156] The optimized seventh time interval has the following length:
[0157] dv I D s,fast * (l - f.fast)
[0158] —, almost = - - -
[0159]
[0160] dt Coss, eq fast
[0161] This is almost the percentage of the chip current that almost charges the equivalent output capacity Coss, eq.
[0162] Alternatively, the optimal length of the seventh time interval can be calculated as follows:
[0163] _ _ Vpc
[0164] I7 8 dv,
[0165] dt' slow
[0166] dv _ Ips,slow * (1 ~ Ä SIOW)
[0167] —,slow
[0168]
[0169] dt Coss, eq stow
[0170] Here, f,slow is the percentage of the chip current that charges the equivalent output capacity Coss, eq slow.
[0171] By adjusting the respective gate current profiles 8 for the SiC MOSFET chips 6, 7, it is possible to achieve the same charging current for the equivalent capacitance Coss, eq of the faster first microchip 6 and the slower second microchip, such that the following applies:
[0172] I DS ,fast * (1 - f,fast) = I DS ,slow * (1 - f,slow)
[0173] In this case, the processing unit 5 determines an eighth section 18 of the gate current profile 8 for each of the two SiC MOSFET chips for the switch-off process 15, based on a quotient of an eighth gate charge of the respective SiC MOSFET chip and an eighth time interval. The processing unit 5 sets an eighth gate current according to the eighth section 18 of the gate current profile 8 and inserts the eighth time interval from the ninth time ts to a tenth time tg, at which a gate-source voltage VGSR.412786
[0174] - 18 -
[0175] A turn-off threshold voltage Vth is reached. The gate current IG, OFF, almost of the first SiC MOSFET chip 6 and the gate current IG, OFF, SIOW of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows:
[0176] _ Q GS,I DS,fast (1 - f,fast)
[0177] I_G, OFF, fast =
[0178] t_9 - t_8
[0179] _ QGS,I DS,slow (1 - f,slow)
[0180] I_G, OFF, slow =
[0181]
[0182] C9 IQ
[0183] Q is involved GS,I DS,fast (1 - f,fast) the gate charge used to commutate the switching current of (1 - f,fast) * I DS,fast 0 amps are required for the first microchip 6. Q GS,I DS,slow (1 - f,slow) is the gate charge used to commutate the switching current of (1 - f,slow) * I DS,slow 0 amps are needed for the second microchip 7.
[0184] The eighth time interval is preferably optimized as follows, if the desired current gradients are known, in order to keep the overvoltage smaller than the breakdown voltage of the SiC MOSFET chips 6, 7.
[0185] IDS, fast * (1 - f, fast)
[0186] ~ fdi \
[0187] desired \^OFF,fastj
[0188] t_9 - t_8 = I DS,slow * (1 - f,slow)
[0189] desired (di / dt OFF, slow)
[0190]
[0191] In the present embodiment, the processing unit 5 determines a ninth section 19 of the gate current profile 8 for each of the two SiC MOSFET chips for the switch-off process 15 from a quotient of a ninth gate charge of the respective SiC MOSFET chip and a ninth time interval. The processing unit 5 sets a ninth gate current according to the ninth section 19 of the gate current profile 8 and defines the ninth time interval from the tenth time t9 until an eleventh time t10, at which a gate-source voltage reaches a level of a gate-source voltage in the off-state of a gate, i.e., the level of the turn-off voltage VGS.OFF. The gate current IG,OFF,fast of the first SiC MOSFET chip 6 and the gate current IG,OFF,slow of the second SiC MOSFET chip 7 are therefore determined for the third time interval as follows: R.412786
[0192] - 19 - - GS th, fast
[0193] 'G, OFF, almost ~L ~L
[0194] HO C 9
[0195] j _ QGS, V th, slow
[0196] 'G, OFF, slow 7 7
[0197] HO C 9
[0198] Here, Qcs.vth is the gate charge upon reaching the turn-on threshold voltage Vth, for the first microchip 6 (with the suffix "fast") and the second microchip (with the suffix "slow"). The first time interval is chosen to be as small as possible in order to minimize dead times between turn-off processes 9 and turn-on processes 15.
[0199] The ninth time interval is preferably set to the minimum value to reduce the dead time. This can be achieved, for example, by setting the gate current of the slower second SiC MOSFET chip 7 to the maximum rated power of the gate driver 1 and the gate current of the faster first SiC MOSFET chip 6 to a lower value, so that both SiC MOSFET chips 6 and 7 reach the turn-off voltage VGS.OFF at the same time.
Claims
R.412786 - 20 - Claims 1. Gate driver (1) configured to compensate for switching losses of at least one power module (2) comprising: a storage unit (3), at least one temperature sensor (4) and a computing unit (5) the computing unit (5) is configured to determine node temperatures of at least two SiC MOSFET chips (6, 7) using the temperature sensor (4), to access at least one parameter from each of two parameter groups from the memory unit (3) on the basis of the node temperatures to calculate a gate current profile (8), wherein a first parameter group comprises temperature-dependent predefined drain-source resistances and a second parameter group comprises temperature-dependent predefined gate charges, to determine a gate current profile (8) for a switch-on process (9) or a switch-off process (15) and to set a gate current to realize the signals corresponding to the gate current profile (8), wherein the storage unit (3) is configured to provide at least two temperature-dependent predefined parameter groups from the at least two SiC MOSFET chips (6, 7) as a basis for determining the gate current profile (8).
2. Gate driver (1) according to claim 1, wherein the computing unit (5) determines, for a switch-on operation (9) of a switch, a first section (10) of the gate current profile (8) for each of the two SiC MOSFET chips (6, 7) from a quotient of a first gate charge of the respective SiC MOSFET chip (6, 7) and a first time interval, sets a first gate current according to the first section (10) of the gate current profile (8) and the first time interval from a first time of a start of charging of a gate-source voltage from a level of a gate-source voltage in the off state of a gate, up to a second - 21 - Determines the point in time at which the gate-source voltage reaches a switching-on threshold voltage.
3. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the switch-on process (9) of the switch determines a second section (11) of the gate current profile (8) for each of the two SiC MOSFET chips (6, 7) from a quotient of a second gate charge of the respective SiC MOSFET chip (6, 7) and a second time interval, sets a second gate current according to the second section (11) of the gate current profile (8) and defines the second time interval from a second time point at which the gate-source voltage reaches a switch-on threshold voltage, to a third time point at which a drain-source current from one of the SiC MOSFET chips first reaches a switch-on drain-source current.
4. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the switch-on process (9) of the switch determines a third section (12) of the gate current profile (8) for each of the two SiC MOSFET chips (6, 7) from a quotient of a third gate charge of the respective SiC MOSFET chip (6, 7) and a third time interval, sets a third gate current according to the third section (12) of the gate current profile (8) and defines the third time interval from a third time point at which a drain-source current from one of the SiC MOSFET chips first reaches a switch-on drain-source current, to a fourth time point at which the gate-source voltage reaches a switch-on start plateau voltage.
5. Gate driver (1) according to a preceding claim, wherein the computing unit (5) for the switch-on process (9) of the switch determines a fourth section (13) of the gate current profile (8) for each of the two SiC MOSFET chips (6, 7) from a quotient of a fourth gate charge of the respective SiC MOSFET chip (6, 7) and a fourth time interval, sets a fourth gate current according to the fourth section (13) of the gate current profile (8) and the fourth time interval from a fourth time at which the gate-source voltage is a switch-on start-R.412786 - 22 - Plateau voltage is reached, up to a fifth time point at which the gate-source voltage reaches a turn-on end plateau voltage.
6. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the switch-on process (9) of the switch determines a fifth section (14) of the gate current profile for each of the two SiC MOSFET chips (6,7) from a quotient of a fifth gate charge of the respective SiC MOSFET chip (6,7) and a fifth time interval, sets a fifth gate current according to the fifth section (14) of the gate current profile (8) and defines the fifth time interval from a fifth time point at which the gate-source voltage reaches a switch-on end plateau voltage, to a sixth time point at which the gate-source voltage reaches a switch-on voltage.
7. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the turn-off process (15) of the switch determines a sixth section (16) of the gate current profile for each of the two SiC MOSFET chips (6,7) from a quotient of a sixth gate charge of the respective SiC MOSFET chip (6,7) and a sixth time interval, sets a sixth gate current according to the sixth section (16) of the gate current profile (8) and defines the sixth time interval from a seventh time at which the gate-source voltage begins to discharge from a turn-on voltage to an eighth time at which a gate-source voltage reaches a turn-off start plateau voltage.
8. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the turn-off process (15) of the switch determines a seventh section (17) of the gate current profile for each of the two SiC MOSFET chips (6, 7) from a quotient of a seventh gate charge of the respective SiC MOSFET chip (6, 7) and a seventh time interval, sets a seventh gate current according to the seventh section (17) of the gate current profile (8) and the seventh time interval from an eighth time point at which a gate-source voltage reaches a turn-off start plateau voltage, to a ninth time point at which an R.412786 - 23 - The gate-source voltage determines when a shutdown end plateau voltage is reached.
9. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the turn-off process (15) of the switch determines an eighth section (18) of the gate current profile for each of the two SiC MOSFET chips (6, 7) from a quotient of an eighth gate charge of the respective SiC MOSFET chip (6, 7) and an eighth time interval, sets an eighth gate current according to the eighth section (18) of the gate current profile (8) and defines the eighth time interval from a ninth time point at which a gate-source voltage reaches a turn-off end plateau voltage to a tenth time point at which a gate-source voltage reaches a turn-off limit voltage.
10. Gate driver (1) according to one of the preceding claims, wherein the computing unit (5) for the turn-off process (15) of the switch determines a ninth section (19) of the gate current profile for each of the two SiC MOSFET chips (6,7) from a quotient of a ninth gate charge of the respective SiC MOSFET chip (6,7) and a ninth time interval, sets a ninth gate current according to the ninth section (19) of the gate current profile (8) and defines the ninth time interval from a tenth time point at which a gate-source voltage reaches a turn-off threshold voltage to an eleventh time point at which a gate-source voltage reaches a level of a gate-source voltage in the off state of a gate.
11. Gate driver (1) according to one of the preceding claims, wherein a drain-source current of a first SiC MOSFET chip (6) is determined by means of a computing unit (5) as a product of a phase current and a quotient of a first drain-source resistance of a first SiC MOSFET chip (6) and a sum of a first drain-source resistance of the first SiC MOSFET chip (6) and the second drain-source resistance of a second SiC MOSFET chip (7).
12. Method for operating a gate driver (1) according to any one of claims 1 to 11 comprising the steps: R.412786 - 24 - Providing (100) at least two temperature-dependent predefined parameter groups from the at least two SiC MOSFET chips (6,7) as a basis for determining the gate current profile, Determining (200) node temperatures of at least two SiC MOSFET chips (6,7) using the temperature sensor (4), based on the node temperatures, Accessing (300) at least one parameter from two parameter groups from the storage unit (3) to calculate a gate current profile (8) using the computing unit (5), wherein a first parameter group includes temperature-dependent predefined drain-source resistances and a second parameter group includes temperature-dependent predefined gate charges, Determining (400) the gate current profile (8) for a switch-on operation (9) or a switch-off operation (15) using the computing unit (5) and setting (500) the gate current to realize the signals corresponding to the gate current profile (8).