A semiconductor device and a method of manufacturing thereof
Patent Information
- Application Number
- PCT/EP2026/055515
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-27
- Filing Date
- 2026-02-27
- Publication Date
- 2026-09-03
Smart Images
Figure EP2026055515_03092026_PF_FP_ABST
Abstract
Description
[0001] TITLE
[0002] A semiconductor device and a method of manufacturing thereof
[0003] TECHNICAL FIELD
[0004] The present disclosure relates to a semiconductor device in particular a trench MOSFET transistor device. This disclosure also relates to a method of manufacturing semiconductor devices, in particular trench MOSFET transistors.
[0005] BACKGROUND OF THE DISCLOSURE
[0006] Known in the prior art technique of reducing Rdson value of a MOSFET device is downscaling its dimensions. Density, scalability, and manufacturability are important considerations in metal-oxide-semiconductor field effect transistor (MOSFET) designs. As MOSFET device miniaturization proceeds, the lithography needed to produce small device features becomes difficult. However, the dimensions of silicone based MOSFET are near both physical and economic limits, as further miniaturization is not further a valid solution. New materials and device architecture are thus required in order to overcome these fundamental scaling obstacles that degrade device performance. A well-known approach to overcome these effects is to increase the drive current of MOSFETs by increasing the mobility of the carriers in the channel.
[0007] A known approach includes forming an embedded SiGe element in the transistor source / drain region. This process includes forming a recess in the source and drain regions and then filling the recess with a second material, having a lattice constant different from the first semiconductor material. For example, the first semiconductor material may be silicon, and the second material may be SiGe. Many problems relate to recess formation and subsequently epitaxial growth of the embedded SiGe element. One problem includes controlling the recess depth. Another problem includes maintaining the silicon surface quality during recess formation. The quality of the epitaxially grown SiGe element is highly dependent upon Si surfacequality. Problems with recess depth and surface damage significantly affect the device short channel effects, Rdson and leakage characteristics.
[0008] Accordingly, it is a goal of the present disclosure to provide an improved semiconductor device of trench power MOSFET device having reduced Rdson, without SiGe embedded into the structure.
[0009] SUMMARY OF THE DISCLOSURE
[0010] According to a first example, a semiconductor device, particularly a silicone based MOSFET device, is proposed, having a top side and a bottom side and an epitaxial layer extending from the bottom side of the semiconductor device towards the top side. A body region extends from the epitaxial layer towards the top side wherein a mesa region is on the top side. The semiconductor device according to the example has at least one trench. The trench is an opening extending from the top side towards the bottom side forming a well-shape structure. The trench extends vertically through the epitaxial layer and also through the body region. A layer of polysilicon is deposited in the trench. The trench walls and the bottom region are covered in oxide layer providing isolation of the polysilicon from the epitaxial layer of the body region. The polysilicon is at least partially filled with oxide. In another example of the disclosure the oxide is located in the bottom region, in the lower portion of the trench.
[0011] In another example of the disclosure the bottom region of the polysilicon has a form of a stepper cone tapering towards the bottom side resulting in wider drift, resulting further lowering the Rdson value.
[0012] In another example of the disclosure an additional polysilicon layer is deposited in the trench, located above the polysilicon. This results in providing the whole drift region with maximum amount and lowering Rdson value.
[0013] According to another example, a method of manufacturing of the semiconductor device is disclosed. The method comprises the steps of providing an epitaxial layer structure with the trench. The trench is an opening extending from the top side towards the bottom side in a vertical direction. On the top side a top mesa surface is located. A further step comprises the forming of an oxide layer on the trench walls and the trench bottom region and on the top mesa surface. The following step comprises forming a polysilicon liner layer on the oxide layer on the trench wallsobtaining a well-shaped, recessed structure with the polysilicon liner layer covering the trench bottom region and the top mesa surface. The next step comprises deposition of a masking material on the polysilicon liner layer. The masking material functions as a photo resistive coating material or sacrificial layer. In further step the masking material is etched to the top mesa surface and further the polysilicon liner layer is partially etched to expose part of the trench walls covered with the oxide layer. Then in a subsequent step, the masking material is removed. Then the oxide layer is filled into the trench bottom region (at least) through wet oxidation (advantageous under 850 °C) or deposition with or without partial wet oxidation, which also covers the polysilicon layer from top.
[0014] A next step comprises wet etching the oxide layer to reduce the liner oxide thickness and dry etching the oxide layer to expose part of the polysilicon liner layer. The following steps comprise the deposition of the polysilicon to fill the trench, followed by CMP and etching back to form IPO (interpoly oxide) and gate. The last step comprises the formulation of the oxide layer into the trench bottom region and filling it to form IPO (inter-poly oxide) and covering the polysilicon layer in the bottom.
[0015] According to another example, a second method of manufacturing of the semiconductor device is disclosed. The method comprises the step of providing an epitaxial layer with the trench shaped as an opening extending from the top side towards the bottom side in a vertical direction. On the top side of the epitaxial layer there is a top mesa surface. A further step comprises the formation of an oxide layer on the trench walls and the trench bottom region and on the top mesa surface and with a deposited layer of the polysilicon on the oxide layer. The polysilicon fills the trench and covers the top mesa surface. A further step comprises partially etching the polysilicon for exposure to a part of the trench walls covered with the oxide layer followed by depositing of a nitride layer on the exposed part of the trench walls covered with the oxide layer. The next step is to perform anisotropic dry etching of the nitride layer to make a nitride spacer on the trench wall. The next step comprises dry etching the polysilicon layer and removing the nitride spacer to obtain a well-shaped structure. In another example of the disclosure an additional process of anisotropic dry etch of a nitride spacer is used. A following step requires filling the oxide layer into the trench bottom region through wet oxidation (advantageous under 850 °C) or depositing with / without partial wet oxidation, which also covers the polysilicon layer from top. Anext step comprises wet etching the oxide layer to reduce the liner oxide thickness and dry etching the oxide layer to expose part of the polysilicon liner layer. The following steps comprise deposition of the polysilicon to fill the trench, followed by CMP and etch back to form IPO (interpoly oxide) and gate. The last step comprises the forming of the oxide layer at into the trench bottom region and filling it to form IPO (inter-poly oxide) and covering the polysilicon layer in the bottom.
[0016] BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The disclosure will now be discussed with reference to the drawings which show in:
[0018] Figure 1 shows the cross section of the semiconductor device having the polysilicon at least partially filled with the oxide layer forming the oxide layer area surrounded by the polysilicon (liner oxide) in the form of a stepped cone.
[0019] Figure 2 shows the cross section of the semiconductor device with the double stepper cone.
[0020] Figure 3 shows the cross section of the RSO trench MOSFET device before ILD (interlayer dielectric) layer deposition.
[0021] Figures 4a-4j show the steps of the first example of the method of manufacturing the semiconductor device.
[0022] Figures 5a-5i show the steps of the second example of the method of manufacturing the semiconductor device.
[0023] Figure 6 shows the cross section of the final device structure cross section includes metal contact through ILD and Silicon with ILD (interlayer dielectric) layer.
[0024] DETAILED DESCRIPTION OF THE DISCLOSURE
[0025] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.
[0026] Figure 1 depicts a semiconductor device in particularly an oxide filled multiple stepped RSO (Resurf Stepped Oxide) trench MOSFET structure having a topside 4 and a bottom side 5 comprises an epitaxial layer (EPI) extending from the bottom side 5 of the semiconductor device 1 towards the top side 4 having a top mesa surface 9 on the top side 4. The semiconductor device 1 further comprises a body region 12 extending from the epitaxial layer (EPI) towards the top side 4 and a trench 3 in a form of an opening extending from the top side 4 towards the bottom side 5 in a vertical direction through the epitaxial layer (EPI) and through the body region 12. Further the semiconductor device 1 comprises a polysilicon 10 located in the trench 3 and an oxide layer 6 on the trench 3 walls and trench 3 bottom region 13 isolating the polysilicon 10 from the epitaxial layer and / or the body region 12. The semiconductor device 1 in this example has the polysilicon 10 at least partially filled with the oxide layer 6 forming the oxide layer 6 area surrounded by the polysilicon 10 (liner oxide) in the form of a stepped cone 2. The semiconductor device 1 according to this example has reduced Rdson having oxide filled multiple stepped RSO trench.
[0027] In another example the semiconductor device 1 has the polysilicon 10 partially filled with oxide in the bottom region 13 and located in the lower portion of the trench 3 forming a protrusion extending to the bottom region 13 of the trench 3. The protrusion forms the stepper cone 2. In this example the stepper cone 2 forms a double stepper cone (Fig. 2). The stepper cone 2 (in a cross-section view) tapers towards the bottom side 5 (Fig. 2). Stepper polysilicon 10 protrusion further lowers the Rdson.
[0028] In another example of the disclosure the semiconductor device 1 has an additional polysilicon 14 layer located in the trench 3 and above the polysilicon 10. The additional polysilicon 14 layer is a gate poly layer wherein the polysilicon 10 layer is a source poly of trench MOSFET device. In this example a terminal 22 is located on the top mesa surface 9 (Fig. 3).
[0029] This disclosure also includes a first example of a method of manufacturing the semiconductor device, in particular an oxide filled multiple stepped RSO (Resurf Stepped Oxide) trench MOSFET structure having a top side 4 and a bottom side 5 and an epitaxial layer EPI extending from the bottom side 5 of the semiconductor device 1 towards the top side 4. Top mesa surface 9 is located on the top side 4. The semiconductor device 1 comprises a body region 12 extending from the epitaxial layer EPI towards the top side 4 and a trench 3 in a form of an opening extending from the top side 4 towards the bottom side 5 in a vertical direction through the epitaxial layer EPI and through the body region 12. Further the semiconductor device 1 also comprises a polysilicon 10 located in the trench 3and an oxide layer 6 on the trench 3 walls and the trench 3 bottom region 13 isolating the polysilicon 10 from the epitaxial layer and / or the body region 12. The semiconductor device 1 manufactured according to this example has the polysilicon 10 at least partially filled with the oxide layer 6 forming the oxide layer 6 area surrounded by the polysilicon 10 (liner poly) (Fig. 1). The method according to this example comprises steps:
[0030] a) providing an epitaxial EPI layer with the trench 3 in a form of an opening extending from the top side 4 towards the bottom side 5 in a vertical direction, wherein on the top side 4 there is a top mesa surface 9 (Fig. 4a);
[0031] b) forming an oxide layer 6 on the trench 3 walls and the trench 3 bottom region 13 and on the top mesa surface 9 filing the trench 3 only partially insignificantly reducing the trench 3 diameter (Fig. 4 b);
[0032] c) forming a polysilicon liner layer 7 on the oxide layer 6 on the trench walls forming a well-shaped structure and the trench 3 bottom region 13 and on the top mesa surface 9 filing the trench 3 only partially insignificantly reducing the trench 3 diameter (Fig. 4 b);
[0033] d) depositing a masking material 8 on the polysilicon liner layer 7 filling the trench 3 completely. Masking material in this example is a blanket Photo Resist coating or deposited sacrificial layer like silicon dioxide or any suitable material (Fig. 4 c); e) etching the masking material 8 to the top mesa surface 9 (Fig. 4 d); f) partially etching the polysilicon liner layer 7 exposing part of the trench 3 walls covered with the oxide layer 6 (Fig. 4 e).
[0034] g) removing the masking material 8 by means of stripping (Fig. 4 e, f); h) depositing the oxide layer 6 at least into the trench 3 bottom region 13 and filing it and covering the polysilicon liner layer 7 (Fig. 4 g). In this example a wet oxidation process under 850°C is used. It is effective in filling oxide inside the polysilicon layer when polysilicon is highly doped with a doping concentration >= 2e20 cm3. Filling the oxide later into the trench bottom region can be done by wet oxidation preferably at temperatures <= 850 °C or through deposition with / without partial wet oxidation together;
[0035] i) wet etching the oxide layer 6 to reduce the liner oxide layer 6 thickness and dry etching the oxide layer 6 to expose part of covering the polysilicon liner layer 7 (Fig. 4 h);
[0036] j) depositing the polysilicon 10 into the trench 3 filing it partially for SourcePoly in the active cell 15 or completely for edge termination cell 16 manufacturing (Fig.
[0037] 4 i).
[0038] k) forming the oxide layer 6 at least into the trench 3 bottom region 13 and walls filling it and covering the polysilicon liner layer 7 (Fig. 4 j).
[0039] In another example of the disclosure step j) and k) are repeated to form an additional polysilicon 14 layer located in the trench 3 and above the polysilicon 10. The additional polysilicon 14 layer is a gate poly layer wherein the polysilicon 10 layer is a source poly of the trench MOSFET device (Fig. 3).
[0040] This disclosure also includes a second example of a method of manufacturing the semiconductor device, in particular an oxide filled multiple stepped RSO (Resurf Stepped Oxide) trench MOSFET structure, having a top side 4 and a bottom side 5 and an epitaxial layer (EPI) extending from the bottom side 5 of the semiconductor device 1 towards the top side 4. The semiconductor device 1 comprises a body region 12 extending from the epitaxial layer (EPI) towards the top side 4 and a trench 3 in the form of an opening extending from the top side 4 towards the bottom side 5 in a vertical direction through the epitaxial layer (EPI) and through the body region 12. Furthermore, the semiconductor device 1 also comprises a polysilicon 10 located in the trench 3 and an oxide layer 6 on the trench 3 walls and the trench 3 bottom region 13 isolating the polysilicon 10 from the epitaxial layer and / or the body region 12. The semiconductor device 1 manufactured according to this example has the polysilicon 10 at least partially filled with the oxide layer 6 forming the oxide layer 6 area surrounded by the polysilicon 10 (liner oxide). The method according to this example comprises steps:
[0041] a) providing an epitaxial EPI layer with the trench 3 in the form of an opening extending from the top side 4 towards the bottom side 5 in a vertical direction, wherein on the top side 4 there is a top mesa surface 9 (Fig. 5 a);
[0042] b) forming an oxide layer 6 on the trench 3 walls and the trench 3 bottom region 13 and on the top mesa surface 9 and depositing the polysilicon 10 on the oxide layer 6 filling the trench 3 completely and depositing the polysilicon 10 on the top mesa surface 9 (Fig. 5 b);
[0043] c) partially etching the polysilicon 10 exposing part of the trench 3 walls covered with the oxide layer 6 (Fig. 5 c);
[0044] d) depositing a nitride spacer 11 on the exposed part of the trench 3 walls covered with the oxide layer 6 (Fig. 5 d);e) dry etching the polysilicon 10 layer forming a well-shaped structure, and with this step the nitride spacer 11 (Fig. 5d) is removed. According to this example anisotropic dry etching is used (Fig. 5 e).
[0045] f) depositing the oxide layer 6 at least into the trench 3 bottom region 13 and filing it and covering the polysilicon 10 (Fig. 5 f). In this example wet oxidation process under 850°C is used.
[0046] g) wet etching the oxide layer 6 to reduce the liner oxide layer 6 thickness and dry etch the oxide layer 6 to expose part of covering the polysilicon 10 (Fig. 5 g); h) depositing the polysilicon 10 into the trench 3 filing it partially for Source Poly in active cell (16) or completely for edge termination cell (15) manufacturing (Fig.
[0047] 5 h);
[0048] i) forming the oxide layer 6 at least into the trench 3 bottom region 13 and walls filling it and covering the polysilicon 10 (Fig. 5 i).LIST OF REFERENCE NUMERALS USED
[0049] 1 semiconductor device
[0050] 2 stepped cone
[0051] 3 trench
[0052] 4 top side
[0053] 5 bottom side
[0054] 6 oxide layer
[0055] 7 polysilicon liner layer
[0056] 8 masking material
[0057] 9 top mesa surface
[0058] 10 polysilicon
[0059] 11 nitride spacer
[0060] 12 body region
[0061] 13 trench bottom region
[0062] 14 additional polysilicon (layer)
[0063] 15 edge termination cell
[0064] 16 active cell
[0065] 17 Power metal
[0066] 18 Barrier metal
[0067] 19 Inter dielectric layer
[0068] 20 silicon contact to body
[0069] 21 High dose Boron Fluoride and contact implant 22 terminal
Claims
CLAIMS1. A semiconductor device having a top side and a bottom side comprising:an epitaxial layer extending from the bottom side of the semiconductor device towards the top side having a mesa region on the top side;a body region extending from the epitaxial layer towards the top side; a trench in the form of an opening extending from the top side towards the bottom side in a vertical direction through the epitaxial layer and through the body region wherein the trench has a bottom region;a polysilicon located in the trench;an oxide layer on the trench walls and the trench bottom region isolating the polysilicon from the epitaxial layer and / or the body region;wherein the polysilicon is at least partially filled with the oxide layer.
2. The semiconductor device according to claim 1, wherein the polysilicon is partially filled with oxide in the bottom region.
3. The semiconductor device according to claim 1 or 2, wherein the polysilicon partially filled with oxide is located in the lower portion of the trench.
4. The semiconductor device according to claims 1 , 2 or 3, wherein the bottom region of the polysilicon has a form of a stepper cone tapering towards the bottom side.
5. The semiconductor device according to claims 1 , 2, 3 or 4, wherein there is an additional polysilicon layer in the trench located above the polysilicon.
6. A method of manufacturing the semiconductor device according to any of claims from 1 to 5, comprising the steps:a) providing an epitaxial layer with a trench in the form of an opening extending from a top side towards a bottom side in a vertical direction, wherein on the top side there is a top mesa surface;b) forming an oxide layer on the trench walls and the trench bottom region and on the top mesa surface;c) forming a polysilicon liner layer on the oxide layer on the trench walls forming a well-shaped structure and the trench bottom region and on the top mesa surface;d) depositing a masking material on the polysilicon liner layer;e) etching the masking material to the top mesa surface;f) partially etching the polysilicon liner layer exposing part of the trench walls covered with the oxide layer;g) removing the masking material;h) filling the oxide layer at least into the trench bottom region through wet oxidation covering the polysilicon layer on the top side;i) wet etching the oxide layer to reduce liner oxide thickness and dry etching the oxide layer to expose partially the polysilicon liner layer;j) depositing the polysilicon filling the trench, followed by chemicalmechanical polishing and back etching to form an interpoly-oxide and a gate;k) forming the oxide layer at least into the trench bottom region and filling it to form on inter-poly oxide and covering the polysilicon layer in the bottom.
7. The method according to claim 6, wherein the masking material is a photo resistive coating material or sacrificial layer.
8. The method according to claim 6 or 7, wherein in the step h) wet oxidation process under 850°C is used.
9. A method of manufacturing the semiconductor device according to any of claims from 1 to 5, comprising the steps:a) providing an epitaxial layer with the trench in the form of an opening extending from the top side towards the bottom side in a vertical direction, wherein on the top side there is a top mesa surface;b) forming an oxide layer on the trench walls and the trench bottom region and on the top mesa surface and depositing the polysilicon on the oxide layer filling the trench and depositing the polysilicon on the top mesa surface;c) partially etching the polysilicon exposing part of the trench walls covered with the oxide layer;d) depositing a nitride layer on the exposed part of the trench walls covered with the oxide layer and performing anisotropic dry etching of nitride layer to form a nitride spacer on the trench wall;e) dry etching the polysilicon layer and removing the nitride spacer forming a well-shaped structure;f) filling the oxide layer at least into the trench bottom region through wet oxidation covering the polysilicon layer on the top side;g) wet etching the oxide layer to reduce liner oxide thickness and dryetching the oxide layer to expose partially the polysilicon liner layer;h) depositing the polysilicon filling the trench, followed by chemicalmechanical polishing and back etching to form an interpoly-oxide and a gate;i) forming the oxide layer at least into the trench bottom region and filling it to form an inter-poly oxide and covering the polysilicon layer in the bottom.
10. The method according to claim 9, wherein in the step h) wet oxidation process under 850°C is used.
11. The method according to claim 9 or 10, wherein the step of an additional process of anisotropic dry etching is used to etch the nitride spacer.