A method for manufacturing a semiconductor power package as well as such semiconductor power package comprising at least one semiconductor device

Abstract

According to a first example of the disclosure, a method for manufacturing a semiconductor power package comprising at least one semiconductor device is proposed. The manufacturing method comprises the steps of i) providing a lead frame structure, wherein the lead frame structure is composed of a dam bar, at least one lead frame die pad, a plurality of lead frame terminals as well as a plurality of lead frame junctions locally interconnecting the at least one lead frame die pad and the plurality of lead frame terminals with the dam bar; ii) mounting at least one semiconductor die in direct contact to a corresponding lead frame die pad; iii) electrically connecting, using one or more connection elements, the at least one semiconductor die with one or more of the plurality of lead frame terminals; iv) encapsulating, using a mold compound, the lead frame structure, the at least one semiconductor die, the connecting elements and the plurality of lead frame terminals, such that at least part of the plurality of lead frame terminals are exposed and thereby forming an encapsulated semiconductor power package; v) removing the lead frame junctions locally interconnecting the plurality of exposed lead frame terminals with the dam bar; vi) plating the exposed free parts of the lead frame terminals with a solder wettable material; and finally vii) removing the remaining lead frame junctions locally interconnecting the at least one lead frame die pad with the dam bar.

Description

[0001] TITLE

[0002] A method for manufacturing a semiconductor power package as well as such semiconductor power package comprising at least one semiconductor device.

[0003] TECHNICAL FIELD

[0004] The present disclosure relates to a method for manufacturing a semiconductor power package as well as such semiconductor power package comprising at least one semiconductor device.

[0005] BACKGROUND OF THE DISCLOSURE

[0006] Power semiconductors are crucial components in various high-efficiency applications, including renewable energy systems, industrial motor drives, and particularly in electric vehicles (EVs). In EVs, power modules are essential for efficient power conversion and motor control, directly impacting vehicle performance and energy efficiency.

[0007] The package technology started from Through-hole which using both sides of a printed circuit board (PCB), then developed into SMD (Surface Mount Device) techniques, which occupied only one side of the PCB. On SMD configurations, lead frame terminals developed from gull-wing to flat leads to leadless terminals, and microlead packages are an extreme version of flat leads which balance between cost and electrical performance. Therefore, microlead packages is key packages format for power application. In particular, in so-called microlead packages, the exposed lead frame terminal ends have a flat configuration and exhibit a limited length exposure out of the encapsulated power package of less than 1 mm. During manufacturing, after mounting of the semiconductor die on the lead frame and moulding the assembly of the lead frame and the die, the exposed lead frame terminal ends are finished by means of a mechanical trimming of mechanical cutting technique. This results in exposed free lead frame terminal ends having only a top and a bottom surface thereof being provided with solder wettable material.

[0008] For automotive customers, AOI (Automatic Optical Inspection) is required and performed after mounting of the semiconductor power package on a PCB and the solder fillet as applied can be visualized from the top side of the semiconductorpower package component. The solder fillet thus formed also function as a buffer for solder volume variation. Furthermore, semiconductor power package PCB mounting flatness and package terminal to PCB interconnect resistance is better and preferred. Accordingly, a visual determination whether a side wall surface or a lead end surface of the exposed terminal lead end is provided with a solder wettable material is a necessary quality assessment feature for customers.

[0009] Therefore, it is a goal of the present disclosure to provide an improved method for manufacturing a semiconductor power package as well as such semiconductor power package comprising at least one semiconductor devices as acquired with the method, which allows for a better inspection and determination whether the exposed terminal lead end is properly provided and covered with a solder wettable material.

[0010] SUMMARY OF THE DISCLOSURE

[0011] According to a first example of the disclosure, a method for manufacturing a semiconductor power package comprising at least one semiconductor device is proposed. The manufacturing method comprises the steps of:

[0012] i) providing a lead frame structure having a first lead frame surface and a second lead frame surface opposite to the first lead frame surface, wherein the lead frame structure is composed of a dam bar, at least one lead frame die pad, a plurality of lead frame terminals as well as a plurality of lead frame junctions locally interconnecting the at least one lead frame die pad and the plurality of lead frame terminals with the dam bar;

[0013] ii) mounting at least one semiconductor die having a first die surface and a second die surface opposite to the first die surface, with its first surface in direct contact to a corresponding lead frame die pad;

[0014] iii) electrically connecting, using one or more connection elements, the at least one semiconductor die with one or more of the plurality of lead frame terminals; iv) encapsulating, using a mold compound, the lead frame structure, the at least one semiconductor die, the connecting elements and the plurality of lead frame terminals, such that at least part of the plurality of lead frame terminals are exposed and thereby forming an encapsulated semiconductor power package;v) removing the lead frame junctions locally interconnecting the plurality of exposed lead frame terminals with the dam bar;

[0015] vi) plating the exposed free parts of the lead frame terminals with a solder wettable material; and finally

[0016] vii) removing the remaining lead frame junctions locally interconnecting the at least one lead frame die pad with the dam bar.

[0017] With the above method steps allows for a better inspection and determination whether the exposed terminal lead end is properly provided and covered with a solder wettable material. Such visual determination is a necessary quality assessment feature for customers and accordingly allows to easy distinguish between correct and faulty semiconductor power packages, causing faulty electrical connections between the semiconductor power packages to a PCB.

[0018] In particular the plating step v) is performed by means of electrolytic plating, wherein the solder wettable material may comprise Tin.

[0019] In a further example of the method according to the disclosure, it further comprises the step viii) of, performed after step vi) or vii), bending the exposed free parts of the lead frame terminals.

[0020] The disclosure also pertains to a semiconductor power package comprising at least one semiconductor device as manufactured in accordance with the method according to the disclosure.

[0021] BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The disclosure will now be discussed with reference to the drawings, which show in:

[0023] Figures 1-5 various steps of the method according to the disclosure; Figure 6A-6B-6C a semiconductor power package as manufactured in accordance with the method according to the disclosure.

[0024] DETAILED DESCRIPTION OF THE DISCLOSURE

[0025] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.For automotive customers, AOI (Automatic Optical Inspection) is required and performed after mounting of the semiconductor power package on a PCB and the solder fillet as applied can be visualized from the top side of the semiconductor power package component. Accordingly, a visual determination whether a side wall surface or a lead end surface of the exposed terminal lead end is provided with a solder wettable material is a necessary quality assessment feature for customers.

[0026] Therefore, in the following detailed description an improved method for manufacturing a semiconductor power package as well as such semiconductor power package comprising at least one semiconductor device as obtained with the method is described. The improved manufacturing method allows for a better inspection and determination whether the exposed terminal lead end is properly provided and covered with a solder wettable material.

[0027] In Figure 1 various steps of a method according to the disclosure are disclosed. The manufacturing method encompasses the provision of a lead frame structure which is denoted with reference numeral 10. The lead frame structure 10 is made from an electrically conducting material, in general copper and is provided in a planer shape. The planar lead frame structure 10 has a first (or bottom) lead frame surface 10a and a second (or top) lead frame surface 10b opposite to the first lead frame surface 10a.

[0028] The lead frame structure 10 is composed of a dam bar 11, that forms the outer periphery of the lead frame structure 10, at least one lead frame die pad, a plurality of lead frame terminals as well as a plurality of lead frame junctions locally interconnecting the at least one lead frame die pad and the plurality of lead frame terminals with the dam bar.

[0029] In this example, as the method according to the disclosure is intended to manufacture a semiconductor power package, the lead frame structure 10 comprises two lead frame die pads, denoted with 12a and 12b. The plurality of lead frame terminals are denoted with 13a and 13b respectively, whereas the plurality of lead frame junctions are associated with reference numerals 14a and 14b respectively.

[0030] In particular, the plurality of lead frame junctions 14a and 14b are formed as a first group of lead frame junctions 14a intended to locally interconnect the various lead frame terminals 13a-13b with the dam bar 11, whereas a second group of lead frame junctions 14b serve to locally interconnect the lead frame die pads 12a and 12b with the dam bar 11.The dam bar 11 holds the important elements of the lead frame structure 10, in particular the various die pads 12a-12b and the plurality of lead frame terminals 13a-13b together with the assistance of the plurality of lead frame junctions 14a and 14b.

[0031] In the manufacturing method according to the disclosure, after the step of providing the lead frame structure 10 as discussed above, in a next step ii) semiconductor dies 20a and 20b are provided. Each semiconductor die 20a and 20b has a first die surface 200a and a second die surface 200b opposite to the first die surface 200a and is mounted with its first surface 200a in direct contact to a corresponding lead frame die pad 12a or 12b (hence to the second (or top) lead frame surface 10b of the lead frame structure 10).

[0032] Although not shown in the Figures, a further step iii) of the method according to the disclosure involves the electrical connection, using one or more connection elements, the semiconductor dies 20a (and 20b) with the plurality of lead frame terminals 13a (and 13b).

[0033] The next step iv) involves encapsulating, using a first mold compound 21a and a second mold compound 21b, the lead frame structure 10, the semiconductor dies 20a-20b, the connecting elements and the plurality of lead frame terminals 13a-13b, such that at least part of the plurality of lead frame terminals 13a-13b are exposed. The encapsulating or molding step creates or forms an encapsulated semiconductor power package 100, yet still accommodated within the dam bar 11 of the lead frame structure 10.

[0034] Accordingly, see Figure 2, step v) involves the removal, through a trimming, stamping or other known technique, of the first group of lead frame junctions 14a which locally interconnect the plurality of exposed lead frame terminals 13a-13b with the dam bar 11. Accordingly, the plurality of exposed lead frame terminals 13a-13b are now fully free and exposed, yet the encapsulated semiconductor power package 100 is still held by the dam bar 11 through the second group of lead frame junctions 14b.

[0035] Note that in Figure 2 not all lead frame junctions 14a of the first group of lead frame junctions are removed, as some lead frame junctions 14a’ at the corners of the first and second mold compounds 21a-21b are still present and interconnected with so-called corner lead frame terminals 13a’-13b’. In an alternative example, see Figure 3, also those corner lead frame junctions 14a’ are being removed in step v), thus resulting in all lead frame terminals 13a-13b being freed.After the step v, a step vi) is performed, see Figure 4 in which the exposed free parts of the lead frame terminals 13a-13b are plated with a solder wettable material 22. Similarly, due to the plating technique, also (parts of) the dam bar 11 and the second group of frame junctions 14b which locally interconnect the lead frame die pads 12a-12b with the dam bar 11 are plated with the solder wettable material 22.

[0036] In a final step vii) of the method according to the disclosure, the remaining lead frame junctions 14b which locally interconnect the lead frame die pads 12a-12b with the dam bar 11 are removed, similarly either through a trimming, stamping or other known technique.

[0037] The above method steps allows for a better inspection and determination whether the exposed terminal lead frame ends 13a-13b are properly provided and covered with a solder wettable material 22. Such visual determination is a necessary quality assessment feature for customers and accordingly allows to easy distinguish between correct and faulty semiconductor power packages 100.

[0038] The dam bar 11 is a lead frame design feature to block the mold compound flow to the inner lead area during molding. With this dam bar design, a molding tool can clamp on the lead frame top side and bottom side only. In an example with no dam bar design, the mold tool need to have AFP (Anti Flash Profile) configuration, using a mold tool feature to block the mold compound to flow to the inner lead area. However, due to tooling tolerance, certain mold flash will remain at lead side walls. In a no dam bar design case, the lead side walls may be covered by mold flash, and a lead end surface is formed by cutting. Therefore, only the top and the bottom surface sides are Sn plated (solder wetting). In a dam bar design case, as compared with a no dam bar design, the cutting positions from the lead end to lead sides, a lead side wall is formed by the cutting process and the top, bottom and end lead surfaces are Sn plated.

[0039] Figures 6A-6B-6C depict a semiconductor power package 100 as manufactured in accordance with the method according to the disclosure. As the exposed lead frame terminals 13a-13b are properly freed from the lead frame structure 10 with the removal of their interconnecting first group of lead frame junctions 14a, all sides of the lead frame terminals 13a-13b, hence the top surface 130d and bottom surface 130d, theirtwo side surfaces 130a-130b as well as theirfree end surface 130z, are properly plated with the solder wettable material 22. Note, that in the method according to the disclosure as depicted in Figure 2, only the corner lead frameterminals 13a’-13b’ are still interconnected with the corner lead frame junctions 14a’, whereas the other lead frame junctions 14a are being removed in step v). In the example of Figure 2, the corner lead frame terminals 13a’-13b’ are only in part plated with the solder wettable material 22 (on its top surface 130d, its bottom surface 130d, one side surface 130a and on its free end surface 130z).

[0040] Accordingly, in this example, the exposed lead frame terminals 13a-13b are e.g. all Drain lead frame terminals and are on all five surface side plated with a solder wettable material. In the event of a Gate terminal, as single lead frame terminal, the outer side surface wall 130b needs to be provided with electrical connection during Tin plating. Therefore, the outer side surface wall 130b will not be covered with a solder wettable material 22 and will show exposed copper after the final removal step vii) of the method according to the disclosure, wherein the remaining lead frame junctions 14b which locally interconnect the lead frame die pads 12a-12b with the dam bar 11 as well as the corner lead frame junctions 14a’ are removed. For the Source lead frame terminal, inner lead is electrical connected, only lead at the outer side surface wall will have a cutting flange due to the step vii) thereby exposing copper material.

[0041] An additional benefit of the present disclosure compared to the prior art, which have lead frame terminals with at least one non-wettable side, is that some of exposed lead frame terminals are fully wettable and the method allows to obtain a semiconductor power package with different lead wettable features.

[0042] Thus as depicted in Figure 6B, in that example of the method a corner lead frame terminal 13a’(or 13b’) is depicted with four sides 130a-130c-130d and 130z being plated and with its other side surface 130b (which is still interconnected with the dam bar 11 through a corner lead frame junctions 14a’) not being plated. After the final step vii) of the method according to the disclosure, the removal of the remaining lead frame junctions 14b including the corner lead frame junctions 14a’ will result in a corner terminal lead end 13a-13b with one side surface 130b not being provided with the solder wettable material 22.

[0043] It is noted that in all examples, the plating step v) is performed by means of electrolytic plating, wherein the solder wettable material may comprise Tin.

[0044] In a further example of the method according to the disclosure, it further comprises a step viii) which can be performed after step vi) or vii), and involves bending the exposed free parts of the lead frame terminals 13a-13b.LIST OF REFERENCE NUMERALS USED

[0045] 100 semiconductor power package

[0046] 10 lead frame structure

[0047] 10a first lead frame surface

[0048] 10b second lead frame surface

[0049] 11 dam bar

[0050] 12a first lead frame die pad

[0051] 12b second (further) lead frame die pad 13a (first group of) lead frame terminals 13b (second group of) lead frame terminals 14a (first group of) lead frame junctions 14b (second group of) lead frame junctions 20a first semiconductor device

[0052] 20b second semiconductor device

[0053] 200a first die surface

[0054] 200b second die surface

[0055] 21a first mold compound

[0056] 21b second mold compound

[0057] 22 plated solder wettable material

Claims

9CLAIMS1. A method for manufacturing a semiconductor power package comprising at least one semiconductor device, the method comprising the steps of:i) providing a lead frame structure having a first lead frame surface and a second lead frame surface opposite to the first lead frame surface, wherein the lead frame structure is composed of a dam bar, at least one lead frame die pad, a plurality of lead frame terminals as well as a plurality of lead frame junctions locally interconnecting the at least one lead frame die pad and the plurality of lead frame terminals with the dam bar;ii) mounting at least one semiconductor die having a first die surface and a second die surface opposite to the first die surface, with its first surface in direct contact to a corresponding lead frame die pad;iii) electrically connecting, using one or more connection elements, the at least one semiconductor die with one or more of the plurality of lead frame terminals; iv) encapsulating, using a mold compound, the lead frame structure, the at least one semiconductor die, the connecting elements and the plurality of lead frame terminals, such that at least part of the plurality of lead frame terminals are exposed and thereby forming an encapsulated semiconductor power package;v) removing the lead frame junctions locally interconnecting the plurality of exposed lead frame terminals with the dam bar;vi) plating the exposed free parts of the lead frame terminals with a solder wettable material;vii) removing the remaining lead frame junctions locally interconnecting the at least one lead frame die pad with the dam bar.

2. The method according to claim 1, wherein the encapsulating step iv) is performed after step v).

3. The method according to claim 1 or 2, wherein the plating step vi) is performed by means of electrolytic plating.

4. The method according to any one of the preceding claims, wherein the solder wettable material comprises Tin.

5. The method according to any or more of the preceding claims, wherein the method further comprises the step of:viii) after step vi) or vii), bending the exposed free parts of the lead frame terminals.

6. A semiconductor power package comprising at least one semiconductor device as manufactured in accordance with anyone or more of the method claims 1-5.

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