Methods, devices and systems for implementing clifford gates on quantum hardware systems

Abstract

In a method for implementing a Clifford gate on a quantum hardware system, a symplectic matrix representation of the Clifford gate is determined that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The method comprises causing the quantum hardware system to implement the sequence of quantum gates.

Description

METHODS, DEVICES AND SYSTEMS FOR IMPLEMENTING CLIFFORD GATES ON QUANTUM HARDWARE SYSTEMSCross-Reference to Related Application

[0001] This application claims priority from US application No. 63 / 764648 filed28 February 2025 and entitled METHODS, DEVICES AND SYSTEMS FOR IMPLEMENTING CLIFFORD GATES ON QUANTUM HARDWARE SYSTEMS which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No. 63 / 764648 filed 28 February 2025 and entitled METHODS, DEVICES AND SYSTEMS FOR IMPLEMENTING CLIFFORD GATES ON QUANTUM HARDWARE SYSTEMS which is hereby incorporated herein by reference for all purposes.Field

[0002] This disclosure generally relates to methods, devices, and systems for implementing a Clifford gate on a quantum hardware system. The disclosure further relates to methods, devices, and systems for executing a logical quantum circuit on a quantum hardware system. The disclosure further relates to methods, devices, and systems for resource estimation of executing a quantum algorithm on a quantum hardware system.Background

[0003] Quantum computing relies on the Clifford group, a set of operations that preserve stabilizer states and play a fundamental role in quantum error correction (QEC) and fault-tolerant computation. This group includes essential gates such as the Hadamard, phase, and controlled-NOT (CNOT) gates, which serve as the foundation for many QEC protocols. The operations in a fault-tolerant quantum computation are generally implemented using deterministic Clifford circuits corresponding to predictable operations, or adaptive Clifford circuits that correspond to operations that change based on intermediate measurementresults. Clifford circuits are widely used in tasks like state preparation, measurement, and gate synthesis. Due to their importance, researchers actively seek cost-effective implementations of these gates, optimizing both algorithmic complexity and the efficiency of gate sequences.

[0004] Decompositions of Clifford gates can be found in Aaronson et al., “Improved Simulation of Stabilizer Circuits”, arXiv: quant-ph / 0406196, 2008, and in Sayginel, “Fault-Tolerant Logical Clifford Gates from Code Automorphisms”, arXiv:2409.18175v1, 2024, which are hereby incorporated by reference in their entirety.

[0005] QEC is a crucial mechanism for protecting quantum information from errors caused by decoherence, noise, and other disturbances. Unlike classical computing, where redundancy can be used to detect and correct errors, quantum errors are more intricate due to the fragile nature of quantum states arising from superposition and entanglement. QEC addresses this challenge by encoding quantum information across multiple qubits through entanglement and redundancy, enabling the detection and correction of errors without directly measuring or collapsing the quantum state. This capability is essential for the development of large-scale, reliable quantum computers.Summary

[0006] The present disclosure has several aspects, including methods, devices, and systems for implementing a Clifford gate on a quantum hardware system, methods, devices, and systems for executing a logical quantum circuit on a quantum hardware system, and methods, devices, and systems for resource estimation of executing a quantum algorithm on a quantum hardware system.

[0007] A first aspect of the disclosure provides a method for implementing a Clifford gate on a quantum hardware system. A symplectic matrix representation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to -diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators is determined. The Clifford gate is synthesized into a sequence of quantum gates, based on thesymplectic matrix representation of the Clifford gate. The method comprises causing the quantum hardware system to implement the sequence of quantum gates.

[0008] According to the method, a product of at least five matrices is computed that alternate between matrices corresponding to -diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. Herein, diagonal operators are diagonal in the computational basis. Subcircuits comprising a sequence of quantum gates are synthesized for each matrix. The subcircuits combine to a sequence of quantum gates corresponding to the Clifford gate.Since the matrices are diagonal, the synthesized subcircuits are strictly abelian, i.e., commutative. This is advantageous because it implies that the subcircuits can be implemented in any desired order. This flexibility can result in a quantum circuit with lower depth. Herein, the depth of a quantum circuit corresponds to the number of time steps needed to execute the gates in the quantum circuit.

[0009] As another advantage, diagonal circuits allow for efficient gate-injection protocols, which can be practically beneficial, especially with respect to an error-corrected computation.

[0010] A quantum mechanical operation on one or more qubits is described by a unitary operator. An important class of unitary operators is described by the Pauli group. The single-qubit Pauli groupis the group of Pauli operators that can each act on the qubit. There are 16 Pauli operators. Up to a complex phase, there are 3 distinct non-trivial operators, the Pauli X, Y, and Z operators. The single-qubit Pauli groupis formed by all products of the Pauli X, Y, and Z operators. The Pauli X operators are also denoted as bit-flip operators because they exchange the two basis states in the computational basis. The Pauli Z operators are also known as phase-flip operators because they change the relative phase of the two basis states in the computational basis.

[0011] The term “n-qubit Pauli group J’ ’ (or simply: “Pauli group”) denotes the group formed by all length n tensor products of elements of the single-qubit Pauli group J’i, where n is an integer greater than 1. The Pauli group is a non-Abelian group, i.e., group elements in general do not commute. The elements of the n-qubit Pauli group are denoted as Pauli operators. The Pauli group comprises n-qubit Pauli X operators which are obtained by applying the (1 -qubit) Pauli X operator to any subset of the n qubits while applying the identity operator to the other qubits. Similarly, the Pauli group comprises n-qubit Pauli Z operators which are obtained by applying the (1 -qubit) Pauli Z operator to any subset of the n qubits while applying the identity operator to the other qubits.

[0012] The term “Clifford group” denotes the group of so-called Clifford gates (or Clifford operators) which are unitary operators that preserve the Pauli group under conjugation. This means that the n-qubit Clifford group C£nis the set of all operators V that map Pauli operators P in the n-qubit Pauli group 풫nto other Pauli operators in the n-qubit Pauli group 풫nunder conjugation:풞ℓn= {V: VPV† ∈ 풫n, ∀P ∈ 풫n}.

[0013] The n-qubit Clifford group C£nis said to “normalize” the n-qubit Pauli group J’n. The fact that the Clifford operators map Pauli operators to other Pauli operators under conjugation makes the Clifford operators easier to describe. Up to a phase, a Clifford operator V can be described by the images of the 2n Pauli operators XLand Z7- under conjugation by V. A Clifford operator can therefore be described by a 2n x (2n + 1) matrix (with one column tracking signs) which is much more efficient than a general unitary operator which can only be fully described by a 2nx 2nmatrix.

[0014] For example, conjugating the Pauli X operator by the Hadamard gate H gives the Pauli Z operator:HXH† = Z.

[0015] Similar relations hold for the Pauli Y and Z operators. The Hadamard gate H is an example of a Clifford operator.

[0016] The Clifford group is generated by the Hadamard gate H, the phase gate S, and the CNOT gate. Herein, a list of gates or operators is said to “generate” a larger collection of gates or operators, if every element of the larger collection can be composed as products of elements from the list of gates. These compositions may be arbitrarily long and may contain repetitions.

[0017] Every element of the Clifford group is uniquely specified (up to a phase) by specifying where the Clifford operator maps a generating set of the Pauli group under conjugation. Advantageously, the Clifford group requires only a single additional gate to form a universal gate set.

[0018] The Hadamard gate H, the phase gate S, and the CNOT gate generate other Clifford group elements such as the Controlled-Z gate (denoted as CZ gate) and the SWAP gates.

[0019] Clifford operators play an important role in QEC. A QEC code can be defined by specifying a code space which is a vector subspace of a Hilbert space and is spanned by so-called code words of the QEC code. A code word is a state which encodes some data. A code word corresponds to a logical state of the QEC code. A QEC code is used to protect quantum information that is processed in the computation from errors due to quantum noise, e.g., decoherence.

[0020] A QEC code is in general a mapping of k qubits onto n qubits, where n > k. The k qubits are elements of a Hilbert space of dimension 2fe. The n qubits are elements of a Hilbert space of dimension 2". Herein, the k qubits are the “logical qubits” or “encoded qubits” that are to be protected from error, e.g., a threshold amount of error. The n qubits are the “physical qubits” implementing the logical qubits. The additional n - k qubits allow the k logical qubits to be stored in a redundant fashion so that the encoded information is less susceptible to noise or other disturbances.

[0021] A QEC code with block size n, encoded qubits k, and distance d is denoted as an “[[n, k, d]] QEC code,” where the distance d is the minimum support of a non-identity logical operator in the code. The distance d sets a bound on the number of errors the QEC code can detect and correct. For example, if there arefewer than errors, a perfect decoder can identify and correct these errorswithout changing the intended quantum state. On the other hand, if there are more than errors, a perfect decoder may be unable to correct all the errors.

[0022] In QEC codes, errors are often modelled as Pauli operators, i.e., elements of the Pauli group J>n. Because the Clifford operators preserve the Pauli group under conjugation, Clifford operators can be used to track and correct errors.

[0023] Elements of the n-qubit Pauli group J>ncan be represented (up to a phase) as elements of GF(2)2n, where GF(2) denotes the finite field of order 2, i.e., the field with two elements that can be labeled 0 and 1, having an additive and a multiplicative structure. The representation is called the binary symplectic representation of the n-qubit Pauli group J>n. The representation is obtained by taking the j-th register of an element of the n-qubit Pauli group J>nand setting the j-th position in the binary vector in GF(2)2nto the power of the X operator at the j-th position and setting the (j + n)-th position to the power of the Z operator at the j-th position. For example, the 4-qubit Pauli operator XIYZ is mapped to:(10100011)with the first four bits corresponding to the X-part and the last four bits corresponding to the Z-part.

[0024] Further, it is known that the n-qubit Clifford group C£nmodulo the n-qubit Pauli groupis isomorphic to the symplectic group Sp(2n, GF(2)) of order 2n over the finite field GF(2), i.e.:C4 / 5’„ = Sp(2n, GF(2)).

[0025] This representation ofis known as the tableau representation. The tableau representation tracks the image of the Pauli X operators and the Pauli Z operators under conjugation, up to a sign. The symplectic group Sp(2n, GF(2)) is the group of matrices with coefficients in the finite field GF(2) that preserve a binary symplectic structure matrix fl defined aswhere Inis the n x n-dimensional unity matrix. That is, the symplectic group Sp(2n, GF(2)) comprises matrices M which satisfyMTQ. M = n,where MTdenotes the transpose of the matrix M.

[0026] The groupof operators generated by Hadamard gates H and SWAP circuits, i.e.,Mn= ⟨H, SWAP⟩,corresponds to the group of symplectic permutation-like operators in the Clifford group (i.e., symplectic analogues of permutations). In other words, the image of the groupof operators generated by Hadamard gates H and SWAP circuits in Sp(2n, GF(2)) is the group given by the intersection of the symplectic group Sp(2n, GF(2)) of order 2n over the finite field GF(2) and the symmetric group S2n(GF(2)) of order 2n over the finite field GF(2),Sp(2n, GF(2)) A S2n(GF(2)).Z-diagonal Clifford operators form a subgroup of the Clifford group. The Z-diagonal Clifford operators are operators that act diagonally on the computational basis and are generated by single-qubit phase gates St and two-qubit controlled- Z gates CZi,j, i.e.:풟(Z)= {Si, CZij| 1 ≤ i,j ≤ n}.

[0027] Up to Pauli operators, the Z-diagonal Clifford operators are represented by symplectic matrices of size 2n x 2n of the formfln0 \In Jfor symmetric binary matrices L of size n x n. The diagonal and off-diagonal entries of the symmetric binary matrix L determine the presence of S and CZ gates, respectively. The maximal column weight of L corresponds to the depth of the circuit. Herein, the maximal column weight is the maximal number of non-zero elements in a single column.

[0028] The Z-diagonal Clifford operators have particularly efficient injection protocols when combined with the transversal CNOT operation, which is a gate that many codes possess.

[0029] X-diagonal Clifford operators form a subgroup of Clifford group. The X-diagonal Clifford operators are operators that act diagonally on the X-eigenbasis and are generated by Hadamard-rotated single-qubit phase gates HiSiHiand Hadamard-rotated two-qubit controlled-Z gates HtHj CZtj HtHj, i.e.,:풟(X)= {HiSiHi, HiHjCZijHiHj| 1 ≤ i,j ≤ n}.

[0030] Up to Pauli operators, the / -diagonal Clifford operators are represented by symplectic matrices of the form(In M\\0 ln)’for symmetric binary matrices M of size n x n. The diagonal and off-diagonal entries of the symmetric matrix M determine the presence of HSH andH⊗2CZ H⊗2gates, respectively. The maximal column weight of M corresponds to the depth of the circuit.

[0031] The Hadamard gates, phase gates, and CNOT gates that generate the Clifford group do not commute with each other. Therefore, the Clifford group is non-abelian (not commutative). Despite this, the Clifford group contains both abelian and non-abelian subgroups. The method relates to a representation (or decomposition) of Clifford operators as a sequence of abelian (commutative) components, the / -diagonal Clifford operators and the Z-diagonal Clifford operators. Decomposing a Clifford operator exclusively into a sequence of abelian components is advantageous because it is possible to implement the synthesized abelian components in any order, yielding significant flexibility.

[0032] According to an embodiment of the method according to the first aspect, the at least five matrices comprise a matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator.

[0033] According to an embodiment of the method according to the first aspect, all of the five matrices have a depth greater than one. Nevertheless, it is advantageous to have at least one depth-one operator, as depth-one operators are generally easier to implement on quantum hardware due to the fewer number of gates required.

[0034] According to an embodiment of the method according to the first aspect, the matrix that corresponds to a depth-one / -diagonal or Z-diagonal Cliffordoperator is a leftmost matrix or a rightmost matrix in the product. The matrix that corresponds to a depth-one / -diagonal or Z-diagonal Clifford operator can be combined with an adjacent matrix, e.g., a matrix of the representation of another Clifford gate or of a non-Clifford gate.

[0035] According to an embodiment of the method according to the first aspect, the at least five matrices comprise a first matrix CX 1that corresponds to a first X-diagonal Clifford operator, a second matrix CZ 1that corresponds to a first Z-diagonal Clifford operator, a third matrix CXi2that corresponds to a second X-diagonal Clifford operator, a fourth matrix CZ 2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dxthat corresponds to a depth-one X-diagonal Clifford operator. The product is one of the following:r,i ’ ^z,i ■ r,2 ’ ^z,2 ■ Dx>Dx ’ CZi ■ CX 1■ CZ 2■ CX 2.

[0036] According to an embodiment of the method according to the first aspect, the at least five matrices comprise a first matrix CX 1that corresponds to a first X-diagonal Clifford operator, a second matrix CZ 1that corresponds to a first Z-diagonal Clifford operator, a third matrix CX 2that corresponds to a second X-diagonal Clifford operator, a fourth matrix CZ 2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dzthat corresponds to a depth-one Z-diagonal Clifford operator. The product is one of the following:Cz,i ’ r,i ’ DZ 2■ CX 2■ Dz,Dz ’,i ’ CZ,i ’ CX,2’ DZ 2.

[0037] According to an embodiment of the method according to the first aspect, factorizing the symplectic matrix representation of the Clifford gate comprises factorizing the symplectic matrix representation of the Clifford gate into a matrix that corresponds to a depth-one / -diagonal or Z-diagonal Clifford operator and amatrix that has a 2 x 2-block form. An upper left block is an invertible matrix. In some embodiments, the Clifford gate can be represented as a 2nx 2n-dimensional binary symplectic matrix ∈ Sp(2n, GF(2)) which factors as follows:=(A B\ (In K\ (A B\X\C D) \0 ln) ’ D)for n x n-dimensional binary matrices A, B, C and D, where Indenotes the n x n-dimensional unity matrix, with an invertible n x n-dimensional binary matrix A ∈ GL(n, GF(2)), with n x n-dimensional binary matrices B, C and D, and with a symmetric n x n-dimensional binary matrix K of weight at most equal to 1.

[0038] According to an embodiment of the method according to the first aspect, the matrix that has the 2 x 2-block form is factorized into a product of four matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The matrix that has the 2 x 2-block form can be factorized as follows:

[0039] Herein, first and second X-diagonal Clifford operators CX,1and CX 2, respectively, and first and second Z-diagonal Clifford operators CZ 1and CZ 2, respectively, have the following general form:(In 0Gx,i =L In(In M'Gz,i=0 In.(In 0Gy, 2 =Nwhere the matrices L, M, N, Q are symmetric n x n-dimensional matrices.

[0040] According to an embodiment of the method according to the first aspect, synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at runtime of the quantum hardware system. For example, application of some Clifford gates in a logical quantum circuit may depend on measurements performed during runtime. Depending on measurement outcomes, required Clifford gates are synthesized.

[0041] According to an embodiment of the method according to the first aspect, synthesizing the Clifford gate into the sequence of quantum gates is performed at compile time. All computations that concern the representation of the Clifford gate can then be performed before the computation on the quantum hardware system is initiated.

[0042] According to an embodiment of the method according to the first aspect, the Clifford gate is part of a logical quantum circuit. The symplectic matrix representation of the Clifford gate is combined with a matrix representation of at least one adjacent quantum gate in the logical quantum circuit. Combining matrices can reduce the number of matrices that appear in the representation of the logical quantum circuit. This, in turn, can reduce the number of gates that appear in the physical implementation of the logical quantum circuit.

[0043] According to an embodiment of the method according to the first aspect, at least two representations of the symplectic matrix representation of the Clifford gate as products comprising at least five matrices are determined. An order of the at least five matrices in the product differs for the at least two representations.

[0044] According to an embodiment of the method according to the first aspect, the Clifford gate is synthesized into a sequence of quantum gates for each of the at least two representations of the Clifford gate. One of the representations is selected for implementing the sequence of quantum gates on the quantumhardware system. By selecting from different representations, more efficient implementations can be found.

[0045] According to an embodiment of the method according to the first aspect, the representation for implementing the sequence of quantum gates is selected based on a comparison of a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system for each one of the representations. The representation with the lower cost can be selected.

[0046] According to an embodiment of the method according to the first aspect, the quantum hardware system is a modular quantum hardware system. A “modular quantum hardware system” comprises a plurality of modules or sub-units which can be physically separate entities, e.g., arranged on different chips. In certain applications, it can be advantageous to link multiple modules instead of building ever-larger monolithic quantum supercomputers (i.e., having only one module). The modules are interconnected. For example, inter-modular operations can be performed by entangling physical qubits on different modules, e.g., using photon-mediated entanglement.

[0047] A second aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method for implementing the Clifford gate on the quantum hardware system according to the first aspect.

[0048] A third aspect of the disclosure provides a non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method for implementing the Clifford gate on the quantum hardware system according to the first aspect.

[0049] A fourth aspect of the disclosure provides a device for implementing a Clifford gate on a quantum hardware system. The device comprises at least one processor and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a symplectic matrixrepresentation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The processor causes the quantum hardware system to implement the sequence of quantum gates.

[0050] A fifth aspect of the disclosure provides an information processing system comprising a quantum hardware system, at least one processor, and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a symplectic matrix representation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The processor causes the quantum hardware system to implement the sequence of quantum gates.

[0051] A sixth aspect of the disclosure provides a method for implementing a Clifford gate on a quantum hardware system. A sequence of at least five operators corresponding to the Clifford gate is determined. The at least five operators alternate in the sequence between / -diagonal Clifford operators and Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the sequence of operators. The method comprises causing the quantum hardware system to implement the sequence of quantum gates.

[0052] According to an embodiment of the method according to the sixth aspect, the at least five operators comprise a depth-one X-diagonal or Z-diagonal Clifford operator.

[0053] According to an embodiment of the method according to the sixth aspect, the depth-one X-diagonal or Z-diagonal Clifford operator is a leftmost operator or a rightmost operator in the sequence.

[0054] According to an embodiment of the method according to the sixth aspect, the at least five operators comprise a first X-diagonal Clifford operator OX1, a first Z-diagonal Clifford operator OZ1, a second X-diagonal Clifford operator OX2, a second Z-diagonal Clifford operator OZ2, and a depth-one X-diagonal Clifford operator Ox. The sequence is one of the following:Ox,i OZ1OX2OZ2Ox,Ox OZiOX 1OZ 2OX 2.

[0055] According to an embodiment of the method according to the sixth aspect, the at least five operators comprise a first X-diagonal Clifford operator OX1, a first Z-diagonal Clifford operator OZ1, a second X-diagonal Clifford operator OX2, a second Z-diagonal Clifford operator OZ2, and a depth-one Z-diagonal Clifford operator Oz. The sequence is one of the following:Oz,i OX1OZ 2OX 2Oz,Oz Ox,i OZ1OX2OZ 2.

[0056] According to an embodiment of the method according to the sixth aspect, synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at runtime of the quantum hardware system.

[0057] According to an embodiment of the method according to the sixth aspect, synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at compile time.

[0058] According to an embodiment of the method according to the sixth aspect, the Clifford gate is part of a logical quantum circuit. The sequence of the at least five operators corresponding to the Clifford gate is combined with a sequence ofat least five operators corresponding to an adjacent quantum gate in the logical quantum circuit.

[0059] According to an embodiment of the method according to the sixth aspect, at least two sequences of at least five operators corresponding to the Clifford gate are determined. An order of the at least five operators corresponding to the Clifford gate differs for the at least two sequences.

[0060] According to an embodiment of the method according to the sixth aspect, the Clifford gate is synthesized into a sequence of quantum gates for each of the at least two sequences of at least five operators corresponding to the Clifford gate. One of the sequences of at least five operators corresponding to the Clifford gate is selected for implementing the sequence of quantum gates on the quantum hardware system.

[0061] According to an embodiment of the method according to the sixth aspect, the sequence of at least five operators corresponding to the Clifford gate is selected based on a comparison of a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system, based on the respective sequence of at least five operators corresponding to the Clifford gate.

[0062] According to an embodiment of the method according to the sixth aspect, the quantum hardware system is a modular quantum hardware system.

[0063] A seventh aspect of the disclosure provides a device for implementing a Clifford gate on a quantum hardware system. The device comprises at least one processor and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a sequence of at least five operators corresponding to the Clifford gate. The at least five operators alternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the sequence of operators. The processor causes the quantum hardware system to implement the sequence of quantum gates.

[0064] An eighth aspect of the disclosure provides an information processing system comprising a quantum hardware system, at least one processor, and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a sequence of at least five operators corresponding to the Clifford gate. The at least five operators alternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the sequence of operators. The processor causes the quantum hardware system to implement the sequence of quantum gates.

[0065] A ninth aspect of the disclosure provides a method for executing a logical quantum circuit on a quantum hardware system. A symplectic matrix representation of at least one Clifford gate in the logical quantum circuit is determined that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The logical quantum circuit is executed on the quantum hardware system, based on the symplectic matrix representation of the at least one Clifford gate.

[0066] According to an embodiment of the method for executing the logical quantum circuit on the quantum hardware system, executing the logical quantum circuit on the quantum hardware system comprises synthesizing the at least one Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate, and implementing the sequence of quantum gates on the quantum hardware system.

[0067] A tenth aspect of the disclosure provides a device for executing a logical quantum circuit on a quantum hardware system, the device comprising at least one processor, and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which storesprocessor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine, for at least one Clifford gate in the logical quantum circuit, a symplectic matrix representation that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The logical quantum circuit is executed on the quantum hardware system, based on the symplectic matrix representation of the at least one Clifford gate.

[0068] An eleventh aspect of the disclosure provides a method for resource estimation of executing a quantum algorithm on a quantum hardware system. For at least one Clifford gate in the quantum algorithm, a symplectic matrix representation of at least one Clifford gate in the logical quantum circuit is determined that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. A resource estimation of executing the quantum algorithm on the quantum hardware system is made, based on the symplectic matrix representation of the at least one Clifford gate. The resource estimation can be helpful to improve the implementation of quantum circuits for given quantum algorithms.

[0069] According to an embodiment of the method according to the eleventh aspect, the at least one Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. The resource estimation of executing the quantum algorithm on the quantum hardware system is based on the sequence of quantum gates.

[0070] According to an embodiment of the method according to the eleventh aspect, at least one cost metric indicative of a cost of executing the quantum algorithm on the quantum hardware system is computed. The cost metric can indicate the amount of resources required for executing the quantum algorithm.

[0071] According to an embodiment of the method according to the eleventh aspect, the at least one cost metric comprises at least one of a gate count, gate depth, qubit count, connectivity, gate fidelity, or quantum circuit fidelity. The gate count refers to the total number of quantum gates in the quantum circuit. The gate depth refers to the maximum number of sequential gates on any qubit. The qubit count refers to the total number of qubits required. The connectivity refers to how the qubits are connected or mapped based on hardware topology. The gate fidelity refers to the quality of individual gate operations. The circuit fidelity refers to the overall probability of circuit success. Further cost metrics may comprise a number and / or depth of non-Clifford gates (e.g., T gates).

[0072] A twelfth aspect of the disclosure provides a device for resource estimation of executing a quantum algorithm on a quantum hardware system, comprising at least one processor and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine, for at least one Clifford gate in the quantum algorithm, a symplectic matrix representation that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. A resource estimation of executing the quantum algorithm on the quantum hardware system is made, based on the symplectic matrix representation of the at least one Clifford gate.

[0073] The disclosure relates to all combinations of the above features, even if these are recited in different aspects or different claims.Brief description of the drawings

[0074] In the following, further aspects and exemplary embodiments will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the described exemplary embodiments and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting.Fig. 1 schematically shows a block diagram illustrating an information processing system according to an embodiment of the disclosure;Fig. 2 shows a flow diagram of a method for implementing a Clifford gate on a quantum hardware system according to an embodiment of the disclosure;Fig. 3 shows a flow diagram of a method for implementing a Clifford gate on a quantum hardware system according to an embodiment of the disclosure;Fig. 4 shows a flow diagram of a method for executing a logical quantum circuit on a quantum hardware system according to an embodiment of the disclosure;Fig. 5 shows a flow diagram of a method for resource estimation of executing a quantum algorithm on a quantum hardware system according to an embodiment of the disclosure; andFig. 6 shows a flow diagram of a method for representing a Clifford gate as a symplectic matrix that can be used in methods according embodiments of the disclosure.Detailed description

[0075] Figure 1 schematically shows a block diagram illustrating an information processing system 100. The information processing system 100 comprises a quantum hardware system 140 which is a physical device or machine (e.g., a quantum computer) which can be used to implement quantum algorithms.

[0076] The quantum hardware system 140 comprises a plurality of modules 141 interconnected via coupling devices 142. The modules 141 include hardware components for performing tasks related to quantum computation, quantum sensing and quantum communication. These components may include physical qubits, measurement devices, control electronics, and readout electronics.Different modules can be spatially separated. The coupling devices 142 can comprise optical links or one or more optical networks to optically connectdifferent modules 141. The quantum hardware system 140 operates the modules 141 when executing a quantum process (e.g., quantum algorithm). For example, modules 141 may be operated to perform “intra-modular” and / or “inter-modular” operations. The term “intra-modular operation” relates to operations (e.g. gates) between physical qubits of the same module 401. The term “inter-modular operation” relates to operations (e.g. gates) between physical qubits of different modules 141. Each physical qubit may be initialized to a first quantum state, second quantum state or a superposition of the first quantum state and second quantum state, which can be used to represent quantum information.

[0077] Whereas the quantum hardware system 140 in Figure 1 is a modular quantum hardware system (i.e., comprises a plurality of modules 141), the disclosure is not restricted to this case. In other embodiments, the quantum hardware system 140 has only a single module 141.

[0078] The quantum hardware system 140 can be a non-locally connected quantum hardware system, as described in Simmons, “Scalable Fault-Tolerant Quantum Technologies with Silicon Colour Centres”, arXiv:2311.04858, 2023, and in Afzal et al., “Distributed Quantum Computing in Silicon”, arXiv: 2406.01704, which are hereby incorporated by reference in their entirety.

[0079] In some embodiments, the modules 141 and the coupling devices 142 comprise hardware components such as optical paths, optical links, optical networks, grating couplers, optical switches, Bell State Analyzers (BSAs) and / or detectors for facilitating optical connection between the physical qubits of the modules 141. Accordingly, the coupling devices 142 may be configured to establish optical coupling between the modules 141. In other embodiments, the modules 141 can be coupled non-optically. Similarly, inter-modular connections can be optical or non-optical. In some embodiments, there can be both optical and non-optical connections. Intra-module connections may comprise optical interconnects, microwave interconnects, physical ion transport, and the like. Intermodular connections (i.e., the coupling devices 142) can comprise optical interconnects, microwave interconnects (with or without microwave to optical transduction), and the like.

[0080] Optical links can be used in connecting the physical qubits of the modules 141 with switches and detectors and can further connect switches and detectors to each other. Similarly, the switches can be controlled to select specific optical links for connecting a physical qubit of the modules 141 to at least one other physical qubit of the modules 141, either of the same module 141 or of another module 141. In some embodiments, by controlling one or more hardware components in a suitable manner, any pair of physical qubits of the modules 141 may be optically connected to each other.

[0081] The detectors can be used in generating entanglement between the physical qubits of the modules 141 based on a photon detection pattern of photon states associated with said physical qubits of the modules 141. The entanglement may be generated according to an entanglement protocol, such as the Barrett-Kok protocol.

[0082] The physical qubits of the modules 141 can be matter qubits or photonic qubits. Example implementation of physical qubits comprise luminescent defects, trapped ions, trapped atoms, neutral atoms, superconducting qubits, quantum dots, quantum wells, nuclear spins within dissolved molecules, trapped atoms coupled to high-finesse cavities, Bose-Einstein condensates, and the like.

[0083] The quantum hardware system 140 may comprise a photon interface (photonic interface). One possible example is a spin-photon interface. Spins generally have long coherence times, so information can be stored for long times. For example, the quantum hardware system 140 may comprise a semiconductor body with luminescent defects which form the physical qubits of the modules 141. The semiconductor body may comprise silicon or similar semiconductor materials. For example, the semiconductor material may include natural silicon, silicon carbide, silicon germanium, isotopically purified paramagnetic silicon, a so-called silicon vacuum or combinations thereof. The semiconductor body may be processed to remove a large fraction of non-paramagnetic isotopes (e.g., silicon-29). The semiconductor body may comprise enriched or purified silicon that has been processed to remove some to nearly all non-zero-nuclear spin isotopes, such as silicon-29. Purified silicon includes material enriched to various levels ofsilicon-28, such as, 99%, 99.9%, and 99.99%. Purified silicon includes material enriched with silicon-28. Purified silicon includes silicon where spectroscopic linewidths are at least ten to hundred times sharper than in natural silicon. The semiconductor body may also comprise an epilayer of isotopically purified silicon, grown on top of a natural silicon wafer.

[0084] The luminescent defects may comprise luminescence centres or colour centres. The luminescent defects may comprise radiation damage centres. The luminescent defects may comprise T centres, as described in any of US 2022 / 0366290 A1, US 2022 / 0327416 A1, and US 2024 / 0012749 A1, which are hereby incorporated by reference in their entirety.

[0085] The physical qubits of the modules 141 can be optically connected via a plurality of optical connections. Each optical connection provides a path that connects a pair of physical qubits of the modules 141 and enables performing operations between these physical qubits. Different optical connections may comprise different hardware components, i.e., different routes including switches, detectors, and the like. In particular, the number of switches, detectors, and the like can vary for different optical connections.

[0086] In embodiments where the physical qubits of the modules 141 are associated with T centres, pairs of T centres may be optically connected by means of a telecom photonic interface (i.e., operating in the telecom frequency band, such as the telecom O-band) of the T centre in the silicon substrate. In some embodiments, each T centre can be optically connected to any other T centre, i.e., all-to-all optical connection between the T centres is possible. The optical connection between a pair of T centres may comprise at least one photonic waveguide integrated in the silicon substrate (“on-chip”). In addition or alternatively, the optical connection can also comprise optical fibres or other components which can be external to the silicon substrate (“off-chip”). In particular, the modules 141 can be arranged in different chips and the coupling devices 142 can comprise at least some off-chip hardware components for coupling physical qubits on different modules 141.

[0087] The optical connection may be configured to facilitate entanglement between T centres. The entanglement can be generated and / or distributed by photons which are transmitted over the optical connections connecting the T centres. The quantum hardware system 140 can be configured to prepare maximally entangled Bell pairs, using the T centres.

[0088] The quantum hardware system 140 may further include means for generating and applying pulses for manipulating the state of physical qubits of the modules 141. The quantum hardware system 140 may be used for any practical application in quantum sensing, quantum computing or quantum communication.

[0089] Quantum sensing comprises measurements which utilize quantum effects such as entanglement, interference or quantum state squeezing.

[0090] Quantum computing comprises any processing of information based on quantum effects, such as superpositions of physical qubits of the modules 141 and (de-)coherence or entanglement of physical qubits of the modules 141.

[0091] Quantum communication comprises the transmission of classical information or of quantum states between different devices, e.g., between the quantum hardware system 140 and another quantum hardware system based on quantum effects as described above.

[0092] Quantum circuits of the quantum hardware system 140 are designed for carrying out the necessary steps to implement a given quantum algorithm. Logical quantum circuits can be implemented by physical quantum circuits. Logical quantum circuits comprise a plurality of logical operators, such as gates.

[0093] The information processing system 100 further comprises a Clifford gate implementing device 110. The Clifford gate implementing device 110 comprises at least one processor 111, and at least one memory 112 (i.e., a tangible computer-readable, or processor-readable storage device) communicatively coupled to the at least one processor 111.

[0094] The processor 111 can be a logic processing unit and can comprise a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller (µC), an integrated circuit (IC), an application-specific integrated circuit (ASIC), adigital signal processor (DSP), a field programmable gate array (FPGA), a program logic unit (PLU), a network processor (NP) or a combination thereof.

[0095] The memory 112 can comprise at least one of a magnetic hard disk, an optical disc (e.g., compact disc, digital video disc, Blu-ray disc), a solid state disc (SSD), a magneto-optical memory or a hard disc drive (HDD). For example, the memory 112 can comprise a volatile semiconductor or solid state memory, e.g., a random access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM). The memory 112 can comprise a non-volatile semiconductor or solid state memory, e.g., a read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), or the like.

[0096] The memory 112 stores processor-executable instructions and / or processor-readable data associated with the operation of the Clifford gate implementing device 110. The processor-executable instructions and / or processor-readable data can comprise an operating system, peripheral drivers, server instructions, application instructions, calibration instructions, or communication channel instructions.

[0097] The Clifford gate implementing device 110 further comprises a user interface 113, having at least one of a display, a keyboard, a touch screen, a mouse, buttons, a microphone, loudspeakers and the like. A user may provide or receive information regarding the operation of the information processing system 100 via the user interface 113.

[0098] Although the user interface 113 is illustrated as a component of the Clifford gate implementing device 110, in some embodiments, the user interface 113 is external to the information processing system 100. For example, the Clifford gate implementing device 110 can be implemented as a remote server which a user can access via the user interface 113.

[0099] An interface 114 is provided for connecting the processor 111 with a compiler 120, an actuator device 130, and a cooling device 150. The interface 114 can be any port or link or interface capable of communicating information toanother system, e.g., a wired connection or a wireless connection (e.g. wireless LAN, Bluetooth®, ethernet, or the like).

[0100] All of the components of the Clifford gate implementing device 110 described above can be controlled and / or can communicate over at least one bus 115. The processor 111 may be configured to control the interface 114 and user interface 113 of the Clifford gate implementing device 110.

[0101] The cooling device 150 may maintain the quantum hardware system 140 at a predefined operating temperature of the quantum hardware system 140. The operating temperature may be a cryogenic temperature, e.g., in a range from about 1 mK to 77 K, or more particularly in a range from about 1.5 K to 4 K. In some embodiments, the cooling device 150 may be omitted. The quantum hardware system 140 may, optionally, also be kept at constant air pressure, e.g., a stable vacuum.

[0102] The actuator device 130 can comprise a plurality of actuators. For example, the actuator device 130 can comprise an electromagnet to apply a time-invariant electric field, a time-varying electric field, or a pulsed electric field to the quantum hardware system 140.

[0103] The compiler 120 can compile a quantum circuit to obtain an executable i.e., can convert the quantum circuit into machine code that is readable by a controller of the quantum hardware system 140.

[0104] In the following, operation of the information processing system 100 is described. The processor 111 may execute instructions stored in the memory 112 to implement a Clifford gate on the quantum hardware system 140.

[0105] In general, a quantum mechanical operation on one or more qubits is described by a unitary operator. An important class of unitary operators is described by the Pauli group. The single-qubit Pauli groupis the group of Pauli operators that can each act on the qubit. There are 16 Pauli operators. Up to a complex phase, there are 3 distinct non-trivial operators, the Pauli X, Y, and Z operators. The single-qubit Pauli group is formed by all products of the Pauli X, Y, and Z operators. The Pauli X operators are also denoted as bit-flip operatorsbecause they exchange the two basis states in the computational basis. The Pauli Z operators are also known as phase-flip operators because they change the relative phase of the two basis states in the computational basis.

[0106] The term “n-qubit Pauli group J>n” (or simply: “Pauli group”) denotes the group formed by all length n tensor products of elements of the single-qubit Pauli group where n is an integer greater than 1. The Pauli group is a non-Abelian group, i.e., group elements in general do not commute. The elements of the n-qubit Pauli group are denoted as Pauli operators. The Pauli group comprises n-qubit Pauli X operators which are obtained by applying the (1 -qubit) Pauli X operator to any subset of the n qubits while applying the identity operator to the other qubits. Similarly, the Pauli group comprises n-qubit Pauli Z operators which are obtained by applying the (1 -qubit) Pauli Z operator to any subset of the n qubits while applying the identity operator to the other qubits.

[0107] The term “Clifford group” denotes the group of so-called Clifford gates (or Clifford operators) which are unitary operators that preserve the Pauli group under conjugation. This means that the n-qubit Clifford group C£nis the set of all operators V that map Pauli operators P in the n-qubit Pauli group 풫nto other Pauli operators in the n-qubit Pauli group 풫nunder conjugation:풞ℓn= {V: VPV† ∈ 풫n, ∀P ∈ 풫n}.

[0108] The n-qubit Clifford group C£nis said to “normalize” the n-qubit Pauli group J’n. The fact that the Clifford operators map Pauli operators to other Pauli operators under conjugation makes the Clifford operators easier to describe. Up to a phase, a Clifford operator V can be described by the images of the 2n Pauli operators XLand Z7- under conjugation by V. A Clifford operator can therefore be described by a 2n x (2n + 1) matrix (with one column tracking signs) which is much more efficient than a general unitary operator which can only be fully described by a 2nx 2nmatrix.

[0109] For example, conjugating the Pauli X operator by the Hadamard gate H gives the Pauli Z operator:HXH† = Z.

[0110] Similar relations hold for the Pauli Y and Z operators. The Hadamard gate H is an example of a Clifford operator.

[0111] The Clifford group is generated by the Hadamard gate H, the phase gate S, and the CNOT gate. Herein, a list of gates or operators is said to “generate” a larger collection of gates or operators, if every element of the larger collection can be composed as products of elements from the list of gates. These compositions may be arbitrarily long and may contain repetitions.

[0112] Every element of the Clifford group is uniquely specified (up to a phase) by specifying where the Clifford operator maps a generating set of the Pauli group under conjugation. Advantageously, the Clifford group requires only a single additional gate to form a universal gate set.

[0113] The Hadamard gate H, the phase gate S, and the CNOT gate generate other Clifford group elements such as the Controlled-Z gate (denoted as CZ gate) and the SWAP gates.

[0114] Clifford operators play an important role in QEC. A QEC code can be defined by specifying a code space which is a vector subspace of a Hilbert space and is spanned by so-called code words of the QEC code. A code word is a state which encodes some data. A code word corresponds to a logical state of the QEC code. A QEC code is used to protect quantum information that is processed in the computation from errors due to quantum noise, e.g., decoherence.

[0115] A QEC code is in general a mapping of k qubits onto n qubits, where n > k. The k qubits are elements of a Hilbert space of dimension 2fe. The n qubits are elements of a Hilbert space of dimension 2". Herein, the k qubits are the “logical qubits” or “encoded qubits” that are to be protected from error, e.g., a thresholdamount of error. The n qubits are the “physical qubits” implementing the logical qubits. The additional n - k qubits allow the k logical qubits to be stored in a redundant fashion so that the encoded information is less susceptible to noise or other disturbances.

[0116] A QEC code with block size n, encoded qubits k, and distance d is denoted as an “[[n, k, d]] QEC code,” where the distance d is the minimum support of a non-identity logical operator in the code. The distance d sets a bound on the number of errors the QEC code can detect and correct. For example, if there are fewer than errors, a perfect decoder can identify and correct these errorswithout changing the intended quantum state. On the other hand, if there are more than errors, a perfect decoder may be unable to correct all the errors.

[0117] In QEC codes, errors are often modelled as Pauli operators, i.e., elements of the Pauli group J>n. Because the Clifford operators preserve the Pauli group under conjugation, Clifford operators can be used to track and correct errors.

[0118] Elements of the n-qubit Pauli group J>ncan be represented (up to a phase) as elements of GF(2)2n, where GF(2) denotes the finite field of order 2, i.e., the field with two elements that can be labeled 0 and 1, having an additive and a multiplicative structure. The representation is called the binary symplectic representation of the n-qubit Pauli group J>n. The representation is obtained by taking the j-th register of an element of the n-qubit Pauli group J>nand setting the j-th position in the binary vector in GF(2)2" to the power of the X operator at the i-th position and setting the (j + n)-th position to the power of the Z operator at the j-th position. For example, the 4-qubit Pauli operator XIYZ is mapped to:(10100011)with the first four bits corresponding to the X-part and the last four bits corresponding to the Z-part.

[0119] Further, it is known that the n-qubit Clifford group C-Enmodulo the n-qubit Pauli groupis isomorphic to the symplectic group Sp(2n, GF(2)) of order 2n over the finite field GF(2), i.e.:C4 / 5’„ = Sp(2n, GF(2)).

[0120] This representation ofis known as the tableau representation. The tableau representation tracks the image of the Pauli X operators and the Pauli Z operators under conjugation, up to a sign. The symplectic group Sp(2n, GF(2)) is the group of matrices with coefficients in the finite field GF(2) that preserve a binary symplectic structure matrix fl defined aswhere Inis the n x n-dimensional unity matrix. That is, the symplectic group Sp(2n, GF(2)) comprises matrices M which satisfyMTQ. M = n,where MTdenotes the transpose of the matrix M.

[0121] The groupof operators generated by Hadamard gates H and SWAP circuits, i.e.,Mn= ⟨H, SWAP⟩,corresponds to the group of symplectic permutation-like operators in the Clifford group (i.e., symplectic analogues of permutations). In other words, the image of the groupof operators generated by Hadamard gates H and SWAP circuits in Sp(2n, GF(2)) is the group given by the intersection of the symplectic group Sp(2n, GF(2)) of order 2n over the finite field GF(2) and the symmetric group S2n(GF(2)) of order 2n over the finite field GF(2),Sp(2n, GF(2)) n S2n(GF(2)).

[0122] Z-diagonal Clifford operators form a subgroup of the Clifford group. The Z-diagonal Clifford operators are operators that act diagonally on the computational basis and are generated by single-qubit phase gates Siand two-qubit controlled- Z gates CZi,j, i.e.:®풟n(Z) = ⟨Si, CZi,j| 1 ≤ i, j ≤ n⟩.

[0123] Up to Pauli operators, the Z-diagonal Clifford operators are represented by symplectic matrices of size 2n x 2n of the form(In0\ In / for symmetric binary matrices L of size n x n. The diagonal and off-diagonal entries of the symmetric binary matrix L determine the presence of S and CZ gates, respectively. The maximal column weight of L corresponds to the depth of the circuit. Herein, the maximal column weight is the maximal number of non-zero elements in a single column.

[0124] The Z-diagonal Clifford operators have particularly efficient injection protocols when combined with the transversal CNOT operation, which is a gate that many codes possess.

[0125] X-diagonal Clifford operators form a subgroup of Clifford group. The X-diagonal Clifford operators are operators that act diagonally on the X-eigenbasis and are generated by Hadamard-rotated single-qubit phase gates HiSiHiand Hadamard-rotated two-qubit controlled-Z gatesCZij HtHj, i.e.,:2)„(X) = ( HiSiHi, HiHjCZi,jHiHj| 1 < i, j < n ).

[0126] Up to Pauli operators, the X-diagonal Clifford operators are represented by symplectic matrices of the form(In M\\0 ln)’for symmetric binary matrices M of size n x n. The diagonal and off-diagonal entries of the symmetric matrix M determine the presence of HSH andH⊗2CZ H⊗2gates, respectively. The maximal column weight of M corresponds to the depth of the circuit.

[0127] The processor 111 determines a symplectic matrix representation of a provided Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators.

[0128] Then, the Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate.

[0129] The Clifford gate can be part of a virtual quantum circuit which is to be mapped to a physical quantum circuit that is then executed on the quantumhardware system 140. The mapping may be based on hardware considerations, i.e., based on the characterization of the quantum hardware system 140.

[0130] The compiler 120 can further optimize the sequence of quantum gates. The compiler 120 might optimize for at least one of a circuit depth of the sequence of quantum gates, a gate count (i.e., the number of gates in the sequence), a specific type of gate count, the number of ancilla qubits required to implement the gates in the sequence, and the like. The compiler 120 then compiles the physical quantum circuit and provides an executable to the quantum hardware system 140. The executable is then output to a controller of the quantum hardware system 140 for execution. Thus, the logical quantum circuit (and in particular the sequence of quantum gates corresponding to the Clifford gate) is implemented on the quantum hardware system 140.

[0131] At run-time, the hardware physical qubits in the modules 141 of the quantum hardware system 140 are prepared in initial states and physical quantum gates and measurements are performed on the hardware physical qubits to perform computations. For example, the state of the corresponding logical qubits are changed. Further, stabilizer measurements can be carried out to extract information about the locations of errors to use in QEC.

[0132] In some embodiments, the representation of the Clifford gate is performed by a first device (e.g., the Clifford gate implementing device 110) which is separate and distinct from a second device (e.g., the compiler 120) which synthesizes the representation of the Clifford gate, i.e. determines the physical gates sequence depending on the architecture of the quantum hardware system 140. In other embodiments, a single device can perform both the representation and the synthesis.

[0133] Figure 2 shows a flow diagram of a method for implementing a Clifford gate on a quantum hardware system, for example the quantum hardware system 140 of Figure 1. The method steps can in some embodiments be performed by the information processing system 100 of Figure 1, for example by the processor 111 of the Clifford gate implementing device 110 of the information processing system 100.

[0134] In step S201, a description of a Clifford gate is obtained, e.g., as an operator acting on logical qubits. The description can be obtained from a user, e.g., via user interface 113.

[0135] In step S202, the Clifford gate is represented as a symplectic matrix that factorizes as a product of at least five symplectic matrices. The at least five matrices can comprise a matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator. Preferably, the depth-one X-diagonal or Z-diagonal Clifford operator is a leftmost or rightmost matrix but the specification is not restricted to this order of matrices.

[0136] For example, the symplectic matrix can be factorized as the product of five symplectic matrices in one of the following ways:r,i ’ ^z,i ■ r,2 ’ z,2 ■ Dx>Dx’ CZ,i ■ CX 1■ CZ2■ CX 2,Cz,i ’,i ’ Cz,2 ’ r,2 ’ Dz>Dz’ ",i ’ ^z,i ’ r,2 ’ z,2 ■

[0137] Here, CX 1denotes a matrix that corresponds to a first X-diagonal Clifford operator, CZ 1denotes a matrix that corresponds to a first Z-diagonal Clifford operator, CX 2denotes a matrix that corresponds to a second X-diagonal Clifford operator, Cz 2denotes a matrix that corresponds to a second Z-diagonal Clifford operator, Dxdenotes a matrix that corresponds to a depth-one X-diagonal Clifford operator,and Dzdenotes a matrix that corresponds to a depth-one Z-diagonal Clifford operator. In any of the above factorizations, the matrices alternate between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators.

[0138] In step S203, the Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate. In someembodiments, multiple representations of the Clifford gate are computed. For example, at least two of the above four representations can be computed. For each representation, the Clifford gate is synthesized into a respective sequence of quantum gates. One of the representations can be selected for implementing the Clifford gate on the quantum hardware system. The representation is selected based on a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system 140. For example, the cost metric can be a circuit depth, a gate count, gate depth, qubit count, connectivity, gate fidelity, quantum circuit fidelity, and the like. The cost metric can also specifically depend on the architecture of the quantum hardware system 140, e.g., can relate to the fewest number of gates requiring long-range connectivity.

[0139] In step S204, the sequence of quantum gates is implemented on the quantum hardware system 140. In some embodiments, the representation of the Clifford gate is performed at runtime of the quantum hardware system 140. In other embodiments, the Clifford gate is synthesized into the sequence of quantum gates at compile time. In some embodiments, the representation of the Clifford gate is performed at runtime of the quantum hardware system 140 when adaptive circuits are performed which will change the Clifford operation that needs to be implemented. In some embodiments, the representation of the Clifford gate is performed at compile time if no adaptive circuits are performed.

[0140] Figure 3 shows a flow diagram of a method for implementing a Clifford gate on a quantum hardware system, for example the quantum hardware system 140 of Figure 1. The method steps can in some embodiments be performed by the information processing system 100 of Figure 1, for example by the processor 111 of the Clifford gate implementing device 110 of the information processing system 100.

[0141] In step S301, a description of a Clifford gate is obtained, e.g., as an operator acting on logical qubits. The description can be obtained from a user, e.g., via user interface 113.

[0142] In step S302, a representation of the Clifford gate as a sequence of at least five operators is determined. The at least five operators can comprise a depth-oneX-diagonal or Z-diagonal Clifford operator. Preferably, the depth-one X-diagonal or Z-diagonal Clifford operator is a leftmost or rightmost operator in the sequence of the at least five operators but the specification is not restricted to this order of operators.

[0143] For example, the Clifford gate can be represented as a sequence of Clifford operators in one of the following ways:OX,1OZ,1OX,2OZ,2OX,OXOZ,1OX,1OZ,2OX,2,OZ,1OX,1OZ,2OX,2OZ,OZOX,1OZ,1OX,2OZ,2.

[0144] Here, OX 1denotes a first X-diagonal Clifford operator, OZ 1denotes a first Z-diagonal Clifford operator, OX2denotes a second X-diagonal Clifford operator, Oz 2denotes a second Z-diagonal Clifford operator, Ozdenotes a depth-one Z-diagonal Clifford operator, and Oxdenotes a depth-one X-diagonal Clifford operator. In any of the above factorizations, the operators alternate between X-diagonal Clifford operators and Z-diagonal Clifford operators.

[0145] In step S303, the Clifford gate is synthesized into a sequence of quantum gates, based on the representation of the Clifford gate as a sequence of operators. In some embodiments, multiple representations of the Clifford gate are computed. For example, at least two of the above four representations can be computed. For each representation, the Clifford gate is synthesized into a respective sequence of quantum gates. One of the representations can be selected for implementing the sequence of quantum gates on the quantum hardware system. The representation is selected based on a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system 140.

[0146] In step S304, the Clifford gate is implemented on the quantum hardware system 140. In some embodiments, the representation of the Clifford gate isperformed at runtime of the quantum hardware system 140. In other embodiments, the Clifford gate is synthesized into the sequence of quantum gates at compile time.

[0147] Figure 4 shows a flow diagram of a method for executing a logical quantum circuit on a quantum hardware system, for example the quantum hardware system 140 of Figure 1. The method steps can in some embodiments be performed by the information processing system 100 of Figure 1, for example by the processor 111 of the Clifford gate implementing device 110 of the information processing system 100.

[0148] In step S401, a description of a logical quantum circuit is obtained which specifies a quantum algorithm. The logical quantum circuit generally comprises a sequence of operations, such as quantum gates, measurements, and initializations of logical qubits to predefined values. Herein, logical quantum gates are basic blocks that operate on a small number of logical qubits. In order to implement the logical quantum circuit, the logical qubits are implemented by (a generally larger number of) physical qubits of the quantum hardware system. The logical quantum circuit comprises at least one Clifford gate and in general a plurality of Clifford gates.

[0149] In step S402, representations for at least one Clifford gate, and in some embodiments all of the Clifford gates are determined. For example, a symplectic matrix representation of the Clifford gate can be determined that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators, as explained with regard to step S202 of the method illustrated in Figure 2. In other embodiments, a sequence of at least five operators corresponding to the Clifford gate is determined, where the at least five operators alternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators, as explained with regard to step S302 of the method illustrated in Figure 3. The Clifford gates are synthesized into sequences of quantum gates, acting on the logical qubits.

[0150] In step S403, the logical quantum circuit is implemented as a virtual quantum circuit by mapping logical qubits of the logical quantum circuit to physical qubits according to a QEC code. Logical gates in the logical quantum circuit are implemented by physical gates or more generally a sequence of physical gates. The physical gates are not necessarily already gates acting on physical qubits of a specific quantum hardware. Rather, the physical gates can act on “physical” (or virtual) qubits of the virtual quantum circuit. In particular, the Clifford gates are implemented in the virtual quantum circuit.

[0151] In step S404, the logical quantum circuit is executed on the quantum hardware system 140 by implementing the virtual quantum circuit on the quantum hardware system 140. Each “physical qubit” of the virtual qubit is now assigned to one or more physical qubits of the quantum hardware system 140. In particular, the sequences of quantum gates corresponding to the Clifford operator are implemented on the quantum hardware system 140.

[0152] Figure 5 shows a flow diagram of a method for resource estimation of executing a quantum algorithm on a quantum hardware system, for example the quantum hardware system 140 of Figure 1. The method steps can in some embodiments be performed by the information processing system 100 of Figure 1, for example by the processor 111 of the Clifford gate implementing device 110 of the information processing system 100.

[0153] In step S501, a description of the quantum algorithm is obtained. In some embodiments, a logical quantum circuit is obtained which specifies the quantum algorithm.

[0154] In step S502, representations for at least one Clifford gate, and in some embodiments all of the Clifford gates are determined. For example, a symplectic matrix representation of the Clifford gate can be determined that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators, as explained with regard to step S202 of the method illustrated in Figure 2. In other embodiments, a sequence of at least five operators corresponding to the Clifford gate is determined, where the at least five operatorsalternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators, as explained with regard to step S302 of the method illustrated in Figure 3.

[0155] In step S503, a resource estimation of executing the quantum algorithm on the quantum hardware system is made, based on the symplectic matrix representation of the at least one Clifford gate. In some embodiments, the at least one Clifford gate is synthesized into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate.

[0156] The resource estimation of executing the quantum algorithm on the quantum hardware system 140 can then be based on the sequence of quantum gates. For example, at least one cost metric is determined which indicates a cost of executing the quantum algorithm on the quantum hardware system 140. The cost metric can comprise a gate count, gate depth, qubit count, connectivity, gate fidelity, quantum circuit fidelity, and the like.

[0157] Figure 6 shows a flow diagram for a method for representing a Clifford gate as a symplectic matrix, being factorized into a product with at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators. The method can be used as a subroutine in step S202 of Figure 2, step S302 of Figure 3, step S402 of Figure 4, or step S502 of Figure 5.

[0158] According to the method of Figure 6, a Clifford gate is already represented as a symplectic matrix, as explained, e.g., with reference to step S201 of Figure 2. The symplectic matrix corresponding to the Clifford gate is a 2n x 2n-dimensional binary symplectic matrix ∈ Sp(2n, GF(2)) which can be written as follows:χ = (A B\C DJfor n x n-dimensional binary matrices A, B, C and D. The matrix has a 2 x 2-block form with blocks A, B, C and D.

[0159] In a first step S601, it is determined whether the upper left block A of the matrix is invertible. If the upper left block of left block A is invertible, the following step (i.e., step S602) is skipped.

[0160] Otherwise, in step S602, a first factorization is determined. According to the first factorization, the matrix is decomposed as follows:(A B) (InK) (A B)=(c oH J c D)’ Equation (1)where Indenotes the n x n-dimensional unity matrix, with an invertible n x n- dimensional binary matrix A ∈ GL(n, GF(2)), with n x n-dimensional binary matrices B, C and D, and with a symmetric n x n-dimensional binary matrix K of weight at most equal to 1.(I K\” j I on both sides from the left, one U *n / finds:in (^ BA f^n(A _ (A B\.0 ij Ac DJ \0 In) \0 in) VC D) ~ vc D)’because (InK / 0 In) squares to the identity matrix. Therefore, K must be determinedU 'n / such that the upper left block ofin K\ (A Bo in) Ac D)corresponding to A, i.e., A + KC, has full rank and is therefore invertible. The (A R~ " is invertible so that the submatrixC )\4\.c)has full rank.

[0162] An invertible transformation is determined that performs column operations on this submatrix until it is in the subblock formA'£'with A' an n x r matrix of rank r and C" an n x (n- r) matrix of rank n - r.

[0163] Next, an n x n permutation is determined that maps the pivots of C" to the last n - r rows. Permuting both the top and bottom rows according to P along with additional column operations yields00FIn-rwhere A"and E are r x r matrices, A'" and E' are (n-r) xr matrices, and F is an r x (n - r) matrix. Because A and C are subblocks of a symplectic matrix, the following condition holds:ATC = CTA.

[0164] This implies:'ET(E')T(X")T(X"')T\ ( A'" 0 I / O O\FTin-ro o ) \E fI vo or\ \ L F-t' l In-r / /

[0165] In particular:(A")TF = (X'")T.

[0166] In other words, the rows of A"' are in the span of the rows of A”, so that the rank of A' is simply the rank of A", and thus A" is full rank.

[0167] Next, any symmetric (n - r) x (n - r) permutation matrix S is determined. Then:Ir0 0 o \ / A" 0 ' A" 0 0 In-r 00I I 0 A'" + SE' S o o iro r I E F E F.0 0 0 ln-rJ \E' In-r. E' In-r

[0168] The upper n x n matrix has now full rank.

[0169] Next, the following matrix is determined:(I K\” j I is determined as follows:U *n / (In K In0.0i.e., K is set to PTS'P. Because column operations do not change the rank of the first n rows nor does left-multiplication by a full-rank n x n matrix,In) \C)yields a full rank n x n matrix in the first n rows. For any such choice of S', the (I K\” j I is a depth-one Z-diagonal Clifford operator.U *n /

[0171] According to Equation (1), the matrix therefore decomposes into a product of two matrices, namely a matrix corresponding to a depth-one Z-diagonal Clifford operator,K\Dz=0and a matrix that has a 2 x 2-block form, wherein an upper left block is an invertible matrix:( vAc DBY)

[0172] In step S603, a second factorization is determined, The matrix isfurther decomposed into a product of four matrices as follows:ACz, 2 Equation (2). C

[0173] Herein, CX,1and CX 2are matrices that correspond to first and second X-diagonal Clifford operators, respectively, and, CZ 1and CZ2are matrices that correspond to Z-diagonal Clifford operators.

[0174] If the upper left block matrix A of the matrix was already invertible in step S601, the matrix itself can be factorized instead of in Equation (2).

[0175] The matrix is symplectic which gives the following constraints:ATC + CTA = 0, Equation (3a) BTD + DTB = 0, Equation (3b) CTB = ATD + In, Equation (3 c)

[0176] The first and second X-diagonal Clifford operators CX,1and CX 2, respectively, and the first and second Z-diagonal Clifford operators CZ 1and CZ 2, respectively, have the following general form:0InM'In.nwhere the matrices L, M, N, Q are symmetric n x n-dimensional matrices.

[0177] Plugging these matrices into Equation (2) gives the following four relations (one for each n x n-dimensional block):A = In+ MN, Equation (4a) B = M + Q + MNQ, Equation (4b) C = L + N + LMN, Equation (4c) D = In+ LM + NQ + LQ + LMNQ. Equation (4d)

[0178] To show that Equation (2) can be satisfied, it suffices to show that Equations (4a) to (4d) can be satisfied for a specific choice of symmetric n x n-dimensional matrices L, M, N, Q.

[0179] Equation (4a) follows from the fact that each square matrix can be written as the product of two symmetric matrices, which is proven in O. Taussky, “The role of symmetric matrices in the study of general matrices”, Linear Algebra and its Applications, Vol. 5, Issue 2, 1972, pages 147-154, which is hereby incorporated by reference in its entirety.

[0180] This implies that the square matrix A - Incan be written as the product MN of two symmetric matrices M and N.

[0181] Equation (4b) is satisfied for the following choice of QQ = (A-1B + M).

[0182] Equation (4c) is satisfied for the following choice of L:L = (C + N)A-1.

[0183] Using the symplectic constraint of Equation (3a), one can show that the matrix L is symmetric. Similarly, using the symplectic constraint of Equation (3b), one can show that the matrix Q is symmetric.

[0184] Equation (4d) is now automatically satisfied. This can be shown using the above explicit forms of the matrices Q and L and using Equations (3a) to (3c).

[0185] As a result, by inserting the second factorization of Equation (2) into the first factorization of Equation (1), the matrix is now factorized as follows:X = DZ· CX,1· CZ,1· CX,2· CZ,2, Equation (4)where Dzis a matrix that corresponds to a depth-one Z-diagonal Clifford operator, CX 1and CX 2are matrices that correspond to first and second X-diagonal Clifford operators, respectively, and, CZ1and CZ2are matrices that correspond to Z-diagonal Clifford operators.

[0186] In further embodiments, the symplectic representation of the Clifford gate is decomposed in one of the following ways:X = Dx■ CZ 1■ CX 1■ CZ 2■ CX 2,X=Cz,i ’ ’ Cz,2 ’ Cx,2 ’ Dz,X=,i ’ Cz,i • Cx 2• CZ 2■ Dx,where Dzis a matrix that corresponds to a depth-one Z-diagonal Clifford operator, Dxis a matrix that corresponds to a depth-one X-diagonal Clifford operator, CX 1and CX 2are matrices that correspond to X-diagonal Clifford operators, and, CZ1and CZ 2are matrices that correspond to Z-diagonal Clifford operators. It is to be noted that these matrices are generally different for different representations, e.g.,Dxcan be different for the representations in the first representation and third representation.

[0187] In summary, methods, devices, and systems have been described which can implement Clifford gates in an effective and efficient manner. In some implementations, there are only Abelian (commutative) operators or matrices which can be commuted through adjacent operators or matrices and / or can be combined with adjacent matrices.

[0188] The devices and systems described in the present disclosure may comprise electronic components and circuits known to those skilled in the art. Therefore, details of the circuitry and its components have not be explained in any greater extent than that considered necessary for the understanding and appreciation of the underlying concepts of the present disclosure.

[0189] Where reference is made to a component, such as a device, component, software module or the like, the reference to that component is intended to include as equivalents any component being functionally equivalent, i.e., performing the same function, even though the component is not necessarily structurally equivalent to the component that performs in the exemplary embodiments.

[0190] In the above description, embodiments have been described with reference to specific details, e.g., parts of a method, components, materials, and the like. A person skilled in the art will understand that embodiments may be implemented without one or more of these specific details.

[0191] AII of the US patents, US patent application publications, US patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification, or referred to on any application data sheet, are incorporated by reference in their entireties for all purposes herein.

[0192] A person skilled in the art may understand that certain method steps may be described or depicted in a particular order of occurrence while such specificity with respect to sequence is not actually required.

[0193] Phrases like “an embodiment” and “another embodiment” are used in the sense that particular features described in connection with the embodiment areincluded in at least one embodiment. Those phrases do not necessarily all refer to the same embodiment. Terms such as “first”, “second”, “third”, and so on, are used to distinguish between the elements described by these terms. These terms do not necessarily imply any temporal or other prioritization of such elements.

[0194] As used herein, the singular forms “a,” “one,” and “the “ are also intended to encompass the plural forms unless the context indicates otherwise. In addition, it is understood that the expressions “includes” and / or “including” when used in this specification relates to the presence of features, numbers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more features, numbers, steps, operations, elements and / or combinations thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed elements.

[0195] In this specification, the present disclosure has been described with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure is not limited to the described exemplary embodiments described and may be modified in various different ways.Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.

[0196] As used herein, the terms “about,” “approximately,” or “substantially” refer to a value, amount, or property that is close to the specified value, amount, or property. The value, amount, or property is such that a desired function or result is still achieved. According to an example, an amount may be less than 10%, 5%, 1%, or 0.1% of the specified amount, respectively.

[0197] Even if the disclosure has been described and illustrated with reference to illustrative embodiments, various modifications may be made without departing from the scope of the present disclosure as defined in the claims. Such modifications may comprise replacement of features, components and / or method steps with equivalent features, components and / or method steps; mixing of features, components and / or method steps from different embodiments; and / or omitting or combining features, components and / or method steps from describedembodiments. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.

Claims

WHAT IS CLAIMED IS:

1. A method for implementing a Clifford gate on a quantum hardware system, the method comprising the steps of:determining a symplectic matrix representation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators;synthesizing the Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate; andcausing the quantum hardware system to implement the sequence of quantum gates.

2. The method according to claim 1, wherein the at least five matrices comprise a matrix that corresponds to a depth-one X-diagonal orZ- diagonal Clifford operator.

3. The method according to claim 2, wherein the matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator is a leftmost matrix or a rightmost matrix in the product.

4. The method according to any of the preceding claims, wherein the at least five matrices comprise a first matrix CX 1that corresponds to a first X- diagonal Clifford operator, a second matrix Czthat corresponds to a first Z-diagonal Clifford operator, a third matrix CX 2that corresponds to a second X-diagonal Clifford operator, a fourth matrix CZ2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dxthat corresponds to a depth-one X-diagonal Clifford operator, wherein theproduct is one of the following:,1 ’ CZ,1 ’,2 ’ ^Z,2 ■ Dx>Dx’ CZ,i ■ Cx t• CZ 2■ CX 2■5. The method according to any of claims 1 to 3, wherein the at least five matrices comprise a first matrix CX 1that corresponds to a first X-diagonal Clifford operator, a second matrix CZ 1that corresponds to a first Z-diagonal Clifford operator, a third matrix CX 2that corresponds to a second X- diagonal Clifford operator, a fourth matrix CZ 2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dzthat corresponds to a depth-one Z-diagonal Clifford operator, wherein the product is one of the following:Cz,i ■ r,i ’ ^z,2 ■ Cx,2 ■ Dz>DZ· CX,1· CZ,1· CX,2· CZ,2.

6. The method according to any of the preceding claims, wherein factorizing the symplectic matrix representation of the Clifford gate comprises:factorizing the symplectic matrix representation of the Clifford gate into a matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator and a matrix that has a 2 x 2-block form, wherein an upper left block is an invertible matrix.

7. The method according to claim 6, wherein the matrix that has the 2 x 2- block form is factorized into a product of four matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators.

8. The method according to any of the preceding claims, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at runtime of the quantum hardware system.

9. The method according to any of the preceding claims, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at compile time.

10. The method according to any of the preceding claims, wherein the Clifford gate is part of a logical quantum circuit, and wherein the symplectic matrix representation of the Clifford gate is combined with a matrix representation of at least one adjacent quantum gate in the logical quantum circuit.

11. The method according to any of the preceding claims, wherein at least two factorizations of the symplectic matrix representation of the Clifford gate as products comprising at least five matrices are determined, wherein an order of the at least five matrices in the product differs for the at least two factorizations.

12. The method according to claim 11, wherein the Clifford gate is synthesized into a sequence of quantum gates for each of the at least two factorizations of the Clifford gate, and wherein one of the factorizations is selected for implementing the sequence of quantum gates on the quantum hardware system.

13. The method according to claim 12, wherein the factorization is selected based on a comparison of a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system, based on the respective factorization.

14. The method according to any of the preceding claims, wherein the quantum hardware system is a modular quantum hardware system.

15. A computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to any of claims 1 to 14.

16. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to any of claims 1 to 14.

17. A device for implementing a Clifford gate on a quantum hardware system, the device comprising:at least one processor; andat least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processorexecutable instructions which, when executed by the at least one processor, cause the at least one processor to:determine a symplectic matrix representation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to -diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators;synthesize the Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate; andcause the quantum hardware system to implement the sequence of quantum gates.

18. The device according to claim 17, wherein the at least five matrices comprise a matrix that corresponds to a depth-one X-diagonal orZ- diagonal Clifford operator.

19. The device according to claim 18, wherein the matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator is a leftmost matrix or a rightmost matrix in the product.

20. The device according to any of claims 17 to 19, wherein the at least five matrices comprise a first matrix CX 1that corresponds to a first X-diagonal Clifford operator, a second matrix CZ 1that corresponds to a first Z-diagonal Clifford operator, a third matrix Cx 2that corresponds to a second X- diagonal Clifford operator, a fourth matrix CZ 2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dxthat corresponds to a depth-one X-diagonal Clifford operator, wherein the product is one of the following:CX,1· CZ,1· CX,2· CZ,2· DX,Dx ’ CZi ■ Cx t• CZ 2■ CX 2.

21. The device according to any of claims 17 to 19, wherein the at least five matrices comprise a first matrix CX 1that corresponds to a first X-diagonal Clifford operator, a second matrix Czthat corresponds to a first Z-diagonal Clifford operator, a third matrix Cx 2that corresponds to a second X- diagonal Clifford operator, a fourth matrix CZ 2that corresponds to a second Z-diagonal Clifford operator, and a fifth matrix Dzthat corresponds to a depth-one Z-diagonal Clifford operator, wherein the product is one of the following:Cz,i ’ CXi ■ CZ 2■ CX 2■ Dz,Dz ’ CX,i ’ CZ,i ’ DX 2■ CZ 2.

22. The device according to any of claims 17 to 21, wherein factorizing the symplectic matrix representation of the Clifford gate comprises:factorizing the symplectic matrix representation of the Clifford gate into a matrix that corresponds to a depth-one X-diagonal or Z-diagonal Clifford operator and a matrix that has a 2 x 2-block form, wherein an upper left block is an invertible matrix.

23. The device according to claim 22, wherein the matrix that has the 2 x 2- block form is factorized into a product of four matrices alternating between matrices corresponding to X-diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators.

24. The device according to any of claims 17 to 23, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at runtime of the quantum hardware system.

25. The device according to any of claims 17 to 24, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at compile time.

26. The device according to any of claims 17 to 25, wherein the Clifford gate is part of a logical quantum circuit, and wherein the symplectic matrix representation of the Clifford gate is combined with a matrix representation of at least one adjacent quantum gate in the logical quantum circuit.

27. The device according to any of claims 17 to 26, wherein at least two factorizations of the symplectic matrix representation of the Clifford gate as products comprising at least five matrices are determined, wherein an order of the at least five matrices in the product differs for the at least twofactorizations.

28. The device according to claim 27, wherein the Clifford gate is synthesized into a sequence of quantum gates for each of the at least two factorizations of the Clifford gate, and wherein one of the factorizations is selected for implementing the sequence of quantum gates on the quantum hardware system.

29. The device according to claim 28, wherein the factorization is selected based on a comparison of a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system, based on the respective factorization.

30. The device according to any of claims 17 to 29, wherein the quantum hardware system is a modular quantum hardware system31. An information processing system comprising:a quantum hardware system;at least one processor; andat least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processorexecutable instructions which, when executed by the at least one processor, cause the at least one processor to:determine a symplectic matrix representation of the Clifford gate that factorizes as a product comprising at least five matrices alternating between matrices corresponding to -diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators;synthesize the Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate; andcause the quantum hardware system to implement the sequence of quantum gates.

32. The information processing system according to claim 31, wherein the quantum hardware system is a modular quantum hardware system.

33. A method for implementing a Clifford gate on a quantum hardware system, the method comprising the steps of:determining a sequence of at least five operators corresponding to the Clifford gate, wherein the at least five operators alternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators;synthesizing the Clifford gate into a sequence of quantum gates, based on the sequence of operators; andcausing the quantum hardware system to implement the sequence of quantum gates on the quantum hardware system.

34. The method according to claim 33, wherein the at least five operators comprise a depth-one X-diagonal or Z-diagonal Clifford operator.

35. The method according to claim 34, wherein the depth-one X-diagonal orZ- diagonal Clifford operator is a leftmost operator or a rightmost operator in the sequence.

36. The method according to any of claims 33 to 35, wherein the at least five operators comprise a first X-diagonal Clifford operator OX 1, a first Z- diagonal Clifford operator OZ 1, a second X-diagonal Clifford operator 0X 2, asecond Z-diagonal Clifford operator 0Z2, and a depth-one X-diagonal Clifford operator 0x, wherein the sequence is one of the following:OX,1OZ,1OX,2OZ,2Ox,OxOZ,1OX,1OZ,2OX,2.

37. The method according to any of claims 33 to 35, wherein the at least five operators comprise a first X-diagonal Clifford operator OX1, a first Z- diagonal Clifford operator OZ1, a second X-diagonal Clifford operator OX2, a second Z-diagonal Clifford operator OZ2, and a depth-one Z-diagonal Clifford operator 0z, wherein the sequence is one of the following:OZ,1OX,1OZ,2OX,2Oz,OzOX,1OZ,1OX,2OZ,2.

38. The method according to any of claims 33 to 37, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at runtime of the quantum hardware system.

39. The method according to any of claims 33 to 38, wherein synthesizing the Clifford gate into the sequence of quantum gates is at least partly performed at compile time.

40. The method according to any of claims 33 to 39, wherein the Clifford gate is part of a logical quantum circuit, and wherein the sequence of the at least five operators corresponding to the Clifford gate is combined with a sequence of at least five operators corresponding to an adjacent quantum gate in the logical quantum circuit.

41. The method according to any of claims 33 to 40, wherein at least two sequences of at least five operators corresponding to the Clifford aredetermined, wherein an order of the at least five operators corresponding to the Clifford gate differs for the at least two sequences.

42. The method according to claim 41, wherein the Clifford gate is synthesized into a sequence of quantum gates for each of the at least two sequences of at least five operators corresponding to the Clifford gate, and wherein one of the sequences of at least five operators corresponding to the Clifford gate is selected for implementing the sequence of quantum gates on the quantum hardware system.

43. The method according to claim 42, wherein the sequence of at least five operators corresponding to the Clifford gate is selected based on a comparison of a cost metric indicative of a cost of implementing the sequence of quantum gates on the quantum hardware system, based on the respective sequence of at least five operators corresponding to the Clifford gate.

44. The method according to any of claims 33 to 43, wherein the quantum hardware system is a modular quantum hardware system.

45. A device for implementing a Clifford gate on a quantum hardware system, the device comprising:at least one processor; andat least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processorexecutable instructions which, when executed by the at least one processor, cause the at least one processor to:determine a sequence of at least five operators corresponding to the Clifford gate, wherein the at least five operators alternate in the sequencebetween X-diagonal Clifford operators and Z-diagonal Clifford operators;synthesize the Clifford gate into a sequence of quantum gates, based on the sequence of operators; andcause the quantum hardware system to implement the sequence of quantum gates.

46. An information processing system comprising:a quantum hardware system;at least one processor; andat least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processorexecutable instructions which, when executed by the at least one processor, cause the at least one processor to:determine a sequence of at least five operators corresponding to the Clifford gate, wherein the at least five operators alternate in the sequence between X-diagonal Clifford operators and Z-diagonal Clifford operators;synthesize the Clifford gate into a sequence of quantum gates, based on the sequence of operators; andcause the quantum hardware system to implement the sequence of quantum gates.

47. A method for executing a logical quantum circuit on a quantum hardware system, the method comprising the steps of:determining, for at least one Clifford gate in the logical quantum circuit, a symplectic matrix representation that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X- diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators;synthesizing the Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate; andexecuting the logical quantum circuit on the quantum hardware system, based on the symplectic matrix representation of the at least one Clifford gate.

48. The method according to claim 47, wherein executing the logical quantum circuit on the quantum hardware system comprises the steps of:synthesizing the at least one Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate; andcausing the quantum hardware system to implementing the sequence of quantum gates.

49. A device for executing a logical quantum circuit on a quantum hardware system, the device comprising:at least one processor; andat least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processorexecutable instructions which, when executed by the at least one processor, cause the at least one processor to:determine, for at least one Clifford gate in the logical quantum circuit, a symplectic matrix representation that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X- diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators;synthesize the Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate, andexecute the logical quantum circuit on the quantum hardware system, based on the symplectic matrix representation of the at least one Clifford gate.

50. A method for resource estimation of executing a quantum algorithm on a quantum hardware system, the method comprising the steps of:determining, for at least one Clifford gate in the quantum algorithm, a symplectic matrix representation that factorizes as a product comprising at least five matrices alternating between matrices corresponding to X- diagonal Clifford operators and matrices corresponding to Z-diagonal Clifford operators; andmaking a resource estimation of executing the quantum algorithm on the quantum hardware system, based on the symplectic matrix representation of the at least one Clifford gate.

51. The method according to claim 50, wherein making the resource estimation further comprises the steps of:synthesizing the at least one Clifford gate into a sequence of quantum gates, based on the symplectic matrix representation of the Clifford gate;andmaking the resource estimation of executing the quantum algorithm on the quantum hardware system based on the sequence of quantum gates.

52. The method according to claim 50 or 51, wherein making the resource estimation further comprises the step of computing at least one cost metric indicative of a cost of executing the quantum algorithm on the quantum hardware system.

53. The method according to claim 52, wherein the at least one cost metric comprises at least one of a gate count, gate depth, qubit count, connectivity, gate fidelity, or quantum circuit fidelity.

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