Semiconductor integrated circuit device

Abstract

A semiconductor chip (3) is provided with a voltage selection circuit (31) that outputs the lower of power supply voltages VDD1, VDD2 as VDDA and VDDB. In a first semiconductor chip (1), an internal circuit (14) operates on the basis of VDD1, and an output buffer circuit (11) and an input buffer circuit (12) operate on the basis of VDDA. In a second semiconductor chip (2), an internal circuit (24) operates on the basis of VDD2, and an output buffer circuit (21) and an input buffer circuit (22) operate on the basis of VDDB.

Description

Semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device.

[0002] There are chiplet and 3D packaging technologies, in which a plurality of semiconductor chips (hereinafter simply referred to as "chips" where appropriate) are arranged on an interposer or stacked to form a semiconductor device. In chiplet and 3D packaging, signals may be transmitted and received between semiconductor chips with different power supply voltages.

[0003] For purposes such as power saving, there is AVS (Adaptive Voltage Scaling) technology, which acquires the operating characteristics of a semiconductor chip and performs control to supply an optimal power supply voltage to the chip according to manufacturing variations of the chip.

[0004] Patent Document 1 discloses a configuration of a semiconductor device that transmits and receives signals between a memory chip with a high power supply voltage and a logic chip with a low power supply voltage.

[0005] Patent Document 2 discloses the AVS technology.

[0006] U.S. Patent No. 9762244, U.S. Patent No. 7643365

[0007] For a plurality of semiconductor chips, (1) there are cases where their power supply voltages are different from each other, or (2) even if the standard (center) value of the power supply voltage is the same, application of AVS may cause a slight difference (about several hundreds of mV or less) in the used voltage. When communicating signals between these chips, it is necessary to address the following problems.

[0008] - When a signal is transmitted from chip 1 with a high power supply voltage to chip 2 with a low power supply voltage, an unnecessary current may flow from chip 1 to chip 2 in some cases. In addition, a signal with a voltage exceeding the withstand voltage that the transistors of chip 2 can tolerate may be input to chip 2 in some cases.

[0009] - When a signal is transmitted from chip 1 with a low power supply voltage to chip 2 with a high power supply voltage, an unnecessary current may occur in chip 2 in some cases. In addition, the logic (Low output / High output) of the input circuit may not be normally determined in some cases.

[0010] - When AVS technology is applied, manufacturing variations in the chip may result in the chip's power supply voltage being higher or lower than the standard value.

[0011] This disclosure provides a configuration for a semiconductor integrated circuit device that enables appropriate and stable communication between multiple chips with different power supply voltages.

[0012] A semiconductor integrated circuit device according to a first aspect of the present disclosure comprises a first semiconductor chip, the first semiconductor chip comprising: a first power node that receives a first power supply voltage from an external source; a second power supply node that receives a second power supply voltage from an external source; a first internal circuit to which the first power supply voltage is supplied; a voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as a third power supply voltage; a first output buffer circuit connected to the first internal circuit and having a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node; and a first input buffer circuit connected to the first internal circuit and having a second P-type transistor and a second N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node.

[0013] According to this embodiment, the first semiconductor chip includes a first power node that receives a first power supply voltage, a second power supply node that receives a second power supply voltage, and a voltage selection circuit that outputs the lower of the first and second power supply voltages as a third power supply voltage. In the first semiconductor chip, the first internal circuit operates based on the first power supply voltage, and the first output buffer circuit and the first input buffer circuit operate based on the third power supply voltage output by the voltage selection circuit. As a result, in a configuration in which the first semiconductor chip communicates with other semiconductor chips supplied with the second power supply voltage, even if the first power supply voltage and the second power supply voltage are different, the power supply voltages of the circuit parts that transmit and receive signals between the semiconductor chips can be made the same.

[0014] A semiconductor integrated circuit device according to a second aspect of the present disclosure comprises a first semiconductor chip and a second semiconductor chip that transmits and receives signals with the first semiconductor chip, wherein the first semiconductor chip includes a first power node that receives a first power supply voltage from an external source, a second power supply node that receives a second power supply voltage from an external source, a first internal circuit to which the first power supply voltage is supplied, a first voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as a third power supply voltage, a first output buffer circuit connected to the first internal circuit and having a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node, and a second P-type transistor and a second N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node. The second semiconductor chip comprises a first input buffer circuit having a 2N type transistor, a third power node that receives the first power supply voltage from an external source, a fourth power supply node that receives the second power supply voltage from an external source, a second internal circuit to which the second power supply voltage is supplied, a second voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as the fourth power supply voltage, a second output buffer circuit connected to the second internal circuit and having a third P type transistor and a third N type transistor connected in series between the node to which the fourth power supply voltage is supplied and a ground node, and a second input buffer circuit connected to the second internal circuit and having a fourth P type transistor and a fourth N type transistor connected in series between the node to which the fourth power supply voltage is supplied and a ground node.

[0015] According to this embodiment, the first semiconductor chip includes a first power node that receives a first power supply voltage, a second power supply node that receives a second power supply voltage, and a first voltage selection circuit that outputs the lower of the first and second power supply voltages as a third power supply voltage. In the first semiconductor chip, the first internal circuit operates based on the first power supply voltage, and the first output buffer circuit and the first input buffer circuit operate based on the third power supply voltage output by the first voltage selection circuit. The second semiconductor chip includes a third power supply node that receives a first power supply voltage, a fourth power supply node that receives a second power supply voltage, and a second voltage selection circuit that outputs the lower of the first and second power supply voltages as a fourth power supply voltage. In the second semiconductor chip, the second internal circuit operates based on the second power supply voltage, and the second output buffer circuit and the second input buffer circuit operate based on the fourth power supply voltage output by the second voltage selection circuit. This makes it possible to make the power supply voltage of the circuit portion that transmits and receives signals between the semiconductor chips the same, even if the first power supply voltage and the second power supply voltage are different in a configuration where the first semiconductor chip and the second semiconductor chip communicate with each other.

[0016] A semiconductor integrated circuit device according to a third aspect of the present disclosure comprises a first semiconductor chip, a second semiconductor chip that transmits and receives signals with the first semiconductor chip, and a third semiconductor chip, wherein the third semiconductor chip comprises a first power node that receives a first power supply voltage from an external source, a second power supply node that receives a second power supply voltage from an external source, a voltage selection circuit that outputs the lower of the first and second power supply voltages as a third power supply voltage and a fourth power supply voltage, a third power supply node that outputs the third power supply voltage, and a fourth power supply node that outputs the fourth power supply voltage, wherein the first semiconductor chip comprises a fifth power supply node that receives the first power supply voltage from an external source, a sixth power supply node connected to the third power supply node of the third semiconductor chip that receives the third power supply voltage, a first internal circuit to which the first power supply voltage is supplied, and a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node, connected to the first internal circuit The second semiconductor chip comprises a first output buffer circuit having an transistor, a first input buffer circuit connected to the first internal circuit and having a second P-type transistor and a second N-type transistor connected in series between a node to which the third power supply voltage is supplied and a ground node, and the second semiconductor chip comprises a seventh power supply node that receives the second power supply voltage from the outside, an eighth power supply node connected to the fourth power supply node of the third semiconductor chip and receiving the fourth power supply voltage, a second internal circuit to which the second power supply voltage is supplied, a second output buffer circuit connected to the second internal circuit and having a third P-type transistor and a third N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node, and a second input buffer circuit connected to the second internal circuit and having a fourth P-type transistor and a fourth N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node.

[0017] In this embodiment, the third semiconductor chip includes a voltage selection circuit that outputs the lower of the first and second power supply voltages as the third and fourth power supply voltages, outputting the third power supply voltage from the third power supply node and the fourth power supply voltage from the fourth power supply node. The first semiconductor chip includes a fifth power supply node that receives the first power supply voltage and a sixth power supply node that receives the third power supply voltage, with the first internal circuit operating based on the first power supply voltage and the first output buffer circuit and first input buffer circuit operating based on the third power supply voltage. The second semiconductor chip includes a seventh power supply node that receives the second power supply voltage and an eighth power supply node that receives the fourth power supply voltage, with the second internal circuit operating based on the second power supply voltage and the second output buffer circuit and second input buffer circuit operating based on the fourth power supply voltage. As a result, in a configuration in which the first semiconductor chip and the second semiconductor chip communicate, even if the first power supply voltage and the second power supply voltage are different, the power supply voltages of the circuit parts that send and receive signals between the semiconductor chips can be made the same.

[0018] According to this disclosure, appropriate and stable communication can be achieved between multiple chips with different power supply voltages in a semiconductor integrated circuit device.

[0019] Configuration examples of semiconductor chips that perform signal communication in a semiconductor integrated circuit device according to the embodiment Configuration examples of semiconductor chips that perform signal communication in a semiconductor integrated circuit device according to the embodiment Configuration examples of semiconductor chips that perform bidirectional signal communication in a semiconductor integrated circuit device according to the embodiment Configuration examples of semiconductor chips that perform bidirectional signal communication in a semiconductor integrated circuit device according to the embodiment (a), (b), and (c) are examples of the placement of the voltage selection circuit (a) is a configuration example in which a semiconductor chip equipped with a voltage selection circuit is provided, (b) and (c) are examples of the placement of the semiconductor chip in (a) Basic configuration of the voltage selection circuit (a) and (b) are examples of the circuit configuration of the voltage selection circuit Example of the circuit configuration of the voltage selection circuit

[0020] The embodiments will be described below with reference to the drawings.

[0021] Figures 1 and 2 show examples of the configuration of semiconductor chips that perform signal communication in a semiconductor integrated circuit device according to an embodiment. The semiconductor integrated circuit device shown in Figures 1 and 2 comprises a first semiconductor chip 1 (Chip 1), a second semiconductor chip 2 (Chip 2), and a third semiconductor chip 3 (Chip 3). Figure 1 shows a configuration in which a signal is sent from the first semiconductor chip 1 to the second semiconductor chip 2, and Figure 2 shows a configuration in which a signal is sent from the second semiconductor chip 2 to the first semiconductor chip 1. As shown in Figures 1 and 2, the first semiconductor chip 1 includes an output buffer circuit 11 and an input buffer circuit 12. The output buffer circuit 11 and the input buffer circuit 12 are connected to an internal circuit 14. The second semiconductor chip 2 also includes an output buffer circuit 21 and an input buffer circuit 22. The output buffer circuit 21 and the input buffer circuit 22 are connected to an internal circuit 24.

[0022] As shown in Figure 1, the first semiconductor chip 1 outputs a signal from the output buffer circuit 11. The signal output from the output buffer circuit 11 is output to the outside of the first semiconductor chip 1 from the signal output node SO1. The second semiconductor chip 2 has a signal input node SI2 that is connected to the signal output node SO1 of the first semiconductor chip 1 via wiring. The input buffer circuit 22 receives the signal input from the signal input node SI2.

[0023] As shown in Figure 2, the second semiconductor chip 2 outputs a signal from the output buffer circuit 21. The signal output from the output buffer circuit 21 is output to the outside of the second semiconductor chip 2 from the signal output node SO2. The first semiconductor chip 1 has a signal input node SI1 that is connected to the signal output node SO2 of the second semiconductor chip 2 via wiring. The input buffer circuit 12 receives the signal input from the signal input node SI1.

[0024] The first semiconductor chip 1 includes a power node 13 that receives a power supply voltage VDD1. The internal circuit 14 of the first semiconductor chip 1 is supplied with VDD1. The second semiconductor chip 2 includes a power node 23 that receives a power supply voltage VDD2. The internal circuit 24 of the second semiconductor chip 2 is supplied with VDD2.

[0025] The third semiconductor chip 3 includes a voltage selection circuit 31, a power supply node 32 that receives the power supply voltage VDD1, and a power supply node 33 that receives the power supply voltage VDD2. The voltage selection circuit 31 receives VDD1 and VDD2 and selects the lower of the two voltages VDD1 and VDD2 to output as power supply voltages VDDDA and VDDDB. That is, When VDD1 > VDD2: VDDDA = VDDDB = VDD2 When VDD1 = VDD2: VDDDA = VDDDB = VDD1 (= VDD2) When VDD1 < VDD2: VDDDA = VDDDB = VDD1

[0026] Although Figures 1 and 2 show the third semiconductor chip 3 as being provided separately from the first and second semiconductor chips 1 and 2, the configuration of this disclosure is not limited to this. As will be described later, the voltage selection circuit 31 in the third semiconductor chip 3 may be included in the first semiconductor chip 1 or in the second semiconductor chip 2. Alternatively, the voltage selection circuit 31 may be included in both the first semiconductor chip 1 and the second semiconductor chip 2, respectively. In these cases, it is not necessary to provide the third semiconductor chip 3 separately.

[0027] In the first semiconductor chip 1, the output buffer circuit 11 and the input buffer circuit 12 receive VDDA as the power supply voltage. The output buffer circuit 11 includes a P-type transistor P11 and an N-type transistor N11. The P-type transistor P11 and the N-type transistor N11 are connected in series between the node to which VDDA is supplied and the ground node. The input buffer circuit 12 includes a P-type transistor P12 and an N-type transistor N12. The P-type transistor P12 and the N-type transistor N12 are connected in series between the node to which VDDA is supplied and the ground node.

[0028] In the second semiconductor chip 2, the output buffer circuit 21 and the input buffer circuit 22 receive VDDB as the power supply voltage. The output buffer circuit 21 includes a P-type transistor P21 and an N-type transistor N21. The P-type transistor P21 and the N-type transistor N21 are connected in series between the node to which VDDB is supplied and the ground node. The input buffer circuit 22 includes a P-type transistor P22 and an N-type transistor N22. The P-type transistor P22 and the N-type transistor N22 are connected in series between the node to which VDDB is supplied and the ground node.

[0029] According to the configuration described above, the voltage selection circuit 31 selects and outputs the lower of the two voltages, VDD1 and VDD2, as VDDDA and VDDDB. The output buffer circuit 11 and input buffer circuit 12 of the first semiconductor chip 1 operate based on VDDDA. The output buffer circuit 21 and input buffer circuit 22 of the second semiconductor chip 2 operate based on VDDDB. In other words, even if VDD1 and VDD2 are different, the power supply voltage of the circuit portion that transmits and receives signals between the chips remains the same.

[0030] Therefore, no unnecessary current is generated during signal transmission or reception. Furthermore, signals with voltages exceeding the transistor's breakdown voltage are not input to the input / output buffer circuits. In addition, the logic of the input buffer circuit is properly established. This enables appropriate and stable communication between multiple chips with different power supply voltages.

[0031] Furthermore, in the above-described configuration, since the power supply voltage is changed only for the circuit portion that transmits and receives signals, the characteristic fluctuations of the semiconductor chip can be kept to a minimum. Therefore, the above-described configuration is also effective for semiconductor chips that optimize the power supply voltage by applying AVS technology.

[0032] Figures 3 and 4 show other configuration examples of semiconductor chips that perform signal communication in a semiconductor integrated circuit device according to the embodiment. In Figures 3 and 4, the first semiconductor chip 1 and the second semiconductor chip 2 perform bidirectional communication. That is, the first semiconductor chip 1 is equipped with a signal input / output node SIO1, and the second semiconductor chip 2 is equipped with a signal input / output node SIO2, and the signal input / output node SIO1 and the signal input / output node SIO2 are connected by wiring.

[0033] In Figure 3, the first semiconductor chip 1 has an output buffer circuit 11 that operates and outputs a signal to the signal input / output node SIO1 (out1). The second semiconductor chip 2 has an input buffer circuit 22 that operates and receives a signal from the signal input / output node SIO2 (in2).

[0034] In Figure 4, the second semiconductor chip 2 operates with its output buffer circuit 21, outputting a signal to the signal input / output node SIO2 (out2). The first semiconductor chip 1 operates with its input buffer circuit 12, receiving a signal from the signal input / output node SIO1 (in1).

[0035] The third semiconductor chip 3, as in the configuration shown in Figures 1 and 2, has a voltage selection circuit 31 that selects and outputs the lower of the two voltages, VDD1 and VDD2, as VDDDA and VDDDB. The output buffer circuit 11 and input buffer circuit 12 of the first semiconductor chip 1 operate based on VDDDA. The output buffer circuit 21 and input buffer circuit 22 of the second semiconductor chip 2 operate based on VDDDB. In other words, even if VDD1 and VDD2 are different, the power supply voltage of the circuit portion that transmits and receives signals between the chips remains the same.

[0036] Therefore, the configurations shown in Figures 3 and 4 can achieve the same effects as the configurations shown in Figures 1 and 2.

[0037] (Example of voltage selection circuit arrangement) Figure 5 shows an example of a voltage selection circuit arrangement. In the figure, (a) is a configuration in which the first semiconductor chip 1 is equipped with a voltage selection circuit 31, (b) is a configuration in which the second semiconductor chip 2 is equipped with a voltage selection circuit 31, and (c) is a configuration in which the first and second semiconductor chips 1 and 2 are each equipped with a voltage selection circuit 31.

[0038] In Figure 5(a), the first semiconductor chip 1 includes a power supply node 13 that receives VDD1, as well as a power supply node 15 that receives VDD2. The voltage selection circuit 31 receives VDD1 and VDD2 and selects and outputs the lower of the two voltages as VDDDA and VDDDB. VDDDA is used as the power supply voltage for the circuit portion of the first semiconductor chip 1 that transmits and receives signals. VDDDB is output externally from the power supply node 16 and sent to the power supply node 27 of the second semiconductor chip 2. VDDDB is used as the power supply voltage for the circuit portion of the second semiconductor chip 2 that transmits and receives signals.

[0039] In Figure 5(b), the second semiconductor chip 2 includes a power supply node 25 that receives VDD1 in addition to a power supply node 23 that receives VDD2. The voltage selection circuit 31 receives VDD1 and VDD2 and selects and outputs the lower of the two voltages as VDDDA and VDDDB. VDDDB is used as the power supply voltage for the circuit portion of the second semiconductor chip 2 that transmits and receives signals. VDDDA is output externally from the power supply node 26 and sent to the power supply node 17 of the first semiconductor chip 1. VDDDA is used as the power supply voltage for the circuit portion of the first semiconductor chip 1 that transmits and receives signals.

[0040] In Figure 5(c), the first semiconductor chip 1 includes a power node 13 that receives VDD1 and a power node 15 that receives VDD2. The second semiconductor chip 2 includes a power node 23 that receives VDD2 and a power node 25 that receives VDD1. The voltage selection circuit 31 of the first semiconductor chip 1 receives VDD1 and VDD2 and outputs the lower of the two voltages as VDDDA. VDDDA is used as the power supply voltage for the circuit portion of the first semiconductor chip 1 that transmits and receives signals. The voltage selection circuit 31 of the second semiconductor chip 2 receives VDD1 and VDD2 and outputs the lower of the two voltages as VDDDB. VDDDB is used as the power supply voltage for the circuit portion of the second semiconductor chip 2 that transmits and receives signals.

[0041] FIG. 6(a) shows a configuration in which the third semiconductor chip 3 includes a voltage selection circuit 31. The third semiconductor chip 3 includes a power supply node 32 that receives VDD1 and a power supply node 33 that receives VDD2. The voltage selection circuit 31 receives VDD1 and VDD2, selectively outputs the lower voltage of the two as VDDA and VDDB. VDDA is output to the outside from the power supply node 34 and sent to the power supply node 17 of the first semiconductor chip 1. VDDA is used as a power supply voltage for a circuit portion that transmits and receives signals of the first semiconductor chip 1. VDDB is output to the outside from the power supply node 35 and sent to the power supply node 27 of the second semiconductor chip 2. VDDB is used as a power supply voltage for a circuit portion that transmits and receives signals of the second semiconductor chip 2.

[0042] FIGS. 6(b) and 6(c) show arrangement examples of the semiconductor chips in the configuration of FIG. 6(a). In FIG. 6(b), the first semiconductor chip 1 and the second semiconductor chip 2 are arranged on an interposer 5, and the third semiconductor chip 3 is arranged between the first semiconductor chip 1 and the second semiconductor chip 2. In FIG. 6(c), the second semiconductor chip 2, the third semiconductor chip 3, and the first semiconductor chip 1 are stacked in this order on the interposer 5.

[0043] As described above, in the present disclosure, since the arrangement pattern of the voltage selection circuit is not limited, the area of the first semiconductor chip 1, the second semiconductor chip 2, or both can be reduced.

[0044] (Configuration Example of Voltage Selection Circuit) FIG. 7 is a circuit diagram showing a configuration example of a voltage selection circuit. The voltage selection circuit in FIG. 7 includes N-type transistors N1 and N2. VDD1 is applied to one node of the N-type transistor N1. VDD2 is applied to one node of the N-type transistor N2. The other nodes of the N-type transistors N1 and N2 are connected to each other, and the connected other node serves as a node nc that outputs VDDA and VDDB.

[0045] The N-type transistors N1 and N2 perform complementary operations in accordance with the magnitude of VDD1 and VDD2, and output the lower voltage of VDD1 and VDD2 from the node nc. That is, when VDD1>VDD2, the N-type transistor N1 is turned off, the N-type transistor N2 is turned on, and VDD2 is output from the node nc. When VDD1<VDD2, the N-type transistor N1 is turned on, the N-type transistor N2 is turned off, and VDD1 is output from the node nc.

[0046] The voltages of the gate na of the N-type transistor N1 and the gate nb of the N-type transistor N2 are controlled such that the N-type transistors N1 and N2 perform complementary operations in accordance with the magnitude of VDD1 and VDD2.

[0047] FIGS. 8(a) and 8(b) show examples of connection of the gates na and nb in the voltage selection circuit of FIG. 7. In the configuration of FIG. 8(a), VDD2 is supplied to the node na, and VDD1 is supplied to the node nb.

[0048] In the configuration of FIG. 8(b), a comparator 51 that compares the magnitude of VDD1 and VDD2 is provided. The output of the comparator 51 is low when VDD1>VDD2, and is high when VDD1<VDD2. The output of the comparator 51 is supplied to the node na, and is also supplied to the node nb via an inverter 52.

[0049] FIG. 9 is a circuit diagram in which the circuit configuration of the comparator 51 is additionally described for the configuration of FIG. 8(b). The resistors R1, R2, and R3 are set to resistance values such that leakage currents between VDD1 and VDD2 and between VDD1 / VDD2 and ground do not affect circuit operation. In FIG. 9, the resistors connected in series have the same resistance value, but they may have the same resistance value, or may have different resistance values that do not affect circuit operation. In addition, the resistors R4 and R5 are inserted to lower the power supply voltage of the comparator in consideration of the withstand voltage of the transistors. However, the resistors R4 and R5 may be omitted.

[0050] As described above, since the voltage selection circuit can be configured using two transistors of the same conductivity type, characteristic fluctuations due to manufacturing variations of the transistors can be suppressed, and design can be facilitated.

[0051] This disclosure enables appropriate and stable communication between multiple chips with different power supply voltages in a semiconductor integrated circuit device, which is useful, for example, for improving the performance of a System on Chip (SoC).

[0052] 1 First semiconductor chip 2 Second semiconductor chip 3 Third semiconductor chip 11 Output buffer circuit 12 Input buffer circuit 13 Power node 14 Internal circuitry 15, 16, 17 Power node 21 Output buffer circuit 22 Input buffer circuit 23 Power node 24 Internal circuitry 25, 26, 27 Power node 31 Voltage selection circuitry 32, 33, 34, 35 Power node VDD1 First power supply voltage VDD2 Second power supply voltage VDDDA Third power supply voltage VDDDB Fourth power supply voltage P11, N11, P12, N12, P21, N21, P22, N22 Transistors N1, N2 Transistors

Claims

1. A semiconductor integrated circuit device comprising a first semiconductor chip, the first semiconductor chip comprising: a first power node that receives a first power supply voltage from an external source; a second power supply node that receives a second power supply voltage from an external source; a first internal circuit to which the first power supply voltage is supplied; a voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as a third power supply voltage; a first output buffer circuit connected to the first internal circuit and having a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node; and a first input buffer circuit connected to the first internal circuit and having a second P-type transistor and a second N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node.

2. A semiconductor integrated circuit apparatus according to claim 1, comprising a second semiconductor chip that transmits and receives signals with the first semiconductor chip, wherein the first semiconductor chip includes a third power node that outputs a fourth power voltage which is the same voltage as the third power voltage to the outside, the second semiconductor chip includes a fourth power node that receives the second power voltage from the outside, a fifth power node connected to the third power node of the first semiconductor chip and receiving the fourth power voltage, a second internal circuit to which the second power voltage is supplied, a second output buffer circuit connected to the second internal circuit and having a third P-type transistor and a third N-type transistor connected in series between the node to which the fourth power voltage is supplied and a ground node, and a second input buffer circuit connected to the second internal circuit and having a fourth P-type transistor and a fourth N-type transistor connected in series between the node to which the fourth power voltage is supplied and a ground node.

3. The semiconductor integrated circuit device according to claim 1, wherein the voltage selection circuit comprises a third N-type transistor having a first node, a second node, and a gate, to which the first power supply voltage is supplied; and a fourth N-type transistor having a first node, a second node, and a gate, to which the first power supply voltage is supplied, wherein the second nodes of the third and fourth N-type transistors are connected to each other, and the third power supply voltage is output from the second node.

4. A semiconductor integrated circuit device comprising a first semiconductor chip and a second semiconductor chip that transmits and receives signals with the first semiconductor chip, wherein the first semiconductor chip comprises a first power node that receives a first power supply voltage from an external source, a second power supply node that receives a second power supply voltage from an external source, a first internal circuit to which the first power supply voltage is supplied, a first voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as a third power supply voltage, a first output buffer circuit connected to the first internal circuit and having a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node, and a first input buffer circuit connected to the first internal circuit and having a second P-type transistor and a second N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node, wherein the second semiconductor chip comprises a third power supply node that receives the first power supply voltage from an external source, a fourth power supply node that receives the second power supply voltage from an external source, and a second internal circuit to which the second power supply voltage is supplied, A semiconductor integrated circuit device comprising: a second voltage selection circuit that outputs the lower of the first power supply voltage and the second power supply voltage as a fourth power supply voltage; a second output buffer circuit connected to the second internal circuit and having a third P-type transistor and a third N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node; and a second input buffer circuit connected to the second internal circuit and having a fourth P-type transistor and a fourth N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node.

5. The semiconductor integrated circuit apparatus according to claim 4, wherein the first voltage selection circuit comprises a fifth N-type transistor having a first node, a second node, and a gate, to which the first power supply voltage is supplied, and a sixth N-type transistor having a first node, a second node, and a gate, to which the second power supply voltage is supplied, wherein the second nodes of the fifth and sixth N-type transistors are connected to each other, and the third power supply voltage is output from the second node, and the second voltage selection circuit comprises a seventh N-type transistor having a first node, a second node, and a gate, to which the first power supply voltage is supplied, and an eighth N-type transistor having a first node, a second node, and a gate, to which the second power supply voltage is supplied, wherein the second nodes of the seventh and eighth N-type transistors are connected to each other, and the fourth power supply voltage is output from the second node, the semiconductor integrated circuit apparatus.

6. A semiconductor integrated circuit device comprising: a first semiconductor chip; a second semiconductor chip that transmits and receives signals with the first semiconductor chip; and a third semiconductor chip, wherein the third semiconductor chip comprises: a first power node that receives a first power supply voltage from an external source; a second power supply node that receives a second power supply voltage from an external source; a voltage selection circuit that outputs the lower of the first and second power supply voltages as a third power supply voltage and a fourth power supply voltage; a third power supply node that outputs the third power supply voltage; and a fourth power supply node that outputs the fourth power supply voltage, wherein the first semiconductor chip comprises: a fifth power supply node that receives the first power supply voltage from an external source; a sixth power supply node connected to the third power supply node of the third semiconductor chip and receiving the third power supply voltage; a first internal circuit to which the first power supply voltage is supplied; and a first output buffer circuit connected to the first internal circuit and having a first P-type transistor and a first N-type transistor connected in series between the node to which the third power supply voltage is supplied and a ground node. A semiconductor integrated circuit device comprising: a first input buffer circuit connected to the first internal circuit and having a second P-type transistor and a second N-type transistor connected in series between a node to which the third power supply voltage is supplied and a ground node; the second semiconductor chip comprising: a seventh power supply node that receives the second power supply voltage from an external source; an eighth power supply node connected to the fourth power supply node of the third semiconductor chip and receiving the fourth power supply voltage; a second internal circuit to which the second power supply voltage is supplied; a second output buffer circuit connected to the second internal circuit and having a third P-type transistor and a third N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node; and a second input buffer circuit connected to the second internal circuit and having a fourth P-type transistor and a fourth N-type transistor connected in series between a node to which the fourth power supply voltage is supplied and a ground node.

7. The semiconductor integrated circuit apparatus according to claim 6, wherein the voltage selection circuit comprises a fifth N-type transistor having a first node, a second node and a gate, to which the first power supply voltage is supplied; and a sixth N-type transistor having a first node, a second node and a gate, to which the first power supply voltage is supplied, wherein the second nodes of the fifth and sixth N-type transistors are connected to each other, and the third power supply voltage and the fourth power supply voltage are output from the second node.

Images