Inference model verification device and inference model verification method

Abstract

This inference model verification device is configured to comprise: a setting reception unit (2) that receives an operation of a slider indicating a numerical range of input data to be given to an inference model, and sets the numerical range of the input data; an output verification unit (3) that verifies whether or not an output of the inference model meets an expected output when each of a plurality of pieces of input data included in the numerical range set by the setting reception unit (2) is given to the inference model; and a failed region identification unit (4) that identifies, on the basis of the verification result of the output verification unit (3), a failed region, which is a numerical range in which the output of the inference model does not meet the expected output, within the numerical range of the input data. The inference model verification device also comprises a display processing unit (5) that superimposes and displays, on the slider, a figure indicating the failed region identified by the failed region identification unit (4).

Description

Inference model verification device and inference model verification method

[0001] This disclosure relates to an inference model verification device and an inference model verification method.

[0002] There are inference model validation devices that verify trained inference models. For example, Patent Document 1 discloses an inference model validation device that verifies whether the output of an inference model satisfies the expected output when each of multiple input data included in the numerical range of the input data is given to the inference model, and identifies a failing region within the numerical range of the input data where the output of the inference model does not satisfy the expected output.

[0003] Patent No. 7496951

[0004] The inference model verification device disclosed in Patent Document 1 can identify the failure region, but it has the problem that it is difficult for the user to intuitively grasp the correspondence between the numerical range of the input data and the failure region.

[0005] This disclosure was made to solve the above-mentioned problems and aims to provide an inference model verification device that can clearly show the correspondence between the numerical range of input data and the failure region.

[0006] The inference model verification device according to this disclosure includes: a setting reception unit that accepts operation of a slider indicating a numerical range of input data to be given to the inference model and sets the numerical range of the input data; an output verification unit that verifies whether the output of the inference model satisfies the expected output when each of the multiple input data included in the numerical range set by the setting reception unit is given to the inference model; and a failure area identification unit that identifies a failure area within the numerical range of the input data, which is a numerical range in which the output of the inference model does not satisfy the expected output, based on the verification result of the output verification unit. The inference model verification device also includes a display processing unit that superimposes a figure indicating the failure area identified by the failure area identification unit onto the slider.

[0007] According to this disclosure, the correspondence between the numerical range of the input data and the unacceptable region can be clearly indicated.

[0008] This is a diagram showing the configuration of an inference model verification device according to Embodiment 1. This is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 1. This is a hardware configuration diagram of a computer when the inference model verification device is implemented by software or firmware, etc. This is a flowchart showing the inference model verification method, which is the processing procedure of the inference model verification device. This is an explanatory diagram showing an example of displaying a slider that shows the numerical range of input data and the numerical range of output data. This is an explanatory diagram showing an example of setting the numerical range of input data. This is an explanatory diagram showing an example of displaying each rejection area and an area that includes one or more rejection areas belonging to each group. This is an explanatory diagram showing an example where a figure indicating a rejection area is superimposed on the slider. This is an explanatory diagram showing an example where the input data area has been changed to the upper left area in the treemap. This is a diagram showing the configuration of an inference model verification device according to Embodiment 2. This is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 2. This is an explanatory diagram showing an example of displaying each rejection area and an area that includes one or more rejection areas belonging to each group. This is a diagram showing the configuration of an inference model verification device according to Embodiment 3. This is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 3. This is an explanatory diagram showing an example of a detailed group whose designation has been accepted by the detailed group designation unit 8. This is an explanatory diagram showing an example of grouping one or more rejection areas belonging to a detailed group. This is a configuration diagram showing the inference model verification device according to Embodiment 4. This is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 4. This is an explanatory diagram showing three rejection areas identified by the rejection area identification unit 4. Input data x ｋ Importance level C ｋ This is an explanatory diagram showing an example of how it is displayed. This is an explanatory diagram showing an example of multiple groups displayed in a pie chart.

[0009] To provide a more detailed explanation of this disclosure, the forms for implementing this disclosure will be described below with reference to the attached drawings.

[0010] Embodiment 1. FIG. 1 is a configuration diagram showing an inference model verification apparatus according to Embodiment 1. FIG. 2 is a hardware configuration diagram showing hardware of the inference model verification apparatus according to Embodiment 1. The inference model verification apparatus shown in FIG. 1 includes an inference model reading unit 1, a setting reception unit 2, an output verification unit 3, a failure region identification unit 4, and a display processing unit 5.

[0011] The inference model reading unit 1 is implemented by, for example, an inference model reading circuit 21 shown in FIG. 2. The inference model reading unit 1 reads an inference model to be verified and outputs the inference model to the output verification unit 3. Examples of the inference model to be verified include trained machine learning models such as a neural network or a decision tree ensemble model. Further, the inference model may be a deterministic system such as a single decision tree. The input data of the inference model is, for example, N-dimensional input data X=(x １ , x ２ , ..., x Ｎ )∈R Ｎ , and the output of the inference model is, for example, one-dimensional output data y∈R, or M-dimensional output data Y=(y １ , y ２ , ..., y Ｍ )∈R Ｍ . Therefore, the inference model corresponds to a function f that returns one-dimensional output data y or M-dimensional output data Y for N-dimensional input data X.

[0012] The setting reception unit 2 is implemented by, for example, a setting reception circuit 22 shown in FIG. 2. The setting reception unit 2 receives an operation of a slider indicating a numerical range of input data to be supplied to the inference model, and sets the numerical range of the input data. Further, the setting reception unit 2 receives setting of a verification condition for the inference model. The verification condition for the inference model corresponds to an expected output of the inference model. The setting reception unit 2 outputs the numerical range of the input data to each of the output verification unit 3 and the failure region identification unit 4, and outputs the verification condition for the inference model to the output verification unit 3.

[0013] The output verification unit 3 is implemented, for example, by the output verification circuit 23 shown in Figure 2. The output verification unit 3 obtains the inference model to be verified from the inference model reading unit 1. The output verification unit 3 obtains the numerical range of the input data and the verification conditions of the inference model from the setting reception unit 2. The output verification unit 3 verifies whether the output of the inference model satisfies the expected output when each of the multiple input data included in the numerical range set by the setting reception unit 2 is given to the inference model. The output verification unit 3 outputs the verification result indicating whether the output of the inference model satisfies the expected output to the failure area identification unit 4.

[0014] The failure region identification unit 4 is implemented, for example, by the failure region identification circuit 24 shown in Figure 2. The failure region identification unit 4 obtains the numerical range of the input data from the setting reception unit 2. The failure region identification unit 4 obtains the verification result from the output verification unit 3. Based on the verification result from the output verification unit 3, the failure region identification unit 4 identifies a failure region within the numerical range of the input data, which is a numerical range in which the output of the inference model does not satisfy the expected output. The failure region identification unit 4 outputs information indicating the failure region to the display processing unit 5.

[0015] The display processing unit 5 is implemented, for example, by the display processing circuit 25 shown in Figure 2. The display processing unit 5 acquires information indicating the defective area from the defective area identification unit 4. The display processing unit 5 overlays a figure indicating the defective area identified by the defective area identification unit 4 onto the slider. The shape of the figure indicating the defective area is, for example, a rectangle.

[0016] In Figure 1, the inference model verification device is assumed to be implemented by dedicated hardware as shown in Figure 2, with each of its components being the inference model reading unit 1, setting reception unit 2, output verification unit 3, failure area identification unit 4, and display processing unit 5. Specifically, the inference model verification device is assumed to be implemented by the inference model reading circuit 21, setting reception circuit 22, output verification circuit 23, failure area identification circuit 24, and display processing circuit 25. Each of the inference model reading circuit 21, setting reception circuit 22, output verification circuit 23, failure area identification circuit 24, and display processing circuit 25 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof.

[0017] The components of an inference model verification device are not limited to those implemented by dedicated hardware; the inference model verification device may also be implemented by software, firmware, or a combination of software and firmware. The software or firmware is stored as a program in the computer's memory. A computer refers to the hardware that executes the program, and includes, for example, a CPU (Central Processing Unit), GPU (Graphics Processing Unit), central processing unit, processing unit, arithmetic unit, microprocessor, microcomputer, processor, or DSP (Digital Signal Processor).

[0018] Figure 3 is a hardware configuration diagram of a computer when the inference model verification device is implemented by software or firmware. When the inference model verification device is implemented by software or firmware, programs that cause the computer to execute the respective processing procedures in the inference model reading unit 1, setting reception unit 2, output verification unit 3, failure area identification unit 4, and display processing unit 5 are stored in memory 41. The computer's processor 42 then executes the programs stored in memory 41.

[0019] Furthermore, Figure 2 shows an example in which each component of the inference model verification device is implemented by dedicated hardware, and Figure 3 shows an example in which the inference model verification device is implemented by software or firmware, etc. However, this is only one example, and some components of the inference model verification device may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware, etc.

[0020] Next, the operation of the inference model verification device shown in Figure 1 will be explained. Figure 4 is a flowchart showing the inference model verification method, which is the processing procedure of the inference model verification device. The inference model reading unit 1 reads the inference model to be verified (step ST1 in Figure 4). The inference model reading unit 1 outputs the inference model to the output verification unit 3.

[0021] The input data for the inference model is, for example, N-dimensional input data X = (x １ , x ２ , ..., x Ｎ ) ∈ R Ｎ The output of the inference model is, for example, one-dimensional output data y ∈ R, or M-dimensional output data Y = (y １ , y ２ , , y Ｍ ) ∈ R ＭThe inference model is, for example, a trained machine learning model. During training, the inference model is given, for example, input data X and one-dimensional output data y or M-dimensional output data Y as training data, and learns the correspondence between input data X and output data y or output data Y. For example, if the inference model is used for real estate search, the training data would be, for example, input data x indicating the living area of ​​the property. １ Input data x indicating the distance from the nearest station to the property ２ If the inference model is given both the residential area and the output data y representing the rental fee of the property, the inference model learns the rental fee corresponding to the residential area and distance. In this case, during inference, the inference model takes the input data x representing the residential area as input data X. １ and input data x indicating distance ２ Given the given values, the output data y will show the rental fee corresponding to the living area and distance.

[0022] As shown in Figure 5, the display processing unit 5 causes the display device 60 to display a slider indicating the numerical range of the input data to be given to the inference model. Figure 5 is an explanatory diagram showing an example of the display of the slider indicating the numerical range of the input data and the numerical range of the output data. In the example in Figure 5, the slider indicating the numerical range of the input data is set to input data X = (x １ , x ２ , x ３ , x ４ Four sliders related to ) are displayed. Hereafter, the numerical range of the input data may be referred to as the input data area. In Figure 5, of the two ●s in each slider, the left ● is, for example, the input data x ｎ The lower limit is shown for (n = 1, 2, 3, 4), and the ● on the right represents, for example, the input data x ｎ This indicates the upper limit.

[0023] The setting reception unit 2 is equipped with a human-machine interface that accepts operation of a slider as shown in Figure 5. In the example in Figure 5, the user inputs data x ｎBy moving the ● on the left side of the slider (n=1,2,3,4) left or right, the input data x ｎ The lower limit of the numerical range can be set to a desired lower limit. Furthermore, the user can input data x ｎ By moving the ● on the right side of the slider related to left or right, the input data x ｎ The upper limit of the numerical range can be set to a desired upper limit. When the user operates the slider, the setting reception unit 2 accepts the slider operation as shown in Figure 6 and receives the input data x ｎ Set the numerical range (step ST2 in Figure 4). Figure 6 is an explanatory diagram showing an example of setting the numerical range for the input data. If the inference model is used for real estate search, for example, input data x indicating the living area of ​​the property. １ The input data x indicates the numerical range and the distance from the nearest station to the property. ２ The numerical range is set.

[0024] The user can set the validation conditions for the inference model by operating the human-machine interface of the setting reception unit 2. The validation conditions for the inference model correspond to the expected output of the inference model. The setting reception unit 2 accepts the user's operation and sets the validation conditions for the inference model (step ST3 in Figure 4). If the inference model is used for, for example, real estate search, then, for example, the rental price of the property will be set as the validation condition for the inference model. The setting reception unit 2 receives the input data x ｎ The numerical range (n=1, ..., N) is output to the output verification unit 3 and the failure region identification unit 4, respectively, and the verification conditions for the inference model are output to the output verification unit 3.

[0025] The output verification unit 3 obtains the inference model to be verified from the inference model reading unit 1. The output verification unit 3 receives the input data x from the setting reception unit 2. ｎ The numerical range (n=1, ..., N) and the verification conditions for the inference model are obtained. The output verification unit 3 provides the inference model with each of the multiple input data included in the numerical range set by the setting reception unit 2, and outputs y of the inference model. ｍWe verify whether (m=1, ..., M) satisfies the expected output (step ST4 in Figure 4).

[0026] The verification process performed by the output verification unit 3 will be described in detail below. The output verification unit 3, for example, takes input data x indicating the living area. １ Input data x showing the numerical range and distance ２ The numerical range and are given to the inference model. The inference model uses input data x representing the living area. １ Input data x showing the numerical range and distance ２ Given a numerical range for x, the input data x １ Data showing one or more residential areas included in the numerical range, and input data x ２ For each combination of one or more distance-indicating data points within the numerical range, output data y shows the rental fee corresponding to the residential area and distance. ｍ Output (m=1, ..., M). The number of combinations in this case is M.

[0027] The output verification unit 3 outputs data y from the inference model that shows the rental fees for each combination. ｍ (m=1, ..., M) is obtained, and the output data y ｍ The system determines whether the rental fee indicated satisfies the expected output of the inference model, which is a verification condition. If the expected output of the inference model is, for example, a rental fee of 150,000 yen or more and less than 200,000 yen, the output verification unit 3 will determine if the rental fee for each combination is within the range of 150,000 to 200,000 yen, and the output data y indicating the rental fee will be determined. ｍ If it is determined that the expected output is met, and the rent for each combination is less than 150,000 yen or 200,000 yen or more, then output data y indicating the rent will be generated. ｍ The output verification unit 3 determines that the expected output is not met. Output verification unit 3 outputs output data y indicating the rental fee for each combination. ｍ The verification result indicating whether or not the expected output is met is output to the failure area identification unit 4.

[0028] The failure area identification unit 4 receives input data x from the setting reception unit 2. ｎThe numerical range (n=1, ..., N) is obtained. The failure area identification unit 4 receives the output data y related to each combination from the output verification unit 3. ｍ The verification result is obtained indicating whether (m=1, ..., M) satisfies the expected output. Based on the verification result of the output verification unit 3, the failure region identification unit 4 identifies the input data x ｎ Within the numerical range, the output y of the inference model ｍ The system identifies a failure region, which is a numerical range that does not meet the expected output (step ST5 in Figure 4).

[0029] The following will specifically explain the process of identifying the unacceptable area by the unacceptable area identification unit 4. For the sake of explanation, the numerical range of the input data is assumed to be the input data x representing the residential area. １ Input data x showing the numerical range and distance ２ When the numerical range is such that the input data x indicates the living area, １ The numerical range is 100 to 150 m ２ , input data x indicating distance ２ Assume the numerical range of is 1.0 to 2.0 km. In this case, input data x indicating the living area １ The numerical range is 120-140m ２ , and input data x indicating distance ２ When the numerical range is 1.3 to 1.8 km, output data y shows the rental fee for each combination. ｍ Assume that (m = 1, ..., M) satisfies the expected output. On the other hand, input data x representing the living area １ The numerical range is 120m ２ Less than or equal to the input data x indicating the residential area. １ The numerical range is 140m ２ When it is greater than or equal to the input data x indicating the distance ２ The numerical range is less than 1.3 km, or the input data x indicating distance is ２ If the numerical range is longer than 1.8 km, output data y will show the rental fee for each combination. ｍ Assume that the expected output is not met. In such a case, the failure area identification unit 4 identifies the input data x indicating the living area. １Within the numerical range, 100 to 120 m ２ The area and 140-150m ２ The system identifies the area and the area that are unacceptable. The unacceptable area identification unit 4 also uses input data x indicating distance. ２ Within the given numerical range, the areas of 1.0 to 1.3 km and 1.8 to 2.0 km are identified as unacceptable.

[0030] The rejection area identification unit 4 identifies multiple rejection areas and then groups them together. Specifically, if the number of groups to be formed is predetermined to be G, the rejection area identification unit 4 performs clustering on the multiple rejection areas to classify each rejection area into one of the G groups. G is an integer greater than or equal to 1. The rejection area identification unit 4 groups the multiple rejection areas such that the spatial distance between two rejection areas belonging to the same group is shorter than the spatial distance between a rejection area belonging to one group and a rejection area belonging to another group. Examples of spatial distances include the Euclidean distance and the Manhattan distance.

[0031] The failure area identification unit 4, when grouping multiple failure areas, also groups the passing areas and undetermined areas. The passing areas are within the numerical range of the input data, and the output y of the inference model ｍ This is the numerical range that satisfies the expected output. The undetermined area is the numerical range within the input data that cannot be determined to belong to either the pass area or the fail area. Therefore, each group may contain not only the fail area but also the pass area and the undetermined area. The fail area identification unit 4 outputs information indicating each fail area, information indicating the group to which each fail area belongs, information indicating the group to which each pass area belongs, and information indicating the group to which each undetermined area belongs to the display processing unit 5.

[0032] The display processing unit 5 obtains from the rejection area identification unit 4 information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs. Figure 7 is an explanatory diagram showing an example of displaying each rejection area and the area that includes one or more rejection areas belonging to each group. As shown in Figure 7, the display processing unit 5 displays a table indicating each rejection area on the display device 60. The table indicating the rejection areas is the table shown in the upper right of the figure. In the table indicating the rejection areas, the rejection areas are identified by the lower and upper limits of the numerical range that constitutes the rejection area. The ID is the identification number of the rejection area. The volume indicates the size of the rejection area when the number of dimensions of the input data is three. If the number of dimensions of the input data is two, the area is shown instead of the volume. As shown in Figure 7, the display processing unit 5 displays the group to which each rejection area belongs on the display device 60. Specifically, the display processing unit 5 causes the display device 60 to display a figure on the display device 60 that represents an area encompassing one or more unacceptable areas, etc., belonging to each group. The area encompassing unacceptable areas, etc., is an area that includes unacceptable areas, acceptable areas, and undetermined areas. In the example in Figure 7, the shape of the figure representing the area encompassing unacceptable areas, etc., is a rectangle.

[0033] In the example in Figure 7, a treemap is displayed showing regions that contain one or more unsatisfactory areas, etc., belonging to each of the eight groups. The grayscale density in the treemap represents the unsatisfactory rate. In the example in Figure 7, the larger the displayed area of ​​the region that contains one or more unsatisfactory areas, etc., belonging to a group, the larger the total sum of unsatisfactory areas, satisfactory areas, and undetermined areas belonging to that group. In Figure 7, the percentage of satisfactory areas, the percentage of unsatisfactory areas, and the percentage of undetermined areas are displayed on the display device 60. These percentages are displayed in the upper left of the figure.

[0034] The display processing unit 5 superimposes the shapes indicating each failure area onto the slider that is previously displayed on the display device 60 (step ST6 in Figure 4). Figure 8 is an explanatory diagram showing an example in which the shapes indicating failure areas are superimposed on the slider. In the example in Figure 8, the area belonging to the upper left group is selected from among the areas belonging to the eight groups displayed in the treemap, and the shapes indicating failure areas are superimposed on the slider only when the failure areas contained within the area belonging to the upper left group are contained within the numerical range of the input data. A failure area being contained within the numerical range of the input data means that the failure area is a proper subset of the numerical range of the input data. The shapes indicating failure areas are the shapes with diagonal lines in the figure, and the shape of the shapes indicating failure areas is a rectangle. The shapes indicating failure areas only need to be superimposed on the slider, and the shape of the shapes indicating failure areas is not limited to a rectangle. Therefore, the shape of the shapes indicating failure areas may be, for example, an ellipse.

[0035] In the example in Figure 8, input data x １ The areas of failure related to input data x １ Because it is included in the numerical range of x, the input data x １ The figure showing the area of ​​failure related to input data x １ It is displayed superimposed on the slider related to it. Also, input data x ３ The areas of failure related to input data x ３ Because it is included in the numerical range of x, the input data x ３ The figure showing the area of ​​failure related to input data x ３ It is displayed superimposed on the slider related to it. On the other hand, input data x ２ The areas of failure related to input data x ２ The numerical range is not included, and the input data x ２ Because it is not a proper subset of the numerical range, the input data x ２ The figure indicating the area of ​​failure related to input data x ２ The slider related to it is not displayed overlaid. Also, input data x ４ The areas of failure related to input data x４ is not included in the numerical range, and the input data x ４ is not a proper subset of the numerical range, so the input data x ４ the graphic representing the fail region associated with is not the input data x ４ is not displayed superimposed on the associated slider.

[0036] Similarly to FIG. 7, FIG. 8 also shows a table representing each fail region. Further, similarly to FIG. 7, FIG. 8 also shows the proportion of pass regions, the proportion of fail regions, and the proportion of undetermined regions. As shown in FIG. 8, the display processing unit 5 causes the display device 60 to display the numerical range of the output data y of the inference model.

[0037] By viewing the display device 60, a user can easily grasp the correspondence between the input data region, which is the numerical range of the input data, and the fail regions. By grasping the correspondence, the user can check whether or not the inference model to be verified has been trained correctly, and if the user determines that the model has not been trained correctly, it becomes possible to cause the inference model to be re-trained so that the inference model is trained correctly.

[0038] For example, if the user determines that it is necessary to investigate the details of regions belonging to each group displayed in a treemap, the user can change the input data region by operating a slider. By receiving the user's operation of the slider, the setting reception unit 2 changes the setting of the input data region to, for example, a region including one or more fail regions belonging to any one of the groups. FIG. 9 is an explanatory diagram showing an example in which the input data region has been changed to be set to the upper left region in a treemap. In the example of FIG. 9, the input data x １ whose numerical range is included in the upper left region in the treemap, the input data x １ has been changed to be set to the associated fail region. Further, the input data x ３ whose numerical range is included in the upper left region in the treemap, the input data x ３The setting has been changed to the unacceptable area. The setting reception unit 2 outputs the input data area after the setting change to the output verification unit 3 and the unacceptable area identification unit 4, respectively.

[0039] The output verification unit 3 obtains the input data area after the setting change from the setting reception unit 2. The output verification unit 3 then outputs the inference model y when each of the multiple input data contained in the input data area after the setting change is given to the inference model. ｍ The output verification unit 3 verifies whether (m=1, ..., M) satisfies the expected output. ｍ The verification result indicating whether or not the expected output is met is output to the failure area identification unit 4.

[0040] The output verification unit 3 obtains the input data area after the setting change from the setting reception unit 2. The output verification unit 3 then outputs the inference model y when each of the multiple input data contained in the input data area after the setting change is given to the inference model. ｍ The system verifies whether the expected output is met. If the failure area identification unit 4 identifies multiple failure areas, it groups the multiple failure areas. The failure area identification unit 4 outputs to the display processing unit 5 information indicating each failure area, information indicating the group to which each failure area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs.

[0041] The display processing unit 5 obtains from the rejection area identification unit 4 information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs. The display processing unit 5 displays a table showing each rejection area on the display device 60, as shown in Figure 9. The display processing unit 5 displays a figure on the display device 60 that shows an area containing one or more rejection areas belonging to each group, as shown in Figure 9.

[0042] In the above embodiment 1, the inference model verification device is configured to include: a setting reception unit 2 that accepts operation of a slider indicating the numerical range of input data to be given to the inference model and sets the numerical range of the input data; an output verification unit 3 that verifies whether the output of the inference model satisfies the expected output when each of the multiple input data included in the numerical range set by the setting reception unit 2 is given to the inference model; and a failure area identification unit 4 that identifies a failure area within the numerical range of the input data, which is a numerical range in which the output of the inference model does not satisfy the expected output, based on the verification result of the output verification unit 3. Furthermore, the inference model verification device includes a display processing unit 5 that superimposes a figure indicating the failure area identified by the failure area identification unit 4 onto the slider.Therefore, the inference model verification device can clearly show the correspondence between the numerical range of the input data and the failure area.

[0043] In Embodiment 1, the inference model verification device is configured such that the setting reception unit 2, upon receiving a slider operation, changes the numerical range of the input data to a region that includes one or more unacceptable regions belonging to any group. Therefore, the inference model verification device can investigate the details of the regions belonging to the group.

[0044] In Embodiment 1, the inference model verification device is configured such that the display processing unit 5 superimposes a graphic indicating a rejection area onto the slider only when the rejection area identified by the rejection area identification unit 4 is included within the numerical range of the input data. Therefore, the inference model verification device allows the user to easily understand whether or not a rejection area is included within the numerical range of the input data.

[0045] In Embodiment 1, the inference model verification device is configured such that when the failure area identification unit 4 identifies multiple failure areas within the input data area, which are numerical ranges where the output of the inference model does not meet the expected output, it groups the multiple failure areas, and the display processing unit 5 displays a figure indicating the failure areas identified by the failure area identification unit 4 superimposed on a slider, as well as a figure indicating the area that contains one or more failure areas belonging to each group. Therefore, the inference model verification device makes it easy for the user to understand the groups that include failure areas.

[0046] Embodiment 2. Embodiment 2 describes an inference model verification device that includes a group number specification unit 6 that accepts the number of groups to be specified when the failure area identification unit 7 performs group division.

[0047] Figure 10 is a configuration diagram showing an inference model verification device according to Embodiment 2. In Figure 10, the same reference numerals as in Figure 1 indicate the same or corresponding parts, so a detailed explanation is omitted. Figure 11 is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 2. In Figure 11, the same reference numerals as in Figure 2 indicate the same or corresponding parts, so a detailed explanation is omitted. The inference model verification device shown in Figure 10 includes an inference model reading unit 1, a setting reception unit 2, an output verification unit 3, a group number specification unit 6, a failure area identification unit 7, and a display processing unit 5.

[0048] The group number specification unit 6 is implemented, for example, by the group number specification circuit 26 shown in Figure 11. The group number specification unit 6 receives the number of groups specified by the rejection area identification unit 7 when grouping. The group number specification unit 6 outputs the received number of groups to the rejection area identification unit 7.

[0049] The failure area identification unit 7 is implemented, for example, by the failure area identification circuit 27 shown in Figure 11. The failure area identification unit 7 obtains the numerical range of the input data from the setting reception unit 2. The failure area identification unit 7 obtains the verification result from the output verification unit 3. The failure area identification unit 7 obtains the number of groups from the group number specification unit 6. Similar to the failure area identification unit 4 shown in Figure 1, the failure area identification unit 7 identifies failure areas within the numerical range of the input data, which are numerical ranges where the output of the inference model does not meet the expected output, based on the verification result of the output verification unit 3. If the failure area identification unit 7 identifies multiple failure areas, it groups the multiple failure areas, similar to the failure area identification unit 4 shown in Figure 1. If the number of groups has been specified by the group number specification unit 6, the failure area identification unit 7 groups the multiple failure areas into groups of the number of groups specified by the group number specification unit 6. The failure area identification unit 7 outputs information indicating each failure area and information indicating the group to which each failure area belongs to the display processing unit 5.

[0050] In Figure 10, it is assumed that each of the components of the inference model verification device—the inference model reading unit 1, the setting reception unit 2, the output verification unit 3, the group number specification unit 6, the failure area identification unit 7, and the display processing unit 5—is implemented by dedicated hardware as shown in Figure 11. That is, it is assumed that the inference model verification device is implemented by an inference model reading circuit 21, a setting reception circuit 22, an output verification circuit 23, a group number specification circuit 26, a failure area identification circuit 27, and a display processing circuit 25. Each of the inference model reading circuit 21, the setting reception circuit 22, the output verification circuit 23, the group number specification circuit 26, the failure area identification circuit 27, and the display processing circuit 25 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0051] The components of the inference model verification device are not limited to those implemented by dedicated hardware; the inference model verification device may also be implemented by software, firmware, or a combination of software and firmware. When the inference model verification device is implemented by software or firmware, a program that causes a computer to execute the respective processing procedures in the inference model reading unit 1, setting acceptance unit 2, output verification unit 3, group number specification unit 6, failure area identification unit 7, and display processing unit 5 is stored in the memory 41 shown in Figure 3. Then, the processor 42 shown in Figure 3 executes the program stored in the memory 41.

[0052] Furthermore, Figure 11 shows an example in which each component of the inference model verification device is implemented by dedicated hardware, and Figure 3 shows an example in which the inference model verification device is implemented by software or firmware, etc. However, this is only one example, and some components of the inference model verification device may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware, etc.

[0053] Next, the operation of the inference model verification device shown in Figure 10 will be explained. Except for the group number specification unit 6 and the failure area identification unit 7, it is the same as the inference model verification device shown in Figure 1. Therefore, here we will mainly explain the operation of the group number specification unit 6 and the failure area identification unit 7.

[0054] The group number specification unit 6 is equipped with a human-machine interface that accepts the number of groups P for the rejection area identification unit 7 to use when dividing into groups. P is an integer of 1 or more. The group number specification unit 6 outputs the accepted number of groups P to the rejection area identification unit 7.

[0055] The failure area identification unit 7 obtains the numerical range of the input data from the setting reception unit 2. The failure area identification unit 7 obtains the verification result from the output verification unit 3. Based on the verification result from the output verification unit 3, the failure area identification unit 7 determines the output y of the inference model within the numerical range of the input data. ｍThe failure region is identified, which is a numerical range where (m = 1, ..., M) does not satisfy the expected output. If the failure region identification unit 7 identifies multiple failure regions, it groups the multiple failure regions.

[0056] If the number of groups for grouping multiple rejection areas has not been received by the group number specification unit 6, the rejection area identification unit 7, similar to the rejection area identification unit 4 shown in Figure 1, performs clustering on the multiple rejection areas to classify each rejection area into one of the predetermined G groups. If the number of groups for grouping multiple rejection areas has been received as P by the group number specification unit 6, the rejection area identification unit 7 obtains the group number P from the group number specification unit 6. The rejection area identification unit 7 classifies each rejection area into one of the P groups by performing clustering on the multiple rejection areas. The rejection area identification unit 7 outputs information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs to, to the display processing unit 5.

[0057] The display processing unit 5 obtains from the rejection area identification unit 7 information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs. The display processing unit 5 displays a table showing each rejection area on the display device 60, as shown in Figure 12. The display processing unit 5 displays a figure on the display device 60 that shows an area containing one or more rejection areas belonging to each group, as shown in Figure 12.

[0058] Figure 12 is an explanatory diagram illustrating an example of displaying each failing area and the area encompassing one or more failing areas belonging to each group. In the example of Figure 12, P = 16, and a treemap is displayed showing the area encompassing one or more failing areas belonging to each of the 16 groups. Each of the 16 groups may contain not only failing areas, but also passing areas and undetermined areas. In the example of Figure 12, the larger the displayed area encompassing one or more failing areas belonging to a group, the larger the total sum of failing areas, passing areas, and undetermined areas belonging to that group.

[0059] In the above embodiment 2, the inference model verification device shown in Figure 10 is configured such that the rejection area identification unit 7 includes a group number specification unit 6 that accepts the number of groups to be specified when performing group division, and the rejection area identification unit 7 performs group division of multiple rejection areas into groups of the specified number. Therefore, the inference model verification device shown in Figure 10 can clearly show the correspondence between the numerical range of the input data and the rejection areas, as well as classify the groups to which the rejection areas belong in detail, similar to the inference model verification device shown in Figure 1.

[0060] Embodiment 3. Embodiment 3 describes an inference model verification device that includes a detailed group designation unit 8 that accepts the designation of a detailed group, which is a group that further subdivides a plurality of groups, and the designation of the level of detail for the detailed group.

[0061] Figure 13 is a configuration diagram showing an inference model verification device according to Embodiment 3. In Figure 13, the same reference numerals as in Figures 1 and 10 indicate the same or corresponding parts, so a detailed explanation is omitted. Figure 14 is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 3. In Figure 14, the same reference numerals as in Figures 2 and 11 indicate the same or corresponding parts, so a detailed explanation is omitted. The inference model verification device shown in Figure 13 includes an inference model reading unit 1, a setting reception unit 2, an output verification unit 3, a detailed group designation unit 8, a failure area identification unit 9, and a display processing unit 5.

[0062] The detailed group designation unit 8 is implemented, for example, by the detailed group designation circuit 28 shown in Figure 14. The detailed group designation unit 8 accepts the designation of a detailed group, which is a group that is further subdivided from among multiple groups, and the designation of the level of detail for the detailed group. The detailed group designation unit 8 outputs information indicating the detailed group and information indicating the level of detail to the rejection area identification unit 9.

[0063] The failure area identification unit 9 is implemented, for example, by the failure area identification circuit 29 shown in Figure 14. The failure area identification unit 9 obtains the numerical range of the input data from the setting reception unit 2. The failure area identification unit 9 obtains the verification result from the output verification unit 3. The failure area identification unit 9 obtains information indicating the detail group and information indicating the level of detail from the detail group designation unit 8. Similar to the failure area identification unit 4 shown in Figure 1, the failure area identification unit 9 identifies failure areas within the numerical range of the input data, which are numerical ranges where the output of the inference model does not meet the expected output, based on the verification result of the output verification unit 3. If the failure area identification unit 9 identifies multiple failure areas, it groups the multiple failure areas, similar to the failure area identification unit 4 shown in Figure 1. When the detail group designation unit 8 accepts the designation of the detail group and the designation of the level of detail, the failure area identification unit 9 groups one or more failure areas belonging to the detail group into the number of groups indicated by the level of detail. The failure area identification unit 9 outputs information indicating each failure area and information indicating the group to which each failure area belongs to the display processing unit 5.

[0064] The inference model verification device shown in Figure 13 is one in which the detailed group designation unit 8 and the rejection area identification unit 9 are applied to the inference model verification device shown in Figure 1. However, this is merely one example, and the detailed group designation unit 8 and the rejection area identification unit 9 may also be applied to the inference model verification device shown in Figure 10.

[0065] In Figure 13, it is assumed that each of the components of the inference model verification device—the inference model reading unit 1, the setting reception unit 2, the output verification unit 3, the detailed group designation unit 8, the failure area identification unit 9, and the display processing unit 5—is implemented by dedicated hardware as shown in Figure 14. That is, it is assumed that the inference model verification device is implemented by an inference model reading circuit 21, a setting reception circuit 22, an output verification circuit 23, a detailed group designation circuit 28, a failure area identification circuit 29, and a display processing circuit 25. Each of the inference model reading circuit 21, the setting reception circuit 22, the output verification circuit 23, the detailed group designation circuit 28, the failure area identification circuit 29, and the display processing circuit 25 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0066] The components of the inference model verification device are not limited to those implemented by dedicated hardware; the inference model verification device may also be implemented by software, firmware, or a combination of software and firmware. When the inference model verification device is implemented by software or firmware, a program that causes a computer to execute the respective processing procedures in the inference model reading unit 1, setting acceptance unit 2, output verification unit 3, detailed group designation unit 8, failure area identification unit 9, and display processing unit 5 is stored in the memory 41 shown in Figure 3. Then, the processor 42 shown in Figure 3 executes the program stored in the memory 41.

[0067] Furthermore, Figure 14 shows an example in which each component of the inference model verification device is implemented by dedicated hardware, while Figure 3 shows an example in which the inference model verification device is implemented by software or firmware. However, this is merely one example, and some components of the inference model verification device may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware.

[0068] Next, the operation of the inference model verification device shown in Figure 13 will be explained. Except for the detailed group designation unit 8 and the failure area identification unit 9, it is the same as the inference model verification device shown in Figure 1. Therefore, here we will mainly explain the operation of the detailed group designation unit 8 and the failure area identification unit 9.

[0069] The failure area identification unit 9, similar to the failure area identification unit 4 shown in Figure 1, determines the output y of the inference model within the numerical range of the input data based on the verification result of the output verification unit 3. ｍ The system identifies a failure region where (m = 1, ..., M) is a numerical range that does not satisfy the expected output. After the failure region identification unit 9 identifies multiple failure regions and groups the multiple failure regions, the detailed group designation unit 8 has a human-machine interface that accepts the designation of a detailed group, which is a group that will be further subdivided from the multiple groups, and the designation of the level of detail for the detailed group. Figure 15 is an explanatory diagram showing an example of a detailed group whose designation has been accepted by the detailed group designation unit 8. In the example in Figure 15, the group in the upper right is designated as a detailed group. The detailed group designation unit 8 outputs information indicating the detailed group and information indicating the level of detail to the failure region identification unit 9.

[0070] The rejection area identification unit 9 obtains the numerical range of the input data from the setting reception unit 2. The rejection area identification unit 9 obtains the verification result from the output verification unit 3. The rejection area identification unit 9 obtains information indicating the detail group and information indicating the level of detail from the detail group designation unit 8. After grouping multiple rejection areas as described above, the rejection area identification unit 9, upon receiving the designation of the detail group and the designation of the level of detail from the detail group designation unit 8, groups one or more rejection areas belonging to the detail group into the number of groups indicated by the level of detail, as shown in Figure 16.

[0071] Figure 16 is an explanatory diagram showing an example of grouping one or more rejection areas belonging to a detail group. In the example in Figure 16, the level of detail is 5, and one or more rejection areas belonging to the detail group are classified into 5 groups. The rejection area identification unit 9 outputs information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs to the display processing unit 5.

[0072] The display processing unit 5 obtains from the rejection area identification unit 9 information indicating each rejection area, information indicating the group to which each rejection area belongs, information indicating the group to which each passing area belongs, and information indicating the group to which each undetermined area belongs. The display processing unit 5 displays a table showing each rejection area on the display device 60, as shown in Figure 16. The display processing unit 5 displays a figure on the display device 60 that shows an area containing one or more rejection areas, etc., belonging to each group, as shown in Figure 16. The display processing unit 5 displays a figure on the display device 60 that shows an area containing one or more rejection areas, etc., belonging to a detailed group, as shown in Figure 16.

[0073] In the above embodiment 3, the inference model verification device shown in Figure 13 is configured such that the device includes a detailed group designation unit 8 that accepts the designation of a detailed group, which is a group that further subdivides from among multiple groups, and the designation of the level of detail for the detailed group, and the rejection area identification unit 9 divides one or more rejection areas belonging to the detailed group into the number of groups indicated by the level of detail. Therefore, the inference model verification device shown in Figure 13 can clearly show the correspondence between the numerical range of the input data and the rejection areas, as well as classify the rejection areas belonging to the detailed group in detail, similar to the inference model verification device shown in Figure 1.

[0074] Embodiment 4. In Embodiment 4, the input data X = (x １ , x ２ , ..., x Ｋ ) ∈ R ＫThe number of dimensions is K (where K is an integer greater than or equal to 2), and each input data x ｋ This section describes an inference model verification device equipped with an importance calculation unit 10 that calculates the importance of (k = 1, 2, ..., K).

[0075] Figure 17 is a configuration diagram showing an inference model verification device according to Embodiment 4. In Figure 17, the same reference numerals as in Figures 1, 10, and 13 indicate the same or corresponding parts, so a detailed explanation is omitted. Figure 18 is a hardware configuration diagram showing the hardware of the inference model verification device according to Embodiment 4. In Figure 18, the same reference numerals as in Figures 2, 11, and 14 indicate the same or corresponding parts, so a detailed explanation is omitted. The inference model verification device shown in Figure 17 comprises an inference model reading unit 1, a setting reception unit 2, an output verification unit 3, a failure area identification unit 4, an importance calculation unit 10, and a display processing unit 11.

[0076] The importance calculation unit 10 is implemented, for example, by the importance calculation circuit 30 shown in Figure 18. The importance calculation unit 10 obtains verification results from the output verification unit 3. Based on the verification results from the output verification unit 3, the importance calculation unit 10 calculates each input data x ｋ The importance of (k = 1, 2, ..., K) is calculated. The importance calculation unit 10 calculates the importance of the input data x ｋ Information indicating the importance of the item is output to the display processing unit 11.

[0077] The display processing unit 11 is implemented, for example, by the display processing circuit 31 shown in Figure 18. The display processing unit 11 acquires information indicating the unacceptable areas from the unacceptable area identification unit 4. In addition to superimposing the figure indicating the unacceptable areas identified by the unacceptable area identification unit 4 onto the slider, the display processing unit 11 also displays the input data x calculated by the importance calculation unit 10. ｋ The importance of each item is displayed on the display device 60.

[0078] The inference model verification device shown in Figure 17 is an application of the importance calculation unit 10 and the display processing unit 11 to the inference model verification device shown in Figure 1. However, this is merely one example, and the importance calculation unit 10 and the display processing unit 11 may also be applied to the inference model verification device shown in Figure 10 or the inference model verification device shown in Figure 13.

[0079] In Figure 17, it is assumed that each of the components of the inference model verification device—the inference model reading unit 1, the setting reception unit 2, the output verification unit 3, the failure area identification unit 4, the importance calculation unit 10, and the display processing unit 11—is implemented by dedicated hardware as shown in Figure 18. Specifically, it is assumed that the inference model verification device is implemented by an inference model reading circuit 21, a setting reception circuit 22, an output verification circuit 23, a failure area identification circuit 24, an importance calculation circuit 30, and a display processing circuit 31. Each of the inference model reading circuit 21, setting reception circuit 22, output verification circuit 23, failure area identification circuit 24, importance calculation circuit 30, and display processing circuit 31 can be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC, an FPGA, or a combination thereof.

[0080] The components of the inference model verification device are not limited to those implemented by dedicated hardware; the inference model verification device may also be implemented by software, firmware, or a combination of software and firmware. When the inference model verification device is implemented by software or firmware, a program that causes a computer to execute the respective processing procedures in the inference model reading unit 1, setting acceptance unit 2, output verification unit 3, failure area identification unit 4, importance calculation unit 10, and display processing unit 11 is stored in the memory 41 shown in Figure 3. Then, the processor 42 shown in Figure 3 executes the program stored in the memory 41.

[0081] Furthermore, Figure 18 shows an example in which each component of the inference model verification device is implemented by dedicated hardware, while Figure 3 shows an example in which the inference model verification device is implemented by software or firmware. However, this is merely one example, and some components of the inference model verification device may be implemented by dedicated hardware, while the remaining components may be implemented by software or firmware.

[0082] Next, the operation of the inference model verification device shown in Figure 17 will be described. Except for the importance calculation unit 10 and the display processing unit 11, it is the same as the inference model verification device shown in Figure 1. Therefore, here we will mainly describe the operation of the importance calculation unit 10 and the display processing unit 11.

[0083] The importance calculation unit 10 obtains the verification result from the output verification unit 3. Based on the verification result from the output verification unit 3, the importance calculation unit 10 calculates the input data x ｋ Importance C of (k = 1, 2, ..., K) ｋ The importance calculation unit 10 calculates the input data x ｋ Importance level C ｋ The display processing unit 11 outputs information indicating this.

[0084] The importance calculation process by the importance calculation unit 10 will be explained in detail below. For the sake of explanation, the input data X is (x １ , x ２ , x ３ ) and input data x １ The numerical range is -3.5 ≤ x １ ≤ 5.2, input data x ２ The numerical range is 0 ≤ x ２ ≤ 10, input data x ３ The numerical range is 15 ≤ x ３ Assume that ≤ 40 and the expected output of the inference model is 50 ≤ y ≤ 80. In this case, assume that the failure region identification unit 4 identifies three failure regions as shown in Figure 19. Figure 19 is an explanatory diagram showing the three failure regions identified by the failure region identification unit 4.

[0085] In Figure 19, of the three failure areas, the failure area with ID = 1 is represented by the input data x １ The range of the failing area is 0.2 ≤ x １ ≤ 0.5, input data x ２ The range of the failing area is 5 ≤ ​​x ２ ≤ 10, input data x ３ The range of the failing area is 15 ≤ x ３ The value is ≤20. For the failure area of ​​ID = 2, the input data x １ The range of the failing area is -3.5 ≤ x １≤ 5.2, input data x ２ The range of the failing region is 0 ≤ x ２ ≤ 5, input data x ３ The range of the failing area is 20 ≤ x ３ The value is ≤30. For the failure area of ​​ID = 3, the input data x １ The range of the failing area is -3.5 ≤ x １ ≤ 5.2, input data x ２ The range of the failing region is 0 ≤ x ２ ≤ 10, input data x ３ The range of the failing area is 30 ≤ x ３ The value is ≤ 40.

[0086] The importance calculation unit 10 calculates the input data x ｋ The range of the failure region for (k=1,2,3) is the input data x ｋ Determine whether the numerical range is narrower than the specified range. In the example in Figure 19, for the failure area with ID = 1 among the three failure areas, the input data x １ The range of the failure area is input data x １ If the numerical range is determined to be narrower than the specified range, the failure area for ID = 2,3 will be determined based on the input data x １ The range of the failure area is input data x １ It is determined that the numerical range is not narrower than the specified range. The importance calculation unit 10 calculates the input data x １ Importance level C １ As input data x １ The range of the failure area is input data x １ The number of values ​​determined to be narrower than the specified numerical range is counted. In the example in Figure 19, since the count is "1", the input data x calculated by the importance calculation unit 10 is counted. １ Importance level C １ It is "1".

[0087] In the example in Figure 19, of the three failure areas, the failure areas with IDs 1 and 2 are determined by the input data x ２ The range of the failure area is input data x ２ If the numerical range is determined to be narrower than the specified range, the failure area with ID = 3 will be treated as follows: input data x ２ The range of the failure area is input data x ２It is determined that the numerical range is not narrower than the specified range. The importance calculation unit 10 calculates the input data x ２ Importance level C ２ As input data x ２ The range of the failure area is input data x ２ The number of values ​​determined to be narrower than the specified numerical range is counted. In the example in Figure 19, since the count is "2", the input data x calculated by the importance calculation unit 10 is counted. ２ Importance level C ２ The answer is "2".

[0088] In the example in Figure 19, for the failing areas ID = 1, 2, and 3, the input data x ３ The range of the failure area is input data x ３ It is determined that the numerical range is narrower than the specified range. The importance calculation unit 10 calculates the input data x ３ Importance level C ３ As input data x ３ The range of the failure area is input data x ３ The number of values ​​determined to be narrower than the specified numerical range is counted. In the example in Figure 19, since the count is "3", the input data x calculated by the importance calculation unit 10 is counted. ３ Importance level C ３ The answer is "3".

[0089] The display processing unit 11 obtains information indicating each defective area from the defective area identification unit 4. The display processing unit 11 obtains input data x from the importance calculation unit 10. ｋ Importance C of (k=1,2,3) ｋ Information indicating the following is obtained. As shown in Figure 20, the display processing unit 11 superimposes a figure indicating the defective area identified by the defective area identification unit 4 onto the slider. As shown in Figure 20, the display processing unit 11 obtains the input data x ｋ Importance level C ｋ The input data x is displayed on the display device 60. Figure 20 shows the input data x ｋ Importance level C ｋ This is an explanatory diagram showing an example of how it can be displayed.

[0090] In the above embodiment 4, the number of dimensions of the input data of the inference model is multiple, and the inference model verification device is equipped with an importance calculation unit 10 that calculates the importance of each input data based on the verification results of the output verification unit 3. The display processing unit 11 displays a figure indicating the unacceptable region identified by the unacceptable region identification unit 4 superimposed on a slider, and also displays the importance of each input data calculated by the importance calculation unit 10. Thus, the inference model verification device can clearly show the correspondence between the numerical range of the input data and the unacceptable region, as well as clearly show the importance of each input data.

[0091] The display processing units 5 and 11 according to embodiments 1 to 4 display a tree map showing a region that includes one or more unsatisfactory areas belonging to each group, as shown in Figure 7, etc. However, this is only one example, and the display processing units 5 and 11 may also display multiple groups in a pie chart, as shown in Figure 21, or display multiple groups in a table. Figure 21 is an explanatory diagram showing an example of multiple groups displayed in a pie chart. In the example in Figure 21, four groups are displayed.

[0092] Furthermore, this disclosure allows for free combination of each embodiment, modification of any component in each embodiment, or omission of any component in each embodiment.

[0093] This disclosure includes a setting reception unit that accepts operation of a slider indicating a numerical range of input data to be given to an inference model and sets the numerical range of the input data; an output verification unit that verifies whether the output of the inference model satisfies the expected output when each of the multiple input data included in the numerical range set by the setting reception unit is given to the inference model; and a failure region identification unit that identifies a failure region within the numerical range of the input data, which is a numerical range in which the output of the inference model does not satisfy the expected output, based on the verification result of the output verification unit. Furthermore, the inference model verification device includes a display processing unit that superimposes a figure indicating the failure region identified by the failure region identification unit onto the slider, making it possible to clearly show the correspondence between the numerical range of the input data and the failure region, and is suitable for an inference model verification device and an inference model verification method.

[0094] 1. Inference model loading unit, 2. Setting reception unit, 3. Output verification unit, 4. Failure area identification unit, 5. Display processing unit, 6. Group number specification unit, 7. Failure area identification unit, 8. Detailed group specification unit, 9. Failure area identification unit, 10. Importance calculation unit, 11. Display processing unit, 21. Inference model loading circuit, 22. Setting reception circuit, 23. Output verification circuit, 24. Failure area identification circuit, 25. Display processing circuit, 26. Group number specification circuit, 27. Failure area identification circuit, 28. Detailed group specification circuit, 29. Failure area identification circuit, 30. Importance calculation circuit, 31. Display processing circuit, 41. Memory, 42. Processor, 60. Display device.

Claims

1. An inference model verification device comprising: a setting reception unit that accepts operation of a slider indicating a numerical range of input data to be given to an inference model and sets the numerical range of the input data; an output verification unit that verifies whether the output of the inference model satisfies the expected output when each of a plurality of input data included in the numerical range set by the setting reception unit is given to the inference model; a failure area identification unit that identifies a failure area within the numerical range of the input data in which the output of the inference model does not satisfy the expected output, based on the verification result of the output verification unit; and a display processing unit that superimposes a figure indicating the failure area identified by the failure area identification unit onto the slider.

2. The inference model verification apparatus according to claim 1, characterized in that the display processing unit superimposes a figure indicating the defective area on the slider only when the defective area identified by the defective area identification unit is included in the numerical range of the input data.

3. The inference model verification apparatus according to claim 1 or 2, characterized in that the failure region identification unit identifies multiple failure regions within the numerical range of the input data in which the output of the inference model does not satisfy the expected output, and groups the multiple failure regions, and the display processing unit displays a figure indicating the failure regions identified by the failure region identification unit superimposed on the slider, as well as a figure indicating a region that includes one or more failure regions belonging to each group.

4. The inference model verification apparatus according to claim 3, characterized in that the setting reception unit changes the numerical range of the input data to a region that includes one or more unacceptable regions belonging to any group by receiving the operation of the slider.

5. The inference model verification apparatus according to claim 3, further comprising a group number specification unit that accepts a specification of the number of groups when the failure area identification unit performs grouping, wherein the failure area identification unit performs grouping of the plurality of failure areas for the group of the specified number of groups.

6. The inference model verification apparatus according to claim 3, comprising a detailed group designation unit that accepts the designation of a detailed group which is a group that is further subdivided from among multiple groups, and the designation of the level of detail for the detailed group, wherein the rejection area identification unit divides one or more rejection areas belonging to the detailed group into a number of groups indicated by the level of detail.

7. The inference model verification device according to any one of claims 1 to 6, wherein the input data of the inference model has multiple dimensions, and the device includes an importance calculation unit that calculates the importance of each input data based on the verification results of the output verification unit, and the display processing unit displays a figure indicating the failure region identified by the failure region identification unit superimposed on the slider, as well as the importance of each input data calculated by the importance calculation unit.

8. The inference model verification device according to any one of claims 1 to 7, characterized in that the shape of the figure indicating the failure area is rectangular.

9. An inference model verification method in which a setting reception unit receives an operation on a slider indicating a numerical range of input data to be given to an inference model and sets the numerical range of the input data; an output verification unit verifies whether the output of the inference model satisfies the expected output when each of the multiple input data included in the numerical range set by the setting reception unit is given to the inference model; a failure area identification unit identifies a failure area within the numerical range of the input data, which is a numerical range in which the output of the inference model does not satisfy the expected output, based on the verification result of the output verification unit; and a display processing unit overlays a figure indicating the failure area identified by the failure area identification unit onto the slider.

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