Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device which has: a first nanosheet transistor; a second nanosheet transistor layered on the first nanosheet transistor; and an intermediate element isolation region disposed between the first nanosheet transistor and the second nanosheet transistor. The intermediate element isolation region has an insulating layer embedded between a semiconductor layer or a gate electrode forming the first nanosheet transistor, and a semiconductor layer or a gate electrode forming the second nanosheet transistor.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] A gate-all-around semiconductor device (Gate All Around Field Effect Transistor; GAA-FET) using nanosheets is known. Further, a CFET (Complementary Field-Effect Transistor) having a structure in which GAA-FETs are vertically stacked is known (see, for example, Patent Document 1 and Patent Document 2). The CFET described in Patent Document 1 has a structure in which nanosheet transistors of different conductivity types are vertically stacked. This CFET has a CMOS (complementary metal oxide semiconductor) logic circuit in which one nanosheet transistor is formed of a PMOS (p-type metal oxide semiconductor) and the other nanosheet transistor is formed of an NMOS (n-type metal oxide semiconductor).

[0003] U.S. Patent Publication No. 2024 / 0387286, U.S. Patent Publication No. 2021 / 0006739

[0004] A CFET has MDI (middle dielectric isolation) formed of an insulating layer as an intermediate element isolation region between an upper transistor and a lower transistor. The insulating layer constituting MDI, the semiconductor layer of the transistor and the substrate cannot be formed by mutual epitaxial growth. For this reason, the insulating layer constituting MDI cannot be formed in the step of laminating semiconductor layers, and it is necessary to replace the semiconductor layer with the insulating layer and embed it in the intermediate portion of the CFET in a subsequent step. However, the replacement of the semiconductor layer with the insulating layer for forming MDI needs to be performed in a narrow region between separated stacked bodies of semiconductor layers. That is, it is necessary to remove the semiconductor layer and embed MDI from a narrow region between separated elements.

[0005] To solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device that can form an insulating layer between an upper transistor and a lower transistor by a simple method.

[0006] The semiconductor device of the present invention comprises a nanosheet transistor having a semiconductor layer formed by nanosheets and a gate electrode stacked on the semiconductor layer. The semiconductor device has a first nanosheet transistor, a second nanosheet transistor stacked on the first nanosheet transistor, and an intermediate element isolation region disposed between the first nanosheet transistor and the second nanosheet transistor. The intermediate element isolation region has an insulating layer embedded between the gate electrode or semiconductor layer constituting the first nanosheet transistor and the gate electrode or semiconductor layer constituting the second nanosheet transistor.

[0007] Furthermore, the present invention provides a method for manufacturing a semiconductor device, which involves manufacturing a semiconductor device in which nanosheet transistors are stacked, each having a semiconductor layer formed from nanosheets and a gate electrode stacked on the semiconductor layer. The method for manufacturing a semiconductor device includes the steps of forming a first stack on a substrate, comprising a first channel semiconductor layer, a first sacrificial semiconductor layer, a second sacrificial semiconductor layer, a second channel semiconductor layer, and a third sacrificial semiconductor layer, and replacing the second sacrificial semiconductor layer with a single-layer insulating layer. The method for manufacturing a semiconductor device also includes the steps of forming a dummy gate on the first stack, transferring the pattern of the dummy gate to the first stack, forming a gate spacer on the sacrificial insulating layer and the side surface of the dummy gate, and replacing a portion of the side surface of the first sacrificial semiconductor layer and the third sacrificial semiconductor layer with an inner spacer. Furthermore, the method for manufacturing a semiconductor device includes the steps of forming source and drain regions on the side surfaces of the first channel semiconductor layer and the second channel semiconductor layer, and replacing the dummy gate, the first sacrificial semiconductor layer, and the third sacrificial semiconductor layer with a gate electrode. The method for manufacturing a semiconductor device involves, in the step of forming a first laminate, forming a second laminate consisting of a first channel semiconductor layer and a first sacrificial semiconductor layer on a substrate, forming a second sacrificial semiconductor layer on the second laminate, and forming a third laminate consisting of a second channel semiconductor layer and a third sacrificial semiconductor layer on the second sacrificial semiconductor layer.

[0008] According to the present invention, a method for manufacturing a semiconductor device and a semiconductor device can be provided that enable the formation of an insulating layer between an upper transistor and a lower transistor by a simple method.

[0009] This is a cross-sectional view showing the schematic configuration of a conventional semiconductor device. This is a cross-sectional view in the gate length direction showing the schematic configuration of the semiconductor device of the first embodiment. This is a cross-sectional view in the gate width direction showing the schematic configuration of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate length direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the first embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the second embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the third embodiment.This is a manufacturing process diagram (gate length direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate length direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the third embodiment. This is a manufacturing process diagram (gate width direction) for the semiconductor device of the third embodiment.

[0010] The following describes examples of embodiments for carrying out the present invention, but the present invention is not limited to these examples. The explanation will be in the following order: 1. Method for manufacturing a semiconductor device and an overview of the semiconductor device 2. Semiconductor device of the first embodiment and method for manufacturing a semiconductor device 3. Semiconductor device of the second embodiment and method for manufacturing a semiconductor device

[0011] <1. Method for Manufacturing a Semiconductor Device and Overview of the Semiconductor Device> Before describing specific embodiments of the present invention, an overview of the semiconductor device will be described below. Figure 1 shows a schematic configuration of the semiconductor device. Figure 1 is a cross-sectional view of the semiconductor device in the gate length direction. In the following description, only the main components of the semiconductor device are shown in the drawings, and other components such as insulating layers are omitted from the description.

[0012] As shown in Figure 1, the semiconductor device 10 is a CFET (Complementary Field Effect Transistor) in which nanosheet transistors (semiconductor elements) having a GAA-FET (Gate All Around Field Effect Transistor) structure are stacked vertically. In semiconductor devices, nanosheets also include nanowires. Therefore, Figure 1 shows a cross-sectional view in the gate length direction of the nanosheet transistors arranged on the upper layer side and the nanosheet transistors arranged on the lower layer side of the CFET.

[0013] As shown in Figure 1, in a cross-sectional view in the gate length direction, the semiconductor device 10 has a CFET in which nanosheet transistors of different conductivity types are stacked vertically. On the substrate 11, the semiconductor device 10 has a transistor Tr20 on the lower layer side and a transistor Tr30 on the upper layer side. An intermediate element isolation region 40 is provided between the lower transistor Tr20 and the upper transistor Tr30. That is, the semiconductor device 10 has a stacked structure of transistor Tr20, intermediate element isolation region 40, and transistor Tr30.

[0014] The upper transistor Tr30 and the lower transistor Tr20 share a gate electrode 16. The upper transistor Tr30 and the lower transistor Tr20 each have a stacked structure of the gate electrode 16 and semiconductor layers 21 and 31. The semiconductor device 10 also has source and drain regions 23 and 33 adjacent to the above stacked structure. The semiconductor layers 21 and 31 are the channel regions of transistors Tr20 and Tr30. The semiconductor layers 21 and 31 are composed of nanosheet semiconductor layers.

[0015] The lower transistor Tr20 has a stacked structure on the substrate 11 consisting of a gate electrode 16 and a semiconductor layer 21. The lower transistor Tr20 has a source / drain region 23 located adjacent to this stacked structure. The upper transistor Tr30 has a stacked structure consisting of a gate electrode 16 and a semiconductor layer 31. The upper transistor Tr30 has a source / drain region 33 located adjacent to this stacked structure. In the semiconductor device 10, adjacent transistors Tr20 and Tr30 in the substrate direction share source / drain regions 23 and 33. In the CFET, transistors Tr20 that share a source / drain region 23 formed on the lower side each have the same structure. Similarly, transistors Tr30 that share a source / drain region 33 formed on the upper side each have the same structure.

[0016] The semiconductor device 10 has an intermediate element isolation region 40 between the lower transistor Tr20 and the upper transistor Tr30. The intermediate element isolation region 40 has an MDI (middle dielectric isolation) 41 formed by an insulating layer. The intermediate element isolation region 40 also has a stacked structure of gate electrode 16 and MDI 41 [MDI 41 / gate electrode 16 / MDI 41 / gate electrode 16 / MDI 41] between the upper transistor Tr30 and the lower transistor Tr20. The MDI 41 is formed of a nanosheet (nanosheet insulating layer) with approximately the same thickness as the semiconductor layers 21 and 31. In the semiconductor device 10, the intermediate element isolation region 40, where the gate electrode 16 and MDI 41 are stacked, does not function as a transistor. The intermediate element isolation region 40 has an insulating layer 43 adjacent to the stacked structure of gate electrode 16 and MDI 41. The insulating layer 43 is placed between the source / drain region 23 of the lower transistor Tr20 and the source / drain region 33 of the upper transistor Tr30. The semiconductor device 10 is separated from the lower transistor Tr20 by the MDI 41 and the insulating layer 43.

[0017] The semiconductor device 10 of the CFET with the above structure is formed by epitaxial growth of a laminate consisting of a semiconductor layer that will serve as the sacrificial layer for the gate electrode 16, semiconductor layers 21 and 31 that will serve as the channel region, and a semiconductor layer that will serve as the sacrificial layer for the MDI 41. Then, after separating the laminate in the gate width direction or the gate length direction, the semiconductor layer that will serve as the sacrificial layer for the MDI 41 is removed from between the separated laminates (trench). Then, an insulating layer that constitutes the MDI 41 is embedded in the space where the semiconductor layer that will serve as the sacrificial layer for the MDI 41 was removed.

[0018] In the manufacturing method described above, the insulating layer constituting MDI41, the sacrificial semiconductor layer, and the semiconductor layer forming the channel region cannot be formed by epitaxial growth of each other. Therefore, the semiconductor layer that will serve as the sacrificial layer of MDI41 is formed by epitaxial growth together with the sacrificial layer or the semiconductor layer forming the channel region. Then, it is necessary to remove the semiconductor layer that will serve as the sacrificial layer of MDI41 from the laminate formed by the three types of semiconductor layers and replace it with an insulating layer.

[0019] However, the removal of semiconductor layers and replacement of insulating layers for forming the MDI41 must be performed in a narrow region between elements. In particular, in CFETs, the number of stacked semiconductor layers is large and the height of the stack is large, so the trench depth for separating the stack is large. For this reason, the removal of semiconductor layers and replacement of insulating layers must be performed in trenches between elements with narrow openings and large depths. As a result, the above manufacturing method makes it difficult to completely remove the semiconductor layers that serve as sacrificial layers for the MDI41. In particular, since it is necessary to completely remove the semiconductor layers that serve as sacrificial layers for the MDI41 while leaving the semiconductor layers that serve as sacrificial layers for the gate electrode intact, the semiconductor layers that serve as sacrificial layers for the MDI41 tend to remain between the semiconductor layers that serve as sacrificial layers for the gate electrode. If semiconductor layers remain, the characteristics of the semiconductor device 10 are likely to change due to an increase in capacitance, etc. Also, because the insulating layers constituting the MDI41 are formed from narrow and deep trenches, it is difficult to embed the insulating layers, and voids tend to occur. Unintended voids within the element may have adverse effects such as changes in semiconductor characteristics and a decrease in reliability.

[0020] <2. Semiconductor device of the first embodiment and method for manufacturing a semiconductor device> The configuration of the semiconductor device of the first embodiment of the present invention and specific embodiments of the method for manufacturing a semiconductor device will be described below. [Configuration of the semiconductor device] Figure 2 shows a schematic configuration diagram of the semiconductor device of the first embodiment. Figure 2A is a cross-sectional view of the semiconductor device in the gate length direction. Figure 2B is a cross-sectional view of the semiconductor device in the gate width direction.

[0021] [Cross-sectional configuration] (Gate length direction) As shown in Figure 2A, in the cross-sectional view in the gate length direction, the semiconductor device 100 has a CFET in which GAA-FETs of different conductivity types are stacked vertically. The semiconductor device 100 has a transistor Tr20 (first nanosheet transistor) on the lower layer side on the substrate 101. The semiconductor device 100 has a transistor Tr30 (second nanosheet transistor) on the upper layer side on top of transistor Tr20. In the example shown in Figure 2A, the semiconductor device 100 has transistor Tr30 arranged on top of transistor Tr20. For example, in the semiconductor device 100, the lower layer transistor Tr20 is of the second conductivity type, and the upper layer transistor Tr30 is of the first conductivity type. In the semiconductor device 100, the first conductivity type is p-type and the second conductivity type is n-type. That is, in the semiconductor device 100, transistor Tr30 is PMOS and transistor Tr20 is NMOS. The conductivity types of the semiconductor device 100 may be reversed.

[0022] The semiconductor device 100 has stacked transistors Tr20 and Tr30 that share a gate electrode 16. Transistors Tr20 and Tr30 each have a stacked structure of a gate electrode 16 and a semiconductor layer (hereinafter also referred to as a first channel semiconductor layer) 21 and a semiconductor layer (hereinafter also referred to as a second channel semiconductor layer) 31. Transistor Tr20 has a semiconductor layer (hereinafter also referred to as a first channel semiconductor layer) 21 that forms a channel region. Transistor Tr30 has a semiconductor layer (hereinafter also referred to as a second channel semiconductor layer) 31 that forms a channel region. The semiconductor layers 21 and 31 are composed of nanosheet semiconductor layers. A gate insulating film (not shown) and a high dielectric constant insulating layer (not shown) are placed between the gate electrode 16 and the semiconductor layers 21 and 31.

[0023] The semiconductor device 100 has source and drain regions 23 and 33 adjacent to the stacked structure. In the semiconductor device 100, adjacent lower-layer transistors Tr20 in the substrate surface direction share a source and drain region 23. In the semiconductor device 100, adjacent upper-layer transistors Tr30 in the substrate surface direction share a source and drain region 33. In the semiconductor device 100, transistors Tr20 that share a source and drain region 23 formed on the lower layer have the same configuration. In the semiconductor device 100, transistors Tr30 that share a source and drain region 33 formed on the upper layer have the same configuration.

[0024] The lower transistor Tr20 has a stacked structure on the substrate 101 consisting of a gate electrode 16 and a semiconductor layer 21 [gate electrode 16 / semiconductor layer 21 / gate electrode 16 / semiconductor layer 21 / gate electrode 16]. The transistor Tr20 has a source / drain region 23 arranged adjacent to this stacked structure. The semiconductor layer 21 is formed continuously between the source / drain region 23. The transistor Tr20 has an inner spacer 25 between the gate electrode 16 and the source / drain region 23. The inner spacer 25 is stacked on the semiconductor layer 21 together with the gate electrode 16.

[0025] The upper transistor Tr30 is formed above transistor Tr20. Transistor Tr30 has a stacked structure of gate electrode 16 and semiconductor layer 31 [gate electrode 16 / semiconductor layer 31 / gate electrode 16 / semiconductor layer 31 / gate electrode 16]. Transistor Tr30 has a source / drain region 33 arranged adjacent to this stacked structure. The semiconductor layer 31 is formed continuously between the source / drain region 33. The semiconductor device 100 has an inner spacer 35 between the gate electrode 16 and the source / drain region 33. The inner spacer 35 is stacked with the semiconductor layer 31 together with the gate electrode 16.

[0026] The semiconductor device 100 has an intermediate element isolation region 40 between the lower layer (substrate 101 side) transistor Tr20 and the upper layer transistor Tr30 stacked on top of them. That is, the semiconductor device 10 has a stacked structure of transistor Tr20, intermediate element isolation region 40, and transistor Tr30. The intermediate element isolation region 40 has an MDI (middle dielectric isolation) 45 formed by an insulating layer. The MDI 45 is continuously formed by a single insulating layer between the stacked structure of the lower layer transistor Tr20 and the stacked structure of the upper layer transistor Tr30. The semiconductor device 100 is isolated from the lower layer transistor Tr20 and the upper layer transistor Tr30 by the MDI 45.

[0027] Furthermore, in the semiconductor device 100, the gate electrode 16 of the uppermost layer of the transistor Tr30 extends perpendicularly to the substrate surface beyond the portion where it is stacked with the semiconductor layers 21 and 31. The semiconductor device 100 also has a gate spacer 109 on the side surface of the extended uppermost gate electrode 16.

[0028] The semiconductor device 100 has a bottom element isolation region 50 on a substrate 101. The bottom element isolation region 50 has a BDI (Base Diffusion Isolation) 103 and a liner layer 107 (Figure 2B). The semiconductor device 100 has transistors Tr20 and Tr30 on the bottom element isolation region 50. That is, the bottom element isolation region 50 is formed between the substrate 101 and the lower transistor Tr20. The semiconductor device 100 has a stacked structure on the substrate 101 consisting of the bottom element isolation region 50, the lower transistor Tr20, the intermediate element isolation region 40, and the upper transistor Tr30.

[0029] (Gate width direction) As shown in Figure 2B, in the cross-sectional view in the gate width direction, the semiconductor device 100 has a transistor Tr20 on the lower layer side on the substrate 101. The semiconductor device 100 also has a transistor Tr30 on the upper layer side on top of the transistor Tr20. Furthermore, the semiconductor device 100 has an intermediate element isolation region 40 made of a single-layer insulating layer between the lower transistor Tr20 and the upper transistor Tr30.

[0030] The lower transistor Tr20 and the upper transistor Tr30 share a common gate electrode 16. Transistor Tr20 has a stacked structure on the substrate 101 consisting of a gate electrode 16 and a semiconductor layer 21 [gate electrode 16 / semiconductor layer 21 / gate electrode 16 / semiconductor layer 21 / gate electrode 16]. Transistor Tr30 has a stacked structure consisting of a gate electrode 16 and a semiconductor layer 31 [gate electrode 16 / semiconductor layer 31 / gate electrode 16 / semiconductor layer 31 / gate electrode 16].

[0031] Furthermore, in the semiconductor device 100, the entire periphery of the cross-section in the gate width direction of the semiconductor layers 21 and 31, which form the channel regions of transistors Tr20 and 30, is surrounded by the gate electrode 16. The gate electrode 16 is formed continuously from transistor Tr20 to transistor Tr30. In the semiconductor device 100, a high dielectric constant insulating layer (not shown) and a gate insulating layer (not shown) are interposed between the gate electrode 16 and the channel semiconductor layers 21 and 31. The channel semiconductor layers 21 and 31 are formed within the region surrounded by the high dielectric constant insulating layer and the gate insulating layer.

[0032] The semiconductor device 100 has a BDI 103 as a bottom element isolation region 50 and a thin film liner layer 107 on a substrate 101. The BDI 103 is formed of an insulating material deposited on the substrate 101. The BDI 103 is formed over the entire surface of the substrate 101. The BDI 103 is separated by the liner layer 107 into a region directly beneath the laminate of the gate electrode 16 and the semiconductor layers 21 and 31, and a region excluding the region directly beneath the laminate of the gate electrode 16 and the semiconductor layers 21 and 31. In the region excluding the region directly beneath the laminate of the gate electrode 16 and the semiconductor layers 21 and 31, the liner layer 107 is interposed between the substrate 101 and the BDI 103. The liner layer 107 is also interposed between the substrate 101 and the BDI 103 in the region excluding the region directly beneath the laminate of the gate electrode 16 and the semiconductor layers 21 and 31. In the region of the BDI 103 excluding the area directly beneath the laminate of the gate electrode 16 and semiconductor layers 21 and 31, the bottom surface and the side surfaces in the gate width direction are covered by the liner layer 107.

[0033] In the semiconductor device 100, transistors Tr20 and Tr30 are formed on a BDI 103 and a liner layer 107. That is, in the semiconductor device 100, the BDI 103 and the liner layer 107 are interposed between the substrate 101 and transistors Tr20 and Tr30. Therefore, in the semiconductor device 100, the lowest semiconductor layer 21 of the lower transistor Tr20, the source / drain region 23, and the gate electrode 16 common to transistors Tr20 and Tr30 do not directly contact the substrate 101.

[0034] [Element Isolation] (Intermediate Element Isolation Region) In the conventional semiconductor device 10 shown in Figure 1 above, the intermediate element isolation region 40 is formed by a stacked structure of MDI 41 and gate electrode 16. On the other hand, the semiconductor device 100 shown in Figures 2A and 2B has an intermediate element isolation region 40 between the lower transistor Tr20 and the upper transistor Tr30. In the semiconductor device 100, the intermediate element isolation region 40 is formed by MDI 45, which is made of a single layer insulating layer. In the intermediate isolation region 40 of the semiconductor device 100, the single layer MDI 45 is embedded between the uppermost gate electrode 16 or channel semiconductor layer 21 that constitutes the lower transistor Tr20 and the lowest gate electrode 16 or semiconductor layer 31 that constitutes the upper transistor Tr30. The intermediate element isolation region 40 of the semiconductor device 100 does not have a gate electrode 16 or semiconductor layers 21, 31 inside the MDI 45.

[0035] The MDI 45 has a length in the gate length direction shown in Figure 2A that is the same as the combined length in the gate length direction of the gate electrode 16 and inner spacers 25 and 35, and the combined length of the gate electrode 16 and gate spacer 109. Furthermore, the MDI 45 has a length in the gate width direction shown in Figure 2B that is the same as the length in the gate width direction of the semiconductor layers 21 and 31. The MDI 45 is filled with an insulating material. The MDI 45 may be a single-layer insulating layer, or it may be an insulating layer consisting of multiple layers of multiple insulating materials.

[0036] In conventional semiconductor devices 10, the nanosheets of the semiconductor layer (third semiconductor layer) formed by epitaxial growth are replaced with an insulating layer that becomes the MDI 41. This presents challenges such as the generation of semiconductor layer residue during the nanosheet removal process and incomplete embedding during the insulating layer embedding process. In contrast, in the semiconductor device 100 of this embodiment, since the MDI 45 is a single-layer insulating layer, it is not necessary to form the semiconductor layer that serves as the sacrificial layer for the MDI formed by epitaxial growth using nanosheets. That is, it is not necessary to form the semiconductor layer that serves as the sacrificial layer for the gate electrode in the region where the MDI 45 is formed. Therefore, it is not necessary to completely remove the semiconductor layer that serves as the sacrificial layer for the MDI 45 while leaving the semiconductor layer that serves as the sacrificial layer for the gate electrode in place. As a result, residue of the semiconductor layer that serves as the sacrificial layer for the MDI 45 is less likely to remain between layers, making it easier to remove the semiconductor layer. Furthermore, in the intermediate element isolation region 40 of the semiconductor device 100, a semiconductor layer that serves as a sacrificial layer for the gate electrode is not required. Therefore, a larger space is secured for embedding the sacrificial layer that will become the MDI 45 compared to the case where nanosheets are substituted. This makes it easier to embed the insulating layer that will become the MDI 45.

[0037] The intermediate element isolation region 40 is formed, for example, with a thickness of approximately 10 nm to 100 nm. Preferably, the intermediate element isolation region 40 is formed with a thickness of approximately 20 nm to 50 nm. In the intermediate element isolation region 40, the MDI 45 contains silicon oxide. The silicon oxide in the MDI 45 includes one or more selected from SiO, SiON, SiOC, and SiOCN.

[0038] (Bottom element isolation region) Furthermore, the semiconductor device 100 shown in Figures 2A and 2B has a bottom element isolation region 50 between the substrate 101 and the transistors Tr20 and 30. The bottom element isolation region 50 has a BDI 103 for element isolation. The BDI 103 is formed over the entire surface of the substrate 101 beneath the transistors Tr20 and 30. As a result, the semiconductor layer 21 and 31, source and drain regions 23 and 33, and gate electrode 16 constituting the transistors Tr20 and 30 do not come into contact with the substrate 101. As a result, the semiconductor device 100 can reduce leakage current through the substrate 101. The BDI 103 contains silicon oxide. The silicon oxide in the BDI 103 includes one or more selected from SiO, SiON, SiOC, and SiOCN.

[0039] [Method for Manufacturing a Semiconductor Device] Next, a method for manufacturing the semiconductor device of the first embodiment described above will be explained. Figures 3 to 10 show an example of a method for manufacturing the semiconductor device of the first embodiment. In the following explanation, the reference numerals for the semiconductor device 100 shown in Figure 2 above will also be used for clarity of the configuration.

[0040] In the manufacturing process of the semiconductor device 100, first, a laminate (hereinafter also referred to as the first laminate) of the fourth sacrificial semiconductor layer 42, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the second sacrificial semiconductor layer 44, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 is formed, as shown in Figures 3A and 3B. Figure 3A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 3B. Figure 3B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 3A.

[0041] In this step, first, a fourth sacrificial semiconductor layer 42 serving as a sacrificial layer for BDI 103 is formed on a substrate 101 by epitaxial growth. The fourth sacrificial semiconductor layer 42 is formed of SiGe containing a high concentration of Ge. For the high Ge concentration SiGe, the Ge content is preferably 40% or more and 75% or less, more preferably 50% or more and 55% or less. The fourth sacrificial semiconductor layer 42 is formed to have a thickness sufficient to ensure insulation, for example, about 10 nm or more and 100 nm or less. Preferably, the fourth sacrificial semiconductor layer 42 is formed to have a thickness of 20 nm or more and 50 nm or less.

[0042] Next, an alternating laminate (hereinafter also referred to as a second laminate) of a first sacrificial semiconductor layer 22 serving as a sacrificial layer for a gate electrode 16 and a first channel semiconductor layer 21 serving as a channel region of a lower-layer transistor Tr20 is formed on the fourth sacrificial semiconductor layer 42 by epitaxial growth. In FIGS. 3A and 3B, the first sacrificial semiconductor layer 22 is formed on the fourth sacrificial semiconductor layer 42 side (the substrate 101 side), and four layers of the first sacrificial semiconductor layer 22 and three layers of the first channel semiconductor layer 21 are formed respectively. The first sacrificial semiconductor layer 22 is formed of low Ge concentration SiGe having a lower Ge concentration than the fourth sacrificial semiconductor layer 42. For the low Ge concentration SiGe, for example, the Ge content is preferably 15% or more and 35% or less, more preferably 20% or more and 25% or less. The first channel semiconductor layer 21 is formed of Ge-free Si, or SiGe having an even lower Ge concentration that exhibits etching selectivity with respect to low Ge concentration SiGe. Each of the first sacrificial semiconductor layer 22 and the first channel semiconductor layer 21 is formed to have a thickness of about 5 to 15 nm, for example.

[0043] Next, a second sacrificial semiconductor layer 44, which will serve as a sacrificial layer for the MDI 45, is formed on an alternating stack of the first sacrificial semiconductor layer 22 and the first channel semiconductor layer 21 by epitaxial growth. The second sacrificial semiconductor layer 44 can be formed in the same manner as the fourth sacrificial semiconductor layer 42 described above. The second sacrificial semiconductor layer 44 is formed of SiGe containing a high concentration of Ge. The high Ge concentration SiGe preferably has a Ge content of 40% to 75%, and more preferably 50% to 55%. The second sacrificial semiconductor layer 44 is formed to a thickness sufficient to ensure insulation, for example, about 10 nm to 120 nm. Preferably, the second sacrificial semiconductor layer 44 is formed to a thickness of about 30-100 nm.

[0044] Next, an alternating stack (hereinafter also referred to as the third stack) is formed on the second sacrificial semiconductor layer 44, consisting of a third sacrificial semiconductor layer 32 which will serve as the sacrificial layer for the gate electrode 16, and a semiconductor layer (hereinafter referred to as the second channel semiconductor layer) 31 which will serve as the channel region for the upper transistor Tr 30. In Figures 3A and 3B, the third sacrificial semiconductor layer 32 is formed on the second sacrificial semiconductor layer 44 side (substrate 101 side), and three layers each of the third sacrificial semiconductor layer 32 and the second channel semiconductor layer 31 are formed. The third sacrificial semiconductor layer 32 can be formed in the same manner as the first sacrificial semiconductor layer 22 described above. The second channel semiconductor layer 31 can be formed in the same manner as the first channel semiconductor layer 21 described above. The third sacrificial semiconductor layer 32 is formed of SiGe with a lower Ge concentration than the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44. For low-Ge concentration SiGe, for example, a Ge content of 15% to 35% is preferred, and 20% to 25% is more preferred. The second channel semiconductor layer 31 is formed of Si that does not contain Ge, or SiGe with an even lower Ge concentration that has etching selectivity to low-Ge concentration SiGe. The third sacrificial semiconductor layer 32 and the second channel semiconductor layer 31 are formed, for example, with a thickness of about 5-15 nm for each layer.

[0045] Next, as shown in Figures 4A and 4B, the laminate of the fourth sacrificial semiconductor layer 42, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the second sacrificial semiconductor layer 44, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 is separated in the gate width direction to form a fin-shaped laminate. Figure 4A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 4B. Figure 4B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 4A. The separation of the laminate is performed using known methods such as forming a hard mask made of SiO or SiN on the laminate structure, forming a pattern on the hard mask, or transferring the hard mask pattern to the laminate structure using reactive ion etching (RIE).

[0046] Next, as shown in FIG. 5A and FIG. 5B, a liner layer 107 is formed to cover the stacked body of the fourth sacrificial semiconductor layer 42, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the second sacrificial semiconductor layer 44, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32. FIG. 5A is a cross-sectional view of the semiconductor device 100 in the gate length direction, and corresponds to the cross-sectional view taken along line A-A shown in FIG. 5B. Further, FIG. 5B is a cross-sectional view of the semiconductor device 100 in the gate width direction, and corresponds to the cross-sectional view taken along line B-B shown in FIG. 5A. Note that FIG. 5A shows not only the cross-sectional view of the semiconductor device 100 in the gate length direction, but also the configuration viewed from the side direction for explaining the configuration. Also in FIG. 5A, each layer of the stacked body disposed below the liner layer 107 is indicated by a broken line. As shown in FIG. 5B, the liner layer 107 is formed so as to cover the side surfaces and the top surface in the gate width direction. Further, as shown in FIG. 5A, the liner layer 107 is formed not on the entire surface of the stacked body but with a predetermined interval in the gate length direction. For example, when separating the stacked body in the gate length direction, the liner layer 107 is formed in a region from which the stacked body is removed. For the liner layer 107, one or more insulating layers selected from, for example, SiN, SiO, SiOC, SiON, SiOCN, SiBCN and the like are used by using chemical vapor deposition (Chemical Vapor Deposition: CVD), ALD (Atomic Layer Deposition) or the like. The liner layer 107 may have a stacked structure of SiO, SiN or the like.

[0047] Next, as shown in Figures 6A and 6B, the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 are removed. Figure 6A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 6B. Figure 6B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 6A. In Figure 6A, not only is the cross-sectional view of the semiconductor device 100 in the gate length direction shown, but the configuration viewed from the side is also shown for explanation purposes. In Figure 6A, each layer of the laminate located below the liner layer 107 is shown with dashed lines. In this step, the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 are removed using chemical dry etching (CDE) or wet etching.

[0048] Next, as shown in Figures 7A and 7B, an insulating layer 105 is formed over the entire surface of the substrate 101. Figure 7A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 7B. Figure 7B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 7A. In addition to the cross-sectional view of the semiconductor device 100 in the gate length direction, Figure 7A also shows the configuration as seen from the side for explanation purposes. In Figure 7A, each layer of the laminate, which is located below the insulating layer 105 and the liner layer 107, is shown with dashed lines. In this step, the insulating layer 105 is formed using CVD or the like, from one or more materials selected from, for example, SiN, SiO, SiOC, SiON, SiOCN, and SiBCN. The insulating layer 105 covers the entire surface of the liner layer 107, the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22, the laminate of the second channel semiconductor layer 31 and the third sacrificial semiconductor layer 32, and the substrate 101. The insulating layer 105 is then embedded in the gaps left by the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 that were removed in a previous step.

[0049] Next, as shown in Figures 8A and 8B, the upper part of the formed insulating layer 105 is removed. Figure 8A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 8B. Figure 8B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 8A. In this step, anisotropic etching such as reactive ion etching (RIE) is performed on the insulating layer 105 formed on the entire surface of the substrate 101. Anisotropic etching removes the insulating layer 105 to a position lower than the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22 of the lower transistor Tr20. Anisotropic etching also removes the liner layer 107 along with the insulating layer 105 to a position lower than the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22 of the lower transistor Tr20. Furthermore, in this process, the insulating layer 105 is removed by anisotropic etching, so the insulating layer 105 embedded in the gaps of the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 remains. As a result, as shown in Figures 8A and 8B, the insulating layer 105 is separated into BDI 103 and MDI 45. BDI 103 remains on the substrate between the laminates and in the region embedded in the gap of the fourth sacrificial semiconductor layer 42. MDI 45 remains in the region embedded in the gap of the second sacrificial semiconductor layer 44. Then, a laminate of BDI 103, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 is formed on the substrate 101.

[0050] Next, as shown in Figures 9A and 9B, a sacrificial insulating layer 17 and a dummy gate 18 are formed. Figure 9A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 9B. Figure 9B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 9A. The sacrificial insulating layer 17 is formed by depositing SiO, etc., on the upper surface of the BDI 103 and on the upper and side surfaces of the laminate of the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 using CVD or the like. The dummy gate 18 is formed by depositing a hard mask of a-Si, SiO, and SiN, etc., on the sacrificial insulating layer 17 using CVD or the like, and then planarizing it using chemical mechanical polishing (CMP) or the like.

[0051] Next, as shown in Figures 10A and 10B, the laminate is separated in the gate length direction to form inner spacers 25, 35 and source / drain regions 23, 33. Figure 10A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 10B. Figure 10B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 10A. In this step, first, the dummy gate 18 is processed to have the same pattern as the gate electrode 16. For example, a photoresist layer with the same pattern as the gate electrode 16 is formed on the dummy gate 18 using a photolithography process. Then, the pattern is transferred to the dummy gate 18 using the photoresist layer as a mask. Furthermore, the dummy gate 18 formed with the same pattern as the gate electrode 16 is used as a mask to transfer the same pattern as the gate electrode 16 to the sacrificial insulating layer 17.

[0052] Next, gate spacers 109 are formed on the patterned sacrificial insulating layer 17 and on the side surfaces of the dummy gate 18. The gate spacers 109 are formed by, for example, using CVD to form gate spacers 109 made of SiN, SiOCN, etc., on the entire surface of the laminate of the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32, as well as the dummy gate 18 and the sacrificial insulating layer 17. Then, anisotropic etching such as RIE is performed on the formed gate spacers 109 and the laminate of the fin-shaped first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32. This process removes the gate spacers 109 from the top surface of the dummy gate 18 and the horizontal surfaces on the laminate. Furthermore, gate spacers 109 are left on the side surfaces of the dummy gate 18 and the sacrificial insulating layer 17. In addition, the top surface of the dummy gate 18 and the top surface of the laminate are exposed.

[0053] Furthermore, anisotropic etching such as RIE is performed on the laminate of the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 using the dummy gate 18 and the gate spacer 109 as masks. This leaves the pillar-shaped laminate of the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the MDI 45, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 directly beneath the dummy gate 18 and the gate spacer 109.

[0054] Next, the sides of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 exposed in the gate length direction are selectively etched to partially remove the sides of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32. This creates recesses on the sides of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 relative to the sides of the first channel semiconductor layer 21 and the second channel semiconductor layer 31. Then, an inner spacer 25 is formed in the recess of the first sacrificial semiconductor layer 22, and an inner spacer 35 is formed in the recess of the third sacrificial semiconductor layer 32. The selective etching of the sides of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 is performed using isotropic etching, such as atomic layer etching (ALE), quasi-ALE, or selective vapor phase etching. In this process, a method is used that allows for selective etching of the low-Ge concentration SiGe constituting the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32, and the Si constituting the first channel semiconductor layer 21 and the second channel semiconductor layer 31. Furthermore, the inner spacers 25 and 35 are formed by depositing an insulating layer, such as SiN, SiO, SiOC, SiON, SiOCN, or SiBCN, over the entire surface. At this time, the insulating layer is also embedded in the recesses of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32. Then, anisotropic etching such as RIE is performed to remove the insulating layer outside the recesses. Through these steps, inner spacers 25 and 35 are formed in the recesses on the sides of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 using insulating layers. Note that SiN is an example of Si ３ N ４ SiO is SiO ２ This indicates.

[0055] Furthermore, source-drain regions 23 are formed on the side surfaces of the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22, and source-drain regions 33 are formed on the side surfaces of the laminate of the second channel semiconductor layer 31 and the third sacrificial semiconductor layer 32. The source-drain regions 23 and 33 are formed, for example, by epitaxial growth of Si from the side surface of the first channel semiconductor layer 21 or the side surface of the second channel semiconductor layer 31. If the lower transistor Tr20 is p-type, the source-drain regions 23 are formed by epitaxial growth of Si while supplying impurities such as B and semiconductor materials such as Ge. If the upper transistor Tr30 is n-type, the source-drain regions 33 are formed by epitaxial growth of Si while supplying impurities such as P, As, and Sb.

[0056] Subsequently, the dummy gate 18 and the sacrificial insulating layer 17 are removed using conventionally known methods, and the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 are removed to form the gate electrode 16. For the removal of the dummy gate 18, for example, wet etching using a chemical such as hydrogen fluoride that can selectively etch SiO and SiN, or plasma etching that can selectively etch polysilicon and a-Si is used. For the removal of the sacrificial insulating layer 17, for example, CDE or wet etching is used, which can selectively etch the SiO and other materials constituting the sacrificial insulating layer 17 from the Si constituting the first channel semiconductor layer 21 and the second channel semiconductor layer 31. For the removal of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32, for example, dry etching using a mixed gas containing hydrogen fluoride and oxygen, or wet etching using a mixed solution of hydrogen fluoride and hydrogen peroxide is used, which can selectively etch SiGe with a low Ge concentration from the Si constituting the first channel semiconductor layer 21 and the second channel semiconductor layer 31. The gate electrode 16 is formed by filling the space between the first channel semiconductor layer 21 and the second channel semiconductor layer 31, which are formed by removing the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32, with gate material. The gate electrode 16 is formed after forming a gate insulating film (not shown) and a high dielectric constant insulating layer (not shown) on the first channel semiconductor layer 21 and the second channel semiconductor layer 31. The gate insulating film is formed, for example, by thermal oxidation of the exposed surface of the first channel semiconductor layer 21 and the second channel semiconductor layer 31. The high dielectric constant insulating layer is formed, for example, by using ALD (Atomic Layer Deposition) to form hafnium dioxide (HfO) ２), hafnium oxynitride (HfON), etc. are formed. Then, gate materials such as work function metal and gate metal are filled onto the gate insulating film or high dielectric constant insulating layer, and the gate material above the gate spacer 109 is removed using CMP or RIE. This forms the gate electrode 16. The gate electrode 16 is formed by depositing a film of tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium (Nb), tungsten (W), etc., using CVD, etc. By the above steps, the semiconductor device of the first embodiment shown in Figures 2A and 2B can be manufactured.

[0057] In the above-described manufacturing method, in the step of removing the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44, the removal of the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 is mainly performed from the exposed surface in the gate width direction of the laminate shown in Figure 6A. In this manufacturing method, the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 are formed as single-layer semiconductor layers. Therefore, compared to the structure in which the sacrificial layer of the gate electrode and the sacrificial layer of the MDI are laminated in the conventional manufacturing method, the removal of the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44, which are the sacrificial layers of the MDI, is easy. Furthermore, since the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 can be removed from the exposed surface side in the gate width direction of the laminate shown in Figure 6A, the opening is large and removal is easy.

[0058] Furthermore, in the above-described manufacturing method, a liner layer 107 covering the laminate is formed before the step of removing the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44. The liner layer 107 covers the laminate of the fourth sacrificial semiconductor layer 42, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the second sacrificial semiconductor layer 44, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32, as well as the upper surface of the substrate 101. Therefore, as shown in Figures 6A and 6B, even after the fourth sacrificial semiconductor layer 42 and the second sacrificial semiconductor layer 44 are removed, the liner layer 107 holds the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22, and the laminate of the second channel semiconductor layer 31 and the third sacrificial semiconductor layer 32. As a result, even if the fourth sacrificial semiconductor layer 42 between the substrate 101 and the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22, and the second sacrificial semiconductor layer 44 between the laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22 and the second channel semiconductor layer 31 and the third sacrificial semiconductor layer 32 are all removed, the laminated structure can be maintained.

[0059] <3. Semiconductor device of the second embodiment and method for manufacturing a semiconductor device> Next, a semiconductor device of the second embodiment and a method for manufacturing a semiconductor device will be described. In the description of the method for manufacturing a semiconductor device of the second embodiment, components similar to those described in the method for manufacturing a semiconductor device of the first embodiment described above will be denoted by the same reference numerals and detailed descriptions will be omitted. Furthermore, the semiconductor device manufactured by the method for manufacturing a semiconductor device of the second embodiment has the same configuration as that of the first embodiment described above. For this reason, the description of the configuration of the semiconductor device will be omitted.

[0060] [Method for Manufacturing a Semiconductor Device] The method for manufacturing a semiconductor device according to the second embodiment will now be described. An example of the method for manufacturing a semiconductor device according to the second embodiment is shown in Figures 11 to 15. First, as shown in Figures 11A and 11B, a laminate of a fourth sacrificial semiconductor layer 42, a first channel semiconductor layer 21, a first sacrificial semiconductor layer 22, a second sacrificial semiconductor layer 44, a second channel semiconductor layer 31, and a third sacrificial semiconductor layer 32 is formed. Figure 11A is a cross-sectional view of the semiconductor device 100 in the gate length direction, and corresponds to the cross-sectional view along line A-A shown in Figure 11B. Figure 11B is a cross-sectional view of the semiconductor device 100 in the gate width direction, and corresponds to the cross-sectional view along line B-B shown in Figure 11A.

[0061] In this process, first, a seventh sacrificial semiconductor layer 46 and an eighth sacrificial semiconductor layer 47 are formed as the fourth sacrificial semiconductor layer 42, which will serve as a sacrificial layer for BDI 103. The seventh sacrificial semiconductor layer 46 is formed from SiGe containing a high concentration of Ge by epitaxial growth. The high Ge concentration SiGe preferably has a Ge content of 40% to 75%, and more preferably 50% to 55%. The eighth sacrificial semiconductor layer 47 is formed from Si by epitaxial growth. If a single layer of SiGe is formed as a thick film as the fourth sacrificial semiconductor layer 42, lattice mismatch is likely to occur. For this reason, a laminated structure of a seventh sacrificial semiconductor layer 46 made of SiGe and an eighth sacrificial semiconductor layer 47 made of Si is formed as the fourth sacrificial semiconductor layer 42. In order to suppress lattice mismatch of SiGe and ensure productivity, the seventh sacrificial semiconductor layer 46 made of SiGe is formed to a thickness of 3 nm to 7 nm. Furthermore, to ensure ease of removal in subsequent processes and productivity, an eighth sacrificial semiconductor layer 47 made of Si is formed with a thickness of 3 nm to 7 nm. In addition, a fourth sacrificial semiconductor layer 42 is formed to a predetermined thickness by stacking the seventh sacrificial semiconductor layer 46 and the eighth sacrificial semiconductor layer 47. The number of stacks of the seventh sacrificial semiconductor layer 46 and the eighth sacrificial semiconductor layer 47 is not particularly limited.

[0062] Next, a laminate of the first channel semiconductor layer 21 and the first sacrificial semiconductor layer 22 is formed using the same method as described above with reference to Figure 3. The first channel semiconductor layer 21 is formed of Si without Ge. The first sacrificial semiconductor layer 22 is formed of SiGe with a lower Ge concentration than the fourth sacrificial semiconductor layer 42. For example, the low Ge concentration SiGe has a Ge content of 15% to 35%, and more preferably 20% to 25%. In Figures 11A and 11B, the first sacrificial semiconductor layer 22 is formed on the fourth sacrificial semiconductor layer 42 side (substrate 101 side), and four layers of the first sacrificial semiconductor layer 22 and three layers of the first channel semiconductor layer 21 are formed.

[0063] Next, the MDI 45 has a second sacrificial semiconductor layer 44, which serves as a sacrificial layer, and a fifth sacrificial semiconductor layer 48 and a sixth sacrificial semiconductor layer 49. The fifth sacrificial semiconductor layer 48 is formed by epitaxial growth of SiGe containing a high concentration of Ge. The high Ge concentration of SiGe is preferably 40% to 75%, and more preferably 50% to 55%. The sixth sacrificial semiconductor layer 49 is formed by epitaxial growth of Si. If a single layer of SiGe is formed as a thick film as the second sacrificial semiconductor layer 44, lattice mismatch is likely to occur. For this reason, the second sacrificial semiconductor layer 44 is formed as a stacked structure of a fifth sacrificial semiconductor layer 48 made of SiGe and a sixth sacrificial semiconductor layer 49 made of Si. In order to suppress lattice mismatch of SiGe and to ensure productivity, the fifth sacrificial semiconductor layer 48 made of SiGe is formed to a thickness of 3 nm to 7 nm. Furthermore, to ensure removeability in subsequent processes and productivity, a sixth sacrificial semiconductor layer 49 made of Si is formed with a thickness of 3 nm to 7 nm. In addition, a fourth sacrificial semiconductor layer 42 is formed to a predetermined thickness by stacking the fifth sacrificial semiconductor layer 48 and the sixth sacrificial semiconductor layer 49. The number of stacks of the fifth sacrificial semiconductor layer 48 and the sixth sacrificial semiconductor layer 49 is not particularly limited.

[0064] Next, a laminate of the second channel semiconductor layer 31 and the third sacrificial semiconductor layer 32 is formed using the same method as described above with reference to Figure 3. The second channel semiconductor layer 31 is formed of Si without Ge. The third sacrificial semiconductor layer 32 is formed of SiGe with a lower Ge concentration than the second channel semiconductor layer 31. For example, the low Ge concentration SiGe has a Ge content of 15% to 35%, and more preferably 20% to 25%. In Figures 11A and 11B, the first sacrificial semiconductor layer 22 is formed on the fourth sacrificial semiconductor layer 42 side (substrate 101 side), and four third sacrificial semiconductor layers 32 and three second channel semiconductor layers 31 are formed. Also in Figures 11A and 11B, the third sacrificial semiconductor layer 32 is formed as the uppermost layer.

[0065] Next, using the same method as described above with reference to Figures 4 and 5, the fin-shaped laminate is formed by separating the laminate and the liner layer 107 covering the laminate is formed, as shown in Figures 12A and 12B. Figure 12A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 12B. Figure 12B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 12A. Note that Figure 12A shows not only a cross-sectional view of the semiconductor device 100 in the gate length direction but also a view of the configuration from the side for explanation purposes. In Figure 12A, each layer of the laminate located below the liner layer 107 is shown by a dashed line.

[0066] Next, using the same method as described above with reference to Figure 6, the seventh sacrificial semiconductor layer 46 and the fifth sacrificial semiconductor layer 48, made of high Ge concentration SiGe, are removed as shown in Figures 13A and 13B. Figure 13A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 13B. Figure 13B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 13A. Note that Figure 13A shows not only a cross-sectional view of the semiconductor device 100 in the gate length direction, but also a view of the configuration from the side for explanation of the configuration. Also, in Figure 13A, each layer of the laminate located below the liner layer 107 is shown with dashed lines. In this step, the seventh sacrificial semiconductor layer 46 and the fifth sacrificial semiconductor layer 48 are removed using chemical dry etching or wet etching. Furthermore, this process employs an etching selectivity method for the seventh sacrificial semiconductor layer 46 and the fifth sacrificial semiconductor layer 48, which are made of high-Ge concentration SiGe, and the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32, which are made of low-Ge concentration SiGe.

[0067] Next, as shown in Figures 14A and 14B, the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49, both made of Si, are removed. Figure 14A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 14B. Figure 14B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 14A. In Figure 14A, not only is the cross-sectional view of the semiconductor device 100 in the gate length direction shown, but the configuration viewed from the side is also shown for explanation purposes. In Figure 14A, each layer of the laminate located below the liner layer 107 is shown with dashed lines. In this step, a method such as wet etching is used that can remove the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49, both made of Si. By removing the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49, a space for forming the BDI 103 and a space for forming the MDI 45 are opened. Furthermore, in this process, similar to the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49, a portion of the exposed surfaces of the first channel semiconductor layer 21 and the second channel semiconductor layer 31, which are formed of Si, are removed. For example, the first channel semiconductor layer 21 and the second channel semiconductor layer 31 are removed from the exposed surface side in the gate width direction of the laminate shown in Figure 14A. As a result, the removal process of the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49 reduces the length of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 in the gate width direction. However, while the removal of the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49 is performed from multiple directions (sideways and vertically), the removal of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 is performed from only one direction in the gate width direction. As a result, the first channel semiconductor layer 21 and the second channel semiconductor layer 31 remain with a sufficient length in the gate width direction. Furthermore, a third sacrificial semiconductor layer 32 is formed on the uppermost layer of the laminate. Therefore, when the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49 are removed, the surface of the uppermost second channel semiconductor layer 31 is protected by the third sacrificial semiconductor layer 32. As a result, when the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49 are removed, the removal of the second channel semiconductor layer 31 can be suppressed.

[0068] Next, using the same method as described above with reference to Figures 7 and 8, the insulating layer 105 is formed and the BDI 103 and MDI 45 are formed by anisotropic etching of the insulating layer 105, as shown in Figures 15A and 15B. Figure 15A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 15B. Figure 15B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 15A. Note that Figure 15A shows not only a cross-sectional view of the semiconductor device 100 in the gate length direction but also a view of the configuration from the side for explanation purposes.

[0069] Next, using the same method as described above with reference to Figures 9 and 10, the sacrificial insulating layer 17 and the dummy gate 18 are formed, the laminate is separated in the gate length direction, the inner spacers 25 and 35 are formed, and the source and drain regions 23 and 33 are formed. Furthermore, using a conventionally known method, the dummy gate 18 and the sacrificial insulating layer 17 are removed, the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 are removed, and the gate electrode 16 is formed. By following these steps, the semiconductor device of the second embodiment can be manufactured.

[0070] In the second embodiment, a stacked structure of a thin film seventh sacrificial semiconductor layer 46 and an eighth sacrificial semiconductor layer 47 is formed as the fourth sacrificial semiconductor layer 42. Then, a thin film fifth sacrificial semiconductor layer 48 and a sixth sacrificial semiconductor layer 49 are formed as the second sacrificial semiconductor layer 44. This suppresses lattice mismatch between the fifth sacrificial semiconductor layer 48 and the seventh sacrificial semiconductor layer 46, which are made of SiGe. This suppresses the generation of crystal defects in each semiconductor layer formed by epitaxial growth.

[0071] <4. Semiconductor device of the third embodiment and method for manufacturing a semiconductor device> Next, a semiconductor device of the third embodiment and a method for manufacturing a semiconductor device will be described. In the description of the method for manufacturing a semiconductor device of the third embodiment, components similar to those described in the method for manufacturing a semiconductor device of the first embodiment described above will be denoted by the same reference numerals and detailed descriptions will be omitted. Furthermore, the semiconductor device manufactured by the method for manufacturing a semiconductor device of the third embodiment has the same configuration as that of the first embodiment described above. For this reason, the description of the configuration of the semiconductor device will be omitted.

[0072] [Method for Manufacturing a Semiconductor Device] The method for manufacturing a semiconductor device according to the third embodiment will now be described. Figures 16 to 20 show an example of the method for manufacturing a semiconductor device according to the second embodiment.

[0073] First, using the same method as described with Figures 11A and 11B, a laminate of the fourth sacrificial semiconductor layer 42, the first channel semiconductor layer 21, the first sacrificial semiconductor layer 22, the second sacrificial semiconductor layer 44, the second channel semiconductor layer 31, and the third sacrificial semiconductor layer 32 is formed, as shown in Figures 16A and 16B. Figure 16A is a cross-sectional view of the semiconductor device 100 in the gate length direction, and corresponds to the cross-sectional view along line A-A shown in Figure 16B. Figure 16B is a cross-sectional view of the semiconductor device 100 in the gate width direction, and corresponds to the cross-sectional view along line B-B shown in Figure 16A.

[0074] Next, using the same method as described above with reference to Figure 4, a fin-shaped laminate is formed by separating the laminate, as shown in Figures 17A and 17B. Figure 17A is a cross-sectional view of the semiconductor device 100 in the gate length direction, corresponding to the cross-sectional view along line A-A shown in Figure 17B. Figure 17B is a cross-sectional view of the semiconductor device 100 in the gate width direction, corresponding to the cross-sectional view along line B-B shown in Figure 17A. In this step, unlike the semiconductor device manufacturing method of the second embodiment described above, the liner layer 107 is not formed.

[0075] Next, using the same method as described above with reference to Figures 13A and 13B, the seventh sacrificial semiconductor layer 46 and the fifth sacrificial semiconductor layer 48, which are made of high-Ge-concentration SiGe, are removed as shown in Figures 18A and 18B. Figure 18A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 18B. Figure 18B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 18A.

[0076] Next, using the same method as described above with reference to Figures 14A and 14B, the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49, made of Si, are removed as shown in Figures 19A and 19B. Figure 19A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 19B. Figure 19B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 19A.

[0077] In this process, since there is no liner layer 107, the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49 are removed with the gate length direction and gate width direction side surfaces of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 exposed. As a result, the exposed surfaces of the first channel semiconductor layer 21 and the second channel semiconductor layer 31, which are made of Si, are removed, similar to the eighth sacrificial semiconductor layer 47 and the sixth sacrificial semiconductor layer 49. As a result, as shown in Figures 19A and 19B, a portion of the surface of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 that is exposed on the gate length direction and gate width direction, for example, the side surface, is removed by about 3 nm. This creates recesses 21a and 31a on the side surfaces of the first channel semiconductor layer 21 and the second channel semiconductor layer 31, relative to the side surfaces of the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32.

[0078] Therefore, the first channel semiconductor layer 21 and the second channel semiconductor layer 31 are designed with a larger pattern in the process of forming a fin-shaped laminate by separating the laminate, taking into consideration the amount of material to be removed from the sides. For example, the lengths of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 in the gate length direction and the gate width direction when forming the pattern are designed to be about 6 nm larger than the actual lengths of the semiconductor device in the gate length direction and the gate width direction. In addition, the laminate is separated in the gate length direction of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 in a later process. For this reason, the recesses 21a and 31a formed on the sides of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 are designed to become areas to be removed for separation in the gate length direction. In this case, the recesses 21a and 31a of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 are removed in the laminate separation process in the gate length direction. With this design, the recesses 21a, 31a formed on the sides of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 do not affect the shape of the semiconductor device. Furthermore, it is not necessary to design the gate length of the first channel semiconductor layer 21 and the second channel semiconductor layer 31 to be large when forming the pattern.

[0079] Next, using the same method as described above with Figures 15A and 15B, the insulating layer 105 is formed and the BDI 103 and MDI 45 are formed by anisotropic etching of the insulating layer 105, as shown in Figures 20A and 20B. Figure 20A is a cross-sectional view of the semiconductor device 100 in the gate length direction and corresponds to the cross-sectional view along line A-A shown in Figure 20B. Figure 20B is a cross-sectional view of the semiconductor device 100 in the gate width direction and corresponds to the cross-sectional view along line B-B shown in Figure 20A. Furthermore, using the same method as described above with Figures 9 and 10, the sacrificial insulating layer 17 and dummy gate 18 are formed, the laminate is separated in the gate length direction, inner spacers 25 and 35 are formed, and source and drain regions 23 and 33 are formed. Furthermore, the dummy gate 18 and the sacrificial insulating layer 17 are removed using conventionally known methods, and the first sacrificial semiconductor layer 22 and the third sacrificial semiconductor layer 32 are removed to form the gate electrode 16. By these steps, the semiconductor device of the third embodiment can be manufactured.

[0080] In the semiconductor device manufacturing method of the third embodiment, the liner layer 107 of the semiconductor device manufacturing method of the second embodiment described above is not formed. Therefore, the semiconductor device manufacturing method of the third embodiment allows for simplification of the process.

[0081] It should be noted that the present invention is not limited to the configuration described in the above-described embodiments, and various modifications and changes are possible without departing from the configuration of the present invention.

[0082] 10, 100... Semiconductor device, 11, 101... Substrate, 16... Gate electrode, 17... Sacrificial insulating layer, 18... Dummy gate, 21... First channel semiconductor layer, 21a, 31a... Recess, 22... First sacrificial semiconductor layer, 23, 33... Source / drain region, 25, 35, 115... Inner spacer, 31... Second channel semiconductor layer, 32... Third sacrificial semiconductor layer, 40... Intermediate element isolation region, 41, 45... MDI, 42... Fourth sacrificial semiconductor layer, 43, 105... Insulating layer, 44... Second sacrificial semiconductor layer, 46... Seventh sacrificial semiconductor layer, 47... Eighth sacrificial semiconductor layer, 48... Fifth sacrificial semiconductor layer, 49... Sixth sacrificial semiconductor layer, 50... Bottom element isolation region, 103... BDI, 107... Liner layer, 109... Gate spacer, 111... Channel semiconductor layer

Claims

1. A semiconductor device comprising a nanosheet transistor having a semiconductor layer formed by nanosheets and a gate electrode stacked on the semiconductor layer, the semiconductor device comprising: a first nanosheet transistor; a second nanosheet transistor stacked on the first nanosheet transistor; and an intermediate element isolation region disposed between the first nanosheet transistor and the second nanosheet transistor, wherein the intermediate element isolation region has an insulating layer embedded between the gate electrode or the semiconductor layer constituting the first nanosheet transistor and the gate electrode or the semiconductor layer constituting the second nanosheet transistor.

2. The semiconductor device according to claim 1, wherein the thickness of the intermediate element isolation region is 10 nm or more and 100 nm or less.

3. The semiconductor device according to claim 1, having a bottom element isolation region formed between the substrate, the first nanosheet transistor, and the second nanosheet transistor.

4. The semiconductor device according to claim 3, wherein the intermediate element isolation region and the bottom element isolation region are made of the same insulating material.

5. The semiconductor device according to claim 3, wherein the bottom element isolation region has a liner layer that separates the region directly beneath the first nanosheet transistor and the second nanosheet transistor from the region excluding the region directly beneath the first nanosheet transistor and the second nanosheet transistor.

6. The semiconductor device according to claim 5, wherein the bottom element isolation region has the liner layer between the insulating layer formed in the region excluding the area directly beneath the first nanosheet transistor and the second nanosheet transistor and the substrate.

7. A method for manufacturing a semiconductor device comprising a nanosheet transistor having a semiconductor layer formed by nanosheets and a gate electrode laminated on the semiconductor layer, comprising the steps of: forming a first laminate on a substrate consisting of a first channel semiconductor layer, a first sacrificial semiconductor layer, a second sacrificial semiconductor layer, a second channel semiconductor layer, and a third sacrificial semiconductor layer; replacing the second sacrificial semiconductor layer with a single insulating layer; forming a dummy gate on the first laminate; transferring the pattern of the dummy gate to the first laminate; forming gate spacers on the sacrificial insulating layer and the side surface of the dummy gate; replacing a part of the side surface of the first sacrificial semiconductor layer and the third sacrificial semiconductor layer with an inner spacer; forming source and drain regions on the side surface of the first channel semiconductor layer and the second channel semiconductor layer; and replacing the dummy gate, the first sacrificial semiconductor layer, and the third sacrificial semiconductor layer with a gate electrode. A method for manufacturing a semiconductor device, comprising the steps of forming the first laminate, forming a second laminate consisting of the first channel semiconductor layer and the first sacrificial semiconductor layer on the substrate, forming the second sacrificial semiconductor layer on the second laminate, and forming a third laminate consisting of the second channel semiconductor layer and the third sacrificial semiconductor layer on the second sacrificial semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the second sacrificial semiconductor layer is formed with a thickness of 10 nm or more and 100 nm or less.

9. The method for manufacturing a semiconductor device according to claim 7, wherein in the step of forming the first laminate, a fourth sacrificial semiconductor layer is formed on the substrate, the second laminate consisting of the first channel semiconductor layer and the first sacrificial semiconductor layer is formed on the fourth sacrificial semiconductor layer, and in the step of replacing the second sacrificial semiconductor layer with an insulating layer, the fourth sacrificial semiconductor layer is also replaced with a single-layer insulating layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein, in the step of replacing the second sacrificial semiconductor layer and the fourth sacrificial semiconductor layer with an insulating layer, the second sacrificial semiconductor layer and the fourth sacrificial semiconductor layer are removed, and the void left by the removal of the second sacrificial semiconductor layer and the fourth sacrificial semiconductor layer is filled with a material of the same insulating properties.

11. A method for manufacturing a semiconductor device according to claim 10, wherein a liner layer is formed to cover the top and side surfaces of the first laminate at predetermined intervals in the gate length direction, and after the liner layer is formed, the second sacrificial semiconductor layer and the fourth sacrificial semiconductor layer are replaced with the same insulating material.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the second sacrificial semiconductor layer and the fourth sacrificial semiconductor layer are replaced with the same insulating material, and then the liner layer is removed to a position lower than the second laminate.

13. The method for manufacturing a semiconductor device according to claim 7, wherein the second sacrificial semiconductor layer is formed of a single semiconductor layer.

14. The method for manufacturing a semiconductor device according to claim 7, wherein a laminate of a fifth sacrificial semiconductor layer and a sixth sacrificial semiconductor layer is formed as the second sacrificial semiconductor layer.

15. The method for manufacturing a semiconductor device according to claim 9, wherein a laminate of a fifth sacrificial semiconductor layer and a sixth sacrificial semiconductor layer is formed as the fourth sacrificial semiconductor layer.

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