Semiconductor device

Abstract

This semiconductor device is provided with a first circuit, a second circuit, a first mount substrate, and a second mount substrate. The first circuit includes a first semiconductor element and a second semiconductor element connected in series to each other. The second circuit includes a passive element. The first semiconductor element is mounted on the first mount substrate, and the second semiconductor element is mounted on the second mount substrate. The first mount substrate includes a substrate body having a wiring part and a hollow part surrounded by the substrate body when viewed in the thickness direction. The hollow part includes a first accommodation part accommodating the passive element. The second circuit is electrically connected in parallel with the first circuit by the wiring part.

Description

Semiconductor Device

[0001] The present disclosure relates to a semiconductor device.

[0002] Conventionally, semiconductor devices including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. For example, Patent Document 1 discloses a semiconductor device including two switching elements connected in series. Such a semiconductor device is mounted on a circuit board of, for example, an electronic device, and is used in power supply circuits (such as DC / DC converters and inverters), motor drive circuits, and the like.

[0003] Japanese Unexamined Patent Publication No. 2009-158787

[0004] [Abstract] One object of the present disclosure is to provide an improved semiconductor device compared to conventional ones. In particular, one object of the present disclosure is to provide a semiconductor device with enhanced functionality.

[0005] The semiconductor device provided by the present disclosure includes: a first circuit that includes a first semiconductor element and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are electrically connected in series; a first mounting substrate having a first mounting surface on which the first semiconductor element is mounted; a second mounting substrate having a second mounting surface on which the second semiconductor element is mounted; and a second circuit including a passive element, wherein the first mounting substrate includes a substrate body having a wiring portion and a hollow portion surrounded by the substrate body as viewed in the thickness direction of the first mounting substrate, the hollow portion includes a first accommodating portion that accommodates the passive element, and the second circuit is electrically connected in parallel to the first circuit via the wiring portion.

[0006] Other features and advantages of the present disclosure will become more apparent from the detailed description given below based on the accompanying drawings.

[0007] Figure 1 is a perspective view showing a semiconductor device according to the first embodiment. Figure 2 is a perspective view of Figure 1 with the sealing member omitted. Figure 3 is a plan view showing a semiconductor device according to the first embodiment. Figure 4 is a plan view of Figure 1 with the sealing member indicated by dashed lines. Figure 5 is a plan view of Figure 4 with a plurality of power terminals indicated by dashed lines. Figure 6 is a partially enlarged view of Figure 5. Figure 7 is a plan view of Figure 5 with the sealing member, plurality of power terminals, and plurality of conductive members omitted. Figure 8 is a plan view of Figure 7 with one of the upper substrates of the two mounting substrates omitted. Figure 9 is a plan view of Figure 7 with one of the lower substrates (excluding the base layer) of the two mounting substrates omitted, and the conductive substrate of the other of the two mounting substrates omitted. Figure 10 is a front view showing a semiconductor device according to the first embodiment. Figure 11 is a bottom view showing a semiconductor device according to the first embodiment. Figure 12 is a side view (left side view) showing a semiconductor device according to the first embodiment. Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 4. Figure 14 is a partially enlarged view of Figure 13. Figure 15 is a partially enlarged view of Figure 13. Figure 16 is a cross-sectional view along the line XVI-XVI in Figures 5 and 8. Figure 17 is a partially enlarged view of Figure 16. Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figures 5 and 8. Figure 19 is a partially enlarged view of Figure 18. Figure 20 is a diagram showing an example of the circuit configuration of a semiconductor device according to the first embodiment. Figure 21 is a schematic diagram of a vehicle equipped with the semiconductor device according to the first embodiment. Figure 22 is a plan view of the main part showing a semiconductor device according to a first modification of the first embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 23 is a plan view of the main part showing a semiconductor device according to a second modification of the first embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 24 is a plan view of the main parts of a semiconductor device according to a third modification of the first embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 25 is a plan view of the main parts of a semiconductor device according to a fourth modification of the first embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 26 is a plan view of the main parts of a semiconductor device according to a fifth modification of the first embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted.Figure 27 is a plan view of the main part of a semiconductor device according to the second embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 28 is a cross-sectional view of the main part of the semiconductor device shown in Figure 27, corresponding to the cross-section in Figure 17. Figure 29 is a plan view of the main part of a semiconductor device according to a modified example of the second embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 30 is a plan view of the main part of a semiconductor device according to the third embodiment, corresponding to a diagram in which one of the two mounting substrates in Figure 8 is omitted. Figure 31 is a cross-sectional view of a semiconductor device according to the fourth embodiment, corresponding to the cross-section in Figure 13. Figure 32 is a cross-sectional view of a semiconductor device according to a first modified example of the fourth embodiment, corresponding to the cross-section in Figure 13. Figure 33 is a cross-sectional view of a semiconductor device according to a second modified example of the fourth embodiment, corresponding to the cross-section in Figure 13. Figure 34 is a cross-sectional view of a semiconductor device according to a third modified example of the fourth embodiment, corresponding to the cross-section in Figure 13. Figure 35 is a cross-sectional view of the main part of a semiconductor device according to a fourth modified example of the fourth embodiment, corresponding to the cross-section in Figure 17. Figure 36 is a perspective view showing a semiconductor device according to the fifth embodiment. Figure 37 is a plan view showing a semiconductor device according to the fifth embodiment, in which the sealing member is shown by dashed lines. Figure 38 is a plan view of Figure 37 in which one of the two conductive members and the sealing member are omitted. Figure 39 is a cross-sectional view along the line XXXIX-XXXIX in Figure 37. Figure 40 is a plan view of the main part showing a semiconductor device according to another configuration example, corresponding to a view in Figure 8 in which one of the two mounting substrates is omitted. Figure 41 is a cross-sectional view of the main part showing a semiconductor device according to another configuration example, corresponding to the cross-section in Figure 17.

[0008] [Detailed Description] Preferred embodiments of the semiconductor devices of the present disclosure are described below with reference to the drawings. Hereafter, identical or similar components are denoted by the same reference numerals, and redundant descriptions are omitted. The terms "first," "second," "third," etc., in this disclosure are used merely as labels and are not necessarily intended to assign a sequence to the objects.

[0009] In this disclosure, "object A is formed on object B" and "object A is formed on object B" include, unless otherwise specified, "object A is directly formed on object B" and "object A is formed on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" and "object A is located on object B" include, unless otherwise specified, "object A is directly located on object B" and "object A is located on object B with another object interposed between object A and object B." Similarly, "object A is located on object B" includes, unless otherwise specified, "object A is in contact with object B and located on object B" and "object A is located on object B with another object interposed between object A and object B." Furthermore, "object A overlaps with object B when viewed in a certain direction" includes, unless otherwise specified, "object A overlaps with all of object B" and "object A overlaps with a part of object B." Also, "object A (or its material) contains material C" includes "object A (or its material) consists of material C" and "the main component of object A (or its material) is material C." Furthermore, "a surface A faces a certain direction B (one side or the other side)" is not limited to cases where the angle of surface A with respect to direction B is 90°, but also includes cases where surface A is inclined with respect to direction B. Furthermore, "a surface A is perpendicular to surface B" is not limited to cases where the angle of surface A with respect to surface B is 90°, but also includes cases where surface A is inclined with respect to surface B.

[0010] First Embodiment: Figures 1 to 20 show a semiconductor device A10 according to the first embodiment. The semiconductor device A10 includes a first circuit 1, a second circuit 2, two signal boards 3A and 3B, a plurality of power terminals 41, 42, and 43, a plurality of signal terminals 44A to 47A and 44B to 47B, a plurality of connecting members 51A to 54A and 51B to 54B, a plurality of conductive members 55, a plurality of conductive members 561 to 564, a sealing member 6, and two mounting boards 7 and 8.

[0011] For the sake of explanation, we will refer to the mutually orthogonal thickness direction z, the first direction x, and the second direction y. The thickness direction z corresponds to the thickness direction of the semiconductor device A10. "Plane view" means when viewed in the thickness direction z. The first direction x is orthogonal to the thickness direction z. The second direction y is orthogonal to both the thickness direction z and the first direction x. One direction in the thickness direction z is sometimes called "up," and the other direction in the thickness direction z is sometimes called "down." Note that terms such as "up," "down," "upper," "downward," "upper surface," and "lower surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define a relationship with the direction of gravity.

[0012] The first circuit 1 is an element that performs the electrical function of the semiconductor device A10. The first circuit 1 includes a plurality of semiconductor elements 1A and a plurality of semiconductor elements 1B. In the illustrated example, the first circuit 1 includes four semiconductor elements 1A and four semiconductor elements 1B. The number of semiconductor elements 1A and semiconductor elements 1B is not limited to this and can be changed according to the performance required of the semiconductor device A10. For example, the semiconductor device A10 may be configured to include one semiconductor element 1A and one semiconductor element 1B. As shown in Figure 20, the first circuit 1 is, for example, a half-bridge type switching circuit. In the first circuit 1, the plurality of semiconductor elements 1A constitute the upper arm circuit of the semiconductor device A10, and the plurality of semiconductor elements 1B constitute the lower arm circuit of the semiconductor device A10. Each semiconductor element 1A and each semiconductor element 1B are electrically connected in series.

[0013] Each of the multiple semiconductor elements 1A and each of the multiple semiconductor elements 1B are, for example, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In addition, each of the multiple semiconductor elements 1A and each of the multiple semiconductor elements 1B may be field-effect transistors including MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) or bipolar transistors such as IGBTs (Insulated Gate Bipolar Transistors). Furthermore, each of the multiple semiconductor elements 1A or each of the multiple semiconductor elements 1B may be a diode. In the description of the semiconductor device A10, each of the multiple semiconductor elements 1A and each of the multiple semiconductor elements 1B are n-channel type and vertical structure MOSFETs. Each of the multiple semiconductor elements 1A and each of the multiple semiconductor elements 1B include a compound semiconductor substrate. The constituent material of the compound semiconductor substrate includes silicon (Si), a wide-bandgap semiconductor with a bandgap wider than Si, or an ultra-wide-bandgap semiconductor with an even wider bandgap than a wide-bandgap semiconductor. Wide bandgap semiconductors include, but are not limited to, silicon carbide (SiC) and gallium nitride (GaN). Ultra-wide bandgap semiconductors include, but are not limited to, gallium oxide (Ga2O3), diamond, and aluminum nitride (AlN). In this embodiment, the constituent material of the compound semiconductor substrate of each of the plurality of semiconductor elements 1A and each of the plurality of semiconductor elements 1B includes SiC.

[0014] Each of the multiple semiconductor elements 1A and 1B has a main element surface 101 and a back element surface 102, as shown in Figures 14 and 15. In each of the multiple semiconductor elements 1A and each of the multiple semiconductor elements 1B, the main element surface 101 and the back element surface 102 are separated in the thickness direction z and face opposite each other in the thickness direction z. The main element surface 101 faces upward in the thickness direction z, and the back element surface 102 faces downward in the thickness direction z.

[0015] As shown in Figures 6, 7, 14, 15, and 17, each of the multiple semiconductor elements 1A and 1B has a back electrode 11, a main electrode 12, a main electrode 13, and an insulating film 14. Each of the multiple semiconductor elements 1A and 1B switches between an ON state (conductive state) and an OFF state (blocked state) between the back electrode 11 and the main electrode 12 by a drive signal input to the main electrode 13. Hereinafter, the drive signal input to the main electrode 13 of each semiconductor element 1A may be referred to as the first drive signal, and the drive signal input to the main electrode 13 of each semiconductor element 1B may be referred to as the second drive signal. In each of the semiconductor elements 1A and 1B, the operation of switching between the ON state and the OFF state alternately is called switching operation. In the ON state, current flows from the back electrode 11 to the main electrode 12, and in the OFF state, this current does not flow. In this embodiment, each of the multiple semiconductor elements 1A and 1B is a switching element. The frequencies of the first drive signal and the second drive signal are, for example, 10 kHz or higher. In other words, the switching frequencies of the multiple semiconductor elements 1A and the multiple semiconductor elements 1B are, for example, 10 kHz or higher. However, the frequencies of the first drive signal and the second drive signal (the switching frequencies of the multiple semiconductor elements 1A and 1B) are not limited to these values.

[0016] As shown in Figures 14, 15, and 17, the back electrode 11 is positioned on the back surface 102 of the element and is exposed on the back surface 102. Each back electrode 11 of the multiple semiconductor elements 1A faces the mounting substrate 7, and each back electrode 11 of the multiple semiconductor elements 1B faces the mounting substrate 8. In each semiconductor element 1A, 1B, current can flow from the back electrode 11 towards the inside of the element. In the example where each semiconductor element 1A, 1B is a MOSFET, the back electrode 11 corresponds to the drain electrode of each semiconductor element 1A, 1B.

[0017] As shown in Figures 6, 7, 14, 15, and 17, the main surface electrode 12 is positioned on the main surface 101 of the element and is exposed on the main surface 101. In each semiconductor element 1A, 1B, current can flow from inside the element toward the main surface electrode 12. In the example where each semiconductor element 1A, 1B is a MOSFET, the main surface electrode 12 corresponds to the source electrode of each semiconductor element 1A, 1B.

[0018] As shown in Figures 6 and 7, the main surface electrode 12 includes a power pad 121 and two signal pads 122. Each of the two signal pads 122 is located in one of the first directions x relative to the power pad 121. The two signal pads 122 are separated in the second direction y. The planar area of ​​the power pad 121 is larger than the planar area of ​​each of the two signal pads 122. The planar area of ​​the main surface electrode 13 is smaller than the planar area of ​​the power pad 121 of the main surface electrode 12. The main surface electrode 13 is located between the two signal pads 122 in the second direction y. Unlike the illustrated example, the power pad 121 of the main surface electrode 12 may be divided into two or more regions. The main surface electrode 12 may include only one of the two signal pads 122, or it may not include either of the two signal pads 122. As shown in Figure 7, in each semiconductor element 1A, the main surface electrode 13 and the two signal pads 122 are located on the same side as the signal substrate 3A with respect to the power pad 121 in the first direction x. As shown in Figure 7, in each semiconductor element 1B, the main surface electrode 13 and the two signal pads 122 are located on the same side as the signal substrate 3B with respect to the power pad 121 in the first direction x.

[0019] As shown in Figures 6, 7, 14, 15, and 17, the main surface electrode 13 is positioned on the main surface 101 of the element and is exposed on the main surface 101. A drive signal (first drive signal or second drive signal) for driving each semiconductor element 1A, 1B is input to the main surface electrode 13. In the example where each semiconductor element 1A, 1B is a MOSFET, the main surface electrode 13 corresponds to the gate electrode of each semiconductor element 1A, 1B. A gate voltage as a drive signal (first drive signal or second drive signal) is applied to the main surface electrode 13. In a plan view, the area of ​​the main surface electrode 13 is smaller than the area of ​​the main surface electrode 12.

[0020] The insulating film 14 is provided on the main surface 101 of the element, as shown in Figure 7. The insulating film 14 has electrical insulating properties. In a plan view, the insulating film 14 surrounds the main surface electrodes 12 and 13. On the main surface 101 of the element, the insulating film 14 insulates the main surface electrodes 12 (power pad 121 and two signal pads 122) from the main surface electrodes 13. The insulating film 14 is made of, for example, SiO ２ (Silicon dioxide) layer, SiN ４ The silicon nitride layer and the polybenzoxazole layer are stacked in this order from the main surface 101 of the device. The structure of the insulating film 14 is not limited to the above; for example, a polyimide layer may be stacked instead of the polybenzoxazole layer.

[0021] Multiple semiconductor elements 1A are mounted on a mounting substrate 7, as shown in Figures 4 to 7, 13, 14, 16, and 17. In the example shown in Figure 7, the multiple semiconductor elements 1A are arranged in the second direction y and spaced apart from each other. As shown in Figure 14, each of the multiple semiconductor elements 1A is electrically bonded to the mounting substrate 7 via a conductive bonding layer 19. This bonding layer 19 is not limited in any way as long as it is conductive, but for example it may be solder or a sintered body of metal particles containing silver or the like. When each semiconductor element 1A is bonded to the mounting substrate 7, the back surface 102 of each semiconductor element 1A faces the mounting substrate 7.

[0022] Multiple semiconductor elements 1B are mounted on a mounting substrate 8, as shown in Figures 4 to 7, 13, and 15. In the example shown in Figure 7, the multiple semiconductor elements 1B are arranged in the second direction y and spaced apart from each other. As shown in Figure 15, each of the multiple semiconductor elements 1B is electrically bonded to the mounting substrate 8 via a conductive bonding layer 19. This bonding layer 19 is not limited in any way as long as it is conductive, but for example it may be solder or a sintered body of metal particles containing silver or the like. When each semiconductor element 1B is bonded to the mounting substrate 8, the back surface 102 of each semiconductor element 1B faces the mounting substrate 8. In the illustrated example, as can be understood from Figure 5 and the like, when viewed in the first direction x, the multiple semiconductor elements 1A and the multiple semiconductor elements 1B overlap each other, but unlike this example, they do not have to overlap each other.

[0023] The second circuit 2 is electrically connected to the first circuit 1 by a mounting board 7 (wiring section 74 described later). As shown in Figures 8, 9, and 16 to 20, the second circuit 2 includes a plurality of passive elements 21 and a plurality of fuse sections 22. In the illustrated example, the second circuit 2 includes three passive elements 21 and three fuse sections 22, but the number of passive elements 21 and fuse sections 22 is not limited to this.

[0024] As shown in Figure 20, each of the multiple passive elements 21 and each of the multiple fuse units 22 are electrically connected in series. Therefore, the second circuit 2 includes multiple series circuits of one passive element 21 and one fuse unit 22. These multiple series circuits are connected in parallel to each other. In semiconductor device A10, as shown in Figure 20, each of the multiple passive elements 21 is connected to the power terminal 41 side (high potential side) of the corresponding fuse unit 22, but the opposite may also be true.

[0025] Each of the multiple passive elements 21 is, for example, a capacitor. Unlike this example, each of the multiple passive elements 21 may be an inductor or a resistor, etc. In the illustrated example, each passive element 21 is a chip-type capacitor. Each of the multiple passive elements 21 can be appropriately changed according to the specifications of the semiconductor device A10 or the function of the first circuit 1.

[0026] Each of the multiple fuse sections 22 is configured to melt when an overcurrent exceeding the rated current of the semiconductor device A10 (multiple semiconductor elements 1A, 1B) occurs. It is desirable that the fuses not melt when the rated current is exceeded instantaneously, such as inrush current. Each of the multiple fuse sections 22 may be configured to melt at a temperature of, for example, 300°C or higher. The melting temperature of each fuse section 22 is not limited to this. When an overcurrent exceeding the rated current flows continuously through each fuse section 22, it generates heat due to parasitic resistance components, etc., and reaches the melting temperature. This can cause each fuse section 22 to melt. On the other hand, when the current flows instantaneously, such as inrush current, it falls below the rated current before reaching the melting temperature, preventing each fuse section 22 from rising to its melting temperature. Thus, each fuse section 22 may be configured to melt when an overcurrent exceeding the rated current occurs (excluding cases where the rated current is exceeded instantaneously). In this embodiment, each fuse section 22 is composed of bonding wire. The wire diameter of the bonding wire is not limited in any way, but is for example 150 μm or more and 400 μm or less. Each fuse portion 22 contains, for example, lead and tin (i.e., solder), but may also contain other metals such as gold, copper, and aluminum. In the semiconductor device A10, as shown in Figure 9, the plurality of passive elements 21 and the plurality of fuse portions 22 are arranged along the second direction y. In other words, the arrangement direction of the plurality of passive elements 21 and the plurality of fuse portions 22 is the same as the arrangement direction of the plurality of semiconductor elements 1A.

[0027] As shown in Figures 4, 5, and 14, a plurality of semiconductor elements 1A are mounted on the substrate 7. The substrate 7 supports the plurality of semiconductor elements 1A.

[0028] As shown in Figures 14 and 16 to 19, the mounting substrate 7 has a mounting surface 70a and a back surface 70b. The mounting surface 70a and the back surface 70b are separated in the thickness direction z and face opposite each other. The mounting surface 70a faces upward in the thickness direction z, and the back surface 70b faces downward in the thickness direction z. Multiple semiconductor elements 1A are mounted on the mounting surface 70a. In this embodiment, the back surface 70b is exposed from the sealing member 6 (bottom surface 62, described later).

[0029] The mounting substrate 7 has a substrate body 70 and a hollow portion 78.

[0030] The substrate body 70 includes, for example, a multilayer laminated substrate. In this embodiment, the substrate body 70 has a plurality of ceramic substrates stacked in the thickness direction z. Each ceramic substrate includes an insulating layer and a wiring layer. The insulating layer of each ceramic substrate includes, for example, aluminum nitride (AlN). Unlike this example, the insulating layer of each ceramic substrate may also include silicon nitride (SiN). The insulating layer 711 and each insulating layer 721 described later correspond to the insulating layers of the ceramic substrates.

[0031] The substrate body 70 includes an upper substrate 71 and a lower substrate 72. The upper substrate 71 and the lower substrate 72 are stacked in the thickness direction z. The upper substrate 71 may be joined to the lower substrate 72 from above in the thickness direction z by a conductive bonding material (not shown) (for example, solder or a sintered body of metal particles).

[0032] The upper substrate 71 includes an insulating layer 711. In the illustrated example, the upper substrate 71 includes one insulating layer 711. The constituent material of the insulating layer 711 includes ceramic. The constituent material of the insulating layer 711 includes, for example, aluminum nitride (AlN) as the ceramic. Unlike this example, the constituent material of the insulating layer 711 may also include silicon nitride (SiN) as the ceramic. The insulating layer 711 is not limited to these, as long as it has excellent insulating properties and high thermal conductivity. The upper substrate 71 includes a circuit pattern. The circuit pattern may include a conductor layer formed on the surface of the insulating layer 711 and a through conductor formed in the inner layer of the insulating layer 711. The circuit pattern corresponds to the upper wiring section 75 described later.

[0033] The lower substrate 72 includes a plurality of insulating layers 721. The plurality of insulating layers 721 are stacked in the thickness direction z. In the illustrated example, six insulating layers 721 are stacked in the thickness direction z. The constituent material of each insulating layer 721 includes ceramic. The constituent material of each insulating layer 721 includes, for example, aluminum nitride (AlN) as the ceramic. Unlike this example, the constituent material of each insulating layer 721 may also include silicon nitride (SiN) as the ceramic. Each insulating layer 721 is not limited to these, as long as it has excellent insulating properties and high thermal conductivity. The lower substrate 72 includes a circuit pattern. The circuit pattern may include a conductor layer formed on the surface layer of the plurality of insulating layers 721, a conductor layer formed between the layers of the plurality of insulating layers 721, and a through conductor formed in the inner layer of the plurality of insulating layers 721. The circuit pattern corresponds to the lower wiring section 76 described later.

[0034] The multiple insulating layers 721 include a base layer 7211. The base layer 7211 is the bottommost of the multiple insulating layers 721. Therefore, in the illustrated example, five insulating layers 721 are laminated on the base layer 7211. The bottom surface of the base layer 7211 (the surface facing downward in the thickness direction z) corresponds to the back surface 70b.

[0035] The substrate body 70 has a wiring section 74. The wiring section 74 electrically connects the back electrodes 11 of a plurality of semiconductor elements 1A to each other, and also electrically connects the first circuit 1 and the second circuit 2. The wiring section 74 includes, for example, copper or a copper alloy. Unlike this example, the wiring section 74 may also be made of a metal other than copper (for example, gold, silver, or aluminum). The constituent material of the wiring section 74 may be changed depending on the part shown below. As shown in Figures 6, 7, and 18, the wiring section 74 has an upper wiring section 75 and a lower wiring section 76.

[0036] The upper wiring section 75 is located on the upper substrate 71. The upper wiring section 75 is the aforementioned circuit pattern formed on the insulating layer 711 of the upper substrate 71. The upper substrate 71 includes the insulating layer 711 and the upper wiring section 75. The insulating layer 711 and a part of the upper wiring section 75 formed on the insulating layer 711 correspond to one of the above-mentioned multiple ceramic substrates. The upper wiring section 75 has a conductor layer 751 and a through conductor 752.

[0037] The conductive layer 751 is formed on the upper surface (the surface facing upward in the thickness direction z) of the insulating layer 711 of the upper substrate 71. The conductive layer 751 includes two pattern portions 7511 and 7512. The two pattern portions 7511 and 7512 are spaced apart from each other. As shown in Figure 17, the back electrodes 11 of multiple semiconductor elements 1A are bonded to each of the pattern portions 7511. As shown in Figure 19, a conductive member 564 is electrically bonded to the pattern portion 7512. The formation area (shape and size) of the conductive layer 751 (each of the two pattern portions 7511 and 7512) is not limited to the illustrated example.

[0038] The through-conductor 752 penetrates at least a portion of the upper substrate 71 in the thickness direction z. In the illustrated example, the through-conductor 752 penetrates the insulating layer 711 in the thickness direction z. The through-conductor 752 includes two through-portions 7521 and 7522. As shown in Figure 17, the through-portion 7521 is located below the pattern portion 7511 in the thickness direction z. The upper surface of the through-portion 7521 is in contact with the pattern portion 7511. As shown in Figure 19, the through-portion 7522 is located below the pattern portion 7512 in the thickness direction z. The upper surface of the through-port 7522 is in contact with the pattern portion 7512.

[0039] The lower wiring section 76 is located on the lower substrate 72. The lower wiring section 76 is the aforementioned circuit pattern formed on a plurality of insulating layers 721 of the lower substrate 72. The lower substrate 72 includes a plurality of insulating layers 721 and the lower wiring section 76. Each insulating layer 721 and a portion of the lower wiring section 76 formed on the insulating layer 721 correspond to one of the plurality of ceramic substrates described above. The lower wiring section 76 has a conductor layer 761 and a through conductor 762.

[0040] The conductor layer 761 can be formed on the surface layer or between layers of the plurality of insulating layers 721 of the lower substrate 72. In this embodiment, the conductor layer 761 is formed on the upper surface of the base layer 7211. As shown in FIG. 9, the conductor layer 761 includes a plurality of pattern portions 7611 to 7613.

[0041] As shown in FIG. 9, in plan view, the pattern portion 7611 includes a strip-shaped portion extending in the first direction x and a plurality of branch portions protruding from the strip-shaped portion. The number of branch portions is appropriately set according to the number of passive elements 21. One terminal of each of the plurality of passive elements 21 is individually conductively bonded to the plurality of branch portions of the pattern portion 7611. As shown in FIGS. 17 and 19, each passive element 21 and the pattern portion 7611 are bonded by, for example, a conductive bonding layer 29. The bonding layer 29 is not particularly limited as long as it is conductive, and may be, for example, solder or a sintered body of metal particles containing silver or the like.

[0042] As shown in FIG. 9, the pattern portion 7612 is located between the pattern portion 7611 and the pattern portion 7613 in the second direction y. In plan view, the pattern portion 7612 includes a plurality of strip-shaped portions extending in the second direction y. The plurality of strip-shaped portions of the pattern portion 7612 are spaced apart from each other. To the plurality of strip-shaped portions of the pattern portion 7612, while the other terminals of the plurality of passive elements 21 are individually conductively bonded respectively, one end of each of the plurality of fuse portions 22 is individually bonded respectively. As shown in FIGS. 17 and 19, each passive element 21 and the pattern portion 7612 are bonded by, for example, a conductive bonding layer 29. The bonding layer 29 is not particularly limited as long as it is conductive, and may be, for example, solder or a sintered body of metal particles containing silver or the like.

[0043] As shown in FIG. 9, in plan view, the pattern portion 7613 includes a strip-shaped portion extending in the first direction x and a plurality of branch portions protruding from the strip-shaped portion. The number of branch portions is appropriately set according to the number of fuse portions 22. The other end of each of the plurality of fuse portions 22 is individually bonded to the plurality of branch portions of the pattern portion 7613.

[0044] In the conductor layer 761, a current path is formed from the pattern portion 7611 to the pattern portion 7613 via a plurality of passive elements 21, the pattern portion 7612, and a plurality of fuse portions 22. The formation regions (shape and size) of the conductor layer 761 (each of the plurality of pattern portions 7611 to 7613) are not limited to the illustrated example.

[0045] The through-conductor 762 penetrates at least a portion of the lower substrate 72 in the thickness direction z. In this embodiment, the through-conductor 762 penetrates the insulating layers 721, excluding the base layer 7211, in the thickness direction z. As shown in Figures 17 and 19, the through-conductor 762 includes two through-ports 7621 and 7622. As shown in Figures 17 and 19, the through-port 7621 is located above the pattern portion 7611 in the thickness direction z. The lower surface of the through-port 7621 is in contact with the pattern portion 7611. As shown in Figure 19, the through-port 7622 is located above the pattern portion 7612 in the thickness direction z. The lower surface of the through-port 7622 is in contact with the pattern portion 7612. In a plan view, the through-conductor 762 overlaps the through-conductor 752 of the upper wiring portion 75. As can be seen from Figures 17 and 19, in a plan view, the through-hole 7621 overlaps the through-hole 7521 (through-conductor 752), and as can be seen from Figure 19, in a plan view, the through-hole 7622 overlaps the through-hole 7522 (through-conductor 752).

[0046] The hollow portion 78 is surrounded by the substrate body 70 in a plan view. The second circuit 2 can be housed in the hollow portion 78. The hollow portion 78 is a space partitioned by openings formed in the multiple insulating layers 721 (excluding the base layer 7211) of the lower substrate 72, the upper substrate 71 (insulating layer 711), and the base layer 7211 of the lower substrate 72. A gas is sealed in the hollow portion 78 (each of the two housing portions 781 and 782 described later). This gas is, for example, air. In other words, in this embodiment, the hollow portion 78 is an air gap. Note that the gas is not limited to air, and may be a gas of one element or a composite gas of several elements. Note that since an artificially created vacuum cannot completely remove the gas, even if the inside of the hollow portion 78 is a vacuum (excluding an absolute vacuum), it may be considered that a gas is sealed inside.

[0047] The hollow portion 78 includes two accommodating portions 781 and 782. The two accommodating portions 781 and 782 are spaced apart from each other. The accommodating portion 781 accommodates a plurality of passive elements 21. In the accommodating portion 781, a part of the conductor layer 751 of the upper wiring portion 75 (a part of each of the two pattern portions 7511 and 7512) is exposed. The plurality of passive elements 21 are respectively conductively bonded to the conductor layer 751 exposed in the accommodating portion 781. The accommodating portion 782 accommodates a plurality of fuse portions 22. In the accommodating portion 782, a part of the conductor layer 751 of the upper wiring portion 75 (a part of each of the two pattern portions 7512 and 7513) is exposed. The plurality of fuse portions 22 are respectively conductively bonded to the conductor layer 751 exposed in the accommodating portion 782. In this embodiment, for example, as described below, the plurality of passive elements 21 can be accommodated in the accommodating portion 781, and the plurality of fuse portions 22 can be accommodated in the accommodating portion 782. The process is as follows: prepare the lower-layer substrate 72, and mount (bond) the plurality of passive elements 21 and the plurality of fuse portions 22 in the opened portion of the lower-layer substrate 72 (the plurality of insulating layers 721). Thereafter, the upper-layer substrate 71 is bonded from above the lower-layer substrate 72 in the thickness direction z by a conductive bonding material, whereby the plurality of passive elements 21 can be accommodated in the accommodating portion 781, and the plurality of fuse portions 22 can be accommodated in the accommodating portion 782.

[0048] In the mounting substrate 7 configured as described above, each back electrode 11 of the plurality of semiconductor elements 1A is conducted to the pattern portion 7511 of the conductor layer 751 of the upper wiring portion 75. The pattern portion 7511 is conducted to the pattern portion 7611 of the conductor layer 761 of the lower wiring portion 76 via the penetrating portion 7521 of the penetrating conductor 752 of the upper wiring portion 75 and the penetrating portion 7621 of the penetrating conductor 762 of the lower wiring portion 76. In addition, the pattern portion 7512 of the conductor layer 751 of the upper wiring portion 75 is conducted to the pattern portion 7613 of the conductor layer 761 of the lower wiring portion 76 via the penetrating portion 7522 of the penetrating conductor 752 of the upper wiring portion 75 and the penetrating portion 7622 of the penetrating conductor 762 of the lower wiring portion 76. Thereby, the second circuit 2 is electrically connected between the two pattern portions 7511 and 7512.

[0049] As shown in FIGS. 4, 5 and 13, a plurality of semiconductor elements 1B are mounted on the mounting substrate 8. The mounting substrate 8 supports the plurality of semiconductor elements 1B.

[0050] As shown in Figures 13 and 15, the mounting substrate 8 has a mounting surface 80a and a back surface 80b. The mounting surface 80a and the back surface 80b are separated in the thickness direction z and face opposite each other. The mounting surface 80a faces upward in the thickness direction z, and the back surface 80b faces downward in the thickness direction z. Multiple semiconductor elements 1B are mounted on the mounting surface 80a. In this embodiment, the back surface 80b is exposed from the sealing member 6 (bottom surface 62, described later).

[0051] As shown in Figures 13 and 15, the mounting substrate 8 includes a base substrate 81 and a conductor substrate 82.

[0052] The base substrate 81 supports the conductor substrate 82. The base substrate 81 may be composed of, for example, a DBC (Direct Bonding Copper) substrate or an AMB (Active Metal Brazing) substrate. Note that the DBC substrate is sometimes called a DCB (Direct Copper Bonding) substrate. As shown in Figures 13 and 15, the base substrate 81 includes an insulating layer 811 and two metal layers 812 and 813. As shown in Figures 13 and 15, the insulating layer 811 is interposed between the two metal layers 812 and 813 in the thickness direction z. Metal layer 812 is located above the insulating layer 811 in the thickness direction z. Metal layer 812 is in contact with the upper surface (the surface facing upward in the thickness direction z) of the insulating layer 811 and is bonded to the upper surface of the insulating layer 811. Metal layer 813 is located below the insulating layer 811 in the thickness direction z. The metal layer 813 is in contact with the lower surface (the surface facing downward in the thickness direction z) of the insulating layer 811 and is bonded to the lower surface of the insulating layer 811. The insulating layer 811 includes, for example, a material with relatively high thermal conductivity. The insulating layer 811 may include, for example, ceramic. The ceramic may include, for example, aluminum nitride or silicon nitride. In addition to ceramic, the insulating layer 811 may also include an insulating resin sheet. The constituent materials of the two metal layers 812 and 813 include copper, but may be other metals.

[0053] The conductive substrate 82 is placed on the base substrate 81. As shown in Figure 15, the conductive substrate 82 is bonded to the metal layer 812 of the base substrate 81 by a conductive bonding layer 829. The bonding layer 829 is not limited in any way as long as it is conductive, but for example it may be solder or a sintered body of metal particles containing silver or the like. The conductive substrate 82 contains, for example, copper or a copper alloy. The conductive substrate 82 is a metal substrate (a thick copper substrate in this embodiment). Each back electrode 11 of the plurality of semiconductor elements 1B is electrically bonded to the conductive substrate 82. As a result, the back electrodes 11 of the plurality of semiconductor elements 1B are electrically connected to each other via the conductive substrate 82. Unlike the illustrated example, the conductive substrate 82 may not be a metal substrate, but for example a multilayer laminated substrate in which a plurality of ceramic substrates are stacked.

[0054] In semiconductor device A10, the dimension of the mounting substrate 7 in the thickness direction z is the same as the dimension of the mounting substrate 8 in the thickness direction z. In particular, the mounting surface 70a of the mounting substrate 7 and the mounting surface 80a of the mounting substrate 8 are at the same position (same height) in the thickness direction z.

[0055] The two signal boards 3A and 3B relay various signals from multiple semiconductor elements 1A and 1B and multiple signal terminals 44A to 47A and 44B to 47B. The two signal boards 3A and 3B may each be composed of, for example, a DBC board or an AMB board. Unlike this example, the two signal boards 3A and 3B may each be printed circuit boards. As shown in Figure 14, the signal board 3A is mounted on the mounting surface 70a of the mounting substrate 7 together with the multiple semiconductor elements 1A, and as shown in Figure 15, the signal board 3B is mounted on the mounting surface 80a of the mounting substrate 8 together with the multiple semiconductor elements 1B. The two signal boards 3A and 3B each include an insulating layer 31 and two metal layers 32 and 33.

[0056] The insulating layer 31 is interposed between the two metal layers 32 and 33 in the thickness direction z. The insulating layer 31 may be made of, for example, ceramic. In addition to ceramic, the insulating layer 31 may be made of an insulating resin sheet.

[0057] The metal layer 32 is formed on the upper surface (the surface facing upward in the thickness direction z) of the insulating layer 31. Each metal layer 32 contains copper or a copper alloy. Unlike this example, each metal layer 32 may contain a metal other than copper (such as gold, silver, copper, iron, or aluminum). The metal layer 32 of the signal board 3A includes two wiring sections 321A and 322A, and the metal layer 32 of the signal board 3B includes two wiring sections 321B and 322B.

[0058] The two wiring sections 321A and 322A are spaced apart from each other. In the illustrated example, the two wiring sections 321A and 322A are each strip-shaped in a plan view, extending in the second direction y. In a plan view, the two wiring sections 321A and 322A are adjacent to each other and parallel in a plan view. In the illustrated example, the wiring section 322A is located closer to the multiple semiconductor elements 1A than the wiring section 321A in the first direction x. The shapes of the two wiring sections 321A and 322A, and the positional relationship between the two wiring sections 321A and 322A, are not limited to the illustrated example.

[0059] The wiring section 321A is electrically connected to the main surface electrode 13 of each semiconductor element 1A via the connecting member 51A. The wiring section 321A transmits a first drive signal that controls the switching operation of each semiconductor element 1A.

[0060] The wiring section 322A is electrically connected to one of the two signal pads 122 of the main surface electrode 12 of each semiconductor element 1A via the connecting member 52A. A voltage corresponding to the maximum current flowing through the main surface electrode 12 of each semiconductor element 1A is applied to the wiring section 322A.

[0061] The two wiring sections 321B and 322B are spaced apart from each other. In the illustrated example, the two wiring sections 321B and 322B are each strip-shaped in a plan view, extending in the second direction y. In a plan view, the two wiring sections 321B and 322B are adjacent to each other and parallel in a plan view. In the illustrated example, the wiring section 322B is located closer to the multiple semiconductor elements 1B than the wiring section 321B in the first direction x. The shapes of the two wiring sections 321B and 322B, and the positional relationship between the two wiring sections 321B and 322B, are not limited to the illustrated example.

[0062] The wiring section 321B is electrically connected to the main surface electrode 13 of each semiconductor element 1B via the connecting member 51B. The wiring section 321B transmits a second drive signal that controls the switching operation of each semiconductor element 1B.

[0063] The wiring section 322B is electrically connected to one of the two signal pads 122 of the main surface electrode 12 of each semiconductor element 1B via the connecting member 52B. A voltage corresponding to the maximum current flowing through the main surface electrode 12 of each semiconductor element 1B is applied to the wiring section 322B.

[0064] The metal layer 33 is formed on the lower surface (the surface facing downward in the thickness direction z) of the insulating layer 31. Each metal layer 33 contains copper or a copper alloy. Unlike this example, each metal layer 33 may contain a metal other than copper (such as gold, silver, copper, iron, or aluminum). As shown in Figure 14, the metal layer 33 of the signal substrate 3A is bonded to the mounting substrate 7 by an adhesive layer 39. As shown in Figure 15, the metal layer 33 of the signal substrate 3B is bonded to the mounting substrate 8 by an adhesive layer 39. Each of these adhesive layers 39 is made of a material that may or may not be conductive, such as solder.

[0065] Each of the power terminals 41 to 43 conducts to one of the semiconductor elements 1A and 1B. Each of the power terminals 41 to 43 carries a current corresponding to the power before conversion (DC power) or the power after conversion (AC power) by the switching operations of the semiconductor elements 1A and 1B. Each of the power terminals 41 to 43 is a metal plate. The constituent materials of each of the power terminals 41 to 43 include, but are not limited to, copper or a copper alloy.

[0066] The power terminal 41 is electrically connected to the back electrode 11 (drain electrode) of each of the multiple semiconductor elements 1A. The power terminal 41 is a P terminal (positive terminal) to which the DC power supply voltage to be converted is applied. As shown in Figures 4 and 5, the power terminal 41 includes an inner portion 411 and a terminal portion 412.

[0067] The inner portion 411 is the part of the power terminal 41 that is covered by the sealing member 6. As shown in Figure 14, the inner portion 411 is electrically bonded to the conductor layer 751 (pattern portion 7511) of the mounting substrate 7 via a conductive member 561. As shown in Figure 14, the inner portion 411 is bonded to the conductive member 561 via a conductive bonding layer 419. As shown in Figure 14, the conductive member 561 is bonded to the conductor layer 751 of the mounting substrate 7 via a conductive bonding layer 569. As a result, the power terminal 41 and the conductor layer 751 (pattern portion 7511) of the mounting substrate 7 are electrically connected. These bonding layers 419 and 569 are not limited in any way as long as they are conductive, but for example they may be solder or a sintered body of metal particles containing silver or the like.

[0068] The terminal portion 412 is the portion of the power terminal 41 that is exposed from the sealing member 6. As shown in Figure 4 and other figures, the terminal portion 412 extends in a first direction x from the sealing member 6 (the side surface 631 described later) in a plan view. The terminal portion 412 is, for example, rectangular in a plan view.

[0069] The power terminal 42 is electrically connected to the power pad 121 (source pad) of each main surface electrode 12 of the plurality of semiconductor elements 1B. The power terminal 42 is the N terminal (negative terminal) to which the DC voltage to be converted is applied. As shown in Figures 4 and 5, the power terminal 42 includes an inner portion 421 and a terminal portion 422.

[0070] The inner portion 421 is the part of the power terminal 42 that is covered by the sealing member 6. As shown in Figure 4, the inner portion 421 includes a connecting portion 421a, a plurality of extension portions 421b, and a connecting portion 421c.

[0071] As shown in Figure 4, the connecting portion 421a is, for example, a strip extending in the second direction y. The connecting portion 421a connects a plurality of extensions 421b.

[0072] Each of the multiple extensions 421b is, for example, a strip extending in a first direction x from the connecting portion 421a, as shown in Figure 4. Each extension 421b extends in the first direction x from the connecting portion 421a until it overlaps with the corresponding semiconductor element 1B in a plan view. In a plan view, the multiple extensions 421b are aligned in a second direction y and spaced apart from each other. As shown in Figure 15, the tip of each extension 421b is joined to the main surface electrode 12 (power pad 121) of each semiconductor element 1B via a conductive member 562. As shown in Figure 15, the tip of each extension 421b is joined to the conductive member 562 via a conductive bonding layer 429, and the conductive member 562 is joined to the main surface electrode 12 (power pad 121) of each semiconductor element 1B via a conductive bonding layer 569. This allows electrical conductivity between the power terminal 42 and the main surface electrode 12 (power pad 121) of each semiconductor element 1B. These bonding layers 429 and 569 are not limited in any way as long as they are conductive, but for example they may be solder or a sintered body of metal particles containing silver or the like.

[0073] As shown in Figure 4, the connecting portion 421c is the part that connects the connecting portion 421a and the terminal portion 422. As shown in Figure 19, the connecting portion 421c is joined to the conductor layer 751 (pattern portion 7512) of the mounting substrate 7 via a conductive member 564. As shown in Figure 19, the connecting portion 421c is joined to the conductive member 564 via a conductive bonding layer 429, and the conductive member 564 is joined to the conductor layer 751 (pattern portion 7512) of the mounting substrate 7 via a conductive bonding layer 569. As a result, the power terminal 42 and the pattern portion 7512 of the conductor layer 751 are electrically connected. These bonding layers 429 and 569 are not limited in any way as long as they are conductive, but for example they may be solder or a sintered body of metal particles containing silver or the like.

[0074] The terminal portion 422 is the portion of the power terminal 42 that is exposed from the sealing member 6. As shown in Figure 4 and other figures, the terminal portion 422 extends in a first direction x from the sealing member 6 (the side surface 631 described later) in a plan view. As shown in Figure 4, the terminal portion 422 is located in one of the second directions y of the terminal portion 412 of the power terminal 41 in a plan view. The plan view shape of the terminal portion 422 is, for example, the same as the plan view shape of the terminal portion 412.

[0075] The power terminal 43 is electrically connected to the power pads 121 (source pads) of the main surface electrodes 12 of each of the multiple semiconductor elements 1A, and also to the back surface electrodes 11 (drain electrodes) of each of the multiple semiconductor elements 1B. AC power converted by the multiple semiconductor elements 1A and 1B is output from the power terminal 43. In other words, the power terminal 43 is an AC power output terminal.

[0076] As shown in Figure 4, the power terminal 43 includes an inner portion 431 and a terminal portion 432.

[0077] The inner portion 431 is the part of the power terminal 43 that is covered by the sealing member 6. As shown in Figure 13, the inner portion 431 is electrically bonded to the conductor substrate 82 of the mounting substrate 8 via a conductive member 563. As shown in Figure 15, the inner portion 431 is bonded to the conductive member 563 via a conductive bonding layer 439, and the conductive member 563 is bonded to the conductor substrate 82 of the mounting substrate 8 via a conductive bonding layer 569. As a result, the power terminal 43 and the conductor substrate 82 are electrically connected. These bonding layers 439 and 569 are not limited in any way as long as they are conductive, but for example they may be solder or a sintered body of metal particles containing silver or the like.

[0078] The terminal portion 432 is the portion of the power terminal 43 that is exposed from the sealing member 6. As shown in Figure 4 and other figures, the terminal portion 432 extends from the sealing member 6 (the side surface 632 described later) in a first direction x. The terminal portion 432 is, for example, rectangular in plan view.

[0079] Multiple signal terminals 44A to 47A and 44B to 47B are terminals for inputting or outputting control signals in the semiconductor device A10. Examples of control signals include signals for controlling the switching operations of multiple semiconductor elements 1A and 11B. The multiple signal terminals 44A to 47A and 44B to 47B are substantially the same shape. Each of the multiple signal terminals 44A to 47A and 44B to 47B forms an L-shape when viewed in the first direction x. The multiple signal terminals 44A to 47A and 44B to 47B are arranged along the first direction x, as shown in Figures 1 to 7, Figure 10, and Figure 11. Each of the signal terminals 44A to 47A and 44B to 47B overlaps when viewed in the first direction x, as can be seen from Figure 12. As shown in Figure 5 and other figures, the multiple signal terminals 44A to 47A are located adjacent to the second direction y of the mounting substrate 7 in a plan view, and the multiple signal terminals 44B to 47B are located adjacent to the second direction y of the mounting substrate 8 in a plan view, as shown in Figure 5 and other figures. Each of the signal terminals 44A to 47A and 44B to 47B protrudes, for example, from a surface of the sealing member 6 facing one side in the second direction y (the side surface 633 described later). The multiple signal terminals 44A to 47A and 44B to 47B can all be formed from the same lead frame.

[0080] As shown in Figures 5 and 6, the signal terminal 44A is electrically connected to the wiring section 322A via the connecting member 54A. The voltage applied to each main surface electrode 12 of the multiple semiconductor elements 1A (voltage corresponding to the source current) is detected from the signal terminal 44A. The signal terminal 44A is the source signal detection terminal for the multiple semiconductor elements 1A.

[0081] As shown in Figures 5 and 6, the signal terminal 44B is electrically connected to the wiring section 322B via the connecting member 54B. The voltage applied to each main surface electrode 12 of the multiple semiconductor elements 1B (voltage corresponding to the source current) is detected from the signal terminal 44B. The signal terminal 44B is the source signal detection terminal for the multiple semiconductor elements 1B.

[0082] The two signal terminals 44A and 44B each include an inner portion 441 and a terminal portion 442, as shown in Figure 6. In each signal terminal 44A and 44B, the inner portion 441 is covered by a sealing member 6. With this configuration, each signal terminal 44A and 44B is supported by the sealing member 6. The terminal portion 442 is connected to the inner portion 441 and is exposed from the sealing member 6. Each signal terminal 44A and 44B is bent at the terminal portion 442.

[0083] As shown in Figures 5 and 6, the signal terminal 45A is electrically connected to the wiring section 321A via the connecting member 53A. A first drive signal (gate voltage) for driving multiple semiconductor elements 1A is applied to the signal terminal 45A. The signal terminal 45A is the input terminal (gate signal input terminal) for the first drive signal of the multiple semiconductor elements 1A.

[0084] As shown in Figures 5 and 6, the signal terminal 45B is electrically connected to the wiring section 321B via the connecting member 53B. A second drive signal (gate voltage) for driving multiple semiconductor elements 1B is applied to the signal terminal 45B. The signal terminal 45B is the input terminal (gate signal input terminal) for the second drive signal of the multiple semiconductor elements 1B.

[0085] The two signal terminals 45A and 45B each include an inner portion 451 and a terminal portion 452, as shown in Figure 6. In each signal terminal 45A and 45B, the inner portion 451 is covered by a sealing member 6. In this configuration, each signal terminal 45A and 45B is supported by the sealing member 6. The terminal portion 452 is connected to the inner portion 451 and is exposed from the sealing member 6. Each signal terminal 45A and 45B is bent at the terminal portion 452.

[0086] The multiple signal terminals 46A, 46B, 47A, and 47B are not electrically connected to other components, as shown in Figures 5 and 6. The semiconductor device A10 may also be configured without these signal terminals 46A, 46B, 47A, and 47B.

[0087] Each of the two signal terminals 46A and 46B includes an inner portion 461 and a terminal portion 462, as shown in Figure 6. In each of the signal terminals 46A and 46B, the inner portion 461 is covered by a sealing member 6. With this configuration, each of the signal terminals 46A and 46B is supported by the sealing member 6. The terminal portion 462 is connected to the inner portion 461 and is exposed from the sealing member 6. Each of the signal terminals 46A and 46B is bent at the terminal portion 462. Each of the two signal terminals 47A and 47B includes an inner portion 471 and a terminal portion 472. In each of the signal terminals 47A and 47B, the inner portion 471 is covered by a sealing member 6. With this configuration, each of the signal terminals 47A and 47B is supported by the sealing member 6. The terminal portion 472 is connected to the inner portion 471 and is exposed from the sealing member 6. Each signal terminal 47A, 47B is bent at the terminal portion 472.

[0088] Each of the connecting members 51A-54A and 51B-54B provides electrical conductivity between two separated parts. In the illustrated example, each of the connecting members 51A-54A and 51B-54B is a bonding wire. Unlike this example, each of the connecting members 51A-54A and 51B-54B may be a bonding ribbon or a metal plate (metal clip). The constituent materials of each of the connecting members 51A-54A and 51B-54B are not limited in any way, but include, for example, gold, aluminum, silver, iron, or copper.

[0089] As shown in Figures 5 and 6, the multiple connecting members 51A electrically connect the main surface electrodes 13 (gate electrodes) of the multiple semiconductor elements 1A to the wiring section 321A. One end of each connecting member 51A is joined to the main surface electrode 13 of any of the semiconductor elements 1A, and the other end of each connecting member 51A is joined to the wiring section 321A.

[0090] As shown in Figures 5 and 6, the multiple connecting members 51B electrically connect the main surface electrodes 13 (gate electrodes) of the multiple semiconductor elements 1B to the wiring section 321B. One end of each connecting member 51B is joined to the main surface electrode 13 of any of the semiconductor elements 1B, and the other end of each connecting member 51B is joined to the wiring section 321B.

[0091] As shown in Figures 5 and 6, the multiple connecting members 52A electrically connect the main surface electrodes 12 (source electrodes) of the multiple semiconductor elements 1A to the wiring section 322A. One end of each connecting member 52A is joined to one of the two signal pads 122 of the main surface electrode 12 of any of the semiconductor elements 1A, and the other end of each connecting member 52A is joined to the wiring section 322A.

[0092] As shown in Figures 5 and 6, the multiple connecting members 52B electrically connect the main surface electrodes 12 (source electrodes) of the multiple semiconductor elements 1B to the wiring section 322B. One end of each connecting member 52B is joined to one of the two signal pads 122 of the main surface electrode 12 of any of the semiconductor elements 1B, and the other end of each connecting member 52B is joined to the wiring section 322B.

[0093] As shown in Figures 5 and 6, the connecting member 53A electrically connects the wiring section 321A and the signal terminal 45A. One end of the connecting member 53A is joined to the wiring section 321A, and the other end of the connecting member 53A is joined to the portion of the signal terminal 45A covered by the sealing member 6 (inner portion 451).

[0094] As shown in Figures 5 and 6, the connecting member 53B electrically connects the wiring section 321B and the signal terminal 45B. One end of the connecting member 53B is joined to the wiring section 321B, and the other end of the connecting member 53B is joined to the portion of the signal terminal 45B covered by the sealing member 6 (inner portion 451).

[0095] As shown in Figures 5 and 6, the connecting member 54A electrically connects the wiring section 322A and the signal terminal 44A. One end of the connecting member 54A is joined to the wiring section 322A, and the other end of the connecting member 54A is joined to the portion of the signal terminal 44A covered by the sealing member 6 (inner portion 441).

[0096] As shown in Figures 5 and 6, the connecting member 54B electrically connects the wiring section 322B and the signal terminal 44B. One end of the connecting member 54B is joined to the wiring section 322B, and the other end of the connecting member 54B is joined to the portion of the signal terminal 44B covered by the sealing member 6 (inner portion 441).

[0097] Multiple conductive members 55 electrically connect the main surface electrodes 12 (power pads 121) of the multiple semiconductor elements 1A to the mounting substrate 8 (conductor substrate 82). Each of the multiple conductive members 55 is, for example, a metal plate (metal clip). Unlike this example, each of the multiple conductive members 55 may be a bonding wire or a bonding ribbon. Each of the multiple conductive members 55 is a strip extending in the first direction x in a plan view. As shown in Figure 5, each of the multiple conductive members 55 overlaps the gap between the mounting substrate 7 and the mounting substrate 8 in a plan view. Each of the multiple conductive members 55 includes a portion electrically connected to the main surface electrode 12 (power pad 121) of the corresponding semiconductor element 1A, and a portion electrically connected to the conductor substrate 82 of the mounting substrate 8. In each conductive member 55, the thickness (dimension in the thickness direction z) of the portion joined to the conductive substrate 82 is greater than the thickness (dimension in the thickness direction z) of the portion joined to the main surface electrode 12 of the corresponding semiconductor element 1A. Each of the multiple conductive members 55 is joined to the power pad 121 of the main surface electrode 12 of the corresponding semiconductor element 1A by a conductive bonding layer 559, and is also joined to the conductive substrate 82 by a conductive bonding layer 559. These bonding layers 559 are not limited in any way as long as they are conductive, but for example they may be solder or a sintered body of metal particles containing silver or the like.

[0098] Each of the conductive members 561 to 564 is a metal block member. Each of the conductive members 561 to 564 is, for example, a cube or a rectangular prism. The constituent material of each of the conductive members 561 to 564 includes, for example, copper or a copper alloy. Unlike this example, the constituent material of each of the conductive members 561 to 564 may be a metal other than copper (such as gold, silver, iron, or aluminum), or a composite material such as copper molybdenum or CIC.

[0099] As shown in Figure 14, the conductive member 561 is interposed between the inner portion 411 of the power terminal 41 and the conductor layer 751 (pattern portion 7511) of the upper wiring portion 75 of the mounting substrate 7. The conductive member 561 is electrically bonded to the conductor layer 751 (pattern portion 7511) by a conductive bonding layer 569. The inner portion 411 is electrically bonded to the upper surface of the conductive member 561 by a conductive bonding layer 419. The bonding between the conductive member 561 and the inner portion 411 is not limited to bonding by the conductive bonding layer 419, but may also be bonded by laser welding or ultrasonic bonding, etc. The inner portion 411 and the conductor layer 751 are not limited to being electrically bonded via the conductive member 561, but may also be directly bonded to the conductor layer 751 by partially bending the inner portion 411 or by partially thickening the inner portion 411.

[0100] As shown in Figure 15, the multiple conductive members 562 are individually interposed between the multiple extensions 421b of the power terminal 42 and the main surface electrodes 12 (power pads 121) of the multiple semiconductor elements 1B. Each of the multiple conductive members 562 is electrically bonded to the corresponding main surface electrode 12 (power pad 121) of the semiconductor element 1B by a conductive bonding layer 569. The upper surface of each conductive member 562 is electrically bonded to the corresponding extension 421b by a conductive bonding layer 429. The bonding between each conductive member 562 and the corresponding extension 421b (power terminal 42) is not limited to bonding by the conductive bonding layer 429, but may also be done by laser welding or ultrasonic bonding. The extension portion 421b and the main surface electrode 12 (power pad 121) of the semiconductor element 1B are not limited to being electrically connected via a conductive member 562. The extension portion 421b may also be directly joined to the main surface electrode 12 (power pad 121) of the semiconductor element 1B by partially bending the extension portion 421b or by partially thickening the extension portion 421b.

[0101] As shown in Figure 13, the conductive member 563 is interposed between the inner portion 431 of the power terminal 43 and the conductor substrate 82 of the mounting substrate 8. The conductive member 563 is electrically bonded to the conductor substrate 82 by a conductive bonding layer 569. The inner portion 431 is electrically bonded to the upper surface of the conductive member 563 by a conductive bonding layer 439. The bonding between the conductive member 563 and the inner portion 431 is not limited to bonding by the conductive bonding layer 439, but may also be bonded by laser welding or ultrasonic bonding, etc. The inner portion 431 and the conductor substrate 82 are not limited to being electrically bonded via the conductive member 563, but the inner portion 431 may be directly bonded to the conductor substrate 82 by partially bending the inner portion 431 or by partially thickening the inner portion 431.

[0102] As shown in Figure 19, the conductive member 564 is interposed between the connection portion 421c of the power terminal 42 and the pattern portion 7512 of the conductor layer 751 of the mounting substrate 7. The conductive member 564 is electrically joined to the pattern portion 7512 by a conductive bonding layer 569. The connection portion 421c of the power terminal 42 is electrically joined to the upper surface of the conductive member 564 by a conductive bonding layer 429. The joining of the conductive member 564 and the inner portion 421 (connection portion 421c) is not limited to joining by the conductive bonding layer 429, but may also be done by laser welding or ultrasonic bonding. The inner portion 421 (connection portion 421c) and the pattern portion 7512 are not limited to being electrically connected via the conductive member 564, but the inner portion 421 may be directly joined to the pattern portion 7512 by partially bending the inner portion 421 or by partially thickening the inner portion 421. In the illustrated example, the conductive member 564, in a plan view, overlaps the through-hole 7521 of the through-conductor 752 of the upper wiring section 75 and the through-hole 7621 of the through-conductor 762 of the lower wiring section 76. As shown in Figure 19, the conductive member 564 is electrically connected to the second circuit 2 (fuse section 22) via the through-conductor 752 (through-hole 7522) and the through-conductor 762 (through-hole 7622).

[0103] As shown in Figures 4, 5, 13, 16, and 18, the sealing member 6 covers a plurality of semiconductor elements 1A, 1B, a mounting substrate 7 (excluding the back surface 70b in this embodiment), and a mounting substrate 8 (the back surface 80b in this embodiment). The sealing member 6 covers two signal substrates 3A, 3B, a portion of each of a plurality of power terminals 41-43, a portion of each of a plurality of signal terminals 44A-47A, 44B-47B, a plurality of connecting members 51A-54A, 51B-54B, a plurality of conductive members 55, and a plurality of conductive members 561-564. The sealing member 6 is made of, for example, a resin material. An example of such a resin material is a thermosetting resin, such as a black epoxy resin. As shown in Figures 3-5, 10-13, 16, and 18, the sealing member 6 has a top surface 61, a bottom surface 62, and a plurality of side surfaces 631-634.

[0104] The top surface 61 and the bottom surface 62 are separated in the thickness direction z, as shown in Figure 10 and other figures. The top surface 61 faces upward in the thickness direction z, and the bottom surface 62 faces downward in the thickness direction z. As shown in Figure 11, the bottom surface 62 is a frame shape that surrounds the back surface 70b of the mounting substrate 7 and the back surface 80b of the mounting substrate 8 in a plan view. As a result, the back surface 70b of the mounting substrate 7 and the back surface 80b of the mounting substrate 8 are exposed from the bottom surface 62. In the illustrated example, the back surface 70b of the mounting substrate 7 and the back surface 80b of the mounting substrate 8 are each located below the bottom surface 62 in the thickness direction z, but they may be flush with the bottom surface 62 or located above the bottom surface 62 in the thickness direction z. Multiple side surfaces 631 to 634 are each connected to both the top surface 61 and the bottom surface 62, and are sandwiched between them in the thickness direction z. As shown in Figures 3-5, 11 and 13, side 631 and side 632 are separated in the first direction x and face opposite each other in the second direction y. Two power terminals 41 and 42 protrude from side 631, and power terminal 43 protrudes from side 632. As shown in Figures 3-5, 16 and 18, side 633 and side 634 are separated in the second direction y and face opposite each other in the second direction y. Multiple signal terminals 44A to 47A and 44B to 47B protrude from side 633.

[0105] As shown in Figures 11, 13, 16, and 18, the sealing member 6 includes a recess 65 that is recessed in the thickness direction z from the bottom surface 62. In a plan view, as shown in Figure 11, the recess 65 is formed in an annular shape surrounding the mounting substrate 7 and the mounting substrate 8. Unlike the illustrated example, the sealing member 6 does not necessarily have to have a recess 65 formed therein.

[0106] In the semiconductor device A10 configured as described above, as shown in Figure 17 and other figures, each back electrode 11 of the multiple semiconductor elements 1A (i.e., one end of the first circuit 1) is electrically connected to one end of each of the multiple passive elements 21 (i.e., one end of the second circuit 2) via the pattern portion 7511 of the conductor layer 751 of the upper wiring portion 75, the through portion 7521 of the through conductor 752 of the upper wiring portion 75, the through portion 7621 of the through conductor 762 of the lower wiring portion 76, and the pattern portion 7611 of the conductor layer 761 of the lower wiring portion 76. Furthermore, as shown in Figures 15 and 19, the power pads 121 of each main surface electrode 12 of the multiple semiconductor elements 1B (i.e., the other end of the first circuit 1) are electrically connected to one end of each of the multiple fuse sections 22 (i.e., the other end of the second circuit 2) via the conductive member 562, the power terminal 42, the conductive member 564, the pattern section 7512 of the conductor layer 751 of the upper wiring section 75, the through section 7522 of the through conductor 752 of the upper wiring section 75, the through section 7622 of the through conductor 762 of the lower wiring section 76, and the pattern section 7613 of the conductor layer 761 of the lower wiring section 76. In this way, in the semiconductor device A10, the first circuit 1 and the second circuit 2 are electrically connected in parallel via the wiring section 74 of the mounting substrate 7.

[0107] Next, we will describe vehicle F1, on which semiconductor device A10 is installed, with reference to Figure 21. Vehicle F1 is, for example, an electric vehicle (EV).

[0108] As shown in Figure 21, the vehicle F1 includes an on-board charger F11, a battery F12, and a drive system F13. Power is supplied to the on-board charger F11 wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, the means of supplying power from the power supply facility to the on-board charger F11 may be wired. The on-board charger F11 is configured with a boost-type DC-DC converter. The voltage of the power supplied to the on-board charger F11 is boosted by the converter and then supplied to the battery F12. The boosted voltage is, for example, 600V.

[0109] The drive system F13 drives the vehicle F1. The drive system F13 includes an inverter F131 and a drive source F132. The semiconductor device A10 constitutes part of the inverter F131. Power stored in the battery F12 is supplied to the inverter F131. The power supplied from the battery F12 to the inverter F131 is DC power. In addition, unlike the power system shown in Figure 21, a boost DC-DC converter may be further provided between the battery F12 and the inverter F131. The inverter F131 converts DC power to AC power. The inverter F131, including the semiconductor device A10, is connected to the drive source F132. The drive source F132 includes an AC motor and a transmission. When the AC power converted by the inverter F131 is supplied to the drive source F132, the AC motor rotates, and that rotation is transmitted to the transmission. The transmission reduces the rotational speed transmitted from the AC motor as needed, and then rotates the drive shaft of vehicle F1. This drives vehicle F1. In driving vehicle F1, it is necessary to freely control the rotational speed of the AC motor based on information such as the amount of fluctuation in the accelerator pedal. Therefore, the semiconductor device A10 in inverter F131 is necessary to output AC power whose frequency is appropriately changed in order to correspond to the required rotational speed of the AC motor.

[0110] The mounting of the semiconductor device A10 on the vehicle F1 is not limited to the illustrated example. For example, the semiconductor device A10 may constitute part of the DC-DC converter of the onboard charger F11.

[0111] The operation and effects of semiconductor device A10 are as follows:

[0112] The semiconductor device A10 includes a first circuit in which semiconductor elements 1A and 1B are electrically connected in series, and a second circuit 2 including a passive element 21. The first circuit 1 and the second circuit 2 are electrically connected in parallel. With this configuration, in addition to the first circuit in which semiconductor elements 1A and 1B are electrically connected in series, the second circuit 2 including the passive element 21 is provided, so the function of the second circuit 2 (passive element 21) can be added to a conventional semiconductor device (for example, Patent Document 1). Therefore, the semiconductor device A10 can be made more functional.

[0113] In semiconductor device A10, the mounting substrate 7 on which the semiconductor element 1A is mounted includes a substrate body 70 having a wiring section 74 and a hollow section 78 surrounded by the substrate body 70. The hollow section 78 includes a housing section 781 in which the passive element 21 is housed. With this configuration, the second circuit 2 (passive element 21) can be incorporated without arranging the passive element 21 above the mounting substrate 7 in the thickness direction z. In other words, semiconductor device A10 can incorporate the second circuit 2 (passive element 21) while securing space for the semiconductor element 1A on the mounting substrate 7.

[0114] In semiconductor device A10, the first circuit 1 is a half-bridge type switching circuit, and the passive element 21 of the second circuit 2 is a capacitor. With this configuration, the passive element 21 functions as a snubber capacitor. Therefore, semiconductor device A10 can suppress surge voltages associated with the switching operation of the first circuit 1 (each semiconductor element 1A and each semiconductor element 1B).

[0115] In semiconductor device A10, the second circuit 2 has a fuse unit 22 electrically connected in series with the passive element 21. In a configuration where the second circuit 2 does not include a fuse unit 22, if the passive element 21 short-circuits, even if there is no abnormality in the first circuit 1 (semiconductor element 1A and semiconductor element 1B), a short-circuit current will flow through the second circuit 2, causing the operation of the first circuit 1 (for example, a switching circuit) to stop. On the other hand, in semiconductor device A10, since the fuse unit 22 is electrically connected in series with the passive element 21, when the passive element 21 short-circuits, even if a short-circuit current flows through the second circuit 2, the fuse unit 22 will melt, interrupting the second circuit 2. Therefore, semiconductor device A10 can avoid the operation of the first circuit 1 (for example, a switching circuit) stopping even if the passive element 21 short-circuits.

[0116] In semiconductor device A10, the hollow portion 78 of the mounting substrate 7 includes a housing portion 782 for housing the fuse portion 22. With this configuration, the fuse portion 22 can be built in without having to place the fuse portion 22 above the mounting substrate 7 in the thickness direction z. In other words, semiconductor device A10 can build in the second circuit 2 (passive element 21 and fuse portion 22) while securing space for the semiconductor element 1A on the mounting substrate 7.

[0117] In semiconductor device A10, the fuse section 22 is made of bonding wire. With this configuration, when the passive element 21 is a capacitor, the fuse section 22 can function as a resistor, allowing the second circuit 2 to function as an RC snubber circuit. In other words, semiconductor device A10 allows the fuse section 22 to function as both a fuse and a resistive component of a snubber circuit.

[0118] In semiconductor device A10, the mounting substrate 7 is a multilayer laminated substrate. With this configuration, a hollow portion 78 can be easily formed by providing openings in the laminated substrate (for example, multiple insulating layers 711, 721). Furthermore, this configuration makes it easy to adjust the thickness of the mounting substrate 7. In other words, in semiconductor device A10, the dimension in the thickness direction z of the mounting substrate 7 can be easily matched to the dimension in the thickness direction z of the mounting substrate 8.

[0119] In semiconductor device A10, the mounting substrate 7 has a plurality of insulating layers 711, 721, and the plurality of 711, 721 include ceramic. In other words, the mounting substrate 7 has a plurality of ceramic substrates. Ceramics such as aluminum nitride and silicon nitride are known to have excellent insulating properties and high thermal conductivity. Therefore, even though the mounting substrate 7 of semiconductor device A10 has a multilayer structure, unintended short circuits between layers can be suppressed while efficiently transferring the heat generated by the energization of the semiconductor element 1A.

[0120] In semiconductor device A10, the mounting substrate 8 includes a conductive substrate 82. In semiconductor device A10, the conductive substrate 82 is a thick copper substrate. This configuration allows for efficient transfer of heat generated by the energization of the semiconductor element 1B.

[0121] In semiconductor device A10, the mounting surface 70a of the mounting substrate 7 and the mounting surface 80a of the mounting substrate 8 are at the same position (same height) in the thickness direction z. With this configuration, the positions of semiconductor element 1A and semiconductor element 1B can be made approximately the same in the thickness direction z.

[0122] Other embodiments and modifications of the semiconductor device of the present disclosure are described below. The configurations of the parts in each embodiment and each modification are interchangeable to the extent that no technical inconsistencies arise.

[0123] Figure 22 shows a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: it differs in that it has one fuse unit 22.

[0124] In semiconductor device A11, the second circuit 2 includes one fuse section 22 for multiple passive elements 21. In the illustrated example, multiple passive elements 21 are electrically connected to the pattern section 7612, and one fuse section 22 is connected to it. Therefore, the current path between the pattern section 7611 and the pattern section 7613 branches to the multiple passive elements 21 and passes through one fuse section 22.

[0125] Figure 23 shows a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: it differs in that it has one passive element 21.

[0126] In semiconductor device A12, the second circuit 2 includes one passive element 21 for multiple fuse sections 22. In the illustrated example, multiple fuse sections 22 are connected to the pattern section 7612 while one passive element 21 is electrically connected to it. Therefore, the current path between the pattern section 7611 and the pattern section 7613 branches to the multiple fuse sections 22 through one passive element 21.

[0127] Figure 24 shows a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respects: it differs in that it has one passive element 21 and one fuse section 22.

[0128] In semiconductor device A13, the second circuit 2 includes one fuse section 22 for each passive element 21. In the illustrated example, one passive element 21 is electrically connected to the pattern section 7612, and one fuse section 22 is connected to it. Therefore, the current path between the pattern section 7611 and the pattern section 7613 passes through one passive element 21 and then through one fuse section 22.

[0129] The semiconductor devices A11 to A13 described above also produce the same effects as semiconductor device A10. Furthermore, as can be seen from these first to third modifications, in the semiconductor devices of this disclosure, the number of passive elements 21 and the number of fuse units 22 in the second circuit 2 are not limited to multiple to multiple, but may be one to multiple, multiple to one, one to one, etc.

[0130] In the examples shown in Figures 22 to 24, the size of the hollow section 78 (each of the two housing sections 781 and 782) is configured to be the same as that of the semiconductor device A10. However, the size may be made smaller or larger as appropriate depending on the number of passive elements 21 housed in housing section 781 and the number of fuse sections 22 housed in housing section 782.

[0131] Figure 25 shows a semiconductor device A14 according to a fourth modification of the first embodiment. The semiconductor device A14 differs from the semiconductor device A10 in the following respects: it differs in the configuration of each of the multiple fuse units 22.

[0132] In semiconductor device A14, the multiple fuse sections 22 are made of bonding ribbons. Each fuse section 22, whether made of bonding ribbons or bonding wires, may contain, for example, lead and tin (i.e., solder), but may also contain other metals such as gold, copper, or aluminum.

[0133] Figure 26 shows a semiconductor device A15 according to a fifth modification of the first embodiment. The semiconductor device A15 differs from the semiconductor device A10 in the following respects: it differs in the configuration of each of the multiple fuse units 22.

[0134] In semiconductor device A15, the multiple fuse sections 22 are composed of a part of the conductor layer 761. In other words, each fuse section 22 is a patterned wiring formed on the base layer 7211. The constituent material of each fuse section 22 is the same as the constituent material of the conductor layer 761.

[0135] The semiconductor devices A14 and A15 described above also produce the same effects as semiconductor device A10. Furthermore, as can be seen from these fourth and fifth modifications, in the semiconductor devices of this disclosure, the fuse portion 22 is not limited to a bonding wire configuration, but may be composed of a bonding ribbon, pattern wiring, or the like.

[0136] Second Embodiment: Figures 27 and 28 show a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the configuration of the hollow portion 78.

[0137] As shown in Figures 27 and 28, the hollow portion 78 of the semiconductor device A20 includes a connecting portion 783. The connecting portion 783 is connected to and links the housing portion 781 and the housing portion 782. In other words, the hollow portion 78 of the semiconductor device A20 is integrally formed with two housing portions 781 and 782, and the multiple passive elements 21 and the multiple fuse portions 22 are housed in one space (hollow portion 78).

[0138] The operation and effects of semiconductor device A20 are as follows:

[0139] Similar to semiconductor device A10, semiconductor device A20 includes a first circuit in which semiconductor elements 1A and 1B are electrically connected in series, and a second circuit 2 including a passive element 21. The first circuit 1 and the second circuit 2 are electrically connected in parallel. Therefore, similar to semiconductor device A10, semiconductor device A20 can be enhanced by adding the function of the second circuit 2 (passive element 21) to a conventional semiconductor device (for example, Patent Document 1). In addition, semiconductor device A20 has a configuration common to semiconductor device A10 and therefore achieves the same effects as semiconductor device A10.

[0140] As can be understood from semiconductor device A20, the semiconductor device of the present disclosure is not limited to a configuration in which a plurality of passive elements 21 and a plurality of fuse portions 22 are each individually housed in two partitioned hollow portions 78 (two housing portions 781, 782), but also includes a configuration in which a plurality of passive elements 21 and a plurality of fuse portions 22 are housed in a single hollow portion 78.

[0141] Figure 29 shows a semiconductor device A21 according to a modified example of the second embodiment. The semiconductor device A21 differs from the semiconductor device A10 in the configuration of the hollow portion 78.

[0142] As shown in Figure 29, the hollow portion 78 of the semiconductor device A21 includes a plurality of housing sections 781 and a plurality of housing sections 782. Each of the housing sections 781 individually houses a plurality of passive elements 21. Each of the housing sections 782 individually houses a plurality of fuse sections 22.

[0143] The semiconductor device A21 also provides the same effects as the semiconductor device A20, that is, the same effects as the semiconductor device A10. Furthermore, as can be understood from this modification, the semiconductor device of this disclosure is not limited to a configuration in which a plurality of passive elements 21 are housed in a common housing 781, but includes a configuration in which a plurality of passive elements 21 are each housed in an individual housing 781, and is not limited to a configuration in which a plurality of fuse units 22 are housed in a common housing 782, but includes a configuration in which a plurality of fuse units 22 are each housed in an individual housing 782.

[0144] Third Embodiment: Figure 30 shows a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the arrangement of the hollow portion 78. For ease of understanding, in Figure 30, the multiple semiconductor elements 1A, the signal substrate 3A, the conductive member 561, and the pattern portion 7511 (conductor layer 751 of the upper wiring portion 75) are shown with dashed lines.

[0145] As shown in Figure 30, the hollow portion 78 of the semiconductor device A30 is offset from the plurality of semiconductor elements 1A in a plan view and does not overlap with the plurality of semiconductor elements 1A. In the illustrated example, the hollow portion 78 of the semiconductor device A30 also does not overlap with the signal substrate 3A and the conductive member 561 in a plan view. Depending on the size (plan view size) of each of the plurality of passive elements 21 and each of the plurality of fuse portions 22, or the size (plan view size) of the mounting substrate 7, the hollow portion 78 (two housing portions 781, 782) may be arranged so as not to overlap with the plurality of semiconductor elements 1A.

[0146] The operation and effects of semiconductor device A30 are as follows:

[0147] Similar to semiconductor device A10, semiconductor device A30 includes a first circuit in which semiconductor elements 1A and 1B are electrically connected in series, and a second circuit 2 including a passive element 21. The first circuit 1 and the second circuit 2 are electrically connected in parallel. Therefore, similar to semiconductor device A10, semiconductor device A30 can be enhanced by adding the function of the second circuit 2 (passive element 21) to a conventional semiconductor device (for example, Patent Document 1), thereby achieving higher functionality. In addition, semiconductor device A30 has a configuration common to other semiconductor devices A10 to A21 and achieves the same effects as those semiconductor devices A10 to A21.

[0148] In semiconductor device A30, the hollow portion 78 does not overlap with the multiple semiconductor elements 1A in a plan view. In this configuration, the hollow portion 78 is not located below the multiple semiconductor elements 1A in the thickness direction z, and the substrate body 70 is located there. Therefore, when each semiconductor element 1A is energized, the heat generated from each semiconductor element 1A can be efficiently transferred to the back surface 70b via the substrate body 70. Consequently, semiconductor device A30 can improve the heat dissipation performance for each semiconductor element 1A.

[0149] Fourth Embodiment: Figure 31 shows a semiconductor device A40 according to the fourth embodiment. The semiconductor device A40 differs from the semiconductor device A10 in the following respects: Firstly, it differs in the configuration of the mounting substrate 7. Secondly, it differs in the configuration of the mounting substrate 8.

[0150] As shown in Figure 31, the mounting substrate 7 of the semiconductor device A40 includes a heat dissipation layer 79. The heat dissipation layer 79 is located below the lower substrate 72 (base layer 7211) of the substrate body 70 in the thickness direction z, and is bonded to the lower surface (surface facing downward in the thickness direction z) of the base layer 7211. The heat dissipation layer 79 contains, for example, a metal with high thermal conductivity. The heat dissipation layer 79 contains, for example, aluminum. The heat dissipation layer 79 is insulated from the wiring portion 74 by at least the base layer 7211.

[0151] As shown in Figure 31, the mounting substrate 8 of the semiconductor device A40 includes a heat dissipation layer 89. The heat dissipation layer 89 is located below the base substrate 81 in the thickness direction z and is bonded to the lower surface (the surface facing downward in the thickness direction z) of the metal layer 813. The heat dissipation layer 89 contains, for example, a metal with high thermal conductivity. The heat dissipation layer 89 contains, for example, aluminum. The heat dissipation layer 89 is insulated from the conductor substrate 82 by at least the insulating layer 811.

[0152] The operation and effects of semiconductor device A40 are as follows:

[0153] Similar to semiconductor device A10, semiconductor device A40 includes a first circuit in which semiconductor elements 1A and 1B are electrically connected in series, and a second circuit 2 including a passive element 21. The first circuit 1 and the second circuit 2 are electrically connected in parallel. Therefore, similar to semiconductor device A10, semiconductor device A40 can be enhanced by adding the function of the second circuit 2 (passive element 21) to a conventional semiconductor device (for example, Patent Document 1), thereby achieving higher functionality. In addition, semiconductor device A40 has a configuration common to the other semiconductor devices A10 to A30 and achieves the same effects as those semiconductor devices A10 to A30.

[0154] In semiconductor device A40, the mounting substrate 7 includes a heat dissipation layer 79. This configuration improves heat dissipation for each semiconductor element 1A. In addition, in semiconductor device A40, the mounting substrate 8 includes a heat dissipation layer 89. This configuration improves heat dissipation for each semiconductor element 1B.

[0155] Figure 32 shows a semiconductor device A41 according to the first modification of the fourth embodiment. The semiconductor device A41 differs from the semiconductor device A10 in the configuration of the mounting substrate 7.

[0156] In semiconductor device A41, the bottom insulating layer 721 (base layer 7211) of the lower substrate 72 of the mounting substrate 7 is made of a DBC substrate (or AMB substrate). Other insulating layers 721 of the lower substrate 72 are bonded to the upper metal layer of the base layer 7211, which is made of a DBC substrate. In addition, the conductor layer 761 (multiple pattern sections 7611 to 7613) of the lower wiring section 76 is made of the upper metal layer of the base layer 7211, which is made of a DBC substrate.

[0157] Figure 33 shows a semiconductor device A42 according to a second modification of the fourth embodiment. The semiconductor device A42 differs from the semiconductor device A41 in the following respect: the base layer 7211 of the mounting substrate 7 and the base substrate 81 of the mounting substrate 8 are made of a common DBC substrate (or AMB substrate).

[0158] In semiconductor device A42, the bottom layer (base layer 7211) of mounting substrate 7 and the bottom layer (base substrate 81) of mounting substrate 8 are integrally formed from a common DBC substrate. The upper metal layer of the DBC substrate includes the conductor layer 761 (multiple pattern sections 7611 to 7613) and the metal layer 812 of the lower wiring section 76.

[0159] Figure 34 shows a semiconductor device A43 according to a third modification of the fourth embodiment. The semiconductor device A43 differs from the semiconductor device A42 in the following respect: the mounting substrate 8 does not have a conductive substrate 82.

[0160] In semiconductor device A43, the mounting surface 80a of the mounting substrate 8 is the upper surface (the surface facing upward in the thickness direction z) of the metal layer 812 of the base substrate 81. Therefore, in semiconductor device A43, the mounting surface 80a of the mounting substrate 8 is located lower in the thickness direction z than the mounting surface 70a of the mounting substrate 7. Each back electrode 11 of the multiple semiconductor elements 1B is electrically connected to the metal layer 812 of the base substrate 81. In the illustrated example, given that the mounting surface 80a of the mounting substrate 8 is located lower in the thickness direction z than the mounting surface 70a of the mounting substrate 7, the conductive members 562 and 563 each have a larger dimension in the thickness direction z, and the multiple conductive members 55 are each bent.

[0161] Figure 35 shows a semiconductor device A44 according to a fourth modification of the fourth embodiment. The semiconductor device A44 differs from the semiconductor device A10 in the following respect: the upper substrate 71 has a plurality of insulating layers 711.

[0162] In the upper substrate 71 of the semiconductor device A44, a plurality of insulating layers 711 are stacked in the thickness direction z. Therefore, the upper substrate 71 of the semiconductor device A44 is composed of a multilayer laminated substrate. As can be understood from this configuration, in the semiconductor device of this disclosure, the upper substrate 71 is not limited to a configuration having one insulating layer 711, but may also have a configuration having a plurality of insulating layers 711 stacked on top of each other.

[0163] Each of the above semiconductor devices A41 to A44 also provides the same effects as semiconductor device A40, that is, the same effects as semiconductor device A10. Furthermore, as can be seen from this modified example, the stacked structure of the mounting substrate 7 and the structure of the mounting substrate 8 in the semiconductor device of this disclosure can be changed as appropriate.

[0164] Fifth Embodiment: Figures 36 to 39 show a semiconductor device A50 according to the fifth embodiment. The semiconductor device A50 differs from the semiconductor device A10 in its package structure. The semiconductor device A50 comprises a plurality of semiconductor elements 1A, a plurality of semiconductor elements 1B, two signal boards 3A and 3B, a plurality of power terminals 41 to 43, a plurality of signal terminals 44A, 45A, 44B, and 45B, a plurality of connecting members 51A, 52A, 51B, and 52B, a conductive member 55, a conductive member 57, a sealing member 6, a mounting board 7, and a mounting board 8.

[0165] In semiconductor device A50, as shown in Figure 36, multiple signal terminals 44A, 45A, 44B, and 45B protrude from the top surface 61 in the thickness direction z. In addition, two power terminals 43 protrude from the side surface 631, and one power terminal 41 and two power terminals 42 protrude from the side surface 632. In the illustrated example, the two power terminals 42 are arranged one on each side of one power terminal 41 in the second direction y.

[0166] The conductive member 55 is joined to each main surface electrode 12 (power pad 121) of the plurality of semiconductor elements 1A and the conductor substrate 82 of the mounting substrate 8, thereby creating electrical conductivity between them. In the illustrated example, one conductive member 55 connects each main surface electrode 12 of the plurality of semiconductor elements 1A and the conductor substrate 82, but multiple conductive members 55 may be used to individually connect each main surface electrode 12 of the plurality of semiconductor elements 1A and the conductor substrate 82.

[0167] The conductive member 57, like the conductive member 55, is a metal plate (metal clip). The conductive member 57 includes two joint portions 571 that are electrically connected to the two power terminals 42, multiple joint portions 572 that are electrically connected to each main surface electrode 12 (power pad 121) of the multiple semiconductor elements 1B, and a connecting portion 573 that connects the two joint portions 571 and the multiple joint portions 572. Through the conductive member 57, each main surface electrode 12 of the multiple semiconductor elements 1B is electrically connected to the two power terminals 42. The semiconductor device A50 includes two conductive members 564, as shown in Figure 38. As shown in Figure 39, the two conductive members 564 are interposed between the conductive member 57 (connecting portion 573) and the pattern portion 7512 of the conductor layer 751 of the upper wiring portion 75 (wiring portion 74), and are electrically connected to the conductive member 57 and the pattern portion 7512, respectively. As a result, the two power terminals 42 are electrically connected to the pattern portion 7512 via the conductive members 57 and 564.

[0168] Power terminal 41 is electrically connected to the pattern portion 7511 of the upper wiring portion 75 (wiring portion 74) of the mounting substrate 7, and is electrically connected to each back electrode 11 of the plurality of semiconductor elements 1A via the pattern portion 7511. Two power terminals 42 are electrically connected to each main surface electrode 12 (power pad 121) of the plurality of semiconductor elements 1B via the conductive member 57. Power terminal 43 is electrically connected to the conductor substrate 82 of the mounting substrate 8, and is electrically connected to each back electrode 11 of the plurality of semiconductor elements 1B via the conductor substrate 82. Each main surface electrode 12 (power pad 121) of the plurality of semiconductor elements 1A and each back electrode 11 of the plurality of semiconductor elements 1B are electrically connected via the conductive member 55 and the conductor substrate 82.

[0169] In the semiconductor device A50, the mounting substrate 7 also includes a substrate body 70 and a hollow portion 78. The substrate body 70 is made of a multilayer laminated substrate. In the illustrated example, the mounting substrate 7 of the semiconductor device A50 has an upper substrate 71 and a lower substrate 72 arranged on a DBC substrate (or AMB substrate) common to the mounting substrate 8. As shown in Figure 39, the hollow portion 78 includes a housing portion 781 for housing a plurality of passive elements 21 and a housing portion 782 for housing a plurality of fuse portions 22. As can be understood from Figures 36 to 39, the electrical connection between the first circuit 1 and the second circuit 2, and the configuration of the mounting substrate 7 and the mounting substrate 8 are configured in the same way as in the other embodiments described above.

[0170] The operation and effects of semiconductor device A50 are as follows:

[0171] Similar to semiconductor device A10, semiconductor device A50 includes a first circuit in which semiconductor elements 1A and 1B are electrically connected in series, and a second circuit 2 including a passive element 21. The first circuit 1 and the second circuit 2 are electrically connected in parallel. Therefore, similar to semiconductor device A10, semiconductor device A50 can be enhanced by adding the function of the second circuit 2 (passive element 21) to a conventional semiconductor device (for example, Patent Document 1), thereby achieving higher functionality. In addition, semiconductor device A50 has a configuration common to other semiconductor devices A10 to A44, and thus achieves the same effects as semiconductor devices A10 to A44.

[0172] As can be understood from semiconductor device A50, the package structure of the semiconductor device of this disclosure is not limited in any way.

[0173] In the first to fifth embodiments described above (including their variations), the second circuit 2 is shown to include at least one passive element 21 and at least one fuse section 22. In configurations different from this example, the second circuit 2 may include at least one passive element 21 but not the fuse section 22. Figure 40 shows a semiconductor device according to such a variation. In the mounting substrate 7 of the semiconductor device shown in Figure 40, the hollow section 78 includes a housing section 781 but does not include a housing section 782. Each of the multiple passive elements 21 is electrically connected to a pattern section 7611 and a pattern section 7613. Thus, in the semiconductor device of this disclosure, the second circuit 2 may include passive elements 21 but not the fuse section 22.

[0174] In the first to fifth embodiments described above (including their variations), an example was shown in which the fuse portion 22 is housed in the housing portion 782 of the hollow portion 78. Unlike this example, the fuse portion 22 may be placed on the mounting substrate 7. That is, the passive element 21 may be housed in the hollow portion 78 of the mounting substrate 7, and the fuse portion 22 may be placed on the mounting substrate 7.

[0175] In the first to fifth embodiments described above (including their variations), an example was shown in which a gas is sealed in the hollow portion 78 of the mounting substrate 7. In a configuration different from this example, an encapsulating material may be sealed in the hollow portion 78 of the mounting substrate 7. Figure 41 shows a semiconductor device according to such a variation. The semiconductor device shown in Figure 41 includes an encapsulating material 69 sealed in the hollow portion 78 of the mounting substrate 7. The encapsulating material 69 is, for example, gel-like (a substance intermediate between solid and liquid) and is softer than the sealing member 6. The constituent materials of the encapsulating material 69 include, but are not limited to, silicone (organosilicon compounds). The encapsulating material 69 is, for example, silicone gel. In the semiconductor device shown in Figure 41, a plurality of passive elements 21 are covered with the encapsulating material 69 within the housing portion 781, and a plurality of fuse portions 22 are covered with the encapsulating material 69 within the housing portion 782.

[0176] The semiconductor device relating to this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device relating to this disclosure can be modified in various ways. For example, this disclosure includes the embodiments described in the following appendix. Appendix 1. The first circuit (1) includes a first semiconductor element (1A) and a second semiconductor element (1B), the first semiconductor element (1A) and the second semiconductor element (1B) being electrically connected in series; a first mounting substrate (7) having a first mounting surface (70a) on which the first semiconductor element (1A) is mounted; a second mounting substrate (8) having a second mounting surface (80a) on which the second semiconductor element (1B) is mounted; and a second circuit (2) including a passive element (21), wherein the first mounting substrate (7) includes a substrate body (70) having a wiring portion (74) and a hollow portion (78) surrounded by the substrate body (70) when viewed in the thickness direction (z) of the first mounting substrate (7), and the hollow portion (78) includes a first housing portion (781) in which the passive element (21) is housed. The second circuit (2) is electrically connected in parallel to the first circuit (1) by the wiring section (74), and is a semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50). Note 2. The second circuit (2) is a semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) as described in Note 1, which includes a fuse section (22) connected in series with the passive element (21). Note 3. The hollow section (78) is a semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) as described in Note 2, which includes a second housing section (782) that houses the fuse section (22). Note 4. The semiconductor device (A20) according to Appendix 3, wherein the hollow portion (78) includes a connecting portion (783) that connects the first housing portion (781) and the second housing portion (782). Appendix 5. The semiconductor device (A10 to A14, A20, A21, A30, A40 to A44, A50) according to any one of Appendix 2 to 4, wherein the fuse portion (22) includes a bonding wire or a bonding ribbon. Appendix 5-1. The semiconductor device (A15) according to any one of Appendix 2 to 4, wherein the fuse portion (22) is composed of the pattern of the wiring portion (74).Note 6. The semiconductor device (A10, A12, A14, A15, A20, A21, A30, A40-A44, A50) according to any one of Notes 2 to 5, wherein the second circuit (2) includes at least one additional fuse section (22), thereby including a plurality of fuse sections (22). Note 7. The semiconductor device (A10, A11, A14, A15, A20, A21, A30, A40-A44, A50) according to any one of Notes 1 to 6, wherein the second circuit (2) includes at least one additional passive element (21), thereby including a plurality of passive elements (21). Note 8. The semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) according to any one of Notes 1 to 7, wherein the passive element (21) is a capacitor. Note 9. A semiconductor device according to any one of Appendix 1 to 8 (A10 to A15, A20, A21, A30, A40 to A44, A50), wherein the hollow portion (78) is filled with gas, and the passive element (21) is covered with the gas. Appendix 10. A semiconductor device according to any one of Appendix 1 to 8, further comprising a gel-like encapsulating material (69) enclosed in the hollow portion (78), and the passive element (21) being covered with the encapsulating material (69). Appendix 10-1. A semiconductor device according to Appendix 10, further comprising a sealing member (6) covering the first circuit (1), at least a part of the first mounting substrate (7), and at least a part of the second mounting substrate (8), wherein the material of the encapsulating material (69) is different from the material of the sealing member (6). Appendix 11. The substrate body (70) is a semiconductor device according to any one of Appendix 1 to Appendix 10, including a multilayer laminated substrate (A10 to A15, A20, A21, A30, A40 to A44, A50). Appendix 12. The substrate body (70) has a plurality of ceramic substrates, and the plurality of ceramic substrates are stacked in the thickness direction (z), according to Appendix 11 (A10 to A15, A20, A21, A30, A40 to A44, A50). Appendix 12-1. Each of the plurality of ceramic substrates contains aluminum nitride, according to Appendix 12 (A10 to A15, A20, A21, A30, A40 to A44, A50).Note 13. The semiconductor device according to Note 11 or Note 12 (A10 to A15, A20, A21, A30, A40 to A44, A50), further comprising a first power terminal (41), wherein the substrate body (70) includes a first substrate (71) and a second substrate (72) stacked in the thickness direction (z), and the first semiconductor element (1A) is bonded to the first substrate (71) and electrically connected to the first power terminal (41) via the first substrate (71). Note 14. The wiring section (74) includes a first wiring section (74) arranged on the first substrate (71) and a second wiring section (74) arranged on the second substrate (72), and the second circuit (2) is electrically connected to the second wiring section (74), as described in Appendix 13 (A10 to A15, A20, A21, A30, A40 to A44, A50). Appendix 15. The first wiring section (74) includes a first through-conductor (752) that penetrates at least a portion of the first substrate (71) in the thickness direction (z), and the second wiring section (74) includes a second through-conductor (762) that penetrates at least a portion of the second substrate (72) in the thickness direction (z), and the first through-conductor (752) and the second through-conductor (762) overlap each other when viewed in the thickness direction (z) and are electrically conductive with each other, as described in Appendix 14 (A10 to A15, A20, A21, A30, A40 to A44, A50). Appendix 16. The semiconductor device (A10 to A15, A20, A21, A30, A40 to A44) according to Appendix 15, further comprising: a second power terminal (42) electrically connected to the second semiconductor element (1B); and a block-shaped conductive member (564) joined to the first mounting surface (70a) of the first mounting substrate (7), wherein the conductive member (564) is electrically connected to the second circuit (2) via the first through conductor (752) and the second through conductor (762); and the second power terminal (42) is electrically joined to the conductive member (564). Appendix 17. The semiconductor device (A10 to A15, A20, A21, A30, A40 to A42, A44, A50) according to any one of Appendix 1 to 16, wherein the second mounting substrate (8) includes a metal conductive substrate (82).Note 17-1. The dimension of the first mounting substrate (7) in the thickness direction (z) and the dimension of the second mounting substrate (8) in the thickness direction (z) are the same, as described in Note 17 (A10 to A15, A20, A21, A30, A40 to A42, A44, A50). Note 17-2. The first mounting surface (70a) and the second mounting surface (80a) are the same height in the thickness direction (z), as described in Note 17 or Note 17-1 (A10 to A15, A20, A21, A30, A40 to A42, A44, A50). Note 17-3. The conductive substrate is a semiconductor device (A10 to A15, A20, A21, A30, A40 to A42, A44, A50) as described in Appendix 17 to Appendix 17-2, which contains copper. Appendix 18. The semiconductor device (A30) as described in any of Appendix 1 to Appendix 17, wherein, when viewed in the thickness direction (z), the hollow portion (78) does not overlap with the first semiconductor element (1A). Appendix 19. The semiconductor device (A10 to A15, A20, A21, A30, A40 to A44, A50) as described in any of Appendix 1 to Appendix 18, which further comprises a sealing member (6) that covers the first circuit (1), at least a part of the first mounting substrate (7), and at least a part of the second mounting substrate (8). Appendix 20. Each of the first semiconductor element (1A) and the second semiconductor element (1B) is a switching element, and the first circuit (1) is a half-bridge circuit, the semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) as described in any of Appendix 1 to Appendix 19. Appendix 21. A vehicle (F1) comprising the semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) as described in any of Appendix 1 to Appendix 19, and a drive source (F132), wherein the semiconductor device (A10-A15, A20, A21, A30, A40-A44, A50) is electrically connected to the drive source.

[0177] A10-A15, A20, A21, A30, A40-A44, A50: Semiconductor device, 1: First circuit, 1A, 1B: Semiconductor element, 101: Main surface of element, 102: Back surface of element, 11: Back surface electrode, 11B: Semiconductor element, 12, 13: Main surface electrode, 121: Power pad, 122: Signal pad, 14: Insulating film, 19: Bonding layer, 2: Second circuit, 21: Passive element, 22: Fuse section, 29: Bonding layer, 3A, 3B: Signal substrate, 31: Insulating layer, 32, 33: Metal layer, 321A, 322A, 321B, 322B: Wiring section, 39: Adhesive layer, 41-43: Power terminals, 411, 421, 431: Inner section, 412, 422, 432: Terminal section, 419, 429, 439: Bonding layer, 421a: Connecting section, 421b: Extension section, 421c: Connection section, 44A-47A, 44B-47B: Signal terminals, 441, 451, 461, 471: Inner section, 442, 452, 462, 472: Terminal section, 51A-54A, 51B-54B: Connecting member, 55: Conductive member, 559: Bonding layer, 561-564: Conductive member, 569: Connection 57: Conductive member, 571, 572: Joint, 573: Connecting part, 6: Sealing member, 61: Top surface, 62: Bottom surface, 631-634: Side surface, 65: Recess, 69: Encapsulating material, 7: Mounting substrate, 70: Substrate body, 70a: Mounting surface, 70b: Back surface, 71: Upper substrate, 711: Insulating layer, 72: Lower substrate, 721: Insulating layer, 7211: Base layer, 74: Wiring section, 75: Upper wiring section, 751: Conductor layer, 7511, 7512, 7513: Pattern section, 752: Through conductor, 7521, 7522: Through section, 76: F1: Lower wiring section, 761: Conductor layer, 7611, 7612, 7613: Pattern section, 762: Through conductor, 7621, 7622: Through section, 78: Hollow section, 781, 782: Housing section, 783: Connecting section, 79: Heat dissipation layer, 8: Mounting substrate, 80a: Mounting surface, 80b: Back surface, 81: Base substrate, 811: Insulating layer, 812, 813: Metal layer, 82: Conductor substrate, 89: Heat dissipation layer, 829: Bonding layer, F1: Vehicle, F11: Onboard charger, F12: Storage battery, F13: Drive system, F131: Inverter, F132: Drive source

Claims

1. A semiconductor device comprising: a first circuit including a first semiconductor element and a second semiconductor element, wherein the first semiconductor element and the second semiconductor element are electrically connected in series; a first mounting substrate having a first mounting surface on which the first semiconductor element is mounted; a second mounting substrate having a second mounting surface on which the second semiconductor element is mounted; and a second circuit including a passive element, wherein the first mounting substrate includes a substrate body having a wiring portion and a hollow portion surrounded by the substrate body when viewed in the thickness direction of the first mounting substrate, the hollow portion includes a first housing portion in which the passive element is housed, and the second circuit is electrically connected in parallel to the first circuit by the wiring portion.

2. The semiconductor device according to claim 1, wherein the second circuit includes a fuse connected in series with the passive element.

3. The semiconductor device according to claim 2, wherein the hollow portion includes a second housing portion for housing the fuse portion.

4. The semiconductor device according to claim 3, wherein the hollow portion includes a connecting portion that connects the first housing portion and the second housing portion.

5. The semiconductor device according to any one of claims 2 to 4, wherein the fuse portion includes a bonding wire or a bonding ribbon.

6. The semiconductor device according to any one of claims 2 to 5, wherein the second circuit includes at least one additional fuse section, thereby including a plurality of fuse sections.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second circuit includes at least one additional passive element, thereby including a plurality of passive elements.

8. The semiconductor device according to any one of claims 1 to 7, wherein the passive element is a capacitor.

9. The semiconductor device according to any one of claims 1 to 8, wherein a gas is sealed in the hollow portion, and the passive element is covered with the gas.

10. The semiconductor device according to any one of claims 1 to 8, further comprising a gel-like encapsulating material sealed in the hollow portion, wherein the passive element is covered by the encapsulating material.

11. The semiconductor device according to any one of claims 1 to 10, wherein the substrate body includes a multilayer laminated substrate.

12. The semiconductor device according to claim 11, wherein the substrate body has a plurality of ceramic substrates, and the plurality of ceramic substrates are stacked in the thickness direction.

13. The semiconductor device according to claim 11 or claim 12, further comprising a first power terminal, wherein the substrate body includes a first substrate and a second substrate stacked in the thickness direction, and the first semiconductor element is bonded to the first substrate and electrically connected to the first power terminal via the first substrate.

14. The semiconductor device according to claim 13, wherein the wiring portion includes a first wiring portion disposed on the first substrate and a second wiring portion disposed on the second substrate, and the second circuit is electrically connected to the second wiring portion.

15. The semiconductor device according to claim 14, wherein the first wiring portion includes a first through conductor that penetrates at least a portion of the first substrate in the thickness direction, the second wiring portion includes a second through conductor that penetrates at least a portion of the second substrate in the thickness direction, and the first through conductor and the second through conductor overlap each other in the thickness direction and are electrically conductive to each other.

16. The semiconductor device according to claim 15, further comprising: a second power terminal electrically connected to the second semiconductor element; and a block-shaped conductive member bonded to the first mounting surface of the first mounting substrate, wherein the conductive member is electrically connected to the second circuit via the first through conductor and the second through conductor, and the second power terminal is electrically connected to the conductive member.

17. The semiconductor device according to any one of claims 1 to 16, wherein the second mounting substrate includes a metal conductive substrate.

18. The semiconductor device according to any one of claims 1 to 17, wherein, when viewed in the thickness direction, the hollow portion does not overlap with the first semiconductor element.

Images