Photodetection element

Abstract

Provided is a photodetection element comprising: a photoelectric conversion unit that is provided within a semiconductor substrate; a charge storage unit that stores a charge generated by the photoelectric conversion unit; and a vertical transfer gate electrode that is provided so as to extend toward the photoelectric conversion unit from a second surface of the semiconductor substrate, the second surface being located on the side reverse of a first surface serving as a light incidence surface, and that transfers the charge to the charge storage unit, wherein one of the side surfaces of the vertical transfer gate electrode is formed along the (111) crystal plane of the semiconductor substrate.

Description

Photodetector

[0001] This disclosure relates to a photodetector.

[0002] The photodetector has multiple photodetectors (pixels) arranged in a two-dimensional matrix on a semiconductor substrate, along the row and column directions. Each photodetector generates an electric charge in response to incident light, and the photodetector can detect light or obtain images by acquiring the generated charge as a pixel signal.

[0003] As described in Patent Document 1 below, in a photodetector element of a CMOS (Complementary Metal-Oxide-Semiconductor) type imaging device (CMOS image sensor), which is an example of a photodetector, a photoelectric conversion unit is provided in a deep region of the semiconductor substrate to perform photoelectric conversion using light incident on the semiconductor substrate and generate an electric charge. Furthermore, in the above imaging device, a transfer gate electrode is provided to transfer the charge generated in the photoelectric conversion unit to a charge storage unit that stores the charge. Moreover, the transfer gate electrode has a vertical gate structure that extends from the surface of the semiconductor substrate into the semiconductor substrate in the direction of the semiconductor substrate's film thickness in order to induce charge from the photoelectric conversion unit located in a deep region of the semiconductor substrate. By having such a vertical gate structure, the transfer gate electrode can modulate the electric field to the deep region of the semiconductor substrate and guide the charge from the photoelectric conversion unit to the charge storage unit.

[0004] Japanese Patent Publication No. 2010-114273

[0005] When forming a transfer gate electrode with a vertical gate structure, dangling bonds may form in the semiconductor substrate near the transfer gate electrode, which can degrade the quality of detection results by the photodetector (specifically, if the photodetector is an imaging device, the image quality may deteriorate). Also, because the photodetector elements (pixels) are very small, if any of the components are misaligned from their desired positions during the fabrication of the photodetector elements, the characteristics of the photodetector elements can change significantly, which can degrade the quality of detection results by the photodetector.

[0006] Therefore, this disclosure proposes a photodetector element that can avoid a decrease in the quality of detection results by a photodetector.

[0007] According to this disclosure, a photodetector is provided, comprising a photoelectric conversion unit provided in a semiconductor substrate, a charge storage unit for storing charge generated in the photoelectric conversion unit, and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate that is the light incident surface, and transferring the charge to the charge storage unit, wherein one of the sides of the vertical transfer gate electrode is formed along the (111) crystal plane of the semiconductor substrate.

[0008] Furthermore, according to this disclosure, a photodetector is provided comprising: a photoelectric conversion unit provided in a semiconductor substrate; a charge storage unit for storing charge generated in the photoelectric conversion unit; and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate that serves as the light incident surface, and transferring the charge to the charge storage unit, wherein the vertical transfer gate electrode has a tapered shape that decreases in diameter toward the photoelectric conversion unit from the second surface.

[0009] This is an explanatory diagram showing a planar configuration example of the imaging device 10 according to an embodiment of this disclosure. This is an explanatory diagram showing a cross-sectional configuration example of a pixel 100a according to a comparative example. This is an explanatory diagram showing a configuration example of a pixel 100 according to the first embodiment of this disclosure. This is an explanatory diagram showing a planar configuration example of a pixel 100 according to the first embodiment of this disclosure. This is an explanatory diagram showing a planar configuration example of a pixel array 30 according to the first embodiment of this disclosure. This is a cross-sectional view (1) for explaining the manufacturing method of the pixel 100 according to the first embodiment of this disclosure. This is a cross-sectional view (2) for explaining the manufacturing method of the pixel 100 according to the first embodiment of this disclosure. This is a cross-sectional view (3) for explaining the manufacturing method of the pixel 100 according to the first embodiment of this disclosure. This is an explanatory diagram (1) showing a configuration example of a pixel 100 according to the second embodiment of this disclosure. This is an explanatory diagram (2) showing a configuration example of a pixel 100 according to the second embodiment of this disclosure. This is an explanatory diagram (3) showing a configuration example of a pixel 100 according to the second embodiment of this disclosure. This is an explanatory diagram (4) showing a configuration example of a pixel 100 according to the second embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the third embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the third embodiment of this disclosure. This is an explanatory diagram (part 3) showing an example configuration of a pixel 100 according to the third embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 3) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 4) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 5) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 6) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 7) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 8) showing an example configuration of a pixel 100 according to the fourth embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the fifth embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the fifth embodiment of this disclosure. This is an explanatory diagram (part 3) showing an example configuration of a pixel 100 according to the fifth embodiment of this disclosure.This is an explanatory diagram (part 4) showing an example configuration of a pixel 100 according to the fifth embodiment of this disclosure. This is an explanatory diagram showing an example configuration of a pixel 100 according to the sixth embodiment of this disclosure. This is an explanatory diagram showing an example configuration of a pixel 100 according to the seventh embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the eighth embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the eighth embodiment of this disclosure. This is an explanatory diagram (part 3) showing an example configuration of a pixel 100 according to the eighth embodiment of this disclosure. This is an explanatory diagram (part 4) showing an example configuration of a pixel 100 according to the eighth embodiment of this disclosure. This is an explanatory diagram (part 5) showing an example configuration of a pixel 100 according to the eighth embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the ninth embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the ninth embodiment of this disclosure. This is an explanatory diagram (part 3) showing an example configuration of a pixel 100 according to the ninth embodiment of this disclosure. This is an explanatory diagram (part 4) showing an example configuration of a pixel 100 according to the ninth embodiment of this disclosure. This is an explanatory diagram (part 1) showing an example configuration of a pixel 100 according to the tenth embodiment of this disclosure. This is an explanatory diagram (part 2) showing an example configuration of a pixel 100 according to the tenth embodiment of this disclosure. This is an explanatory diagram showing an example of a cross-sectional configuration of a pixel 100a and its surroundings according to a comparative example. This is an explanatory diagram showing an example of a cross-sectional configuration of a pixel 100 and its surroundings according to the eleventh embodiment of this disclosure. This is an explanatory diagram showing an example of a cross-sectional configuration of a pixel 100 and its surroundings according to a modified example of the eleventh embodiment of this disclosure. This is a cross-sectional diagram for explaining a method for manufacturing a pixel 100 according to the eleventh embodiment of this disclosure. This is an explanatory diagram (part 1) for explaining a method for manufacturing a pixel 100 according to a modified example of the eleventh embodiment of this disclosure. This is an explanatory diagram (part 2) for explaining a method for manufacturing a pixel 100 according to a modified example of the eleventh embodiment of this disclosure. This is a block diagram showing an example of a schematic functional configuration of a smartphone. This is a block diagram showing an example of a schematic configuration of a vehicle control system. This is an explanatory diagram showing an example of the installation position of an external information detection unit and an imaging unit.

[0010] Preferred embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configuration will be denoted by the same reference numeral to avoid redundant explanation. In addition, in this specification and drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding a different alphabet after the same reference numeral. However, if there is no particular need to distinguish each of multiple components having substantially the same or similar functional configurations, only the same reference numeral will be used.

[0011] Furthermore, the drawings referenced in the following description are intended to illustrate and facilitate understanding of one embodiment of this disclosure, and for the sake of clarity, the shapes, dimensions, ratios, etc. shown in the drawings may differ from those of the actual product. In addition, the apparatus shown in the drawings may be modified in design as appropriate, taking into consideration the following description and known technology.

[0012] The descriptions of specific shapes in the following explanation do not refer only to geometrically defined shapes. More specifically, the descriptions of specific shapes in the following explanation include shapes that have acceptable differences (errors and distortions) in the photodetector and photodetector elements, their manufacturing processes, and their use and operation, as well as shapes that are similar to those shapes. For example, when the following explanation uses the expression "approximately right-angled triangle," it does not mean that it is limited to a geometrically defined "right-angled triangle," but also includes shapes similar to a right-angled triangle, such as triangles with angles close to 90 degrees, or right-angled triangles with rounded corners.

[0013] Furthermore, in the following explanation, "sharing" means that different elements (e.g., pixels) share one other element (e.g., a charge storage unit).

[0014] The explanation will proceed in the following order: 1. Outline configuration of the imaging device 1.1 Imaging device 1.2 Pixels 2. Background 3. First embodiment 3.1 Detailed configuration 3.2 Manufacturing method 4. Second embodiment 5. Third embodiment 6. Fourth embodiment 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Eighth embodiment 11. Ninth embodiment 12. Tenth embodiment 13. Eleventh embodiment 13.1 Background 13.2 Detailed configuration 13.3 Modification 13.4 Manufacturing method 14. Summary 15. Application examples 15.1 Application example to smartphones 15.2 Application example to mobile devices 16. Supplementary information

[0015] <<1. Outline Configuration of the Imaging Device>> <1.1 Imaging Device> First, with reference to Figure 1, the outline configuration of the imaging device 10 (an example of a photodetector) according to the embodiment of this disclosure will be described. Figure 1 is an explanatory diagram showing an example of the planar configuration of the imaging device 10 according to the embodiment of this disclosure. As shown in Figure 1, the imaging device 10 according to the embodiment of this disclosure has a pixel array section 30 in which a plurality of pixels (photodetectors) 100 are arranged in a matrix-like manner along the row and column directions on a semiconductor substrate 300 made of, for example, Si (silicon). The imaging device 10 also has a peripheral circuit section provided on the semiconductor substrate 300 so as to surround the pixel array section 30. Furthermore, the imaging device 10 includes a vertical drive circuit section 32, a column signal processing circuit section 34, a horizontal drive circuit section 36, an output circuit section 38, a control circuit section 40, etc. as the peripheral circuit section. The details of each block of the imaging device 10 will be described below.

[0016] (Pixel Array Section 30) The pixel array section 30 has a plurality of pixels 100 arranged in a matrix on a semiconductor substrate 300 in a two-dimensional manner along the row and column directions. Each pixel (photodetector) 100 performs photoelectric conversion on incident light and generates an electric charge, thereby detecting light as a pixel signal. The pixel 100 has a photoelectric conversion section 310 (see Figure 2) and a plurality of pixel transistors (for example, MOS (Metal-Oxide-Semiconductor) transistors) (not shown). The pixel transistors include, for example, four MOS transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor. The detailed structure of the pixel 100 will be described later.

[0017] (Vertical drive circuit section 32) The vertical drive circuit section 32 is formed, for example, by a shift register, and selects a pixel drive wiring 42, supplies pulses to the selected pixel drive wiring 42 to drive the pixels 100, and drives the pixels 100 row by row. That is, the vertical drive circuit section 32 sequentially selects and scans each pixel 100 of the pixel array section 30 in the vertical direction (up and down direction in Figure 1) row by row, and supplies a pixel signal based on the signal charge generated according to the amount of light received by the photoelectric conversion section (not shown) of each pixel 100 to the column signal processing circuit section 34, which will be described later, through the vertical signal line 44.

[0018] (Column signal processing circuit 34) The column signal processing circuit 34 is arranged for each column of pixels 100 and performs signal processing such as noise reduction on each pixel column for the pixel signal output from one row of pixels 100. For example, the column signal processing circuit 34 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove pixel-specific fixed pattern noise.

[0019] (Horizontal drive circuit section 36) The horizontal drive circuit section 36 is formed by, for example, a shift register and sequentially outputs horizontal scanning pulses to sequentially select each of the column signal processing circuit sections 34 described above, and to output pixel signals from each of the column signal processing circuit sections 34 to the horizontal signal line 46.

[0020] (Output circuit section 38) The output circuit section 38 processes the pixel signals that are sequentially supplied from each of the column signal processing circuit sections 34 described above through the horizontal signal line 46 and outputs them. The output circuit section 38 may function as a buffering function, or it may perform processing such as black level adjustment, column variation correction, and various digital signal processing. Buffering refers to temporarily storing pixel signals to compensate for differences in processing speed or transfer speed during the exchange of pixel signals. Furthermore, the input / output terminal 48 is a terminal for exchanging signals with an external device.

[0021] (Control circuit unit 40) The control circuit unit 40 receives the input clock and data that commands the operating mode, etc., and outputs data such as internal information of the imaging device 10. Specifically, the control circuit unit 40 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit unit 32, the column signal processing circuit unit 34, and the horizontal drive circuit unit 36, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. The control circuit unit 40 then outputs the generated clock signals and control signals to the vertical drive circuit unit 32, the column signal processing circuit unit 34, and the horizontal drive circuit unit 36, etc.

[0022] In the embodiments of this disclosure, the configuration of the imaging device 10 is not limited to the configuration shown in Figure 1.

[0023] <1.2 Pixels> Next, with reference to Figure 2, the configuration of a pixel (photodetector) 100a according to a comparative example that the present inventors had been studying before creating the embodiments of the present disclosure will be described. Figure 2 is an explanatory diagram showing an example of the cross-sectional configuration of a pixel 100a according to a comparative example, and in detail shows a cross-section when the pixel 100a is cut along the film thickness direction of the semiconductor substrate 300.

[0024] As explained earlier, the imaging device 10 and the like have a pixel array section 30 in which pixels 100a are regularly arranged in two dimensions on a semiconductor substrate 300. As shown in Figure 2, the pixels 100a in the comparative example are provided within a pixel region in the semiconductor substrate 300 surrounded by a pixel isolation wall 320. The pixel isolation wall 320 consists of, for example, a trench provided as a through-DTI (Deep Trench Isolation) that penetrates the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300, and a material consisting of an oxide film or a metal film embedded in the trench.

[0025] As shown in Figure 2, the pixel 100a has a photoelectric conversion unit (PD (Photodiode)) 310 that converts light (incident light) incident from the back surface (first surface) 300b of the semiconductor substrate 300 into photoelectric energy to generate charge. The pixel 100a also mainly has a charge storage unit (FD (Floating Diffusion)) 330 that stores the charge generated in the photoelectric conversion unit 310, and a transfer gate electrode 360 ​​that transfers charge from the photoelectric conversion unit 310 to the charge storage unit 330. Furthermore, the pixel 100a has a diffusion region 380 that functions as a contact to which a reference potential (for example, ground potential) is applied.

[0026] Furthermore, in the comparative example, as explained earlier, the transfer gate electrode 360 ​​has an electrode portion 360h provided on the surface 300a of the semiconductor substrate 300, as well as a vertical gate electrode portion (VG (Vertical Gate)) 360i that extends from the surface 300a side into the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300. By driving the transfer gate electrode 360, the electric field can be modulated to deep regions within the semiconductor substrate 300 by the vertical gate electrode portion 360i, thereby forming a charge transfer channel. The charge is then transferred from the photoelectric conversion unit 310 to the charge storage unit 330 via this transfer channel. In the comparative example, such a vertical gate electrode portion 360i allows the electric field to be modulated to deep regions within the semiconductor substrate 300, and the charge can be efficiently guided to the charge storage unit 330.

[0027] <<2. Background>> Next, the background to the present inventors' creation of the embodiments of this disclosure will be explained. As explained above, the transfer gate electrode 360 ​​of the pixel 100a according to the comparative example has a vertical gate electrode portion 360i that extends from the surface 300a side of the semiconductor substrate 300 into the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300.

[0028] Such a vertical gate electrode portion 360i is fabricated by forming a trench in a semiconductor substrate 300 made of, for example, Si, and embedding an insulating film and an electrode film in the trench. However, when forming such a vertical gate electrode portion 360i, dangling bonds may occur on the surface of the trench. Dangling bonds are unbonded bonds resulting from atoms constituting the crystal structure of the semiconductor substrate 300 not being bonded to other atoms. As a result of such dangling bonds, defect levels are generated near the vertical gate electrode portion 360i, and when the transfer gate electrode 360 ​​is driven, leakage current may occur due to these defect levels. This leakage current appears as unintended white spots in the image acquired by the imaging device 10, thus adversely affecting the quality of the image obtained by the imaging device 10.

[0029] Therefore, in light of this situation, the present inventors have diligently studied the pixels 100 in order to suppress the deterioration of image quality obtained by the imaging device 10, and have come up with the embodiments of the present disclosure described below. For example, in a (100) semiconductor substrate 300 made of Si or the like, the interface of the (111) plane can be selectively obtained by using wet etching with an alkaline solution. Therefore, the present inventors conceived of selectively forming trenches in which the (111) crystal plane is exposed by using the above-described crystal anisotropy etching when fabricating the vertical gate electrode portion 360i. Then, the present inventors have come up with an embodiment of the present disclosure in which, by applying the trenches in which the (111) crystal plane is exposed to the transfer gate electrode 360, the generation of leakage current caused by defect levels is suppressed by the exposure of various crystal planes, and a deterioration of image quality can be avoided.

[0030] In other words, in the embodiments of this disclosure, a vertical gate electrode portion 360i is formed by selectively forming trenches with exposed (111) crystal planes using crystal anisotropic etching with an alkaline solution, and then embedding an insulating film and an electrode film in the trenches.

[0031] The present inventors will now describe in detail the embodiments of this disclosure they have created.

[0032] <<3. First Embodiment>> <3.1 Detailed Configuration> First, with reference to Figure 3A, the detailed configuration of the pixel (photodetector) 100 according to the first embodiment of this disclosure will be described. Figure 3A is an explanatory diagram showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figure 3A shows a plan view of the pixel 100 as seen from above the surface 300a side of the semiconductor substrate 300 (plan view), and the lower part of Figure 3A shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figure 3A in the direction of the film thickness of the semiconductor substrate 300.

[0033] In this embodiment, the pixel transistors, such as transfer transistors, selection transistors, reset transistors, and amplification transistors mentioned above, are provided on another substrate (not shown) stacked on top of the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0034] As shown in Figure 3A, the pixels 100 are provided within a pixel region divided, for example, into a rectangular shape by a pixel separation wall 320. The pixel separation wall 320 is, for example, a through-DTI, a trench (not shown) provided to penetrate the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300, and SiO embedded in the trench. ２It consists of an oxide film such as silicon oxide, and a metal film such as poly-Si (polysilicon) or W (tungsten). In this embodiment, the trench is not limited to penetrating the entire semiconductor substrate 300, but may penetrate only a part of the semiconductor substrate 300. Furthermore, the pixel separation wall 320 may be covered with a material containing at least one of Si, N (nitrogen), O (oxygen), In (indium), Ti (titanium), Sn (tin), Ga (gallium), Al (aluminum), Ta (tantalum), Hf (hafnium), Mg (magnesium), Sc (scandium), Zr (zirconium), La (lanthanum), Gd (gadolinium), and Y (yttrium).

[0035] The semiconductor substrate 300 is a single crystal substrate of, for example, a second conductivity type (e.g., P-type) having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. The semiconductor substrate 300 is made of a material containing at least one of Si, Ge (germanium), Sn, C (carbon), B (boron), Al, Ga, In, N, P (phosphorus), As (arsenic), and Sb (antimony). Specifically, the semiconductor substrate 300 is made of, for example, a Si substrate.

[0036] Furthermore, as shown in the lower part of Figure 3A, the pixel 100 is provided in a semiconductor substrate 300 of, for example, a second conductivity type (e.g., type P), and has a photoelectric conversion unit 310 having an impurity of a first conductivity type (e.g., type N) (first impurity). The photoelectric conversion unit 310 can absorb incident light and generate an electric charge.

[0037] Furthermore, the charge generated in the photoelectric conversion unit 310 is transferred to the charge accumulation unit (FD) 330 by the transfer gate electrode (VG) 360 provided on the side of the front surface 300a (second surface) located on the opposite side of the back surface (first surface) 300b, which is the light incident surface of the semiconductor substrate 300. The charge accumulation unit 330 contains an impurity (first impurity) having the same first conductivity type (for example, N-type) as the photoelectric conversion unit 310 at a higher concentration than the photoelectric conversion unit 310, and is capable of accumulating the aforementioned charge. For example, the charge accumulation unit 330 is provided in the center of the pixel region as shown in the upper part of FIG. 3A, and is further provided on the front surface 300a side in the semiconductor substrate 300 as shown in the lower part of FIG. 3A.

[0038] Furthermore, around the charge accumulation unit 330, a diffusion region (first diffusion region) 340 containing an impurity (first impurity) having the first conductivity type (for example, N-type) at a lower concentration than that of the charge accumulation unit 330 is provided so as to be adjacent to the charge accumulation unit 330. As shown in the upper part of FIG. 3A, at least a part of the diffusion region 340 is provided between the transfer gate electrode 360 and the charge accumulation unit 330, and adjusts the transfer potential in the semiconductor substrate 300 so that charge transfer can be performed efficiently.

[0039] As shown in the lower part of FIG. 3A, the transfer gate electrode 360 has a vertical gate structure extending from the front surface 300a of the semiconductor substrate 300 toward the photoelectric conversion unit 310. Specifically, the transfer gate electrode 360 extends to a deeper position in the semiconductor substrate 300 than the bottom surface of the charge accumulation unit 330. Further, as shown in the upper part of FIG. 3A, the transfer gate electrode 360 is provided, for example, at a corner (first corner) of the pixel region. In addition, the transfer gate electrode 360 is made of a material containing at least one of Si, Ti, W, Ni (nickel), N, Ru (ruthenium), Cu (copper), and Co (cobalt), for example. Furthermore, between the transfer gate electrode 360 and the semiconductor substrate 300 is SiO ２ An insulating film (gate insulating film) 370 made of or the like is provided.

[0040] Further, in the present embodiment, the side surface of the transfer gate electrode 360 on the charge storage portion 330 side is formed along the (111) crystal plane of the semiconductor substrate 300. The entire transfer gate electrode 360 has, for example, a substantially triangular pyramid shape, and has a substantially right triangle shape in plan view as shown in the upper part of FIG. 3A.

[0041] In the present embodiment, by providing one side surface of the transfer gate electrode 360 along the (111) crystal plane, generation of defect levels in the vicinity of the transfer gate electrode 360 can be avoided. Therefore, according to the present embodiment, it is possible to suppress the occurrence of leakage current caused by defect levels and avoid degradation of image quality.

[0042] Note that in the present embodiment, the configuration of the pixel 100 is not limited to the configuration shown in FIG. 3A.

[0043] In addition, the pixels 100 can be arranged in the pixel array portion 30 as shown in FIGS. 3B and 3C. FIGS. 3B and 3C are explanatory diagrams showing an example of a planar configuration of the pixel 100 according to the present embodiment.

[0044] In the present embodiment, for example, four pixels 100 can be arranged in 2 rows and 2 columns as shown in FIG. 3B. At this time, for example, each pixel 100 is arranged such that the transfer gate electrode 360 of each pixel 100 is located on the outer side. By electrically connecting the charge storage portion 330 of each pixel 100 via the wiring 400 provided on the surface 300a of the semiconductor substrate 300, the charge storage portion 330 can be shared by each pixel 100.

[0045] Further, in the present embodiment, for example, a plurality of pixels 100 are arranged as shown in FIG. 3C. At this time, for example, in four pixels 100 arranged in 2 rows and 2 columns (center of FIG. 3C), each pixel 100 is arranged such that the transfer gate electrode 360 of each pixel 100 is located at the center of the four pixels 100. By doing so, the transfer gate electrodes 360 of the four pixels 100 form an integrated substantially quadrangular pyramid as shown on the right side of FIG. 3C.

[0046] <3.2 Manufacturing Method> Next, an example of a manufacturing method for the pixel 100 according to this embodiment will be described with reference to Figures 4A to 4C. Figures 4A to 4C are cross-sectional views for illustrating the manufacturing method for the pixel 100 according to this embodiment, and in detail correspond to the cross-sectional view shown in the lower part of Figure 3A.

[0047] First, as shown on the left side of Figure 4A, a semiconductor substrate (Sub (Substrate)) 300 of a second conductivity type (e.g., type P) is prepared. Then, by injecting impurities of a first conductivity type (e.g., type N) into the semiconductor substrate 300, a photoelectric conversion unit 310 is formed, as shown second from the left in Figure 4A.

[0048] Next, as shown in the third image from the left in Figure 4A, a trench 322 is formed in the semiconductor substrate 300, penetrating the semiconductor substrate 300 in the direction of the semiconductor substrate 300's film thickness. Then, as shown on the right side of Figure 4A, SiO is poured into the trench 322. ２ An insulating film is embedded to form a pixel separation wall 320.

[0049] Furthermore, as shown on the left side of Figure 4B, a mask 500 having an opening in the region where the transfer gate electrode 360 ​​is provided is formed on the surface 300a of the semiconductor substrate 300. Then, as shown second from the left in Figure 4B, the region of the semiconductor substrate 300 exposed through the opening of the mask 500 is dry-etched to form a trench 362, and the mask 500 is removed.

[0050] Next, as shown third from the left in Figure 4B, a mask 502 having an opening that exposes the trench 362 is formed on the surface 300a of the semiconductor substrate 300. Then, the trench 362 exposed through the opening of the mask 502 is wet etched. At this time, for example, TMAH (tetramethylammonium hydroxide), KOH (potassium hydroxide), EDP (ethylenediamine pyrocatechol), NaOH (sodium hydroxide), CsOH (cesium hydroxide), N ２ H ４ By performing wet etching using an alkaline solution such as (hydrazine) or a mixture thereof, a roughly triangular pyramidal trench 362 is formed, selectively exposing the (111) plane.

[0051] Furthermore, as shown on the left side of Figure 4B, after removing the mask 502, impurities are injected into the surface 300a side of the semiconductor substrate 300 to form the charge accumulation region 330, diffusion regions 340, and 380 (see Figure 5).

[0052] Next, as shown on the left side of Figure 4C, SiO is poured so as to cover the side of the trench 362. ２ An insulating film 370 is formed. Furthermore, as shown second from the left in Figure 4C, a metal film is embedded in the trench 362 to form a transfer gate electrode 360. Then, as shown on the right side of Figure 4C, vias 410 are formed on the transfer gate electrode 360 ​​and the diffusion region 380, which are electrically connected to them.

[0053] In this embodiment, the method for manufacturing the pixel 100 is not limited to the method shown in Figures 4A to 4C.

[0054] <<4. Second Embodiment>> Next, the detailed configuration of the pixel 100 according to the second embodiment of the present disclosure will be described with reference to Figures 5 to 8. Figures 5 to 8 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figures 5 to 8 shows a plan view of the pixel 100 as seen from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 5 to 8 shows a cross-section when the pixel 100 is cut along the line A-A' shown in the upper part of Figures 5 to 8 in the direction of the film thickness of the semiconductor substrate 300. Here, the explanation of points common to the first embodiment described above will be omitted.

[0055] In this embodiment, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. In this embodiment, the above-mentioned pixel transistor is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0056] In the example shown in Figure 5, the pixel 100 has a diffusion region (second diffusion region) 380 containing an impurity (second impurity) having a second conductivity type (e.g., type P). A via 420 is provided in the diffusion region 380, and a reference potential (ground (GND) potential), for example, is applied through the via 420. In detail, as shown in the upper part of Figure 5, the diffusion region 380 is provided in a corner (second corner) that is on the same diagonal as the corner (first corner) where the transfer gate electrode 360 ​​is located.

[0057] Furthermore, in the example shown in Figure 6, unlike the example in Figure 5 described above, the charge storage unit 330 is located in a corner (second corner) that is on the same diagonal as the corner (first corner) where the transfer gate electrode 360 ​​is located, as shown in the upper part of Figure 6. Moreover, in the example shown in Figure 6, at least a part of the charge storage unit 330 overlaps with the pixel separation wall 320, as shown in the lower part of Figure 6. In the example shown in Figure 6, for example, in four pixels 100 arranged in a 2x2 grid, each pixel 100 can be arranged such that the charge storage unit 330 of each pixel 100 is located at the center of the four pixels 100. Therefore, in the example shown in Figure 6, by doing so, the charge storage units 330 of the four pixels 100 can be shared by each adjacent pixel 100. Furthermore, in the example shown in Figure 6, the diffusion region 380 is located in a corner (third corner) that is not on the same diagonal as the corner (first corner) where the transfer gate electrode 360 ​​is located. Furthermore, in the example shown in Figure 6, the diffusion region 340 is provided between the transfer gate electrode 360 ​​and the charge storage unit 330 to adjust the potential within the semiconductor substrate 300, thereby enabling more efficient charge transfer.

[0058] In the example shown in Figure 7, unlike the example in Figure 5 described above, an isolation section (STI (Shallow Trench Isolation)) 390 is provided around the charge storage section 330. The isolation section 390 consists of a trench provided on the surface 300a of the semiconductor substrate 300 and SiO embedded in the trench. ２It consists of an insulating film, etc. More specifically, as shown in the lower part of Figure 7, the separation portion 390 extends to a deeper position within the semiconductor substrate 300 compared to the bottom surface of the charge storage portion 330. In the example shown in Figure 7, this makes it possible to suppress the influence between the diffusion region 380 and the charge storage portion 330. In this embodiment, it is preferable that the separation portion 390 is provided at least between the charge storage portion 330 and the diffusion region 380.

[0059] Furthermore, in the example shown in Figure 8, unlike the example in Figure 6 described above, a separation section 390 is provided around the diffusion region 340. In the example shown in Figure 8, this makes it possible to suppress the influence between the diffusion region 340 and the charge accumulation section 330.

[0060] Furthermore, in this embodiment shown in Figures 5 to 8, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. According to this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0061] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 5 to 8.

[0062] <<5. Third Embodiment>> Next, the detailed configuration of the pixel 100 according to the third embodiment of the present disclosure will be described with reference to Figures 9 to 11. Figures 9 to 11 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figures 9 to 11 shows a plane of the pixel 100 as viewed from above on the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 9 to 11 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 9 to 11 in the direction of the film thickness of the semiconductor substrate 300.

[0063] In this embodiment as well, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. In this embodiment as well, the pixel transistor described above is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0064] In the example shown in Figure 9, unlike the second embodiment described above, a sidewall 364 made of an insulating film is provided between the charge storage portion 330 side of the transfer gate electrode 360 ​​and the diffusion region 340, as shown in the upper part of Figure 9. More specifically, as shown in the lower part of Figure 9, the sidewall 364 overlaps with a part of the diffusion region 340. In the example shown in Figure 9, this makes it possible to suppress the application of a strong electric field to the channel through which charge is transferred.

[0065] Furthermore, in the example shown in Figure 10, unlike the second embodiment described above, the transfer gate electrode 360 ​​has a canopy-like structure. More specifically, as shown in the lower part of Figure 10, the end of the transfer gate electrode 360 ​​on the charge storage portion 330 side extends toward the charge storage portion 330 and overlaps with a part of the diffusion region 340. In the example shown in Figure 10, such a transfer gate electrode 360 ​​allows an electric field to be effectively applied to the transfer channel, and the charge to be efficiently transferred to the charge storage portion 330.

[0066] In the example shown in Figure 11, a sidewall 364, as shown in Figure 9, is provided with respect to the transfer gate electrode 360 ​​shown in Figure 10. In the example shown in Figure 11, this configuration suppresses the application of a strong electric field to the channel through which charge is transferred, while allowing the transfer gate electrode 360 ​​to efficiently transfer charge to the charge storage unit 330.

[0067] Furthermore, in this embodiment shown in Figures 9 to 11, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. In this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0068] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 9 to 11.

[0069] <<6. Fourth Embodiment>> Next, the detailed configuration of the pixel 100 according to the fourth embodiment of the present disclosure will be described with reference to Figures 12 to 19. Figures 12 to 19 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. Specifically, the upper part of Figures 12 to 19 shows a plane of the pixel 100 as viewed from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 12 to 19 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 12 to 19 in the direction of the film thickness of the semiconductor substrate 300. In this embodiment, one pixel 100 is provided with two transfer gate electrodes 360a and 360b.

[0070] In the examples shown in Figures 12 to 15, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. Also, in the examples shown in Figures 12 to 15, the pixel transistor described above is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0071] In the example shown in Figure 12, unlike the second embodiment described above, the pixel 100 has a transfer gate electrode (second gate electrode) 360b in addition to the transfer gate electrode (first gate electrode) 360a provided at the corner (first corner) of the pixel area. The transfer gate electrode 360b is provided at a corner (third corner) that is not on the same diagonal as the corner where the transfer gate electrode 360a is located. In the example shown in Figure 12, this arrangement allows the charge to be transferred to the charge storage unit 330 more efficiently by the two transfer gate electrodes 360a and 360b.

[0072] In the example shown in Figure 13, unlike the example shown in Figure 12 described above, the diffusion region 380 is provided in the corner (second corner) which is on the same diagonal as the corner (first corner) where the transfer gate electrode 360a is located, as shown in the upper part of Figure 13. More specifically, as shown in the lower part of Figure 13, the diffusion region 380 is provided such that at least a part of the diffusion region 380 overlaps with the pixel separation wall 320. In the example shown in Figure 13, for example, in four pixels 100 arranged in a 2x2 grid, each pixel 100 can be arranged such that the diffusion region 380 of each pixel 100 is located in the center of the four pixels 100. Therefore, in the example shown in Figure 13, by doing so, the diffusion region 380 of the four pixels 100 can be shared by each adjacent pixel 100.

[0073] In the example shown in Figure 14, unlike the example in Figure 12 described above, a separation section 390 is provided around the charge storage section 330. In the example shown in Figure 14, this arrangement makes it possible to suppress the influence between the diffusion region 380 and the charge storage section 330.

[0074] In the example shown in Figure 15, unlike the example in Figure 13 described above, a separation section 390 is provided around the charge storage section 330. In the example shown in Figure 14, this arrangement makes it possible to suppress the influence between the diffusion region 380 and the charge storage section 330.

[0075] Furthermore, in the examples shown in Figures 16 to 19, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. Also, in the examples shown in Figures 16 to 19, the above-mentioned pixel transistor is provided on the surface 300a of the semiconductor substrate 300 (single-stage pixel configuration).

[0076] In the example shown in Figure 16, unlike the second embodiment described above, the pixel 100 has a transfer gate electrode (second gate electrode) 360b in addition to the transfer gate electrode (first gate electrode) 360a provided at the corner (first corner) of the pixel region. The transfer gate electrode 360b is provided so as to be in contact with the edge (first edge) extending from the corner where the transfer gate electrode 360a is located. Furthermore, the transfer gate electrode 360b is in contact with the separation portion 390, suppressing the influence of the transfer gate electrode 360b on adjacent pixels 100. In the example shown in Figure 16, this arrangement allows the charge to be transferred to the charge storage portion 330 more efficiently by the two transfer gate electrodes 360a and 360b. Also, in the example shown in Figure 16, since the transfer gate electrodes 360a and 360b are arranged close together, a pixel transistor 430, such as a reset transistor (RST (reset)), can be provided on the surface 300a of the semiconductor substrate 300.

[0077] In the example shown in Figure 17, unlike the example shown in Figure 16 described above, the diffusion region 380 is provided in the corner (second corner) which is on the same diagonal as the corner (first corner) where the transfer gate electrode 360a is located, as shown in the upper part of Figure 17. More specifically, as shown in the lower part of Figure 17, the diffusion region 380 is provided such that at least a part of the diffusion region 380 overlaps with the pixel separation wall 320. In the example shown in Figure 17, for example, in four pixels 100 arranged in a 2x2 grid, each pixel 100 can be arranged such that the diffusion region 380 of each pixel 100 is located in the center of the four pixels 100. Therefore, in the example shown in Figure 17, by doing so, the diffusion region 380 of the four pixels 100 can be shared by each adjacent pixel 100.

[0078] In the example shown in Figure 18, unlike the example in Figure 16 described above, isolation units 390 are provided around the charge storage unit 330 and the pixel transistor 430. In the example shown in Figure 18, this arrangement makes it possible to suppress the influence of the charge storage unit 330 and the pixel transistor 430 on their surroundings.

[0079] In the example shown in Figure 19, unlike the example in Figure 17 described above, isolation units 390 are provided around the charge storage unit 330 and the pixel transistor 430. In the example shown in Figure 19, this makes it possible to suppress the influence of the charge storage unit 330 and the pixel transistor 430 on their surroundings.

[0080] Furthermore, in this embodiment shown in Figures 12 to 19, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. According to this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0081] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 12 to 19.

[0082] <<7. Fifth Embodiment>> Next, the detailed configuration of the pixel 100 according to the fifth embodiment of the present disclosure will be described with reference to Figures 20 to 23. Figures 20 to 23 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. Specifically, the upper part of Figures 20 to 23 shows a plane of the pixel 100 as viewed from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 20 to 23 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 20 to 23 in the direction of the film thickness of the semiconductor substrate 300. In this embodiment, one pixel 100 is provided with three transfer gate electrodes 360a, 360b, and 360c.

[0083] In this embodiment as well, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. In this embodiment as well, the pixel transistor described above is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0084] In the example shown in Figure 20, unlike the fourth embodiment described above, the pixel 100 has a transfer gate electrode (first gate electrode) 360a provided at the corner of the pixel region (first corner), a transfer gate electrode (second gate electrode) 360b provided at a corner (third corner) that is not on the same diagonal as the corner where the transfer gate electrode 360a is located, and a transfer gate electrode (third gate electrode) 360c. The transfer gate electrode 360c is provided at a corner (fourth corner) that is on the same diagonal as the corner where the transfer gate electrode 360a is located. In the example shown in Figure 20, this configuration allows the charge to be transferred to the charge storage unit 330 more efficiently by the three transfer gate electrodes 360a, 360b, and 360c.

[0085] In the example shown in Figure 21, unlike the example in Figure 20 described above, a separation unit 390 is provided between the charge storage unit 330 and the diffusion region 380. In the example shown in Figure 21, this arrangement makes it possible to suppress the influence of the diffusion region 380 on the charge storage unit 330.

[0086] In the example shown in Figure 22, unlike the example shown in Figure 20 described above, the diffusion region 380 is provided in the corner (second corner) which is on the same diagonal as the corner (first corner) where the transfer gate electrode 360a is located, as shown in the upper part of Figure 22. More specifically, as shown in the lower part of Figure 22, the diffusion region 380 is provided such that at least a part of the diffusion region 380 overlaps with the pixel separation wall 320. In the example shown in Figure 22, for example, in four pixels 100 arranged in a 2x2 grid, each pixel 100 can be arranged such that the diffusion region 380 of each pixel 100 is located in the center of the four pixels 100. Therefore, in the example shown in Figure 22, by doing so, the diffusion region 380 of the four pixels 100 can be shared by each adjacent pixel 100.

[0087] In the example shown in Figure 23, unlike the example shown in Figure 22 described above, a separation unit 390 is provided between the charge storage unit 330 and the diffusion region 380. In the example shown in Figure 23, this arrangement makes it possible to suppress the influence of the diffusion region 380 on the charge storage unit 330.

[0088] Furthermore, in this embodiment shown in Figures 20 to 23, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. In this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0089] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 20 to 23.

[0090] <<8. Sixth Embodiment>> Next, with reference to Figure 24, the detailed configuration of the pixel 100 according to the sixth embodiment of the present disclosure will be described. Figure 24 is an explanatory diagram showing an example of the configuration of the pixel 100 according to the present embodiment. In detail, the upper part of Figure 24 shows a plan view of the pixel 100 as seen from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figure 24 shows a cross-section when the pixel 100 is cut along the line A-A' shown in the upper part of Figure 24 in the direction of the film thickness of the semiconductor substrate 300.

[0091] In this embodiment as well, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface. Specifically, for example, on the surface of the semiconductor substrate 300, the X direction is the

[100] direction and the Y direction is the

[010] direction. In this embodiment as well, the pixel transistor described above is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0092] In the embodiments of the present disclosure described so far, a pixel 100 has been described in which the first conductivity type is N-type, the second conductivity type is P-type, and electrons are used as the signal charge. However, the embodiments of the present disclosure are not limited to such examples. For example, in the sixth embodiment of the present disclosure, a pixel 100 may have the same configuration as in the first embodiment, but the first conductivity type is P-type, the second conductivity type is N-type, and holes are used as the signal charge.

[0093] In this embodiment as well, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. Furthermore, according to this embodiment, it is possible to suppress the generation of leakage current caused by defect levels and avoid a decrease in image quality.

[0094] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figure 24.

[0095] <<9. Seventh Embodiment>> Next, with reference to Figure 25, the detailed configuration of the pixel 100 according to the seventh embodiment of the present disclosure will be described. Figure 25 is an explanatory diagram showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figure 25 shows a plan view of the pixel 100 as seen from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figure 25 shows a cross-section when the pixel 100 is cut along the line A-A' shown in the upper part of Figure 25 in the direction of the film thickness of the semiconductor substrate 300. Here, the explanation of points common to the first embodiment described above will be omitted.

[0096] In this embodiment, although the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface, unlike the embodiments of the disclosure described so far, the X and Y directions on the surface of the semiconductor substrate 300 are in the

[110] direction. Furthermore, in this embodiment, the above-mentioned pixel transistor is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0097] As shown in the lower part of Figure 25, in this embodiment as well, the transfer gate electrode 360 ​​has a vertical gate structure that extends from the surface 300a of the semiconductor substrate 300 toward the photoelectric conversion unit 310. In this embodiment as well, as shown in the upper part of Figure 25, the transfer gate electrode 360 ​​is provided so as to be in contact with the pixel separation wall 320 along the edge (second edge) of the pixel region. Furthermore, in this embodiment, the side surface of the transfer gate electrode 360 ​​on the charge storage unit 330 side is formed along the (111) crystal plane of the semiconductor substrate 300. The overall shape of the transfer gate electrode 360 ​​is, for example, a roughly triangular prism shape as shown on the right side of Figure 25, and in plan view, a roughly rectangular shape as shown in the upper part of Figure 25.

[0098] Furthermore, in this embodiment, as shown in the upper part of Figure 25, the diffusion region 380 is provided in the corner of the pixel region far from the transfer gate electrode 360.

[0099] In this embodiment, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. Furthermore, according to this embodiment, it is possible to suppress the generation of leakage current caused by defect levels and avoid a decrease in image quality.

[0100] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figure 25.

[0101] <<10. Eighth Embodiment>> Next, the detailed configuration of the pixel 100 according to the eighth embodiment of the present disclosure will be described with reference to Figures 26 to 30. Figures 26 to 30 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. Specifically, the upper part of Figures 26 to 30 shows a plan view of the pixel 100 from above on the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 26 to 30 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 26 to 30 in the direction of the film thickness of the semiconductor substrate 300.

[0102] In this embodiment, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface, and the X and Y directions on the surface of the semiconductor substrate 300 are in the

[110] direction. In this embodiment, the above-mentioned pixel transistor is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0103] In the example shown in Figure 26, the transfer gate electrode 360 ​​is provided along the edge (second edge) of the pixel region, in contact with the pixel separation wall 320, as shown in the upper part of Figure 26. Also in the example shown in Figure 26, the diffusion region 380 is provided in the corner of the pixel region, far from the transfer gate electrode 360.

[0104] Furthermore, in the example shown in Figure 27, the diffusion region 380 is located in a different corner of the pixel area than in the example shown in Figure 26. Moreover, in the example shown in Figure 27, unlike the example shown in Figure 26 described above, the diffusion region 380 is provided such that at least a part of the diffusion region 380 overlaps with the pixel separation wall 320, as shown in the upper part of Figure 27. In the example shown in Figure 27, for example, in four pixels 100 arranged in two rows and two columns, each pixel 100 can be arranged such that the diffusion region 380 of each pixel 100 is located in the center of the four pixels 100. Therefore, in the example shown in Figure 27, by doing so, the diffusion region 380 of the four pixels 100 can be shared by each adjacent pixel 100.

[0105] In the example shown in Figure 28, unlike the example in Figure 26 described above, a separation section 390 is provided around the charge storage section 330. In the example shown in Figure 28, this arrangement makes it possible to suppress the influence of the surroundings on the charge storage section 330.

[0106] In the example shown in Figure 29, unlike the example in Figure 27 described above, a separation section 390 is provided around the charge storage section 330. In the example shown in Figure 29, this arrangement makes it possible to suppress the influence of the surroundings on the charge storage section 330.

[0107] In the example shown in Figure 30, unlike the example in Figure 26 described above, a separation section 390 is provided between the transfer gate electrode 360 ​​and the pixel separation wall 320. In the example shown in Figure 30, this arrangement makes it possible to suppress the influence of the transfer gate electrode 360 ​​on its surroundings.

[0108] Furthermore, in this embodiment shown in Figures 26 to 30, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. According to this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0109] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 26 to 30.

[0110] <<11. Ninth Embodiment>> Next, the detailed configuration of the pixel 100 according to the ninth embodiment of the present disclosure will be described with reference to Figures 31 to 34. Figures 31 to 34 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figures 31 to 34 shows a plane of the pixel 100 as viewed from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 31 to 34 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 31 to 34 in the direction of the film thickness of the semiconductor substrate 300. In this embodiment, one pixel 100 is provided with two transfer gate electrodes 360a and 360b.

[0111] In this embodiment, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface, and the X and Y directions on the surface of the semiconductor substrate 300 are in the

[110] direction. In this embodiment, the above-mentioned pixel transistor is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0112] In the example shown in Figure 31, unlike the eighth embodiment described above, the pixel 100 has a transfer gate electrode (second gate electrode) 360b in addition to the transfer gate electrode (first gate electrode) 360a which is provided so as to be in contact with the pixel separation wall 320 along the edge of the pixel region (second edge). The transfer gate electrode (second gate electrode) 360b is provided so as to be in contact with the pixel separation wall 320 along an edge (third edge) that is perpendicular to the edge to which the transfer gate electrode 360a is in contact. In the example shown in Figure 31, this arrangement allows the charge to be efficiently transferred to the charge storage unit 330 by the two transfer gate electrodes 360a and 360b.

[0113] In the example shown in Figure 32, unlike the example in Figure 31 described above, a separation section 390 is provided around the charge storage section 330. In the example shown in Figure 32, this configuration makes it possible to suppress the influence of the surroundings on the charge storage section 330.

[0114] In the example shown in Figure 33, unlike the embodiment shown in Figure 31, the transfer gate electrode (second gate electrode) 360b is provided so as to be in contact with the pixel separation wall 320 along the side opposite to the side to which the transfer gate electrode 360a is in contact (the fourth side). Furthermore, in the example shown in Figure 33, the diffusion region 380 is provided along the side of the pixel region that is far from the transfer gate electrodes 360a and 360b. In the example shown in Figure 33, this configuration allows the charge to be efficiently transferred to the charge storage unit 330 by the two transfer gate electrodes 360a and 360b.

[0115] In the example shown in Figure 34, unlike the example in Figure 33 described above, a separation section 390 is provided around the diffusion region 380. In the example shown in Figure 34, the influence of the diffusion region 380 on the charge accumulation section 330 can be suppressed.

[0116] Furthermore, in this embodiment shown in Figures 31 to 34, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. In this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0117] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 31 to 34.

[0118] <<12. Tenth Embodiment>> Next, the detailed configuration of the pixel 100 according to the tenth embodiment of the present disclosure will be described with reference to Figures 35 and 36. Figures 35 and 36 are explanatory diagrams showing an example of the configuration of the pixel 100 according to this embodiment. In detail, the upper part of Figures 35 and 36 shows a plane of the pixel 100 as viewed from above the surface 300a side of the semiconductor substrate 300, and the lower part of Figures 35 and 36 shows a cross-section of the pixel 100 when it is cut along the line A-A' shown in the upper part of Figures 35 and 36 in the direction of the film thickness of the semiconductor substrate 300. In this embodiment, one pixel 100 is provided with three transfer gate electrodes 360a, 360b, and 360c.

[0119] In this embodiment, the semiconductor substrate 300 is a single crystal substrate having a (100) plane surface, and the X and Y directions on the surface of the semiconductor substrate 300 are in the

[110] direction. In this embodiment, the above-mentioned pixel transistor is provided on another substrate (not shown) stacked above the surface 300a of the semiconductor substrate 300 (two-stage pixel configuration).

[0120] In the example shown in Figure 35, unlike the example shown in Figure 33 described above, the pixel 100 has a transfer gate electrode (first gate electrode) 360a provided along the edge of the pixel region, a transfer gate electrode (second gate electrode) 360b provided along the edge opposite to the edge to which the transfer gate electrode 360a is in contact (a fourth edge), and a transfer gate electrode (third gate electrode) 360c. The transfer gate electrode 360c is provided so as to be in contact with the pixel separation wall 320 along the edge perpendicular to the edge to which the transfer gate electrode 360a is in contact (a third edge). In the example shown in Figure 35, in this way, the charge can be efficiently transferred to the charge storage unit 330 by the three transfer gate electrodes 360a, 360b, and 360c.

[0121] In the example shown in Figure 36, unlike the example in Figure 35 described above, a separation section 390 is provided around the diffusion region 380. In the example shown in Figure 36, the influence of the diffusion region 380 on the charge accumulation section 330 can be suppressed.

[0122] Furthermore, in this embodiment shown in Figures 35 and 36, by providing one of the sides of the transfer gate electrode 360 ​​along the (111) crystal plane, it is possible to avoid the generation of defect levels near the transfer gate electrode 360. In this embodiment, the generation of leakage current caused by defect levels can be suppressed, and a decrease in image quality can be avoided.

[0123] In this embodiment, the configuration of the pixel 100 is not limited to the configuration shown in Figures 35 and 36.

[0124] <<13. Eleventh Embodiment>> <13.1 Background> Next, with reference to Figure 37, the background to the inventors' creation of the eleventh embodiment of this disclosure will be explained. Figure 37 is an explanatory diagram showing an example of a cross-sectional configuration of a pixel (photodetector) 100a and its surroundings according to a comparative example, and in detail, it shows a cross-section when the pixel 100a and its surroundings are cut in the direction of the film thickness of the semiconductor substrate 300. Here, the comparative example refers to the structure of the pixel 100a that the inventors had been studying before creating the eleventh embodiment of this disclosure.

[0125] As shown in Figure 37, the transfer gate electrode 360 ​​of the pixel 100a in the comparative example has an electrode portion 360h provided on the surface 300a of the semiconductor substrate 300, as well as a vertical gate electrode portion 360i that extends from the surface 300a side into the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300. In a pixel 100a having such a structure, a diffusion region (OFB (Over Flow Barrier)) 610 is provided in the region that becomes a transfer channel located near the vertical gate electrode portion 360i. The diffusion region 610 contains, for example, an impurity of a first conductivity type (e.g., N-type) and adjusts the potential of the region that becomes a transfer channel, thereby realizing efficient charge transfer.

[0126] Furthermore, in the comparative example, as shown in Figure 37, a diffusion region (PXP) 600 is provided within the semiconductor substrate 300 to separate the charge storage portion 330 and pixel transistors 440, 450, etc., provided on the surface 300a of the semiconductor substrate 300 from other regions. The diffusion region 600 contains, for example, an impurity of a second conductivity type (e.g., type P). More specifically, as shown in Figure 37, the diffusion regions 600 and 610 are provided at approximately the same depth within the semiconductor substrate 300.

[0127] Furthermore, during the manufacturing process of the pixel 100a, if the diffusion regions 600 and 610 are misaligned from their predetermined positions (positional misalignment) or if their size deviates from a predetermined size (size misalignment), charge transfer failures and image quality defects may occur. For example, if the diffusion region 600 is moved closer to the vertical gate electrode portion 360i due to positional or size misalignment of the diffusion regions 600 and 610, the transfer potential generated by the diffusion region 610 adjacent to the vertical gate electrode portion 360i becomes shallower. As a result, charge transfer failures may occur. On the other hand, if the diffusion region 600 is moved further away from the vertical gate electrode portion 360i due to positional or size misalignment of the diffusion regions 600 and 610, the transfer potential generated by the diffusion region 610 adjacent to the vertical gate electrode portion 360i becomes deeper. As a result, the area that functions as the photoelectric conversion unit 310 becomes smaller, the conversion efficiency decreases, and image quality defects may occur.

[0128] Furthermore, in the comparative example, because the margin for positional and size misalignment was small, pixels 100a with positional or size misalignment were treated as defective products with reduced image quality, thus lowering the manufacturing yield of the imaging device 10.

[0129] Therefore, in light of these circumstances, the inventors have created an eleventh embodiment of the present disclosure that can avoid a decrease in image quality. The details of the eleventh embodiment of the present disclosure created by the inventors will be described below.

[0130] <13.2 Detailed Configuration> Next, the detailed configuration of the pixel (photodetector) 100 according to the 11th embodiment of the present disclosure will be described with reference to Figure 38. Figure 38 is an explanatory diagram showing an example of a cross-sectional configuration of the pixel 100 and its surroundings according to the present embodiment, and more specifically, it shows a cross-section when the pixel 100 and its surroundings are cut in the direction of the film thickness of the semiconductor substrate 300.

[0131] In this embodiment, as shown in Figure 38, the pixel transistors 440 and 450 are provided on the surface (second surface) 300a of the semiconductor substrate 300 (single-stage pixel configuration). The semiconductor substrate 300 is, for example, a single-crystal substrate having a (100) plane, and more specifically, is composed of, for example, a Si substrate. Although not shown in Figure 38, in this embodiment, for example, a photoelectric conversion unit 310 having an impurity of a first conductivity type (for example, N-type) (first impurity) is provided within the semiconductor substrate 300 of a second conductivity type (for example, P-type). The photoelectric conversion unit 310 can absorb incident light and generate an electric charge.

[0132] Furthermore, the charge generated in the photoelectric conversion unit 310 is transferred to the charge storage unit (FD) 330 by a transfer gate electrode 360 ​​provided on the surface 300a (second surface) side of the semiconductor substrate 300. The charge storage unit 330 contains an impurity (first impurity) having the same first conductivity type (e.g., N-type) as the photoelectric conversion unit 310, at a higher concentration than the photoelectric conversion unit 310, and can store the above charge. In this embodiment, the charge storage unit 330 is provided on the surface 300a side of the semiconductor substrate 300, as shown in Figure 38.

[0133] As shown in Figure 38, the transfer gate electrode 360 ​​has an electrode portion 360d provided on the surface 300a of the semiconductor substrate 300, as well as a vertical gate electrode portion 360e that extends from the surface 300a side into the semiconductor substrate 300 along the film thickness direction of the semiconductor substrate 300. In detail, the vertical gate electrode portion 360e extends to a deeper position in the semiconductor substrate 300 than the bottom surface of the charge storage portion 330. Furthermore, the vertical gate electrode portion 360e has a tapered shape that decreases in diameter from the surface 300a towards the photoelectric conversion portion 310 located deep within the semiconductor substrate 300. Specifically, in the cross-sectional view shown in Figure 38, the right and left sides (first side and second side) of the vertical gate electrode portion 360f have surfaces that are inclined obliquely with respect to the surface 300a of the semiconductor substrate 300. In this embodiment, for example, a tapered vertical gate electrode portion 360e may be fabricated by forming the side surface of the vertical gate electrode portion 360e along the (111) crystal plane of the semiconductor substrate 300. Furthermore, the electrode portion 360d and the vertical gate electrode portion 360e of the transfer gate electrode 360 ​​can be formed from a material containing at least one of Si, Ti, W, Ni, N, Ru, Cu, and Co.

[0134] Furthermore, in this embodiment, a diffusion region (third diffusion region) 610 containing an impurity having, for example, a first conductivity type (e.g., N-type) (first impurity) is provided along the side surface (first side surface) of the vertical gate electrode portion 360e on the charge storage portion 330 side. The diffusion region 610 adjusts the potential of the region that becomes the transfer channel, thereby realizing efficient charge transfer. In this embodiment, by providing the diffusion region 610 along the side surface of the diagonal vertical gate electrode portion 360e, displacement of the diffusion region 610 in position and size can be suppressed. As a result, according to this embodiment, charge transfer failures and decreases in conversion efficiency can be suppressed, and a decrease in image quality can be avoided.

[0135] Furthermore, in this embodiment, as shown in Figure 38, a diffusion region (PXP) 600 is provided within the semiconductor substrate 300 to separate the charge storage portion 330 and pixel transistors 440, 450, etc., provided on the surface 300a of the semiconductor substrate 300 from other regions. The diffusion region 600 contains, for example, a second conductivity type (e.g., type P) impurity. In this embodiment, the diffusion region 600 is provided within the semiconductor substrate 300 located between the pixel transistors 440, 450 and the transfer gate electrode 360.

[0136] Furthermore, in this embodiment, a separation section 390 is provided around the pixel transistors 440, 450 and the transfer gate electrode 360 ​​to separate the pixel transistors 440, 450 and the transfer gate electrode 360 ​​from other regions. The separation section 390 consists of a trench provided on the surface 300a of the semiconductor substrate 300 and SiO embedded in the trench. ２ It consists of an insulating film such as the above.

[0137] In this embodiment, the configuration of the pixel 100 and the surrounding area of ​​the pixel 100 is not limited to the configuration shown in Figure 38.

[0138] <13.3 Modified Examples> Next, with reference to Figure 39, the detailed configuration of the pixel 100 according to a modified example of this embodiment will be described. Figure 39 is an explanatory diagram showing an example of the cross-sectional configuration of the pixel 100 and its surroundings according to this modified example, and in detail, it shows a cross-section when the pixel 100 and its surroundings are cut in the direction of the film thickness of the semiconductor substrate 300.

[0139] In the embodiment described above, the right and left sides of the vertical gate electrode portion 360f had surfaces that were inclined at an angle with respect to the surface 300a of the semiconductor substrate 300. On the other hand, in this modified example, as shown in Figure 39, only the side of the vertical gate electrode portion 360f on the charge storage portion 330 side may be inclined at an angle with respect to the surface 300a of the semiconductor substrate 300.

[0140] Also in this modification, a diffusion region 610 is provided along the side surface of the vertical gate electrode portion 360f on the charge storage portion 330 side. Also in this modification, by providing the diffusion region 610 along the side surface of the oblique vertical gate electrode portion 360f, positional deviation and size deviation of the diffusion region 610 can be suppressed. As a result, according to this modification, it is possible to suppress the occurrence of charge transfer defects and a decrease in conversion efficiency, and avoid a decrease in image quality.

[0141] <13.4 Manufacturing Method> Next, an example of a method for manufacturing the pixel 100 according to the present embodiment will be described with reference to FIG. 40. FIG. 40 is a cross-sectional view for explaining the method for manufacturing the pixel 100 according to the present embodiment, and more specifically, corresponds to the cross-sectional view shown in FIG. 38.

[0142] First, as shown in the upper stage of FIG. 40, for example, a semiconductor substrate 300 of a second conductivity type (e.g., P-type) is prepared, and a diffusion region, an isolation portion 390, and the like are formed in the semiconductor substrate 300. Further, a mask 504 having an opening exposing a portion to become the transfer gate electrode 360 is formed on the semiconductor substrate 300.

[0143] Subsequently, as shown in the second row from the top of FIG. 40, the region of the semiconductor substrate 300 exposed through the opening of the mask 504 is wet-etched. In this case, for example, TMAH, KOH, EDP, NaOH, CsOH, N ２ H ４ By performing wet etching using an alkaline solution such as the above or a mixture thereof, a trench 366 having an oblique side surface along the (111) plane of the semiconductor substrate 300 can be easily formed.

[0144] Further, as shown in the lower stage of FIG. 40, dry etching is performed on the trench 366 exposed from the opening of the mask 504.

[0145] Then, for example, by implanting impurities into the semiconductor substrate 300 through the trench 366, the diffusion region 610 can be formed. Further, SiO is formed so as to cover the side surface of the trench 366 ２An insulating film 370 is formed, and a metal film is embedded to form a transfer gate electrode 360. Furthermore, for example, pixel transistors 440 and 450 may be formed on the surface 300a of the semiconductor substrate 300, and a diffusion region 600 may be formed by injecting impurities into the semiconductor substrate 300 located between them. By forming the diffusion region 600 in this way, misalignment and size deviation of the diffusion region 600 can be suppressed.

[0146] In this embodiment, the method for manufacturing the pixel 100 is not limited to the method shown in Figure 40.

[0147] As described above, in this embodiment, by providing the diffusion region 610 along the side surface of the diagonal vertical gate electrode portion 360e, positional and size deviations of the diffusion region 610 can be suppressed. As a result, according to this embodiment, charge transfer failures and decreases in conversion efficiency can be suppressed, and a decrease in image quality can be avoided.

[0148] Next, an example of a method for manufacturing a pixel 100 according to a modified example of this embodiment will be described with reference to Figures 41A and 41B. Figure 41A is a cross-sectional view for illustrating the method for manufacturing a pixel 100 according to this modified example, and in detail is an explanatory diagram showing an example of the planar configuration of the pixel 100 and its surroundings according to this modified example. Figure 41B is also a cross-sectional view for illustrating the method for manufacturing a pixel 100 according to this modified example, and in detail corresponds to a cross-sectional view when the semiconductor substrate 300 is cut along the line B-B' shown in Figure 41A.

[0149] In this modified example, as shown in Figure 41A, the separation portion 390 is provided adjacent to the electrode portion 360d of the transfer gate electrode 360. More specifically, in this modified example, as shown in Figure 41B, the separation portion 390 is provided adjacent to the vertical gate electrode portion 360f. By providing the separation portion 390 in this manner, the separation portion 390 can be used as a stopper during wet etching, and only the side surface of the vertical gate electrode portion 360f on the charge storage portion 330 side can be formed to be inclined at an angle with respect to the surface 300a of the semiconductor substrate 300.

[0150] Furthermore, in this modified example, by providing the diffusion region 610 along the side surface of the diagonal vertical gate electrode portion 360f, displacement of the diffusion region 610 in position and size can be suppressed. As a result, this modified example suppresses charge transfer failures and decreases in conversion efficiency, thereby avoiding a decrease in image quality.

[0151] In this modified example, the method for manufacturing the pixel 100 is not limited to the method shown in Figures 41A and 41B.

[0152] <<14. Summary>> As described above, each embodiment of the present disclosure makes it possible to avoid a decrease in the quality of detection results by the optical detection device. Furthermore, each embodiment of the present disclosure can be combined with one another.

[0153] Furthermore, although the embodiments of this disclosure described above have been applied to a pixel 100 having a back-illuminated CMOS (Complementary MOS) image sensor structure, the embodiments of this disclosure are not limited thereto and may also be applied to a front-illuminated CMOS image sensor structure.

[0154] Furthermore, the imaging device 10 according to the embodiment of this disclosure is not limited to an imaging device that detects the distribution of the amount of incident visible light and captures it as an image. For example, this embodiment can be applied to imaging devices (physical quantity distribution detection devices) such as imaging devices that capture the distribution of incident amounts of infrared rays, X-rays, or particles as an image, distance measuring devices that receive reflected infrared light, and fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture it as an image.

[0155] Furthermore, in this embodiment, the imaging device 10 can be manufactured using methods, apparatus, and conditions commonly used in the manufacture of semiconductor devices. In other words, in this embodiment, existing semiconductor device manufacturing processes can be used.

[0156] Examples of the methods mentioned above include the PVD (Physical Vapor Deposition) method, the CVD (Chemical Vapor Deposition) method, and the ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, electron beam (EB) deposition, various sputtering methods (magnetron sputtering, RF (Radio Frequency)-DC (Direct Current) coupled bias sputtering, ECR (Electron Cyclotron Resonance) sputtering, counter-target sputtering, high-frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE (Molecular Beam Epitaxy)), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal-organic (MO) CVD, and optical CVD. Furthermore, other methods include electrolytic plating, electroless plating, spin coating, immersion, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, as well as stamping, spraying, air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calender coater. In addition, patterning methods include chemical etching such as shadow masking, laser transfer, and photolithography, as well as physical etching using ultraviolet light or lasers. Furthermore, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0157] <<15. Application Examples>> <15.1 Application Example to Smartphones> The technology relating to this disclosure (this technology) can be applied to a variety of other products. For example, the technology relating to this disclosure may be applied to smartphones, etc. With reference to Figure 42, an example of the configuration of a smartphone 900 as an electronic device to which this technology is applied will be described. Figure 42 is a block diagram showing an example of a schematic functional configuration of a smartphone 900 to which the technology relating to this disclosure (this technology) can be applied.

[0158] As shown in Figure 42, the smartphone 900 includes a CPU (Central Processing Unit) 901, a ROM (Read Only Memory) 902, and a RAM (Random Access Memory) 903. The smartphone 900 also includes a storage device 904, a communication module 905, and a sensor module 907. Furthermore, the smartphone 900 includes an imaging device 909, a display device 910, a speaker 911, a microphone 912, an input device 913, and a bus 914. The smartphone 900 may also have a processing circuit such as a DSP (Digital Signal Processor) instead of, or together with, the CPU 901.

[0159] The CPU 901 functions as an arithmetic processing unit and control unit, controlling all or part of the operation of the smartphone 900 according to various programs recorded in the ROM 902, RAM 903, or storage device 904. The ROM 902 stores programs and calculation parameters used by the CPU 901. The RAM 903 temporarily stores programs used in the execution of the CPU 901 and parameters that change as appropriate during its execution. The CPU 901, ROM 902, and RAM 903 are interconnected by a bus 914. The storage device 904 is a data storage device configured as an example of the storage unit of the smartphone 900. The storage device 904 is composed of, for example, a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, or an optical storage device. This storage device 904 stores programs executed by the CPU 901, various data, and various data acquired from external sources.

[0160] The communication module 905 is a communication interface composed of, for example, a communication device for connecting to the communication network 906. The communication module 905 may be, for example, a communication card for wired or wireless LAN (Local Area Network), Bluetooth®, or WUSB (Wireless USB). Alternatively, the communication module 905 may be a router for optical communication, a router for ADSL (Asymmetric Digital Subscriber Line), or a modem for various types of communication. The communication module 905 transmits and receives signals, etc., to and from the Internet or other communication devices using a predetermined protocol such as TCP (Transmission Control Protocol) / IP (Internet Protocol). Furthermore, the communication network 906 connected to the communication module 905 is a network connected by wire or wireless means, such as the internet, a home LAN, infrared communication, or satellite communication.

[0161] The sensor module 907 includes various sensors, such as motion sensors (e.g., acceleration sensors, gyroscopes, geomagnetic sensors, etc.), biometric information sensors (e.g., pulse sensors, blood pressure sensors, fingerprint sensors, etc.), or position sensors (e.g., GNSS (Global Navigation Satellite System) receivers, etc.).

[0162] The imaging device 909 is provided on the surface of the smartphone 900 and can image objects located on the back or front side of the smartphone 900. More specifically, the imaging device 909 may be configured to include an imaging device 10 to which the technology of this disclosure (this technology) can be applied. Furthermore, the imaging device 909 may further have an optical system mechanism (not shown) composed of an imaging lens, a zoom lens, and a focus lens, etc., and a drive system mechanism (not shown) that controls the operation of the optical system mechanism. The imaging device 909 can acquire an image by reading out an imaging signal obtained by collecting incident light from an object as an optical image and converting it into an optical signal, and then processing the image.

[0163] The display device 910 is provided on the surface of the smartphone 900 and can be, for example, an LCD (Liquid Crystal Display) or an organic EL (Electroluminescence) display. The display device 910 can display an operation screen or captured images acquired by the imaging device 909 described above.

[0164] The speaker 911 can output, for example, call audio or audio associated with video content displayed by the display device 910 described above, to the user.

[0165] The microphone 912 can, for example, pick up the user's voice during a call, voices including commands to activate functions of the smartphone 900, and sounds from the surrounding environment of the smartphone 900.

[0166] The input device 913 is a device operated by the user, such as a button, keyboard, touch panel, or mouse. The input device 913 includes an input control circuit that generates an input signal based on information entered by the user and outputs it to the CPU 901. By operating this input device 913, the user can input various types of data to the smartphone 900 or instruct it to perform processing operations.

[0167] The above shows an example configuration of the smartphone 900. Each of the above components may be made up of general-purpose materials, or it may be made up of hardware specialized for the function of each component. Such a configuration can be appropriately changed depending on the technological level at the time of implementation.

[0168] <15.2 Examples of Application to Mobile Devices> The technology relating to this disclosure (this technology) can be applied to various products. For example, the technology relating to this disclosure may be implemented as a device mounted on any type of mobile device such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots.

[0169] Figure 43 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0170] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 43, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0171] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0172] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0173] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0174] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0175] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0176] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0177] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0178] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0179] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 43, the output devices are exemplified as an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0180] Figure 44 shows an example of the installation position of the imaging unit 12031.

[0181] In Figure 44, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0182] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0183] Figure 44 shows an example of the imaging ranges of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0184] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0185] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, etc., that drives autonomously without driver operation, can be performed.

[0186] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0187] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0188] The above describes an example of a vehicle control system to which the technology described herein may be applied. The technology described herein may be applied to, for example, the imaging unit 12031, among the configurations described above.

[0189] <<16. Supplement>> Although preferred embodiments of the present disclosure have been described in detail with reference to the attached drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person with ordinary skill in the art of the present disclosure may conceive of various modifications or alterations within the scope of the technical ideas described in the claims, and these will naturally also be understood to fall within the technical scope of the present disclosure.

[0190] Furthermore, the effects described herein are merely descriptive or illustrative and not limiting. In other words, the technology relating to this disclosure may produce other effects that will be apparent to those skilled in the art from the description herein, in addition to or in lieu of the effects described herein.

[0191] Furthermore, this technology can also take the following configurations: (1) A photodetector comprising: a photoelectric conversion unit provided in a semiconductor substrate; a charge storage unit for storing the charge generated in the photoelectric conversion unit; and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate that is the light incident surface, and transferring the charge to the charge storage unit, wherein one of the sides of the vertical transfer gate electrode is formed along the (111) crystal plane of the semiconductor substrate. (2) The photodetector according to (1) above, wherein the charge storage unit is provided on the second surface side of the semiconductor substrate. (3) The photodetector according to (2) above, wherein the vertical transfer gate electrode extends to a deeper position within the semiconductor substrate than the bottom surface of the charge storage unit. (4) In a plan view, the photodetector is provided in a pixel region divided into a rectangular shape by a pixel separation wall within the semiconductor substrate, and the vertical transfer gate electrode is provided at a first corner of the pixel region, the photodetector according to any one of (1) to (3) above. (5) The charge storage portion contains a first impurity having a first conductivity type, and is adjacent to a first diffusion region containing the first impurity at a lower concentration than the charge storage portion, the photodetector according to (4) above. (6) In a plan view, at least a part of the first diffusion region is provided between the vertical transfer gate electrode and the charge storage portion, the photodetector according to (5) above. (7) In a plan view, the charge storage portion is provided in the center of the pixel region, the photodetector according to (5) or (6) above. (8) The photodetector further comprises an insulating film provided between the vertical transfer gate electrode and the first diffusion region, the photodetector according to any one of (5) to (7) above. (9) The vertical transfer gate electrode has a gate electrode film on the second surface side, and in a plan view, a part of the gate electrode film overlaps with a part of the first diffusion region, the photodetector element according to any one of (5) to (8) above. (10) The photodetector element according to (5) or (6) above, in a plan view, the charge storage portion is provided at the second corner of the pixel region which is on the same diagonal as the first corner.(11) The photodetector according to any one of (5) to (7) above, comprising a plurality of vertical transfer gate electrodes, wherein in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided at the first corner of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided at a third corner of the pixel region that is not on the same diagonal as the first corner. (12) The photodetector according to (11) above, wherein a third gate electrode included in the plurality of vertical transfer gate electrodes is provided at a fourth corner of the pixel region that is on the same diagonal as the third corner. (13) The photodetector according to any one of (5) to (7) above, comprising a plurality of vertical transfer gate electrodes, wherein in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided at the first corner of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided so as to be tangent to the first edge of the pixel region extending from the first corner of the pixel region. (14) The photodetector element according to (13) above, further comprising a pixel transistor provided on the second surface side of the semiconductor substrate. (15) The photodetector element according to any one of (5) to (7) above, further comprising a second diffusion region provided on the second surface side of the semiconductor substrate, containing a second impurity having a second conductivity type opposite to the first conductivity type, and to which a reference potential is applied. (16) The photodetector element according to (15) above, further comprising a separation portion provided between the charge storage portion and the second diffusion region. (17) The photodetector element according to (15) or (16) above, wherein, in a plan view, the second diffusion region is provided at a second corner of the pixel region which is on the same diagonal as the first corner. (18) The photodetector element according to (15) above, wherein, in a plan view, the second diffusion region is provided at a third corner of the pixel region which is not on the same diagonal as the first corner.(19) In a plan view, the photodetector is provided in a pixel region divided into a rectangular shape by a pixel separation wall within the semiconductor substrate, and the vertical transfer gate electrode is provided along the second edge of the pixel region, the photodetector according to any one of (1) to (3) above. (20) In a plan view, the vertical transfer gate electrode is provided so as to be in contact with the pixel separation wall, the photodetector according to (19) above. (21) The photodetector according to (19) or (20) above, comprising a plurality of vertical transfer gate electrodes, wherein in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided along the second edge of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided along the third edge of the pixel region perpendicular to the second edge, the photodetector according to (19) or (20) above. (22) The photodetector element according to (19) or (20) above, comprising a plurality of vertical transfer gate electrodes, wherein in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided along the second edge of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided along the fourth edge of the pixel region opposite to the second edge. (23) The photodetector element according to (22) above, wherein in a plan view, a third gate electrode included in the plurality of vertical transfer gate electrodes is provided along the third edge of the pixel region perpendicular to the second edge. (24) A photodetector comprising: a photoelectric conversion unit provided in a semiconductor substrate; a charge storage unit for storing charge generated in the photoelectric conversion unit; and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate which is the light incident surface, and transferring the charge to the charge storage unit, wherein the vertical transfer gate electrode has a tapered shape that decreases in diameter toward the photoelectric conversion unit from the second surface. (25) The photodetector according to (24), wherein in a cross-section obtained by cutting the photodetector along the film thickness direction of the semiconductor substrate, one side surface of the vertical transfer gate electrode, which is a first side surface, is inclined obliquely with respect to the surface of the semiconductor substrate.(26) The photodetector element according to (25), wherein the first side surface is formed along the (111) crystal plane of the semiconductor substrate. (27) The photodetector element according to (25) or (26), further comprising a third diffusion region for adjusting the transfer potential generated in the semiconductor substrate by the vertical transfer gate electrode, wherein the third diffusion region is provided along the first side surface. (28) The photodetector element according to any one of (25) to (27), wherein in a cross-section obtained by cutting the photodetector element along the film thickness direction of the semiconductor substrate, the second side surface, which is the other side surface of the vertical transfer gate electrode, is inclined obliquely with respect to the surface of the semiconductor substrate. (29) The photodetector element according to any one of (1) to (28), wherein the semiconductor substrate contains at least one element selected from the group consisting of Si, Ge, Sn, C, B, Al, Ga, In, N, P, As, and Sb. (30) The photodetector according to any one of (1) to (29) above, wherein the vertical transfer gate electrode contains at least one element selected from the group consisting of Si, Ti, W, Ni, N, Ru, Cu, and Co.

[0192] 10 Imaging device 30 Pixel array section 32 Vertical drive circuit section 34 Column signal processing circuit section 36 Horizontal drive circuit section 38 Output circuit section 40 Control circuit section 42 Pixel drive wiring 44 Vertical signal line 46 Horizontal signal line 48 Input / output terminals 100, 100a Pixel 300 Semiconductor substrate 300a Front surface 300b Back surface 310 Photoelectric conversion section 320 Pixel isolation wall 322, 362, 366 Trench 330 Charge storage section 360, 360a, 360b, 360c Transfer gate electrode 340, 380, 600, 610 Diffusion region 360d, 360h Electrode section 360e, 360f, 360i Vertical gate electrode section 364 Sidewall 370 Insulating film 390 Separation section 400 Wiring 410, 420 Vias 430, 440, 450 Pixel Transistors 500, 502, 504 Mask

Claims

1. A photodetector comprising: a photoelectric conversion unit provided in a semiconductor substrate; a charge storage unit for storing the charge generated in the photoelectric conversion unit; and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate that is the light incident surface, and transferring the charge to the charge storage unit, wherein one of the sides of the vertical transfer gate electrode is formed along the (111) crystal plane of the semiconductor substrate.

2. The photodetector element according to claim 1, wherein the charge storage portion is provided on the second surface side of the semiconductor substrate.

3. In a plan view, the photodetector is provided in a pixel region divided into a rectangular shape by a pixel separation wall within the semiconductor substrate, and the vertical transfer gate electrode is provided at a first corner of the pixel region, as described in claim 1.

4. The photodetector element according to claim 3, wherein the charge storage portion contains a first impurity having a first conductivity type, and is adjacent to a first diffusion region containing the first impurity at a lower concentration than that of the charge storage portion.

5. In a plan view, at least a portion of the first diffusion region is provided between the vertical transfer gate electrode and the charge storage unit, the photodetector element according to claim 4.

6. The photodetector according to claim 4, wherein the vertical transfer gate electrode has a gate electrode film on the second surface side, and in a plan view, a portion of the gate electrode film overlaps with a portion of the first diffusion region.

7. In a plan view, the charge storage portion is provided at a second corner of the pixel region which is on the same diagonal as the first corner, according to claim 4.

8. The photodetector according to claim 4, comprising a plurality of vertical transfer gate electrodes, wherein, in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided at the first corner of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided so as to be tangent to the first edge of the pixel region extending from the first corner of the pixel region.

9. The photodetector according to claim 8, further comprising a pixel transistor provided on the second surface side of the semiconductor substrate.

10. The photodetector element according to claim 4, further comprising a second diffusion region provided on the second surface side of the semiconductor substrate, containing a second impurity having a second conductivity type opposite to the first conductivity type, to which a reference potential is applied.

11. The photodetector according to claim 10, further comprising a separation portion provided between the charge storage portion and the second diffusion region.

12. In a plan view, the second diffusion region is provided at the second corner of the pixel region which is on the same diagonal as the first corner, according to claim 10.

13. In a plan view, the photodetector is provided in a pixel region divided into a rectangular shape by a pixel separation wall within the semiconductor substrate, and the vertical transfer gate electrode is provided along the second edge of the pixel region, as described in claim 1.

14. The photodetector element according to claim 13, comprising a plurality of vertical transfer gate electrodes, wherein, in a plan view, a first gate electrode included in the plurality of vertical transfer gate electrodes is provided along the second edge of the pixel region, and a second gate electrode included in the plurality of vertical transfer gate electrodes is provided along the third edge of the pixel region perpendicular to the second edge.

15. A photodetector comprising: a photoelectric conversion unit provided in a semiconductor substrate; a charge storage unit for storing the charge generated in the photoelectric conversion unit; and a vertical transfer gate electrode provided extending toward the photoelectric conversion unit from a second surface located opposite to a first surface of the semiconductor substrate that serves as the light incident surface, and transferring the charge to the charge storage unit, wherein the vertical transfer gate electrode has a tapered shape that decreases in diameter toward the photoelectric conversion unit from the second surface.

16. The photodetector element according to claim 15, wherein in a cross-section obtained by cutting the photodetector element along the film thickness direction of the semiconductor substrate, the first side surface, which is one side surface of the vertical transfer gate electrode, is inclined obliquely with respect to the surface of the semiconductor substrate.

17. The photodetector according to claim 16, wherein the first side surface is formed along the (111) crystal plane of the semiconductor substrate.

18. The photodetector according to claim 16, further comprising a third diffusion region for adjusting the transfer potential generated in the semiconductor substrate by the vertical transfer gate electrode, wherein the third diffusion region is provided along the first side surface.

19. The photodetector element according to claim 16, wherein in a cross-section obtained by cutting the photodetector element along the film thickness direction of the semiconductor substrate, the second side surface, which is the other side surface of the vertical transfer gate electrode, is inclined obliquely with respect to the surface of the semiconductor substrate.

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