Photodetection element

Abstract

The present disclosure relates to a photodetection element that makes it possible to suppress deterioration of quantum efficiency caused by a pixel separation unit. This photodetection element comprises: a semiconductor substrate; a plurality of photoelectric conversion units arranged in a matrix on the semiconductor substrate; a plurality of on-chip lenses arranged on a first surface side which is a light-receiving surface of the semiconductor substrate; and a first trench formed in at least a portion of a region between the photoelectric conversion units of the semiconductor substrate. The first trench has a first conductor layer in which a first conductive material is used and a second conductor layer in which a second conductive material having a smaller light absorption coefficient than the first conductive material is used. The second conductor layer is provided further inside the first trench than the first conductor layer in a cross-sectional view and is connected to the first conductor layer in a region in the vicinity of the first surface of the semiconductor substrate. The technology of the present disclosure can be applied to, for example, a photodetection element or the like that generates and outputs an imaging signal corresponding to the amount of incident light.

Description

Photodetector element

[0001] The present disclosure relates to a photodetector element, and particularly to a photodetector element capable of suppressing degradation of quantum efficiency caused by a pixel separation portion.

[0002] Patent Document 1 discloses a photodetection device that suppresses the generation of dark current by embedding a conductor in a pixel separation portion in a region between photoelectric conversion portions of a semiconductor substrate and applying a negative bias to the conductor.

[0003] Japanese Patent Laid-Open No. 2024-10307

[0004] Patent Document 1 discloses a pixel structure in which a conductor is embedded in a pixel separation portion near a focal point of an on-chip lens, but providing the conductor at the focal point causes degradation of quantum efficiency (QE).

[0005] The present disclosure has been made in view of such circumstances, and aims to enable suppression of degradation of quantum efficiency caused by a pixel separation portion.

[0006] A photodetector element according to one aspect of the present disclosure includes: a semiconductor substrate; a plurality of photoelectric conversion portions arranged in a matrix on the semiconductor substrate; a plurality of on-chip lenses arranged on a first surface side that is a light-receiving surface of the semiconductor substrate; and a first trench formed in at least a part of a region between the photoelectric conversion portions of the semiconductor substrate, wherein the first trench has a first conductor layer made of a first conductive material, and a second conductor layer made of a second conductive material having a smaller light absorption coefficient than the first conductive material, and in a cross-sectional view, the second conductor layer is provided closer to an inner side of the first trench than the first conductor layer, and is connected to the first conductor layer in a region near the first surface of the semiconductor substrate.

[0007] In one aspect of this disclosure, a semiconductor substrate is provided, along with a plurality of photoelectric conversion units arranged in a matrix on the semiconductor substrate, a plurality of on-chip lenses arranged on the first surface side of the semiconductor substrate which is a light-receiving surface, and a first trench formed in at least a portion of the region between the photoelectric conversion units of the semiconductor substrate. The first trench is provided with a first conductor layer made of a first conductive material and a second conductor layer made of a second conductive material having a lower light absorption coefficient than the first conductive material. In cross-sectional view, the second conductor layer is provided inside the first trench relative to the first conductor layer and is connected to the first conductor layer in the vicinity region of the first surface of the semiconductor substrate.

[0008] The photodetector may be a standalone device or a module incorporated into another device.

[0009] This figure shows the schematic configuration of a photodetector element to which the technology of this disclosure is applied. This figure shows the equivalent circuit of a pixel of the photodetector element. This is a cross-sectional view of a pixel according to the first embodiment. This is a plan view of a pixel according to the first embodiment. This is a cross-sectional view of the cross section corresponding to the Y-Y' line in Figure 4B. This is a diagram illustrating a negative bias transmission path. This is a diagram illustrating a negative bias transmission path. This is a plan view illustrating a pixel according to the second embodiment. This is a plan view illustrating a pixel according to the third embodiment. This is a plan view illustrating a pixel according to the fourth embodiment. This is a plan view illustrating a pixel according to the fifth embodiment. This is a cross-sectional view illustrating a first modified example of the pixel separation section. This is a cross-sectional view illustrating a second modified example of the pixel separation section. This is a cross-sectional view illustrating a third modified example of the pixel separation section. This is a cross-sectional view illustrating a fourth modified example of the pixel separation section. This is a cross-sectional view illustrating a fifth modified example of the pixel separation section. This is a cross-sectional view illustrating a sixth modified example of the pixel separation section. This is a plan view illustrating a sixth modified example of the pixel separation section. This is a diagram illustrating a method for manufacturing This is a diagram illustrating a method for manufacturing a pixel separation unit. This is a diagram illustrating a method for manufacturing a pixel separation unit. This is a block diagram showing an example configuration of an imaging device as an electronic device to which the technology of this disclosure is applied. This is a diagram illustrating an example of the use of an image sensor.

[0010] The following describes embodiments for carrying out the technology of this disclosure (hereinafter referred to as "embodiments") with reference to the attached drawings. The description will proceed in the following order: 1. Example of overall configuration of the photodetector element 2. Equivalent circuit of the pixel 3. Example of pixel configuration of the first embodiment 4. Negative bias transmission path 5. Example of pixel configuration of the second embodiment 6. Example of pixel configuration of the third embodiment 7. Example of pixel configuration of the fourth embodiment 8. Example of pixel configuration of the fifth embodiment 9. First and second modified examples of the pixel separation unit 10. Third modified example of the pixel separation unit 11. Fourth modified example of the pixel separation unit 12. Fifth modified example of the pixel separation unit 13. Sixth modified example of the pixel separation unit 14. Method for manufacturing the inter-pixel separation unit 15. Summary of embodiments 16. Examples of application to electronic devices 17. Examples of image sensor use

[0011] In this specification and the drawings, identical or similar parts are denoted by the same or similar reference numerals, thereby omitting redundant explanations as appropriate. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.

[0013] The technology disclosed herein can be applied to all photodetectors having a pixel array in which pixels are arranged two-dimensionally in a matrix, and which convert incident light into photoelectric signals and output a pixel signal corresponding to the amount of light. The light to be detected may be light in the visible light region including wavelengths such as R (Red), G (Green), and B (Blu), or it may be light in the invisible light region such as infrared light. Alternatively, both visible and invisible light regions may be used as the detection target. The photodetector can be used as a solid-state imaging device that generates and outputs an imaging signal corresponding to the amount of incident light, or as a light-receiving device (distance sensor) in a distance measuring system that receives reflected light (reflected light) from infrared light irradiated as active light and measures the distance to the subject using a direct ToF (Time of Flight) or indirect ToF (Time of Flight) method. Below, an example of applying the technology disclosed herein to a photodetector that receives light in the visible light region and generates and outputs an imaging signal corresponding to the amount of incident light will be described.

[0014] <1. Example of overall configuration of a photodetector> Figure 1 is a diagram showing a schematic configuration of a photodetector to which the technology of this disclosure is applied.

[0015] The photodetector element 1 in Figure 1 is constructed on a semiconductor substrate 31 made of, for example, single-crystal silicon (Si) as the semiconductor, and has a pixel array section 3 and a peripheral circuit region around it. The peripheral circuit region includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, and the like.

[0016] The pixel array section 3 has a configuration in which pixels 2, each having a photoelectric conversion unit that generates and stores photocharges corresponding to the amount of light received, are arranged in two dimensions in the row and column directions, i.e., in a matrix. Here, the row direction refers to the horizontal arrangement direction of the pixel array section 3, and the column direction refers to the vertical arrangement direction of the pixel array section 3.

[0017] Pixel 2 has a photodiode and multiple pixel transistors. The multiple pixel transistors consist of, for example, four transistors: a transfer transistor, a selection transistor, a reset transistor, and an amplification transistor, each of which is a MOS transistor (MOS FET).

[0018] The control circuit 8 receives the input clock and data that commands the operating mode, and outputs data such as internal information of the photodetector 1. In other words, the control circuit 8 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, and horizontal drive circuit 6, etc.

[0019] The vertical drive circuit 4 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 10, supplies pulses to the selected pixel drive wiring 10 to drive the pixels 2, and drives the pixels 2 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 2 of the pixel array 3 row by row in the vertical direction, and supplies a signal based on the signal charge generated in the photoelectric conversion unit of each pixel 2 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 9.

[0020] The column signal processing circuit 5 is located for each column of pixels 2 and performs signal processing such as noise reduction on the signals output from each row of pixels 2 for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD conversion to remove pixel-specific fixed pattern noise.

[0021] The horizontal drive circuit 6 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, causing each of the column signal processing circuits 5 to output a pixel signal to the horizontal signal line 11.

[0022] The output circuit 7 processes the signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 11 and outputs them. The output circuit 7 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 13 exchanges signals with the outside.

[0023] The photodetector element 1, configured as described above, has a structure called a column AD system, in which column signal processing circuits 5 that perform CDS processing and AD conversion processing are arranged in each column. The photodetector element 1 receives infrared or visible light at each pixel 2 of the pixel array 3, generates a signal according to the amount of light received, and outputs it to the outside.

[0024] <2. Equivalent Circuit of Pixel> Figure 2 shows the equivalent circuit of pixel 2.

[0025] Pixel 2 includes, for example, a photodiode PD, a transfer transistor TG electrically connected to the photodiode PD, and a floating diffusion transistor FD electrically connected to the transfer transistor TG. Pixel 2 also includes a reset transistor RST, an amplification transistor AMP, and a selection transistor SEL. The transfer transistor TG, reset transistor RST, amplification transistor AMP, and selection transistor SEL are composed of, for example, N-type MOS transistors (MOS FETs).

[0026] A photodiode (PD) converts incident light into electricity, generating an electric charge (signal charge) corresponding to the amount of incident light received. In a photodiode (PD), the cathode is electrically connected to the source of a transfer transistor (TG), and the anode is electrically connected to a reference potential line (e.g., ground).

[0027] The transfer transistor TG controls the transfer of charge generated by the photodiode PD. When the transfer transistor TG is turned ON, it transfers the charge generated by the photodiode PD to the floating diffusion FD. In the transfer transistor TG, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to the pixel drive wiring. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0028] The floating diffusion transistor (FD) is a charge storage unit that temporarily stores the charge transferred from the photodiode (PD), and also a charge-voltage conversion unit that generates a voltage corresponding to the amount of charge. The floating diffusion transistor (FD) is electrically connected to the gate of the amplification transistor (AMP) and the source of the reset transistor (RST).

[0029] The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on by the pixel drive wiring supplied to the gate, it resets the potential of the floating diffusion FD to the potential of the power line VDD. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1. When the potential of the floating diffusion FD is reset, the reset transistor RST is also controlled to be turned on at the same time.

[0030] The amplification transistor AMP generates a signal with a voltage corresponding to the level of charge accumulated in the floating diffusion FD as a pixel signal. The amplification transistor AMP is connected in series with the selection transistor SEL and is connected to the vertical signal line 9 via the selection transistor SEL. This amplification transistor AMP, together with the load circuit in the column signal processing circuit 5 connected to the vertical signal line 9, constitutes a source follower. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing circuit 5 via the vertical signal line 9. The drain of the amplification transistor AMP is connected to the power line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.

[0031] The selection transistor SEL controls the output timing of the pixel signal. The source of the selection transistor SEL is connected to the vertical signal line 9, and the gate of the selection transistor SEL is connected to the pixel drive wiring. When the selection transistor SEL is turned on by the pixel drive wiring supplied to its gate, it outputs the pixel signal from the amplification transistor AMP to the vertical signal line 9. This pixel drive wiring is part of the pixel drive wiring 10 described in Figure 1.

[0032] The selection transistor SEL may be located between the power line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP. The source of the amplification transistor AMP (the output terminal of pixel 2) is electrically connected to the vertical signal line 9, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST.

[0033] The pixel 2, configured as described above, converts incident light into photoelectric light according to the control of the vertical drive circuit 4 and outputs a pixel signal corresponding to the amount of light received to the column signal processing circuit 5 via the vertical signal line 9.

[0034] Pixel 2 can also have a shared pixel structure. When pixel 2 has a shared pixel structure, a photodiode PD and a transfer transistor TG are provided for each pixel, and the reset transistor RST, amplification transistor AMP, and selection transistor SEL are shared by the multiple pixels that make up the shared unit. For example, if the shared unit is 2x2 with 4 pixels, the reset transistor RST, amplification transistor AMP, and selection transistor SEL are shared and used by the 2x2 with 4 pixels.

[0035] <3. Pixel Configuration Example of the First Embodiment> Figure 3 is a cross-sectional view of a pixel according to the first embodiment, and Figure 4 is a plan view of a pixel according to the first embodiment. The cross-sectional view in Figure 3 shows the cross-sectional view along the line X-X' in Figure 4B.

[0036] As will be explained later in Figure 4, in Figure 3, pixel 2 has one on-chip lens 77 formed for 2x2 4 pixels, and Figure 3 is a cross-sectional view of two horizontally aligned pixels among the 2x2 4 pixels that share one on-chip lens 77.

[0037] The semiconductor substrate 31 shown in Figure 3 is a silicon substrate using silicon (Si) as the semiconductor, for example. A photodiode PD is formed on each pixel unit of the semiconductor substrate 31 by forming a P-type semiconductor region 41 (hereinafter referred to as the P-type semiconductor region 41) and an N-type semiconductor region 42 (hereinafter referred to as the N-type semiconductor region 42) for each pixel 2. The N-type semiconductor region 42 is the photoelectric conversion part of the pixel 2 that converts incident light into signal charge and stores the signal charge generated by the photoelectric conversion. The semiconductor substrate 31 has a first surface FA and a second surface SA. The first surface FA is the light-receiving surface to which the light to be photoelectrically converted is incident, and the second surface SA is the transistor-forming surface on which pixel transistors (not shown), such as a transfer transistor TG and an amplification transistor AMP, are formed. Two insulating layers, a first insulating layer 32 and a second insulating layer 33, are formed on the second surface SA of the semiconductor substrate 31. The first insulating layer 32 and the second insulating layer 33 are different types of insulating layers. For example, the first insulating layer 32 is silicon oxide (SiO2), and the second insulating layer 33 is silicon nitride (SiN).

[0038] At the boundary between adjacent pixels on the semiconductor substrate 31, a pixel isolation region 43 is formed that penetrates the semiconductor substrate 31 and separates the photodiode PD of each pixel 2. P-type semiconductor regions 41 are formed in the vicinity of the first surface FA and the second surface SA of the semiconductor substrate 31, and in the vicinity of the pixel isolation region 43, with an N-type semiconductor region 42 formed inside them. The P-type semiconductor region 41 in the vicinity of the first surface FA of the semiconductor substrate 31 also serves as a hole charge accumulation region for suppressing dark current.

[0039] The pixel separation section 43 includes a first trench 44 on the first surface FA side of the semiconductor substrate 31 and a second trench 45 on the second surface SA side. The first trench 44 and the second trench 45 are connected by a connecting section 46, which is located closer to the second surface SA than to the first surface FA of the semiconductor substrate 31. The first trench 44 is a forward-tapered trench in which the opening width (opening area) gradually decreases from the first surface FA to the second surface SA side of the semiconductor substrate 31. The second trench 45 is a trench that has the same opening width (opening area) at any depth position. Note that the first trench 44 may not be a forward-tapered shape, but rather a shape that does not have a taper and has the same opening width at any depth position.

[0040] Inside the first trench 44, a first insulating layer 51, a first conductor layer 52, and a second insulating layer 53 are arranged in that order from the side wall side toward the inside. In other words, the first conductor layer 52 sandwiches the second insulating layer 53 on the inside (center of the trench), and the outer first insulating layer 51 sandwiches the inner first conductor layer 52 and the second insulating layer 53. The second trench 45 is composed of a first insulating layer 51 formed on the side wall side and a second insulating layer 53 inside it, and the first conductor layer 52 is not formed in the second trench 45. For the materials of the first insulating layer 51 and the second insulating layer 53, for example, SiO2, SiC, SiON, etc. can be used. For the material of the first conductor layer 52, silicon materials doped with impurities such as BDAS (Bron Doped Amorphous Silicon), PDAS (Phosphorus Doped Amorphous Silicon), and B-poly (Bron Doped Poly-silicon) can be used.

[0041] On the first surface FA of the semiconductor substrate 31, a fixed charge film 34, an anti-reflective film 35, an insulating layer 36, a second conductive layer 37, and an insulating layer 38 are stacked in that order. For the fixed charge film 34, oxide films such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), lanthanum oxide (La2O3), and yttrium oxide (Y2O3) can be used. For the anti-reflective film 35, materials such as silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), and lanthanum oxide (La2O3) can be used. Materials such as silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON) can be used for the insulating layer 36 and the insulating layer 38.

[0042] The material used for the second conductor layer 37 is a transparent electrode material that transmits light. Furthermore, the material used for the second conductor layer 37 is one whose light absorption coefficient is smaller than that of the first conductor layer 52. For example, transparent electrode materials such as InO, ITO, IGZO, and ZnO can be used for the second conductor layer 37. As will be described in detail with reference to Figure 5, the second conductor layer 37 is in contact with the first conductor layer 52 of the pixel separation section 43 at the cross section 100CR of the pixel 2 and is electrically connected. A negative bias supplied at the outer periphery of the pixel array section 3 is applied to the second conductor layer 37. By applying a negative bias to the second conductor layer 37, the region near the first trench 44 of the photodiode PD can be made into a high hole concentration state (hole accumulation state), and the generation of dark current in the region near the first trench 44 can be suppressed.

[0043] A color filter layer 71 is formed on the upper surface of the insulating layer 38. The color filter layer 71 is formed by rotary coating, for example, a photosensitive resin containing a pigment or dye. The color filter layer 71 has a predetermined arrangement, such as a Bayer array, of R (red), G (green), or B (blue), with 4 pixels in a 2x2 arrangement corresponding to one on-chip lens 77 being the same color unit.

[0044] Further, an inter-pixel light shielding wall 72 is disposed at a boundary between adjacent pixels in the color filter layer 71. The inter-pixel light shielding wall 72 is composed of a light shielding film 73, an insulating film 74, a low-refractive index film 75, and an insulating film 76. The light shielding film 73 has, for example, a two-layer structure of TiN / Ti, a two-layer structure of W / Ti, or the like. The light shielding film 73 can also be configured as a three-layer structure or a four-layer structure using two or more types of materials. The insulating film 74 and the insulating film 76 are each composed of an oxide film such as SiO2, for example. The low-refractive index film 75 is composed of a film having a lower refractive index than that of the color filter layer 71.

[0045] An on-chip lens 77 is formed on the upper surface of the color filter layer 71. The on-chip lens 77 is disposed so as to be shared by four 2×2 pixels. The on-chip lens 77 is formed of a resin material such as a styrene-based resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane-based resin, for example.

[0046] 4A is a diagram illustrating the arrangement of the on-chip lenses 77 and the pixel separation portions 43.

[0047] As shown in FIG. 4A, one on-chip lens 77 is disposed so as to be shared by four 2×2 pixels in a plan view. The pixel separation portions 43 are formed in a grid pattern so as to separate the photodiodes PD of each pixel 2.

[0048] 4B is a plan view showing a detailed configuration of the pixel separation portion 43.

[0049] Among the pixel separation portions 43 formed in a grid pattern in a plan view, an intersection portion (a corner portion of the pixel 2) where a linearly extending portion extending in the row direction and a linearly extending portion extending in the column direction of the pixel array portion 3 intersect each other is defined as a cross portion 100CR, and linear portions parallel to the row direction or the column direction other than the cross portion 100CR are defined as slit portions 100SL.

[0050] The slit portion 100SL has a first insulating layer 51 on a side (outer side) closest to the side wall of the first trench 44 (FIG. 3), a first conductor layer 52 inside the first insulating layer 51, and a second insulating layer 53 inside the first conductor layer 52.

[0051] On the other hand, the cross section 100CR has a first insulating layer 51 on the side (outside) closest to the side wall of the first trench 44 (Figure 3), a first conductor layer 52 inside the first insulating layer 51, and a second conductor layer 37 inside the first conductor layer 52.

[0052] Figure 5 is a cross-sectional view of the cross section 100CR corresponding to the Y-Y' line in Figure 4B. The right cross section 100CR in Figure 5 corresponds to the Y-Y' line in Figure 4B, and the left cross section 100CR is another diagonally adjacent cross section 100CR. Note that the plan view shown in Figure 4B corresponds to the X-X' line in Figure 5.

[0053] As shown in Figure 5, the cross portion 100CR of the pixel separation portion 43 includes a second conductor layer 37 from the first surface FA of the semiconductor substrate 31 to a predetermined depth, and the second conductor layer 37 is in contact with the first conductor layer 52 within the semiconductor substrate 31 and is electrically connected to it. The focusing point FC of the on-chip lens 77 is included in the region in which the second conductor layer 37 is embedded. Inside the first trench 44, from the side wall side toward the inside, a first insulating layer 51, a first conductor layer 52, a second conductor layer 37, and a second insulating layer 53 are provided in that order, and the second conductor layer 37 and the second insulating layer 53 are provided at different depths in the semiconductor substrate 31. In other words, the first conductor layer 52 sandwiches the second insulating layer 53 and the second conductor layer 37 on the inside (center of the trench), and the outer first insulating layer 51 is provided so as to sandwich the inner first conductor layer 52, the second insulating layer 53, and the second conductor layer 37. Furthermore, as shown in Figure 3, in the slit portion 100SL of the pixel separation portion 43, the second conductor layer 37 is formed only on the upper side of the insulating layer 36 and is not connected to the pixel separation portion 43. In contrast, in the cross portion 100CR of the pixel separation portion 43, as shown in Figure 5, the fixed charge film 34, the anti-reflective film 35, and the insulating layer 36 are open, and the second conductor layer 37 formed on the upper layer of the first surface FA side of the semiconductor substrate 31 is connected to the second conductor layer 37 in the first trench 44.

[0054] The cross portion 100CR of the pixel separation portion 43 differs from the slit portion 100SL not only in the embedded region of the second conductor layer 37 near the first surface FA of the semiconductor substrate 31, but also in the embedding material of the second trench 45. In the slit portion 100SL, the second trench 45 was embedded with the insulating materials of the first insulating layer 51 and the second insulating layer 53, but in the cross portion 100CR, the second trench 45 is embedded with the first insulating layer 51 and the contact electrode 111, and the contact electrode 111 is connected to metal wiring (not shown) in the wiring layer. The contact electrode 111 is connected to a floating diffusion FD formed in a high-concentration N-type semiconductor region, or to a well contact formed in a high-concentration P-type semiconductor region. The contact electrode 111 connected to the floating diffusion FD is made of, for example, N-type polysilicon, and the contact electrode 111 connected to the well contact is made of, for example, P-type polysilicon.

[0055] As is clear from the arrangement of the on-chip lens 77 in Figure 4A, the cross portion 100CR of the pixel separation portion 43 is the region that includes the focal point FC of the on-chip lens 77 in a plan view, and more specifically, the focal point FC is the region of the second conductor layer 37. If a material with a large light absorption coefficient is placed in the region that includes the focal point FC of the on-chip lens 77, the quantum efficiency (QE) of the photodiode PD will deteriorate.

[0056] Therefore, in the cross portion 100CR of the pixel separation portion 43, a second conductor layer 37 made of a material with a small light absorption coefficient is arranged in the region including the focal point FC of the on-chip lens 77 in a plan view. This suppresses the degradation of quantum efficiency. The second conductor layer 37 is in contact with the first conductor layer 52 near the light-receiving surface (first surface FA) side of the semiconductor substrate 31 and is electrically connected. The first conductor layer 52 is formed along the side wall of the first trench 44 of the pixel separation portion 43, extending over the entire depth of the first trench 44. Since a negative bias is applied to the second conductor layer 37, the generation of dark current in the region near the first trench 44 can be suppressed.

[0057] The second conductor layer 37, which serves as a negative bias transmission path, is formed on the entire first surface FA side of the semiconductor substrate 31 and on the cross portion 100CR of the pixel separation portion 43. The cross portion 100CR includes the focal point FC of the on-chip lens 77. By providing the second conductor layer 37, which is made of a material with a smaller light absorption coefficient than the first conductor layer 52, in the region including the focal point FC, the degradation of quantum efficiency in the pixel separation portion 43 is suppressed. This makes it possible to improve the quantum efficiency of the photodiode PD.

[0058] Therefore, according to the pixel structure of the first embodiment, the quantum efficiency of the photodiode PD can be improved.

[0059] <4. Negative Bias Transmission Path> As described above, a negative bias is applied to the first conductor layer 52 of the pixel separation section 43 via the second conductor layer 37. The negative bias transmission path will be explained with reference to Figure 6.

[0060] The pixel array section 3, in a plan view, consists of an effective pixel area 3A and an outer OPB area 3B. Furthermore, a terminal area 121 is provided on the outside of the pixel array section 3, where electrode pads and the like are provided as external input / output terminals.

[0061] Figure 6 is a cross-sectional view of the slit portion 100SL and cross portion 100CR of the effective pixel area 3A, the slit portion 200SL and cross portion 200CR of the OPB area 3B, and the pad connection portion 300EX of the terminal area 121.

[0062] The configuration of the slit portion 100SL and cross portion 100CR in the effective pixel area 3A is the same as in Figures 3 and 5. The configuration of the slit portion 200SL and cross portion 200CR in the OPB area 3B will be explained, focusing on the differences from the slit portion 100SL and cross portion 100CR in the effective pixel area 3A.

[0063] The slit portion 200SL and cross portion 200CR of the OPB region 3B are constructed by embedding contact electrodes 112 in the second trench 45. The contact electrodes 112 are made of, for example, P-type polysilicon or a metal material and are connected to metal wiring (not shown) in the wiring layer. The contact electrodes 112 are connected to the first conductor layer 52 of the first trench 44, and the negative bias supplied from the metal wiring in the wiring layer to the contact electrodes 112 is supplied to the first conductor layer 52 of the slit portion 100SL and cross portion 100CR of the effective pixel region 3A via the first conductor layer 52 and second conductor layer 37 of the first trench 44 of the slit portion 200SL and cross portion 200CR.

[0064] The pad connection portion 300EX of the terminal region 121 includes an electrode pad 114 to which a negative bias is input to be applied to the substrate region 122 of the semiconductor substrate 31. The electrode pad 114 is formed using, for example, tungsten (W), aluminum (Al), copper (Cu), etc., and is physically connected to the substrate region 122. The negative bias is supplied to the electrode pad 114 via a bonding wire or the like, and then applied to the substrate region 122. The second trench 45 of the pad connection portion 300EX is configured with a contact electrode 113 embedded in it. The contact electrode 113 is made of N-type or P-type polysilicon.

[0065] As described above, the negative bias supplied to the contact electrode 112 on the second surface SA side of the semiconductor substrate 31 in the OPB region 3B is taken out to the first surface FA side of the semiconductor substrate 31, transmitted through the second conductor layer 37 on the first surface FA side, and supplied to the pixel separation section 43 of the effective pixel region 3A. In this way, the negative bias terminal (contact electrode 112) can be provided separately from the negative bias applied to the substrate region 122, and a different potential can be set for the negative bias applied to the substrate.

[0066] If the negative bias supplied to the pixel separation unit 43 and the negative bias applied to the substrate region 122 can be at the same potential, then the electrode pad 114 and the second conductor layer 37 can be connected as shown in Figure 7. In this case, the negative bias supplied to the electrode pad 114 and the contact electrode 112 is supplied to the second conductor layer 37 and the first conductor layer 52 of the first trench 44 of the effective pixel region 3A via the second conductor layer 37 on the first surface FA side of the semiconductor substrate 31. The contact electrode 112 of the slit portion 200SL and cross portion 200CR of the OPB region 3B may be omitted.

[0067] <5. Example of Pixel Configuration in the Second Embodiment> Figure 8 is a plan view illustrating the pixels according to the second embodiment.

[0068] Figure 8A is a plan view showing the arrangement of the on-chip lens 77 and the pixel separation unit 43, similar to Figure 4A in the first embodiment, and Figure 8B is a plan view showing the detailed configuration of the pixel separation unit 43, similar to Figure 4B in the first embodiment.

[0069] In the first embodiment described above, the pixel 2 had four 2x2 photodiodes PD, which are lens-sharing units sharing one on-chip lens 77, completely separated by a grid-like pixel separation section 43. In contrast, in the second embodiment, as shown in Figure 8A, the four pixels of the lens-sharing unit are connected by a P-type semiconductor region 41 at the center, and are not completely separated by a pixel separation section 43 for each pixel. In other words, in a plan view, the pixel separation section 43 (cross section 100CR) at the focal point FC of the on-chip lens 77 is replaced by a P-type semiconductor region 41. Cross sections 100CR of the pixel separation section 43 are provided at the corners of the pixels 2 that form the four corners of the lens-sharing unit. In a plan view, the pixel separation section 43 is formed as a pixel boundary portion at the outer periphery of the lens-sharing unit and a slit section 100SL protruding from the outer periphery of the lens-sharing unit toward the center of the lens-sharing unit (the focal point FC of the on-chip lens 77). In the second embodiment, the slit portion 100SL that protrudes from the outer periphery of the lens sharing unit toward the central part of the lens sharing unit will hereinafter be referred to as the "protruding portion 100SLX".

[0070] In this second embodiment of the pixel structure, since there is no pixel separation portion 43 in the central part of the lens-sharing unit, the second conductor layer 37 is not arranged in the region including the focal point FC of the on-chip lens 77. In plan view, the protruding portion 100SLX has a second conductor layer 37 near the center of the width in a direction perpendicular to the direction from the outer periphery to the central part of the lens-sharing unit, between the four pixels that constitute the lens-sharing unit, and a second insulating layer 53 near the photodiode PD on both sides thereof. In cross-sectional view, the protruding portion 100SLX is provided in the order of a first insulating layer 51, a first conductor layer 52, a second insulating layer 53, and a second conductor layer 37 from the outside. In the substrate depth direction, the second conductor layer 37 of the protruding portion 100SLX is formed near the first surface FA of the semiconductor substrate 31.

[0071] <6. Example of Pixel Configuration in the Third Embodiment> Figure 9 is a plan view illustrating a pixel according to the third embodiment.

[0072] Figure 9A is a plan view showing the arrangement of the on-chip lens 77 and the pixel separation unit 43, and Figure 9B is a plan view showing the detailed configuration of the pixel separation unit 43.

[0073] The third embodiment is an example of a rectangular pixel, where the pixel shape of pixel 2 is rectangular, and the pixel area of ​​two adjacent pixels is square. As shown in Figure 9A, one on-chip lens 77 is shared by two square-shaped pixels, so the lens sharing unit is two pixels.

[0074] A P-type semiconductor region 41 is provided in the center of the two pixels of the lens-sharing unit, and the two pixels of the lens-sharing unit are not completely separated by the pixel separation portion 43. In other words, in a plan view, the region that becomes the focal point FC of the on-chip lens 77 is provided with the P-type semiconductor region 41, not the pixel separation portion 43. Cross portions 100CR of the pixel separation portion 43 are provided at the corners of the pixels 2 that form the four corners of the lens-sharing unit. The pixel separation portion 43 between the two pixels of the lens-sharing unit is a protruding portion 100SLX.

[0075] In this third embodiment of the pixel structure, since there is no pixel separation portion 43 in the central part of the lens-sharing unit, the second conductor layer 37 is not arranged in the region including the focal point FC of the on-chip lens 77. In plan view, the protruding portion 100SLX has a second conductor layer 37 near the center of the width in a direction perpendicular to the direction from the outer periphery to the central part of the lens-sharing unit, between two pixels which are the lens-sharing unit, and a second insulating layer 53 near the photodiode PD on both sides thereof. In cross-sectional view, the protruding portion 100SLX is provided in the order of a first insulating layer 51, a first conductor layer 52, a second insulating layer 53, and a second conductor layer 37 from the outside. In the substrate depth direction, the second conductor layer 37 of the protruding portion 100SLX is formed near the first surface FA of the semiconductor substrate 31.

[0076] <7. Example of Pixel Configuration in the Fourth Embodiment> Figure 10 is a plan view illustrating the pixels according to the fourth embodiment.

[0077] Figure 10A is a plan view showing the arrangement of the on-chip lens 77 and the pixel separation unit 43, and Figure 10B is a plan view showing the detailed configuration of the pixel separation unit 43.

[0078] The fourth embodiment differs from the first embodiment in the unit in which a single on-chip lens 77 is arranged. In the first embodiment, one on-chip lens 77 was arranged for 4 pixels in a 2x2 arrangement, but in the fourth embodiment, one on-chip lens 77 is arranged for each pixel. That is, the pixel 2 according to the fourth embodiment has a pixel structure in which the on-chip lens 77 is not shared by multiple pixels, but is arranged for each pixel. The arrangement and detailed configuration of the pixel separation unit 43 are the same as in the first embodiment.

[0079] <8. Example of Pixel Configuration in the Fifth Embodiment> Figure 11 is a plan view illustrating a pixel according to the fifth embodiment.

[0080] Figure 11A is a plan view showing the arrangement of the on-chip lens 77 and the pixel separation unit 43, and Figure 11B is a plan view showing the detailed configuration of the pixel separation unit 43.

[0081] The fifth embodiment shows an example in which the unit for arranging a single on-chip lens 77 is a mix of a pixel unit and a 1x2 pixel unit. The region including the condensation point FC of the on-chip lens 77 with a lens sharing unit of 1x2 pixels is the slit portion 100SL of the pixel separation portion 43, as shown in Figure 11B, and the second conductor layer 37 is not arranged therein. The on-chip lenses 77 with a lens sharing unit of 1x2 pixels may be arranged regularly or randomly in the pixel array portion 3. An on-chip lens 77 with a lens sharing unit of 1x2 pixels may be arranged for all pixels in the pixel array portion 3. The on-chip lenses 77 with a lens sharing unit of 1x2 pixels may be arranged in a mix of a horizontal 1x2 pixel arrangement and a vertical 2x1 pixel arrangement. The arrangement and detailed configuration of the pixel separation portion 43 are the same as in the first embodiment.

[0082] In the second to fifth embodiments described above, when a single on-chip lens 77 is shared by multiple pixels, the second conductor layer 37 is not arranged in the region including the focal point FC of the on-chip lens 77 in a plan view. Therefore, the degradation of quantum efficiency in the pixel separation section 43 can be suppressed. Accordingly, the quantum efficiency of the photodiode PD can also be improved in the pixel structures of the second to fifth embodiments.

[0083] <9. First and Second Modified Examples of the Pixel Separation Unit> Next, modified examples of the pixel separation unit 43 will be described. The structure of the pixel separation unit 43 in the first embodiment described above will be referred to as the basic structure of the pixel separation unit 43.

[0084] Figure 12 is a first modified example of the pixel separation section 43 and a cross-sectional view showing a modified example of the cross section 100CR.

[0085] In the cross section 100CR of the basic structure described above, the inside of the first conductor layer 52 of the first trench 44 was filled with the second insulating layer 53. In contrast, in the cross section 100CR of the first modified example, a gap 151 is formed in the center of the width of the inside of the first conductor layer 52 of the first trench 44, and is filled with air 152. Therefore, the inside of the first conductor layer 52 consists of the second insulating layer 53 and air 152. As shown in the second modified example in Figure 13, a fixed charge film 153 may be embedded in the gap 151 in the center of the width of the inside of the first conductor layer 52. The fixed charge film 153 may be made of the same material as the fixed charge film 34 formed on the first surface FA of the semiconductor substrate 31, or it may be made of a different material. If the fixed charge film 34 and the fixed charge film 153 are made of the same material, they can be formed simultaneously. Even when air 152 or a fixed charge film 153 is provided inside the second insulating layer 53, the quantum efficiency is about the same as that of the basic structure described above.

[0086] <10. Third Modification of Pixel Separation Section> Figure 14 is a third modification of the pixel separation section 43, and is a cross-sectional view showing a modification of the cross section 100CR.

[0087] In the cross section 100CR of the basic structure described above, a second conductor layer 37 is formed on the insulating layer 36 of the first surface FA of the semiconductor substrate 31, and the second conductor layer 37 is embedded to a predetermined depth within the semiconductor substrate 31. In contrast, in the cross section 100CR of the third modified example, the second conductor layer 37 is not formed on the insulating layer 36 on the first surface FA side of the semiconductor substrate 31, and the second conductor layer 37 is formed only within the first trench 44. The insulating layer 36 and the insulating layer 38 may be made of the same material and integrated.

[0088] Thus, even if the second conductor layer 37 is not provided over the entire surface of the first surface FA of the semiconductor substrate 31, and is only provided within the first trench 44 of the cross portion 100CR, the second conductor layer 37 of the cross portion 100CR is electrically connected to other adjacent cross portions 100CR via the first conductor layer 52 provided around the photodiode PD of each pixel 2. Therefore, the negative bias can be supplied to the first conductor layer 52 of the first trench 44 of all pixels in the pixel array portion 3.

[0089] <11. Fourth Modification of Pixel Separation Section> Figure 15 is a fourth modification of the pixel separation section 43, and is a cross-sectional view showing a modification of the cross section 100CR.

[0090] In the cross section 100CR of the basic structure described above, the second conductor layer 37 extends to a predetermined depth within the semiconductor substrate 31, and the second insulating layer 53 is embedded below the second conductor layer 37 within the first trench 44. In other words, the area inside the first conductor layer 52 within the first trench 44 has a two-layer embedded structure consisting of the second conductor layer 37 and the second insulating layer 53.

[0091] In contrast, in the cross section 100CR of the fourth modified example shown in Figure 15, only the second conductor layer 37 is embedded inside the first conductor layer 52 within the first trench 44. The second conductor layer 37 is embedded to the same depth as the first conductor layer 52. By omitting the second insulating layer 53 within the first trench 44 and using the second conductor layer 37 instead, the contact area between the second conductor layer 37 and the first conductor layer 52 can be increased. This reduces the resistance of the negative bias transmission line and suppresses IR drop.

[0092] <12. Fifth Modification of Pixel Separation Section> Figure 16 is a fifth modification of the pixel separation section 43, and is a cross-sectional view showing a modification of the cross section 100CR.

[0093] In the fifth modified example shown in Figure 16, the second conductor layer 37 of the cross portion 100CR of the basic structure described above is replaced with a conductive metal thin film 161. Specifically, the metal thin film 161 is formed on the upper surface of the fixed charge film 34 on the first surface FA, and the metal thin film 161 is also provided in the cross portion 100CR and is in contact with the first conductor layer 52. An insulating layer 36 is formed on top of the metal thin film 161, and the insulating layer 36 is also embedded in the first trench 44 of the cross portion 100CR. The material of the metal thin film 161 can be, for example, TiN.

[0094] Whether the conductor that transmits the negative bias and connects to the first conductor layer 52 is the second conductor layer 37 or the metal thin film 161 can be appropriately determined according to the contact characteristics with the first conductor layer 52.

[0095] <13. Sixth Modification of Pixel Separation Section> Figure 17 is a sixth modification of the pixel separation section 43, and is a cross-sectional view showing a modification of the slit section 100SL.

[0096] In the first embodiment described above, in the slit portion 100SL, the second conductor layer 37 on the upper layer of the first surface FA of the semiconductor substrate 31 was separated from the first conductor layer 52 in the first trench 44 by a fixed charge film 34, an anti-reflective film 35, and an insulating layer 36, without contact.

[0097] However, as shown in Figure 17, in the slit portion 100SL, similar to the cross portion 100CR, the fixed charge film 34, the anti-reflective film 35, and the insulating layer 36 may be opened, and the second conductor layer 37 may be embedded to a predetermined depth in the semiconductor substrate 31 and connected to the first conductor layer 52 in the first trench 44.

[0098] Figure 18 is a plan view along the line X-X' in Figure 17.

[0099] In the slit portion 100SL, if the second conductor layer 37 is embedded to a predetermined depth within the semiconductor substrate 31, as shown in Figure 18, the second conductor layer 37 is formed in the region near the first surface FA of the semiconductor substrate 31 over the entire area of ​​the grid-like pixel separation portion 43. By embedding the second conductor layer 37 to a predetermined depth within the semiconductor substrate 31 in the slit portion 100SL, the area in contact with the first conductor layer 52 in the first trench 44 is increased, which reduces the resistance of the negative bias transmission line and suppresses IR drop.

[0100] <14. Method for Manufacturing the Inter-Pixel Separation Section> Next, the method for manufacturing the pixel separation section 43 will be described with reference to Figures 19 to 28.

[0101] First, as shown in Figure 19A, a first insulating layer 32 and a second insulating layer 33 are formed on the upper surface of the second surface SA of the semiconductor substrate 31, for example, using a CVD method. The first insulating layer 32 and the second insulating layer 33 are different types of insulating layers; for example, the first insulating layer 32 is silicon oxide (SiO2) and the second insulating layer 33 is silicon nitride (SiN). Then, a first trench 44 and a second trench 45 are formed in the region that will become the slit portion 100SL and the cross portion 100CR, for example, using a lithography method and a dry etching method, and a first insulating layer 51 is formed on the inner and bottom surfaces of the first trench 44 and the second trench 45, and on the upper surface of the second insulating layer 33. The first insulating layer 51 can be, for example, silicon oxide (SiO2), and can be formed using, for example, the ISSG method or the ALD method. After forming the film with the ISSG method, it may be further formed with the ALD method. The first trench 44 is formed in a tapered shape (reverse tapered shape) where the trench width (opening area) increases from the second surface SA side to the first surface FA side. The trench width of the second trench 45 is the same regardless of its depth. The connection portion 46 between the first trench 44 and the second trench 45 is located closer to the second surface SA than to the first surface FA.

[0102] Next, as shown in Figure 19B, a first conductor layer 52 is formed on top of the first insulating layer 51 formed on the inner and bottom surfaces of the first trench 44 and the second trench 45. The material of the first conductor layer 52 can be, for example, BDAS, and it can be formed using the LPCVD method.

[0103] Next, as shown in Figure 20A, the first conductor layer 52 above the second trench 45 (on the second surface SA side) is removed by etch-back, and then, as shown in Figure 20B, a second insulating layer 53 is formed on the inner and bottom surfaces of the first trench 44 and the second trench 45, for example, using the ALD method. At this time, the first trench 44 has an inverse taper shape in which the trench width increases from the second surface SA side to the first surface FA side, and the trench width at the connection portion 46 between the first trench 44 and the second trench 45 is narrow, so the connection portion 46 is closed by the formed second insulating layer 53, and the second insulating layer 53 is embedded in the second trench 45 above the connection portion 46. A gap 151 is formed in the first trench 44.

[0104] Alternatively, as shown in Figures 21A, B, and C, the second insulating layer 53 (53A, 53B, 53C) may be formed by sequentially depositing the second insulating layers 53A, 53B, and 53C on the inner and bottom surfaces of the first trench 44 and the second trench 45. The second insulating layer 53A may be, for example, a silicon oxide film produced by the ALD method, and the second insulating layers 53B and 53C may be, for example, silicon oxide films produced by the CVD method. The second insulating layers 53B and 53C can be NSG (Non-dope Silicate Glass) films, HDP (High Density Plasma) oxide films, TEOS films, etc.

[0105] In this example, in both the formation method of B in Figure 20 and the formation method in Figure 21, a void 151 is formed in the first trench 44. However, the second insulating layer 53 may be embedded so that there is no void 151.

[0106] Next, as shown in Figure 22, a portion of the second insulating layer 53 embedded in the cross portion 100CR of the effective pixel region 3A and the second trench 45 of the slit portion 200SL and cross portion 200CR of the OPB region 3B is removed to form a shallow trench 182. Then, as shown in Figure 23, a contact electrode 111 or 112 is embedded in the formed shallow trench 182. The contact electrode 111 is made of N-type polysilicon when connected to a floating diffusion FD, and of P-type polysilicon when connected to a well contact. The contact electrode 112 is made of, for example, P-type polysilicon or a metallic material. In Figure 23, when forming the shallow trench 182, even if the shallow trench 182 reaches the connection portion 46 between the first trench 44 and the second trench 45, and the contact electrodes 111 and 112 penetrate into the gap 151, it does not affect the characteristics because it is in a negative bias region.

[0107] Next, as shown in Figure 24, the semiconductor substrate 31 is inverted so that the first surface FA side of the semiconductor substrate 31 becomes the upper surface, and then, as shown in Figure 25, the semiconductor substrate 31 is thinned. For example, the CMP (Chemical Mechanical Polishing) method can be used to thin the semiconductor substrate 31. It is not a problem if the void 151 is exposed due to the thinning.

[0108] Next, as shown in Figure 26, a fixed charge film 34, an anti-reflective film 35, and an insulating layer 36 are sequentially deposited on the upper surface of the first surface FA side of the semiconductor substrate 31. At this time, the fixed charge film 34 is embedded in the void 151 of the first trench 44, but this does not affect the quantum efficiency and is not a problem.

[0109] Next, as shown in Figure 27, trenches 183 are formed only in the cross portion 100CR of the effective pixel region 3A, the cross portion 200CR of the OPB region 3B, and the pad connection portion 300EX of the terminal region 121, using methods such as lithography and dry etching, from the first surface FA side of the semiconductor substrate 31 to a predetermined depth within the semiconductor substrate 31.

[0110] Next, as shown in Figure 28, a second conductor layer 37 is formed inside the formed trench 183 and on the upper surface of the insulating layer 36, and an insulating layer 38 is further formed on the upper surface of the second conductor layer 37. For the material of the second conductor layer 37, a transparent electrode material such as InO, ITO, IGZO, or ZnO is used. The insulating layer 38 is composed of an oxide film such as SiO2. An electrode pad 114 is formed in the trench 183 of the pad connection portion 300EX of the terminal region 121. The electrode pad 114 is formed using a metallic material such as tungsten (W), aluminum (Al), or copper (Cu).

[0111] Although not shown in the diagram, in the process after Figure 28, a color filter layer 71 and an inter-pixel light-shielding wall 72 are formed on the upper surface of the insulating layer 38, after which the on-chip lens 77 is formed.

[0112] <15. Summary of Embodiments> The photodetector element 1 comprises a semiconductor substrate 31, a plurality of photoelectric conversion units (N-type semiconductor regions 42) arranged in a matrix on the semiconductor substrate 31, a plurality of on-chip lenses 77 arranged on the first surface FA side which is the light-receiving surface of the semiconductor substrate 31, and a first trench 44 formed in at least a part of the region between the photoelectric conversion units of the semiconductor substrate 31. The first trench 44 has a first conductor layer 52 made of a first conductive material and a second conductor layer 37 made of a second conductive material which has a smaller light absorption coefficient than the first conductive material. In cross-sectional view, the second conductor layer 37 is provided inside the first trench 44 more than the first conductor layer 52 and is connected to the first conductor layer 52 in the vicinity region of the first surface FA of the semiconductor substrate 31.

[0113] With the above configuration, even if the focal point FC of the on-chip lens 77 is located in the pixel separation section 43, the second conductor layer 37 of the first trench 44, which includes the focal point FC, uses a conductive material with a low light absorption coefficient, thus suppressing the degradation of quantum efficiency caused by the pixel separation section 43.

[0114] In the embodiments described above, examples of sharing the on-chip lens 77 among multiple pixels were explained, specifically in the case of sharing among 1x2 pixels and 2x2 pixels. However, the lens sharing unit is not limited to these examples. For example, the lens sharing unit could be set to 3x3 pixels, and one on-chip lens 77 could be shared among 9 pixels.

[0115] <16. Examples of Application to Electronic Devices> The technology of this disclosure is not limited to application to photodetectors. That is, the technology of this disclosure is applicable to all electronic devices that use photodetectors in the image acquisition unit (photoelectric conversion unit), such as imaging devices such as digital still cameras and video cameras, portable terminal devices with imaging functions, and photocopiers that use photodetectors in the image reading unit. The photodetector may be formed as a single chip, or it may be in the form of a module with imaging functions in which the imaging unit and the signal processing unit or optical system are packaged together.

[0116] Figure 29 is a block diagram showing an example configuration of an electronic device to which the technology of this disclosure is applied.

[0117] The electronic device 500 in Figure 14 is, for example, an imaging device capable of capturing still and moving images, such as a digital still camera or a digital video camera. The electronic device 500 may also be a mobile phone, smartphone, IoT (Internet of Things) camera, or in-vehicle camera equipped with imaging capabilities.

[0118] The electronic device 500 in Figure 14 includes an optical unit 501 consisting of a lens group, a photodetector (imaging device) 502 employing the configuration of the photodetector 1 in Figure 1, and a DSP (Digital Signal Processor) circuit 503 which is a camera signal processing circuit. The electronic device 500 also includes a frame memory 504, a display unit 505, a recording unit 506, an operation unit 507, and a power supply unit 508. The DSP circuit 503, frame memory 504, display unit 505, recording unit 506, operation unit 507, and power supply unit 508 are interconnected via a bus line 509.

[0119] The optical unit 501 captures incident light (image light) from the subject and forms an image on the imaging surface of the photodetector element 502. The photodetector element 502 converts the amount of incident light formed on the imaging surface by the optical unit 501 into an electrical signal on a pixel-by-pixel basis and outputs it as a pixel signal. As this photodetector element 502, the photodetector element 1 in Figure 1, that is, a photodetector element that suppresses the generation of dark current while suppressing the degradation of quantum efficiency, can be used by applying a negative bias to the pixel separation section 43 in which the first conductor layer 52 and the second conductor layer 37 are connected in the vicinity region of the first surface FA of the semiconductor substrate 31.

[0120] The display unit 505 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays a video or still image captured by the photodetector element 502. The recording unit 506 records the video or still image captured by the photodetector element 502 onto a recording medium such as a hard disk or semiconductor memory.

[0121] The operation unit 507 issues operation commands for various functions of the electronic device 500 under the user's input. The power supply unit 508 appropriately supplies various power sources to the DSP circuit 503, frame memory 504, display unit 505, recording unit 506, and operation unit 507.

[0122] As described above, by using a photodetector 1 having pixels 2 according to the first to fifth embodiments described above as the photodetector 502, it is possible to suppress the generation of dark current while suppressing the deterioration of quantum efficiency. Therefore, even in electronic devices 500 such as video cameras, digital still cameras, and camera modules for mobile devices such as mobile phones, miniaturization and improvement of the image quality of captured images can be achieved.

[0123] <17. Examples of Image Sensor Use> Figure 30 shows an example of using an image sensor with the above-described photodetector 1.

[0124] The above-described photodetector 1 can be used as an image sensor in various cases where light such as visible light, infrared light, ultraviolet light, and X-rays is sensed, for example, as follows.

[0125] - Devices that capture images for viewing purposes, such as digital cameras and portable devices with camera functions. - Devices used for traffic purposes, such as in-vehicle sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. - Devices used in home appliances such as TVs, refrigerators, and air conditioners that capture user gestures and allow device operation according to those gestures. - Devices used for medical and healthcare purposes, such as endoscopes and devices that perform angiography using infrared light reception. - Devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person recognition. - Devices used for beauty purposes, such as skin measuring devices that capture images of skin and microscopes that capture images of the scalp. - Devices used for sports purposes, such as action cameras and wearable cameras for sports use. - Devices used for agriculture, such as cameras that monitor the condition of fields and crops.

[0126] In the example described above, a photodetector element using electrons as the signal charge was explained, with the first conductivity type being N-type and the second conductivity type being P-type. However, this disclosure can also be applied to a photodetector element using holes as the signal charge. In this case, the first conductivity type can be P-type and the second conductivity type can be N-type, and the aforementioned semiconductor regions can be composed of semiconductor regions of the opposite conductivity types.

[0127] Furthermore, this disclosure is not limited to photodetectors that detect the distribution of incident light intensity of visible light and capture it as an image, but is also applicable to photodetectors that capture the distribution of incident amounts of infrared rays, X-rays, or particles as an image, and in a broader sense, to all photodetectors (physical quantity distribution detection devices) such as fingerprint detection sensors that detect the distribution of other physical quantities such as pressure and capacitance and capture it as an image.

[0128] Furthermore, the technology disclosed herein is applicable not only to photodetectors but also to semiconductor devices in general that have other semiconductor integrated circuits.

[0129] The embodiments of this disclosure are not limited to those described above, and various modifications are possible without departing from the gist of the technology of this disclosure.

[0130] Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also occur.

[0131] The technology of this disclosure may adopt the following configurations: (1) A photodetector comprising: a semiconductor substrate; a plurality of photoelectric conversion units arranged in a matrix on the semiconductor substrate; a plurality of on-chip lenses arranged on the first surface side which is the light-receiving surface of the semiconductor substrate; and a first trench formed in at least a part of the region between the photoelectric conversion units of the semiconductor substrate, wherein the first trench has a first conductor layer made of a first conductive material and a second conductor layer made of a second conductive material having a smaller light absorption coefficient than the first conductive material, and the second conductor layer is provided in the inside of the first trench than the first conductor layer in a cross-sectional view and is connected to the first conductor layer in a region near the first surface of the semiconductor substrate. (2) The photodetector according to (1), wherein the first trench is provided in the order of a first insulating layer, the first conductor layer, and the second conductor layer from the outside in a cross-sectional view. (3) The photodetector element according to (2), wherein the first trench further has a second insulating layer inside the first conductor layer in a cross-sectional view, and the second conductor layer and the second insulating layer are provided at different depths in the semiconductor substrate. (4) The photodetector element according to any one of (1) to (3), wherein a negative bias is applied to the first conductor layer and the second conductor layer. (5) The photodetector element according to any one of (1) to (4), wherein the on-chip lens is provided shared by 2x2 pixels, and the first trench has the second conductor layer in a region including the focal point of the on-chip lens. (6) The on-chip lens is shared by 2x2 pixels, and the first trench includes a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect in a plan view, and a slit portion which is a linear portion other than the cross portion, and the cross portion of the first trench has the second conductor layer extending to a predetermined depth from the first surface of the semiconductor substrate, as described in any of (1) to (5). (7) The on-chip lens is shared by 2x2 pixels, and in a plan view the region including the focal point of the on-chip lens has a semiconductor region of a second conductivity type opposite to the semiconductor region of a first conductivity type constituting the photoelectric conversion unit, as described in any of (1) to (6).(8) The first trench includes, in plan view, a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect, and a slit portion which is a linear portion other than the cross portion, and the slit portion between the pixels of the four pixels that share the on-chip lens has, in plan view, the second conductor layer near the center of the width, as described in (7). (9) The on-chip lens is shared by two rectangular pixels that form a square shape with two adjacent pixels, and in plan view, the region including the focal point of the on-chip lens has a semiconductor region of a second conductivity type opposite to the semiconductor region of a first conductivity type that constitutes the photoelectric conversion unit, as described in any of (1) to (8). (10) The first trench includes, in plan view, a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect, and a slit portion which is a linear portion other than the cross portion, and the slit portion between the pixels of two pixels sharing the on-chip lens has, in plan view, the second conductor layer near the center of the width, as described in (9). (11) The plurality of on-chip lenses include the on-chip lens shared by 1x2 pixels, as described in any of (1) to (10). (12) The first trench includes air in the center of the width in cross view, as described in any of (1) to (11). (13) The first trench includes a fixed charge film in the center of the width in cross view, as described in any of (1) to (12). (14) The first trench includes, in plan view, a cross portion which is an intersection portion where a straight portion extending in the row direction and a straight portion extending in the column direction intersect, and a slit portion which is a straight portion other than the cross portion, and the second conductor layer is also formed on the upper layer on the first surface side of the semiconductor substrate, and the second conductor layer formed on the upper layer on the first surface side of the semiconductor substrate is connected to the second conductor layer in the first trench at the cross portion of the first trench, the photodetector element according to any one of (1) to (13).(15) The photodetector element according to any one of (1) to (14), wherein the semiconductor substrate further comprises a second trench on the second surface side opposite to the first surface, and the first trench and the second trench include a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect in a plan view, and a slit portion which is a linear portion other than the cross portion, and the cross portion of the second trench includes a contact electrode. (16) The photodetector element according to (15), wherein the second conductor layer is also formed in the upper layer on the first surface side of the semiconductor substrate and is connected to an electrode pad formed on the first surface side of the semiconductor substrate, and a negative bias is supplied to the contact electrode of the cross portion of the second trench outside the effective pixel region, and the negative bias supplied to the electrode pad and the contact electrode is supplied to the first conductor layer and the second conductor layer of the first trench via the second conductor layer formed in the upper layer on the first surface side of the semiconductor substrate.

[0132] 1. Photodetector element, 2. Pixel, 3. Pixel array section, 3A. Effective pixel area, 3B. OPB area, 31. Semiconductor substrate, 32. First insulating layer, 33. Second insulating layer, 34. Fixed charge film, 35. Anti-reflective film, 36. Insulating layer, 37. Second conductor layer, 38. Insulating layer, 41. P-type semiconductor area, 42. N-type semiconductor area, 43. Pixel separation section, 44. First trench, 45. Second trench, 46. Connection section, 51. First insulating layer, 52. First conductor layer, 53, 53A, 53B, 53C. Second insulating layer, 71. Color filter layer, 72. Inter-pixel light-shielding wall, 73. Light-shielding film, 74. Insulating film, 75. Low refractory film, 76. Insulating film, 77. On-chip lens, 100CR. Cross section, 100SL. Slit section, 100SLX protruding section, 200CR cross section, 200SL slit section, 300EX pad connection section, 500 electronic equipment, 502 photodetector element, FA first surface, SA second surface, FC focusing point

Claims

1. A photodetector comprising: a semiconductor substrate; a plurality of photoelectric conversion units arranged in a matrix on the semiconductor substrate; a plurality of on-chip lenses arranged on the first surface side of the semiconductor substrate which is a light-receiving surface; and a first trench formed in at least a part of the region between the photoelectric conversion units of the semiconductor substrate, wherein the first trench has a first conductor layer made of a first conductive material and a second conductor layer made of a second conductive material which has a smaller light absorption coefficient than the first conductive material, and the second conductor layer is provided in the inside of the first trench than the first conductor layer in a cross-sectional view and is connected to the first conductor layer in a region near the first surface of the semiconductor substrate.

2. The photodetector element according to claim 1, wherein the first trench is provided with a first insulating layer, a first conductor layer, and a second conductor layer in that order from the outside in a cross-sectional view.

3. The photodetector element according to claim 2, wherein the first trench further has a second insulating layer inside the first conductor layer in a cross-sectional view, and the second conductor layer and the second insulating layer are provided at different depths in the semiconductor substrate.

4. The photodetector element according to claim 1, configured such that a negative bias is applied to the first conductor layer and the second conductor layer.

5. The photodetector element according to claim 1, wherein the on-chip lens is shared by 2x2 pixels, and the first trench has the second conductive layer in a region including the focal point of the on-chip lens.

6. The on-chip lens is shared by 2x2 pixels, and the first trench includes a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect in a plan view, and a slit portion which is a linear portion other than the cross portion, and the cross portion of the first trench has the second conductive layer extending to a predetermined depth from the first surface of the semiconductor substrate, as described in claim 1.

7. The photodetector element according to claim 1, wherein the on-chip lens is shared by 2x2 pixels, and in a plan view, the region including the focal point of the on-chip lens is provided with a semiconductor region of a second conductivity type opposite to the semiconductor region of a first conductivity type constituting the photoelectric conversion unit.

8. The first trench includes, in a plan view, a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect, and a slit portion which is a linear portion other than the cross portion, and the slit portion between the pixels of the four pixels sharing the on-chip lens has, in a plan view, the second conductor layer near the center of its width, as described in claim 7.

9. The photodetector element according to claim 1, wherein the on-chip lens is shared by two rectangular pixels that form a square shape with two adjacent pixels, and in a plan view, the region including the focal point of the on-chip lens is provided with a semiconductor region of a second conductivity type opposite to the semiconductor region of a first conductivity type that constitutes the photoelectric conversion unit.

10. The photodetector element according to claim 9, wherein the first trench includes, in a plan view, a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect, and a slit portion which is a linear portion other than the cross portion, and the slit portion between the pixels of two pixels sharing the on-chip lens has, in a plan view, the second conductor layer near the center of its width.

11. The photodetector according to claim 1, wherein the plurality of on-chip lenses include on-chip lenses that are shared by 1x2 pixels.

12. The first trench contains air in the center of its width in a cross-sectional view, as described in claim 1.

13. The photodetector element according to claim 1, wherein the first trench includes a fixed charge film in the central part of its width in a cross-sectional view.

14. The first trench includes, in a plan view, a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect, and a slit portion which is a linear portion other than the cross portion, the second conductor layer is also formed on the upper layer on the first surface side of the semiconductor substrate, and the second conductor layer formed on the upper layer on the first surface side of the semiconductor substrate is connected to the second conductor layer in the first trench at the cross portion of the first trench, the photodetector element according to claim 1.

15. The photodetector element according to claim 1, further comprising a second trench on the second surface side of the semiconductor substrate opposite to the first surface, wherein the first trench and the second trench include a cross portion which is an intersection portion where a linear portion extending in the row direction and a linear portion extending in the column direction intersect in a plan view, and a slit portion which is a linear portion other than the cross portion, and the cross portion of the second trench includes a contact electrode.

16. The photodetector element according to claim 15, wherein the second conductor layer is also formed in the upper layer on the first surface side of the semiconductor substrate and is connected to an electrode pad formed on the first surface side of the semiconductor substrate, a negative bias is supplied to the contact electrode of the cross portion of the second trench outside the effective pixel region, and the negative bias supplied to the electrode pad and the contact electrode is supplied to the first conductor layer and the second conductor layer of the first trench via the second conductor layer formed in the upper layer on the first surface side of the semiconductor substrate.

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