Chip resistor and method for manufacturing chip resistor

Abstract

Provided is a chip resistor in which adhesion between a ceramic substrate and a resistor that is disposed on the ceramic substrate is ensured. A chip resistor (10) comprises: a ceramic substrate (1) that contains an alumina sintered body; a first electrode (411) and a second electrode (421) that are disposed on the ceramic substrate (1); an interface layer (52) that is disposed on the ceramic substrate (1) and is in contact with the ceramic substrate (1); and a resistor (51) that overlaps the interface layer (52). The resistor (51) contains a conductive component and a silicate glass matrix. The resistor (51) is electrically connected to the first electrode (411) and the second electrode (421). The interface layer (52) contains a BaAl2Si2O8 crystal phase.

Description

Chip resistor and method for manufacturing chip resistor

[0001] The present disclosure relates to a chip resistor used in various electronic devices and a method for manufacturing the chip resistor.

[0002] Patent Document 1 discloses a resistor composition comprising a ruthenium-based conductive component containing no lead component, a lead-free glass having a glass basicity (Po value) of 0.4 to 0.9, and an organic vehicle, wherein MSi is contained in a thick film resistor obtained by firing the composition at a high temperature ２ Al ２ O ８ crystal (M: Ba or Sr) is present.

[0003] Japanese Patent Application Laid-Open No. 2007-103594

[0004] The presence of MSi ２ Al ２ O ８ crystal (M: Ba or Sr) makes it possible to form a thick film resistor excellent in TCR characteristics, current noise characteristics, withstand voltage characteristics, heat cycle characteristics and the like in a wide resistance range. On the other hand, in the industry, it is desired to ensure adhesion between such a thick film resistor and a substrate on which the thick film resistor is arranged.

[0005] An object of the present disclosure is to provide a chip resistor in which adhesion between a ceramic substrate and a resistor arranged on the ceramic substrate is ensured, and a method for manufacturing the chip resistor.

[0006] A chip resistor according to an aspect of the present disclosure includes a ceramic substrate containing an alumina sintered body, a first electrode and a second electrode arranged on the ceramic substrate, an interface layer arranged on the ceramic substrate and in contact with the ceramic substrate, and a resistor overlapping the interface layer. The resistor contains a conductive component and a silicate glass matrix. The resistor is electrically connected to the first electrode and the second electrode. The interface layer contains BaAl ２ Si ２ O ８ crystal phase.

[0007] The present disclosure is a method for manufacturing a chip resistor, comprising: applying a resistive composition containing a silicate glass containing Ba and Si to the support surface of a ceramic substrate; firing the resistive composition at 800°C or higher to produce the resistor; and creating the interface layer at the boundary between the resistor and the ceramic substrate.

[0008] According to this disclosure, it is possible to provide a chip resistor and a method for manufacturing a chip resistor in which adhesion between a ceramic substrate and a resistor disposed on the ceramic substrate is ensured.

[0009] Figure 1 is a schematic cross-sectional view of a chip resistor according to an embodiment of this disclosure, viewed from the front. Figure 2 is a diagram showing the XRD measurement results of an evaluation sample. Figure 3 is a photograph of a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C. Figure 4 is a photograph of an image obtained by performing Ba element mapping analysis on a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C using SEM-EDX. Figure 5 is a photograph of the area where elemental analysis was performed on a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C. Figure 6 is a photograph of a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 750°C. Figure 7 is a photograph of an image obtained by performing Ba element mapping analysis on a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 750°C using SEM-EDX. Figure 8 shows a photograph of the section of a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 750°C, where elemental analysis was performed.

[0010] 1. Overview Embodiments of this disclosure will be described with reference to the figures. Note that the embodiments described below are only a part of the various embodiments of this disclosure. Furthermore, the embodiments described below can be modified in various ways depending on the design, etc., as long as the objectives of this disclosure are achieved. The figures referred to below are schematic diagrams, and the dimensional ratios of the components in the figures do not necessarily reflect the actual dimensional ratios. The arrows indicating direction in the drawings (arrows indicating the up / down and left / right directions) are not intended to define the direction in which the chip resistor 10 is used, but are merely included to make the explanation easier to understand and do not have any actual meaning. In this disclosure, the up / down direction is also the thickness direction, and viewing along the thickness direction is called a plan view.

[0011] Figure 1 is a schematic cross-sectional view of a chip resistor 10 according to an embodiment of the present disclosure, viewed from the front. The chip resistor 10 according to the embodiment comprises a ceramic substrate 1 containing an alumina sintered body, a first electrode 411 and a second electrode 421 disposed on the ceramic substrate 1, an interface layer 52 disposed on the ceramic substrate 1 and in contact with the ceramic substrate 1, and a resistor 51 overlapping the interface layer 52. The resistor 51 contains a silicate glass matrix and a conductive component. The resistor 51 is electrically connected to the first electrode 411 and the second electrode 421. The interface layer 52 is made of BaAl ２ Si ２ O ８ It contains a crystalline phase. With the above configuration, good adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1 is ensured.

[0012] The reason why the chip resistor 10 according to this embodiment can exhibit the above effects is not fully clear, but it is presumed to be due to the following reasons. The chip resistor 10 is made of BaAl ２ Si ２ O ８ The BaAl includes an interface layer 52 containing a crystalline phase, ２ Si ２ O ８The crystalline phase has high adhesion to the ceramic substrate 1 containing the alumina sintered body. Furthermore, since the interface layer 52, which has high adhesion to the ceramic substrate 1, is interposed between the ceramic substrate 1 and the resistor 51, adhesion between the ceramic substrate 1 and the resistor 51 is ensured.

[0013] Furthermore, the BaAl contained in the interface layer 52 ２ Si ２ O ８ The crystalline phase can be determined by examining cross-sectional SEM images (SEM stands for Scanning Electron Microscope) of the ceramic substrate 1, resistor 51, and interface layer 52, and confirming the mapping of the Ba element. Specifically, the Ba element is mapped onto the cross-sectional SEM images of the ceramic substrate 1, resistor 51, and interface layer 52 using SEM-EDS (EDS stands for Energy Dispersive X-ray Spectroscopy). Subsequently, the regions where the Ba element can be confirmed in the mapped image can be identified as the resistor 51 and interface layer 52. The regions where the Ba element cannot be confirmed in the mapped image can be identified as the ceramic substrate 1. Among the regions identified as the resistor 51 and interface layer 52, the region with a high density of the Ba element and where a layer is formed can be identified as the interface layer 52. Furthermore, among the regions identified as the resistor 51 and the interface layer 52, the region different from the interface layer 52 can be identified as the resistor 51. Then, elemental analysis is performed on the locations in the interface layer 52 where the element Ba is present. At this time, the closer the Ba:Al:Si ratio is to 1:2:2, the more likely it is to be BaAl ２ Si ２ O ８ It can be determined that a larger amount of the crystalline phase has been formed.

[0014] 2. The chip resistor 10 in the detailed embodiment will be described with reference to the drawings.

[0015] 2.1 The specific components of the chip resistor 10 according to the configuration embodiment will be described.

[0016] (Ceramic Substrate) The chip resistor 10 comprises a ceramic substrate 1. The ceramic substrate 1 has a rectangular shape when viewed from above. Therefore, the ceramic substrate 1 has two opposing surfaces in the thickness direction. For example, the thickness of the ceramic substrate 1 is 100 μm or more and 600 μm or less.

[0017] The ceramic substrate 1 is made of alumina (Al ２ O ３ ) Contains a sintered body. The ceramic substrate 1 may contain components other than the alumina sintered body in addition to the alumina sintered body. However, if the ceramic substrate 1 does not contain an alumina sintered body, BaAl may be added at the boundary between the ceramic substrate 1 and the resistor 51. ２ Si ２ O ８ It becomes difficult to form an interface layer 52 containing a crystalline phase. As a result, it becomes difficult to ensure good adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1. The content of the alumina sintered body in the ceramic substrate 1 is preferably 96% by mass or more. In this case, it becomes easier to ensure good adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1. This content is more preferably 99% by mass or more, and even more preferably 100% by mass.

[0018] (First electrode and second electrode) The chip resistor 10 is equipped with electrodes. In this embodiment, the chip resistor 10 is equipped with a first electrode 411 and a second electrode 421 arranged on a ceramic substrate 1 (see Figure 1).

[0019] For example, a first electrode 411 and a second electrode 421 are arranged on one of two opposing surfaces of the ceramic substrate 1 in the thickness direction. The first electrode 411 is positioned at the left end in the left-right direction of one of the two opposing surfaces of the ceramic substrate 1 in the thickness direction. The second electrode 421 is positioned at the right end in the left-right direction of one of the two opposing surfaces of the ceramic substrate 1 in the thickness direction. Each of the first electrode 411 and the second electrode 421 may be made of metal, a metal alloy, or a resin composition containing metal. In this embodiment, the first electrode 411 and the second electrode 421 are made of AgPd.

[0020] (Resistor) The chip resistor 10 includes a resistor 51. For example, the resistor 51 is placed on one of two opposing surfaces of the ceramic substrate 1 in the thickness direction, on the surface where the first electrode 411 and the second electrode 421 are located. The resistor 51 overlaps the interface layer 52. The resistor 51 is electrically connected to the first electrode 411 and the second electrode 421. The resistor 51 is positioned to cover the area sandwiched between the first electrode 411 and the second electrode 421. In other words, each of the two left-right ends of the resistor 51 partially overlaps the first electrode 411 and the second electrode 421.

[0021] For example, the resistor 51 and the interface layer 52 are in direct contact. In this embodiment, the components contained in the resistor 51 and the components contained in the interface layer 52 can form chemical bonds. This significantly enhances the adhesion between the resistor 51 and the interface layer 52.

[0022] The thickness of the resistor 51 is not particularly limited, but is, for example, 5 μm or more and 30 μm or less. The thickness of the resistor 51 is preferably 24 μm or less, and more preferably 18 μm or less. In this case, better adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1 is ensured. Furthermore, the thickness of the resistor 51 is preferably 6 μm or more, and more preferably 8 μm or more. In this case, the influence of diffusion of the Ag component from the first electrode 411 and the second electrode 421 to the resistor 51 can be reduced, and the variation in the temperature resistance coefficient (TCR) of the resistor 51 can be reduced.

[0023] The resistor 51 contains a silicate glass matrix. The silicate glass matrix is ​​formed from silicate glass. More specifically, the silicate glass matrix can be formed by heating and fusing silicate glass. The silicate glass matrix contains, for example, at least one element selected from the group consisting of Si, Ba, Al, Sr, B, Ca, Zr, Ta, Cu, Zn, W, and Li. In this embodiment, the silicate glass matrix does not contain Pb. However, the absence of Pb does not exclude the unavoidable presence of Pb.

[0024] The resistor 51 contains a conductive component. The content of the conductive component is preferably 10% by mass or more and 50% by mass or less relative to the resistor 51. The conductive component is not particularly limited, but it is preferably a ruthenium-based conductive component. Examples of ruthenium-based conductive components include ruthenium dioxide (RuO2). ２ ), neodymium ruthenate (Nd ２ Ru ２ O ７ ), samarium ruthenate (Sm ２ Ru ２ O ７ ), neodymium calcium ruthenate (NdCaRu ２ O ７ ), samarium strontium ruthenate (SmSrRu ２ O ７ ), barium ruthenate (BaRuO ３ ), cobalt ruthenate (Co ２ RuO ４ ) and strontium ruthenate (Sr ２ RuO ４ The conductive component includes at least one selected from the group consisting of ) . Among these, it is particularly preferable that the ruthenium-based conductive component includes ruthenium dioxide. In this case, adhesion between the ceramic substrate 1 and the resistor 51 can be ensured. In addition to the ruthenium-based conductive component, the conductive component may also include at least one selected from the group consisting of silver, silver oxide, gold, palladium, palladium oxide, platinum, and copper.

[0025] (Interface layer) The chip resistor 10 includes an interface layer 52. The interface layer 52 is placed on the ceramic substrate 1 and is in contact with the ceramic substrate 1. The interface layer 52 is interposed between the ceramic substrate 1 and the resistor 51.

[0026] In this embodiment, the interface layer 52 is BaAl ２ Si ２ O ８ It contains a crystalline phase. The interface layer 52 is BaAl ２ Si ２ O ８ In addition to the crystalline phase, BaAl ２ Si ２ O８ It may contain components different from the crystalline phase. BaAl ２ Si ２ O ８ Components different from the crystalline phase include silicate glass matrix or conductive components. The silicate glass matrix or conductive component may be the same as that contained in the resistor 51. Note that BaAl is used for the interface layer 52. ２ Si ２ O ８ The content of the crystalline phase is appropriately set to ensure good adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1. A content of 100% by mass is particularly preferred. In other words, from the viewpoint of improving adhesion with the ceramic substrate 1, the interface layer 52 is made of BaAl ２ Si ２ O ８ It is preferable that the crystalline phase is composed solely of this phase.

[0027] In this embodiment, the thickness of the interface layer 52 is 2% or more of the thickness of the resistor 51. In this case, because the thickness of the interface layer 52 is moderately increased, fusion between the interface layer 52 and the ceramic substrate 1 is likely to occur. Therefore, better adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1 can be ensured. The thickness of the interface layer 52 is preferably 4% or more of the thickness of the resistor 51, and more preferably 5% or more. Furthermore, the thickness of the interface layer 52 is preferably 15% or less of the thickness of the resistor 51. In this case, the variation in the temperature resistance coefficient (TCR) of the resistor 51 tends to be smaller. The thickness of the interface layer 52 is more preferably 14% or less of the thickness of the resistor 51, and even more preferably 9% or less. The thickness of the interface layer 52 is not particularly limited, but for example, it may be 0.1 μm or more and 2.0 μm or less. In this case, better adhesion between the ceramic substrate 1 and the resistor 51 placed on the ceramic substrate 1 can be ensured, and variations in the temperature resistance coefficient (TCR) of the resistor 51 can be reduced.

[0028] (Other components) In addition to the ceramic substrate 1, first electrode 411, second electrode 421, resistor 51 and interface layer 52, the chip resistor 10 according to this embodiment may also include components other than the ceramic substrate 1, first electrode 411, second electrode 421, resistor 51 and interface layer 52.

[0029] For example, the chip resistor 10 according to the embodiment may include, in addition to the first electrode 411 and the second electrode 421, electrodes different from the first electrode 411 and the second electrode 421. For example, the chip resistor 10 may include, in addition to the first electrode 411 and the second electrode 421, a first back electrode 412 and a second back electrode 422, a first end electrode 413 and a second end electrode 423, a first intermediate electrode 414 and a second intermediate electrode 424, and a first external electrode 415 and a second external electrode 425 (see Figure 1).

[0030] The first back electrode 412 is positioned at the left edge in the left-right direction of one of the two opposing surfaces of the ceramic substrate 1 in the thickness direction, where the first electrode 411 and the second electrode 421 are not located. The second back electrode 422 is positioned at the right edge in the left-right direction of one of the two opposing surfaces of the ceramic substrate 1 in the thickness direction, where the first electrode 411 and the second electrode 421 are not located. Each of the first back electrode 412 and the second back electrode 422 may be made of metal, a metal alloy, or a resin composition containing metal.

[0031] The first end electrode 413 is positioned to cover a portion of the first electrode 411 and a portion of the first back electrode 412. The second end electrode 423 is positioned to cover a portion of the second electrode 421 and a portion of the second back electrode 422. Each of the first end electrode 413 and the second end electrode 423 may be made of a metal, a metal alloy, or a resin composition containing a metal.

[0032] The first intermediate electrode 414 is positioned to cover the first electrode 411, the first back electrode 412, and the first end electrode 413. The second intermediate electrode 424 is positioned to cover the second electrode 421, the second back electrode 422, and the second end electrode 423. Each of the first intermediate electrode 414 and the second intermediate electrode 424 may be made of a metal, a metal alloy, or a resin composition containing a metal.

[0033] The first external electrode 415 is positioned to cover the first intermediate electrode 414. The second external electrode 425 is positioned to cover the second intermediate electrode 424. Each of the first external electrode 415 and the second external electrode 425 may be made of a metal, a metal alloy, or a resin composition containing a metal.

[0034] For example, the chip resistor 10 may include a protective film 6 that covers a portion of the first electrode 411, a portion of the second electrode 421, and the resistor 51. The protective film 6 can be formed from, for example, an epoxy resin composition containing epoxy resin, inorganic filler, and pigment.

[0035] For example, the chip resistor 10 may include an inorganic protective film 7 interposed between the resistor 51 and the protective film 6. The inorganic protective film 7 is made of a metal oxide. The metal oxide may include, for example, silicate glass.

[0036] 2.2 Manufacturing Method A method for manufacturing the chip resistor 10 according to the embodiment will be described. In the manufacturing method of the chip resistor 10 according to the embodiment, a resistor composition (M) containing silicate glass containing Si and Ba is applied to a ceramic substrate 1, and a resistor 51 is produced by firing the resistor composition (M) at 800°C or higher, and an interface layer 52 is produced at the boundary between the resistor 51 and the ceramic substrate 1.

[0037] As already mentioned, the silicate glass matrix contained in the resistor 51 does not contain Pb. In other words, silicate glass does not contain Pb. However, if the silicate glass contained in the composition forming the resistor 51 does not contain Pb, the fluidity of the composition is easily impaired. In that case, the wettability of the composition to the substrate is not sufficiently high, and therefore, the adhesion between the substrate and the resistive film formed from the composition coated on the substrate is easily impaired. In contrast to this, in the embodiment, since the resistive composition (M) that satisfies a specific composition is fired at 800°C or higher, BaAl is laid on the ceramic substrate 1. ２ Si ２ O ８ The crystalline phase is particularly easily formed. Therefore, adhesion between the ceramic substrate 1 and the resistor 51 is particularly easy to ensure.

[0038] A detailed explanation will be given regarding the manufacturing method of the chip resistor 10 according to this embodiment.

[0039] First, a first electrode 411 and a second electrode 421 are formed on one of two opposing surfaces of the ceramic substrate 1 in the thickness direction. Specifically, an electrode paste containing AgPd is applied to both the left and right edges of one of the two opposing surfaces of the ceramic substrate 1 in the thickness direction. The applied electrode paste is then dried and subsequently fired at 850°C to form the first electrode 411 and the second electrode 421.

[0040] Next, a resistor composition (M) for forming the resistor 51 and the interface layer 52 is prepared.

[0041] The resistor composition (M) contains silicate glass. The silicate glass may be in the form of flakes, powder, etc.

[0042] Silicate glass contains silicate glass that includes Si and Ba. In other words, silicate glass contains SiO ２ and BaO is included. In this case, BaAl is present at the boundary between the resistor 51 and the ceramic substrate 1. ２ Si ２ O ８ Crystalline phases are easily formed.

[0043] Furthermore, if the proportion of Si or Ba is within a specific range, BaAl will form at the boundary between the resistor 51 and the ceramic substrate 1. ２ Si ２ O ８ The crystalline phase is more easily formed. The ratio of Si is SiO to silicate glass. ２ It is preferable that the amount is between 25% by mass and 40% by mass. The proportion of Ba is preferably between 14% by mass and 45% by mass relative to the silicate glass, in terms of BaO.

[0044] Furthermore, silicate glass may contain, in addition to Si and Ba, at least one element selected from the group consisting of Al, Sr, B, Ca, Zr, Ta, Cu, Zn, W, and Li. In more specific terms, silicate glass may contain Si ２ In addition to O and BaO, Al ２ O３ , SrO, B ２ O ３ , CaO, ZrO, Ta ２ O ３ , CuO, ZnO, WO ３ and Li ２ may contain at least one selected from the group consisting of O.

[0045] When the silicate glass contains Al, the proportion of Al is, based on the entire silicate glass, Al ２ O ３ in terms of conversion, preferably 2% by mass or more and 5% by mass or less. In this case, the atomic concentration of Al in the silicate glass is appropriately reduced, whereby the components contained in the silicate glass and the alumina (Al ２ O ３ ) contained in the ceramic substrate 1 react efficiently, and the resistor 51 and BaAl formed on the ceramic substrate 1 ２ Si ２ O ８ crystalline phase is efficiently formed. The proportion of Al is more preferably 4% by mass or less, and still more preferably 3% by mass or less.

[0046] Further, the silicate glass contains SiO ２ , BaO, Al ２ O ３ , B ２ O ３ preferably contains CaO and ZnO. In this case, BaAl is formed at the boundary between the resistor 51 and the ceramic substrate 1 ２ Si ２ O ８ crystalline phase is efficiently formed. In this case, B ２ O ３ the proportion of the above is preferably 9.0% by mass or more and 15% by mass or less based on the silicate glass. The proportion of CaO is preferably 4.0% by mass or more and 15% by mass or less based on the silicate glass. The proportion of ZnO is preferably 9.5% by mass or more and 15% by mass or less based on the silicate glass.

[0047] Note that the silicate glass does not contain Pb. Note that "does not contain Pb" does not exclude the inclusion of unavoidably mixed Pb.

[0048] The resistor composition (M) contains a conductive component in addition to silicate glass. The conductive component can be one that can be contained in the resistor 51. The ratio of the mass of the conductive component to the mass of the silicate glass is preferably 10 / 90 or more and 50 / 50 or less. In this case, BaAl is used on the ceramic substrate 1. ２ Si ２ O ８ The formation of the crystalline phase can proceed efficiently. This can ensure better adhesion between the ceramic substrate 1 and the resistor 51.

[0049] The resistor composition (M) may contain an organic vehicle. In this case, the ease of application of the resistor composition (M) may be improved. The organic vehicle includes, for example, at least one selected from the group consisting of ethylcellulose, nitrocellulose, (meth)acrylic acid ester, and rosin.

[0050] The resistor composition (M) may contain a solvent. The solvent includes, for example, at least one selected from the group consisting of terpineol and its ester compounds, carbitol and its ester compounds, butyl carbitol and its ester compounds, cellosolve and its ester compounds, butyl cellosolve and its ester compounds, and aromatic hydrocarbons such as toluene and xylene.

[0051] Next, the resistor composition (M) is applied between the first electrode 411 and the second electrode 421. The applied resistor composition (M) is then dried, and subsequently the dried resistor composition (M) is fired. As a result, the resistor composition (M) is sintered to produce a resistor 51, and at the interface between the resistor composition (M) and the ceramic substrate 1, the resistor composition (M) reacts with the ceramic substrate 1 to produce an interface layer 52. In other words, in this embodiment, a resistor 51 and an interface layer 52 can be formed from the resistor composition (M).

[0052] As described above, in the embodiment, the resistor composition (M) applied to the ceramic substrate 1 is fired at 800°C or higher. The firing temperature is preferably 810°C or higher, more preferably 830°C or higher, and even more preferably 850°C or higher. However, even if the resistor composition (M) applied to the ceramic substrate 1 is fired at a temperature of less than 800°C, BaAl is formed between the ceramic substrate 1 and the resistor 51. ２ Si ２ O ８ A crystalline phase may be formed. In this case, BaAl is more effective than when the resistor composition (M) is calcined at 800°C or higher. ２ Si ２ O ８ Although the formation of the crystalline phase is gradual, sufficient adhesion between the ceramic substrate 1 and the resistor 51 can be achieved. There is no specific upper limit set for the firing temperature, but for example, it is 900°C or lower. In this case, there is the advantage that defects such as deformation and foaming of the resistor 51 are less likely to occur.

[0053] Subsequently, components other than the first electrode 411, the second electrode 421, the resistor 51, and the interface layer 52 are added. Specifically, the first back electrode 412 and the second back electrode 422 are formed on the two opposing surfaces of the ceramic substrate 1 in the thickness direction where the first electrode 411 and the second electrode 421 are not located. Next, the first end electrode 413 is formed so as to cover a part of the first electrode 411 and a part of the first back electrode 412, and the second end electrode 423 is formed so as to cover a part of the second electrode 421 and a part of the second back electrode 422. Next, an inorganic protective film 7 and a protective film 6 are formed on the resistor 51 in this order. Then, the first intermediate electrode 414 is formed so as to cover the first electrode 411, the first back electrode 412, and the first end electrode 413, and the second intermediate electrode 424 is formed so as to cover the second electrode 421, the second back electrode 422, and the second end electrode 423. Then, a first external electrode 415 is formed so as to cover the first intermediate electrode 414, and a second external electrode 425 is formed so as to cover the second intermediate electrode 424. In this way, the chip resistor 10 according to the embodiment is manufactured.

[0054] The present disclosure will be specifically described below with reference to examples. However, the present disclosure is not limited to the following examples.

[0055] 1. Resistor Composition (Resistor Composition #1) Resistor composition #1 was prepared containing ruthenium dioxide, glass powder with the composition shown in Table 1, and an organic vehicle.

[0056] (Resistor composition #2) Resistor composition #2 was prepared, containing ruthenium dioxide, glass powder with the composition shown in Table 1, and an organic vehicle.

[0057]

[0058] 2. Evaluation 1 2.1 Preparation of Evaluation Samples An electrode paste containing AgPd was screen printed onto one of two surfaces in the thickness direction of a ceramic substrate 1 (alumina sintered substrate). After drying the applied electrode paste, it was fired at 850°C to form a first electrode 411 and a second electrode 421. Subsequently, a resistor composition #1 was screen printed between the first electrode 411 and the second electrode 421. After drying the applied resistor composition #1, six evaluation samples (chip resistors 10) were prepared by firing the resistor composition #1 at 750°C, 790°C, 810°C, 830°C, 850°C, or 870°C.

[0059] 2.2 Evaluation Details (XRD) For the six evaluation samples, X-ray diffraction measurements (XRD measurements) were performed from the upper surface of the formed resistor 51, and BaAl ２ Si ２ O ８ The presence or absence of a diffraction peak corresponding to was checked. Figure 2 shows the XRD measurement results of the evaluation sample. As shown in Figure 2, for the evaluation sample in which resistor composition #1 was fired at 750°C or higher, BaAl ２ Si ２ O ８ A diffraction peak corresponding to this was confirmed. Furthermore, for the evaluation sample in which resistor composition #1 was calcined at 810°C or higher, BaAl ２ Si ２ O ８ We were able to confirm that the intensity of the diffraction peak corresponding to this value was significantly increased.

[0060] (SEM-EDX) For an evaluation sample in which a resistor 51 and an interface layer 52 were formed by firing resistor composition #1 at 850°C, the evaluation sample was cut so that the cross-sections of the ceramic substrate 1, interface layer 52 and resistor 51 could be confirmed, and cross-sectional SEM images were obtained. Figure 3 is a photograph of a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C.

[0061] For the evaluation sample in which the resistor 51 and interface layer 52 were formed by firing resistor composition #1 at 750°C, the evaluation sample was cut so that the cross-sections of the ceramic substrate 1, interface layer 52, and resistor 51 could be confirmed, and cross-sectional SEM images were obtained. Figure 6 shows a photograph of the cross-sectional SEM image of the evaluation sample obtained by firing resistor composition #1 at 750°C.

[0062] A cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C was subjected to Ba element mapping analysis using SEM-EDX. Figure 4 is a photograph of the image obtained by SEM-EDX mapping analysis of the cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 850°C. In Figure 4, the white areas indicate the presence of Ba element. As shown in Figure 4, it was visually confirmed that a large amount of Ba element was present on the ceramic substrate 1, forming a layered structure. Therefore, in the evaluation sample obtained by firing resistor composition #1 at 850°C, BaAl was present on the ceramic substrate 1. ２ Si ２ O ８ It was clearly confirmed that an interface layer 52 composed of the above was formed.

[0063] A cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 750°C was subjected to Ba element mapping analysis using SEM-EDX. Figure 7 is a photograph of a cross-sectional SEM image of an evaluation sample obtained by firing resistor composition #1 at 750°C, showing the Ba element mapping analysis performed by SEM-EDX. In Figure 7, the white areas indicate the presence of Ba element. As shown in Figure 7, the presence of Ba element on the ceramic substrate 1 could be visually confirmed, but compared to Figure 4, it was not clearly confirmed that the Ba element formed a layer. This suggests that a higher firing temperature for resistor composition #1 results in the presence of BaAl on the ceramic substrate 1. ２ Si ２ O ８ It was confirmed that it is easily formed.

[0064] Furthermore, using SEM-EDX, six arbitrary points were extracted from the cross-sectional SEM image of the evaluation sample obtained by firing resistor composition #1 at 850°C, and elemental analysis was performed at each point. Figure 5 shows a photograph of the area where elemental analysis was performed on the cross-sectional SEM image of the evaluation sample obtained by firing resistor composition #1 at 850°C. The measurement results for the six points shown in Figure 5 are shown in Table 2.

[0065]

[0066] From the results in Table 2, the elemental ratio of Ba:Al:Si near the boundary with the ceramic substrate 1 is approximately 1:2:2, and when combined with the XRD results, it appears that BaAl is present near the boundary. ２ Si ２ O ８ It was confirmed that precipitates had formed.

[0067] Furthermore, six arbitrary points were extracted from the cross-sectional SEM image of the evaluation sample obtained by firing resistor composition #1 at 750°C using SEM-EDX, and elemental analysis was performed at each point. Figure 8 shows a photograph of the area where elemental analysis was performed on the cross-sectional SEM image of the evaluation sample obtained by firing resistor composition #1 at 750°C. The measurement results for the six points shown in Figure 8 are shown in Table 3.

[0068]

[0069] From the results in Table 3, it was confirmed that the elemental ratio of Ba:Al:Si near the boundary with the ceramic substrate 1 was not close to 1:2:2.

[0070] From the above results, the higher the firing temperature of resistor composition #1, the closer the Ba:Al:Si elemental ratio on the ceramic substrate 1 approaches 1:2:2, and as a result, BaAl ２ Si ２ O ８ It was confirmed that this makes it easier for the formation of [the substance] to occur.

[0071] 3. Evaluation 2 3.1 Preparation of Evaluation Samples Following the method described in "2. Evaluation 1 2.1 Preparation of Evaluation Samples," a first electrode and a second electrode were formed on one of the two surfaces in the thickness direction of the ceramic substrate 1 (alumina sintered substrate). Subsequently, resistor composition #1 was screen printed between the first electrode 411 and the second electrode 421, and the applied resistor composition #1 was fired at 850°C to produce four evaluation samples (chip resistors 10) of the embodiment, each having a resistor 51 and an interface layer 52 of the thickness shown in Table 4. Furthermore, following the method described in "2. Evaluation 1 2.1 Preparation of Evaluation Samples," a first electrode 411 and a second electrode 421 were formed on one of the two surfaces in the thickness direction of the ceramic substrate 1 (alumina sintered substrate). Next, resistor composition #2 was screen-printed between the first electrode 411 and the second electrode 421, and the resistor composition #2 was fired at 850°C to produce four comparative evaluation samples (chip resistors 10) having resistors 51 with the thicknesses shown in Table 4.

[0072] For an evaluation sample of an embodiment comprising a resistor 51 and an interface layer 52, the total thickness of the resistor 51 and interface layer 52 was measured using a contact-type step meter (product name: SurfCorder ET4000A, manufactured by Kosaka Research Institute Co., Ltd.). The measurement position was the central part when viewing the resistor in the left-right direction, and the total thickness of the resistor 51 and interface layer 52 was determined by measuring the thickness from the ceramic substrate 1 to the maximum height of the resistor. For an evaluation sample of a comparative example comprising a resistor 51, the total thickness of the resistor 51 was measured using a contact-type step meter. The measurement position was the central part when viewing the resistor 51 in the left-right direction, and the thickness of the resistor 51 was determined by measuring the thickness from the ceramic substrate 1 to the maximum height of the resistor.

[0073] Furthermore, cross-sectional SEM images of the ceramic substrate 1, interface layer 52, and resistor 51 of the evaluation sample of the example were acquired at a magnification of 500x. From a region within a range of 200 μm in the left-right direction of this image, five portions were arbitrarily selected, and for each portion, an image was acquired at a magnification of 2000x within a range of 14 μm in the left-right direction. For the cross-sectional SEM images of each portion, a mapping analysis of the Ba element was performed using SEM-EDX. Based on the results, the areas where the Ba element was layered in each portion were confirmed. The average thickness of the areas where the Ba element was layered in each of the five portions was then taken as the thickness of the interface layer 52. Cross-sectional SEM images of the ceramic substrate 1, interface layer 52, and resistor 51 of the evaluation sample of the comparative example were acquired. For the acquired cross-sectional SEM images, a mapping analysis of the Ba element was performed using SEM-EDX. The cross-sectional SEM images did not confirm that the Ba element was layered on the ceramic substrate 1.

[0074] Next, for the evaluation sample of the embodiment, the thickness of the resistor 51 was determined by subtracting the thickness of the interface layer 52, which was confirmed by measurement, from the total thickness of the resistor 51 and interface layer 52 measured with a contact-type step meter. Then, by comparing the thickness of the resistor 51 with the thickness of the interface layer 52, the ratio (%) of the thickness of the interface layer 52 to the thickness of the resistor 51 was calculated using the following formula.

[0075] Ratio of the thickness of the interface layer 52 to the thickness of the resistor 51 = (thickness of interface layer 52 / thickness of resistor 51) × 100 (Peeling test) Cellotape (registered trademark) (Nichiban Co., Ltd. CT-18) was attached to the resistor 51 of the evaluation sample (chip resistor 10) of the example or comparative example, and the tape was peeled off. The degree of peeling of the resistor 51 from the ceramic substrate 1 was evaluated according to the following criteria.

[0076] A: No peeling of the resistor 51 was observed. B: Some peeling of the resistor 51 was observed. C: The resistor 51 was completely peeled off.

[0077]

[0078] [Aspects] As is clear from the embodiments described above, this disclosure includes the following aspects. Hereafter, reference numerals are enclosed in parentheses solely to indicate their correspondence with the embodiments.

[0079] A chip resistor (10) according to a first aspect of the present disclosure comprises a ceramic substrate (1) containing an alumina sintered body, a first electrode (411) and a second electrode (421) disposed on the ceramic substrate (1), an interface layer (52) disposed on the ceramic substrate (1) and in contact with the ceramic substrate (1), and a resistor (51) overlapping the interface layer (52). The resistor (51) contains a silicate glass matrix and a conductive component. The resistor (51) is electrically connected to the first electrode (411) and the second electrode (421). The interface layer (52) is made of BaAl ２ Si ２ O ８ It contains a crystalline phase.

[0080] In the first embodiment, the chip resistor (10) according to a second aspect of the present disclosure comprises a ruthenium-based conductive component.

[0081] In the third aspect of the present disclosure, the chip resistor (10) is such that, in the first or second aspect, the thickness of the interface layer (52) is 2% or more of the thickness of the resistor (51).

[0082] In a chip resistor (10) according to a fourth aspect of the present disclosure, in any one of the first to third aspects, a resistor (51) is produced by coating a resistor composition (M) containing a silicate glass containing Ba and Si onto a ceramic substrate (1), firing the resistor composition (M) at 800°C or higher, and an interface layer (52) is produced at the boundary between the resistor (51) and the ceramic substrate (1).

[0083] A chip resistor (10) according to a fifth aspect of this disclosure, in a fourth aspect, further comprises Al in the silicate glass. The proportion of Al in the silicate glass is Al relative to the total silicate glass. ２ O ３ This is equivalent to less than 3% by mass.

[0084] A method for manufacturing a chip resistor (10) according to a sixth aspect of the present disclosure is a method for manufacturing a chip resistor (10) according to any one of the first to fifth aspects, comprising: applying a resistor composition (M) containing silicate glass containing Ba and Si to a ceramic substrate (1); firing the resistor composition (M) at 800°C or higher to produce a resistor (51); and creating an interface layer (52) at the boundary between the resistor (51) and the ceramic substrate (1).

[0085] The chip resistor and method for manufacturing a chip resistor according to this disclosure ensure good adhesion between the ceramic substrate and the resistor placed on the ceramic substrate. Therefore, peeling of the thick-film resistor from the substrate can be reduced, improving the manufacturing yield of the chip resistor. Thus, the chip resistor and method for manufacturing a chip resistor according to this disclosure are industrially useful.

[0086] 1 Ceramic substrate 51 Resistor 10 Chip resistor 411 First electrode 421 Second electrode

Claims

1. The device comprises a ceramic substrate containing an alumina sintered body, a first electrode and a second electrode disposed on the ceramic substrate, an interface layer disposed on the ceramic substrate and in contact with the ceramic substrate, and a resistor overlapping the interface layer, wherein the resistor contains a silicate glass matrix and a conductive component, the resistor is electrically connected to the first electrode and the second electrode, and the interface layer is made of BaAl ２ Si ２ O ８ A chip resistor containing a crystalline phase.

2. The chip resistor according to claim 1, wherein the conductive component includes a ruthenium-based conductive component.

3. The chip resistor according to claim 1, wherein the thickness of the interface layer is 2% or more of the thickness of the resistor.

4. The chip resistor according to claim 1, wherein the resistor is manufactured by coating the ceramic substrate with a resistor composition containing a silicate glass containing Ba and Si, and firing the resistor composition at 800°C or higher, and the interface layer is formed at the boundary between the resistor and the ceramic substrate.

5. The silicate glass further contains Al, and the proportion of Al contained in the silicate glass is Al relative to the total amount of the silicate glass. ２ O ３ The chip resistor according to claim 4, wherein the converted amount is 3% by mass or less.

6. A method for manufacturing a chip resistor according to claim 1, comprising: applying a resistive composition containing a silicate glass containing Ba and Si to a ceramic substrate; firing the resistive composition at 800°C or higher to produce the resistive body; and producing the interface layer at the boundary between the resistive body and the ceramic substrate.

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