Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor layer that is composed of SiC and includes a plurality of gate trenches separated from each other; a plurality of gate electrodes that are respectively located in the plurality of gate trenches; a conductive cap part that is located outside of the plurality of gate trenches and extends so as to cover at least one among the plurality of gate trenches; and an insulating layer that covers the semiconductor layer and the conductive cap part. The conductive cap part is connected to the gate electrode located in the at least one gate trench covered by the conductive cap part.

Description

Semiconductor equipment

[0001] This disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device including a trench-gate structure MOSFET. In a trench-gate structure MOSFET, the gate electrode is embedded in the gate trench via a gate insulating film.

[0003] Japanese Patent Publication No. 2015-220334

[0004] [Overview] In semiconductor devices with a trench gate structure, there is a need to reduce gate resistance.

[0005] A semiconductor device according to one aspect of the present disclosure comprises a semiconductor layer made of SiC, including a plurality of gate trenches spaced apart from each other; a plurality of gate electrodes each located within the plurality of gate trenches; a conductive cap portion located outside the plurality of gate trenches and extending to cover at least one of the plurality of gate trenches; and an insulating layer covering the semiconductor layer and the conductive cap portion, wherein the conductive cap portion is connected to a gate electrode located within the at least one gate trench covered by the conductive cap portion.

[0006] Other features and embodiments will become apparent from the following detailed description, drawings, and claims.

[0007] Figure 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view of the semiconductor device along the line F2-F2 in Figure 1. Figure 3 is an enlarged schematic plan view of the semiconductor device on the first surface of the semiconductor layer. Figure 4 is a schematic cross-sectional view of the semiconductor device along the line F4-F4 in Figure 3. Figure 5 is a schematic plan cross-sectional view of the semiconductor device along the line F5-F5 in Figure 4. Figure 6 is a schematic cross-sectional view of the semiconductor device along the line F6-F6 in Figure 1. Figure 7 is a schematic plan view of an exemplary semiconductor device according to a second embodiment of the present disclosure. Figure 8 is a schematic cross-sectional view of the semiconductor device along the line F8-F8 in Figure 7. Figure 9 is a schematic plan cross-sectional view of the semiconductor device along the line F9-F9 in Figure 8. Figure 10 is a schematic cross-sectional view of the semiconductor device along the line F10-F10 in Figure 9. Figure 11 is a schematic plan view of an exemplary semiconductor device according to a third embodiment of the present disclosure. Figure 12 is a schematic cross-sectional view of the semiconductor device along the line F12-F12 in Figure 11. Figure 13 is a schematic cross-sectional view of a semiconductor device along the line F13-F13 in Figure 11. Figure 14 is a schematic plan cross-sectional view of a semiconductor device along the line F14-F14 in Figure 12. Figure 15 is a schematic plan view of a semiconductor device according to a modified example of the third embodiment. Figure 16 is a schematic plan view of a semiconductor device according to a modified example of the third embodiment. Figure 17 is a schematic plan view of a semiconductor device according to a modified example of the third embodiment. Figure 18 is a schematic plan view of a semiconductor device according to a modified example of the third embodiment. Figure 19 is a schematic cross-sectional view illustrating an exemplary manufacturing process of a semiconductor device. Figure 20 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 19. Figure 21 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 20. Figure 22 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 21. Figure 23 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 22. Figure 24 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 23. Figure 25 is a schematic cross-sectional view showing a manufacturing process following the process shown in Figure 24. Figure 26 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 25. Figure 27 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 26. Figure 28 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 27. Figure 29 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 28. Figure 30 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 29.Figure 31 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 30. Figure 32 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 31. Figure 33 is a schematic cross-sectional view showing the manufacturing process following the process shown in Figure 32.

[0008] [Detailed Description] Hereinafter, several embodiments of the semiconductor devices of the present disclosure will be described with reference to the accompanying drawings. Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative sizes, proportions, and depictions of elements in the drawings may be exaggerated for clarity, illustrative purposes, and convenience. Also, for clarity, not all components are labeled in all drawings, and not all components in each embodiment of the present disclosure are shown where it is not necessary to illustrate them to enable those skilled in the art to understand the present disclosure.

[0009] The following detailed description provides a comprehensive understanding of the described methods, apparatus, and / or systems. Modifications and equivalents of the described methods, apparatus, and / or systems will be obvious to those skilled in the art. Except for operations that necessarily occur in a specific order, the order of operations is illustrative and can be modified as will be obvious to those skilled in the art. Descriptions of functions and structures well known to those skilled in the art may be omitted. The exemplary embodiments may have different forms and are not limited to the examples described.

[0010] <First Embodiment> An exemplary semiconductor device 10 according to the first embodiment of the present disclosure will be described with reference to Figures 1 to 6. Figure 1 is a schematic plan view of the semiconductor device 10. Figure 2 is a schematic cross-sectional view of the semiconductor device 10 along the line F2-F2 in Figure 1. Figure 3 is an enlarged schematic plan view of the semiconductor device 10 on the first surface 12A of the semiconductor layer 12, which will be described later. Figure 4 is a schematic cross-sectional view of the semiconductor device 10 along the line F4-F4 in Figure 3. Figure 5 is a schematic plan cross-sectional view of the semiconductor device 10 along the line F5-F5 in Figure 4. Figure 6 is a schematic cross-sectional view of the semiconductor device 10 along the line F6-F6 in Figure 1. As can be understood from the following description, the semiconductor device 10 may be a semiconductor switching device including an insulated gate type transistor having a trench gate structure.

[0011] (Overall Structure of Semiconductor Device) As shown in FIGS. 1 to 6, a semiconductor device 10 includes a semiconductor layer 12. The semiconductor layer 12 may include a single crystal of wide bandgap semiconductor, and accordingly, the semiconductor device 10 may be a wide bandgap semiconductor device.

[0012] A wide bandgap semiconductor is a semiconductor having a bandgap larger than that of Si (silicon). Examples of wide bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In the present embodiment, the semiconductor layer 12 may be formed of SiC, and accordingly, the semiconductor device 10 may be a SiC semiconductor device.

[0013] In one example, the semiconductor layer 12 may include a hexagonal SiC single crystal. A hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC, 4H-SiC, and 6H-SiC. In the present embodiment, the semiconductor layer 12 may include a 4H-SiC single crystal, but is not limited thereto, and may include single crystals of other polytypes. In another example, the semiconductor layer 12 may also include cubic or polycrystalline SiC. For example, the semiconductor layer 12 may include a 3C (Cubic)-SiC single crystal or 3C-SiC polycrystal.

[0014] The semiconductor layer 12 may include a first surface 12A, a second surface 12B opposite to the first surface, and a first side surface 12C1, a second side surface 12C2, a third side surface 12C3, and a fourth side surface 12C4 connected between the first surface 12A and the second surface 12B. The Z-axis direction of the mutually orthogonal XYZ axes shown in FIG. 1 and other drawings is a direction that intersects (for example, is orthogonal to) the first surface 12A of the semiconductor layer 12. As used herein, the term "plan view" is used to refer to a drawing drawn from a viewpoint of looking down an object from above along the Z-axis direction, unless explicitly stated otherwise. The first surface 12A and the second surface 12B may be rectangular in plan view. The Z-axis direction can be referred to as the depth direction of the semiconductor layer 12. In the example shown in FIG. 1, the first side surface 12C1 and the third side surface 12C3 extend in the X-axis direction in plan view. The second side surface 12C2 and the fourth side surface 12C4 extend in the Y-axis direction in plan view. The first side surface 12C1 is connected to the second side surface 12C2, the second side surface 12C2 is connected to the third side surface 12C3, the third side surface 12C3 is connected to the fourth side surface 12C4, and the fourth side surface 12C4 is connected to the first side surface 12C1.

[0015] The first surface 12A and the second surface 12B may be formed by a c-plane (a plane perpendicular to the c-axis) of SiC single crystal. In one example, the first surface 12A may be formed by the (0001) plane (Si plane) of SiC single crystal, and the second surface 12B may be formed by the (000-1) plane (C plane) of SiC single crystal.

[0016] In the example shown in FIG. 1, the X-axis direction may be the m-axis direction ([1-100] direction) of the SiC single crystal, and the Y-axis direction may be the a-axis direction ([11-20] direction) of the SiC single crystal. In another example, the X-axis direction may be the a-axis direction of the SiC single crystal, and the Y-axis direction may be the m-axis direction of the SiC single crystal.

[0017] The first surface 12A (second surface 12B) of the semiconductor layer 12 may have a predetermined off-angle θ with respect to the c-plane of the SiC single crystal. In other words, the normal vector (Z-axis direction) of the first surface 12A of the semiconductor layer 12 may have an off-angle θ with respect to the c-axis <0001> of the SiC single crystal. The c-axis of the SiC single crystal is tilted by an off-angle θ in the off-direction from the normal vector of the first surface 12A. The off-direction is the direction of the projection vector when the normal vector of the first surface 12A is projected onto the c-plane.

[0018] In one example, the off-direction may be the a-axis direction of the SiC single crystal (the Y-axis direction in the example shown in Figure 1). The off-angle θ may be greater than 0° and 10° or less. Preferably, the off-angle θ may be 5° or less. Particularly preferably, the off-angle θ may be between 2° and 4.5°. The off-angle θ can typically be set in the range of 4° ± 0.1°. However, this disclosure does not exclude the example where the off-angle θ is 0°.

[0019] The semiconductor layer 12 includes a first semiconductor layer 14. The first semiconductor layer 14 may be made of a semiconductor substrate. The first semiconductor layer 14 includes the second surface 12B of the semiconductor layer 12 and a portion of the first to fourth surfaces 12C1 to 12C4 of the semiconductor layer 12. The first semiconductor layer 14 may contain a single crystal of a wide-bandgap semiconductor.

[0020] In this embodiment, the first semiconductor layer 14 may be a SiC substrate containing a hexagonal SiC single crystal. In this example, the first semiconductor layer 14 may contain a 4H-SiC single crystal and have the aforementioned off-direction and off-angle θ. In another example, the first semiconductor layer 14 may contain a single crystal of another polytype (e.g., 3C-SiC).

[0021] As shown in Figure 2, the first semiconductor layer 14 has a thickness T1 in the Z-axis direction. The thickness T1 may be greater than 0 μm and 500 μm or less. The first semiconductor layer 14 may have a uniform n-type impurity concentration along the depth direction. The impurity concentration of the first semiconductor layer 14 is 1 × 10⁻¹⁶. １７ cm －３ The above 1 x 10 ２１ cm －３The following is also acceptable. The first semiconductor layer 14 can also be called the drain region.

[0022] In this disclosure, n-type may be referred to as the first conductivity type, and p-type as the second conductivity type. n-type impurities may include, for example, nitrogen (N), phosphorus (P), arsenic (As), and / or antimony (Sb). p-type impurities may include, for example, boron (B), aluminum (Al), gallium (Ga), and / or indium (In). In one example, the n-type impurity contained in the first semiconductor layer 14 may be nitrogen (N).

[0023] The semiconductor layer 12 may include a second semiconductor layer 16 located on top of the first semiconductor layer 14. The second semiconductor layer 16 includes the first surface 12A of the semiconductor layer 12 and a portion of the first to fourth sides 12C1 to 12C4 of the semiconductor layer 12. The second semiconductor layer 16 may include a single crystal of a wide-bandgap semiconductor.

[0024] In this embodiment, the second semiconductor layer 16 may be a SiC epitaxial layer containing a hexagonal SiC single crystal. In this example, the second semiconductor layer 16 may contain a 4H-SiC single crystal and have the aforementioned off-direction and off-angle θ. In another example, the second semiconductor layer 16 may contain a single crystal of another polytype (e.g., 3C-SiC).

[0025] The second semiconductor layer 16 has a thickness T2 in the Z-axis direction that is smaller than the thickness T1 of the first semiconductor layer 14. The thickness T2 may be greater than 0 μm and 50 μm or less. As shown in Figures 1 and 2, the semiconductor layer 12 may include an active region 18 and an outer peripheral region 20 surrounding the active region 18. The active region 18 may be a region that contributes to the operation of the semiconductor device 10 as a transistor. The active region 18 may be covered by a source electrode 40, which will be described later.

[0026] The active region 18 may be an inner region of the semiconductor layer 12 in a plan view. The active region 18 may be separated from the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12. The outer peripheral region 20 may be a peripheral region of the semiconductor layer 12 in a plan view. The outer peripheral region 20 may include the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12 and the active region 18.

[0027] The ratio of the area of ​​the active region 18 to the area of ​​the first surface 12A of the semiconductor layer 12 may be 0.5 or more and 0.95 or less. (Gate Trench) Next, a plurality of gate trenches 22 located in the active region 18 will be described with reference to Figures 2 to 6. As shown in Figures 2 to 6, the semiconductor layer 12 includes a plurality of gate trenches 22 that are spaced apart from each other. In this embodiment, the plurality of gate trenches 22 may extend in the Y-axis direction and be spaced apart from each other in the X-axis direction. The plurality of gate trenches 22 are provided on the first surface 12A of the semiconductor layer 12. In other words, the plurality of gate trenches 22 have openings in the first surface 12A of the semiconductor layer 12. The direction in which the plurality of gate trenches 22 extend may coincide with the off-direction of the semiconductor layer 12, which is a SiC single crystal. In this embodiment, the off-direction of the semiconductor layer 12 is the a-axis direction of the SiC single crystal, i.e., the Y-axis direction.

[0028] Each of the multiple gate trenches 22 may include a side wall 22A extending from the first surface 12A into the semiconductor layer 12 and a bottom wall 22B. The side wall 22A shown in Figure 4 may be mainly formed by the m-plane ((1-100) plane) of the SiC single crystal. The plane of the SiC single crystal forming the side wall 22A may differ depending on the direction in which the gate trench 22 extends, and may, for example, be formed by the a-plane ((11-20) plane) of the SiC single crystal. In Figure 4, the side wall 22A is shown as extending perpendicular to the first surface 12A, but it may extend at a different angle to the first surface 12A.

[0029] The bottom wall 22B may be flat or partially curved. At least a portion of the bottom wall 22B may be formed by the c-plane (Si plane) of a SiC single crystal. Each gate trench 22 may have a width of 0.1 μm or more and 2 μm or less. Preferably, the width of the gate trench 22 may be 1 μm or less.

[0030] Each of the multiple gate trenches 22 may have a depth of 0.1 μm or more and 3 μm or less. The depth of the gate trench 22 is the depth relative to the first surface 12A of the semiconductor layer 12. Preferably, the depth of the gate trench 22 may be 0.5 μm or more and 1.5 μm or less.

[0031] The gate trench 22 may have an aspect ratio of 1 to 3. The aspect ratio of the gate trench 22 is the ratio of the depth of the gate trench 22 to the width of the gate trench 22. Preferably, the aspect ratio is 1.5 to 2.5.

[0032] Multiple gate trenches 22 may be arranged at intervals of 0.1 μm to 2 μm. In the example shown in Figure 3, the spacing between gate trenches 22 is the distance in the X-axis direction between multiple gate trenches 22. Preferably, the spacing between gate trenches 22 may be 1 μm or less.

[0033] (Impurity region in semiconductor layer) As shown in Figure 4, the second semiconductor layer 16 may include an n-type drift region 24 located on the first semiconductor layer 14 (drain region), a p-type body region 26 adjacent to the drift region 24, and an n-type source region 28 adjacent to the body region 26. The source region 28 may include at least a part of the first surface 12A of the semiconductor layer 12.

[0034] The drift region 24 is a region containing n-type impurities at a concentration lower than the n-type impurity concentration of the first semiconductor layer 14. The impurity concentration in the drift region 24 is 1 × 10⁻⁶. １５ cm －３ The above 1 x 10 １９ cm －３ The following is acceptable:

[0035] The n-type impurity included in the drift region 24 may include nitrogen (N), phosphorus (P), arsenic (As), and / or antimony (Sb). In one example, the n-type impurity included in the drift region 24 may be nitrogen (N).

[0036] The body region 26 may be located in the active region 18. The body region 26 may not be formed in the peripheral region 20. The p-type impurity concentration of the body region 26 is 1.0×10 １６ cm －３ to 1.0×10 １９ cm －３ and may be

[0037] The body region 26 forms a pn junction with the drift region 24. Accordingly, a body diode structure (pn junction diode structure) having the body region 26 as an anode and the drift region 24 as a cathode is formed in the semiconductor device 10. When a reverse bias voltage is applied to this body diode structure, a depletion layer spreads in the second semiconductor layer 16.

[0038] The source region 28 is a region containing an n-type impurity at a concentration higher than the n-type impurity concentration of the drift region 24. The n-type impurity concentration of the source region 28 is 1×10 １８ to 1×10 ２１ cm －３ and may be. The source region 28 may have a smaller thickness than the body region 26.

[0039] Each gate trench 22 penetrates the source region 28 and the body region 26 and reaches the drift region 24. In the present disclosure, the source region 28 may be referred to as a first semiconductor region, the body region 26 may be referred to as a second semiconductor region, and the drift region 24 may be referred to as a third semiconductor region. The source region 28 may form part of a sidewall 22A of the gate trench 22. The body region 26 may form part of a sidewall 22A of the gate trench 22. The drift region 24 may form part of the sidewall 22A of the gate trench 22 and the entire bottom wall 22B of the gate trench 22.

[0040] (Trench Gate Structure) As shown in Figure 4, the semiconductor device 10 further comprises an insulating layer 30 covering the semiconductor layer 12. The insulating layer 30 may include a first insulating layer 32 located on the first surface 12A of the semiconductor layer 12 and covering the side walls 22A and bottom wall 22B of the gate trench 22, and a second insulating layer 34 located on the first insulating layer 32.

[0041] In one example, the insulating layer 30 is made of silicon oxide (SiO ２ ), silicon nitride (SiN), and silicon oxynitride (SiON), hafnium oxide (HfO ２ ) may contain at least one of the following. The first insulating layer 32 may or may not contain the oxide of the second semiconductor layer 16.

[0042] The thickness of the first insulating layer 32 may be between 10 nm and 250 nm. The second insulating layer 34 may have a greater thickness than the first insulating layer 32. The thickness of the second insulating layer 34 may be between 0.1 μm and 5 μm.

[0043] The semiconductor device 10 further comprises a plurality of gate electrodes 36, each located within a plurality of gate trenches 22. The plurality of gate electrodes 36 are separated from the semiconductor layer 12 by a first insulating layer 32. Each gate electrode 36 is embedded in the corresponding gate trench 22 via the first insulating layer 32. Each gate electrode 36 faces a drift region 24, a body region 26, and a source region 28 via the first insulating layer 32.

[0044] When a predetermined voltage (for example, a voltage equal to or greater than the gate threshold voltage) is applied to the gate electrode 36, an inversion layer is formed in the body region 26 along the side wall 22A of the gate trench 22. The inversion layer in the p-type body region 26 functions as a channel between the n-type source region 28 and the n-type drift region 24. As a result, the semiconductor device 10 turns on. On the other hand, when the voltage applied to the gate electrode 36 is less than the gate threshold voltage, the semiconductor device 10 turns off, and no inversion layer is formed in the body region 26.

[0045] The channel length between the source region 28 and the drift region 24 may be greater than 0 nm and 500 nm or less. Preferably, the channel length may be 300 nm or less. The semiconductor device 10 further includes conductive cap portions 38 located outside the plurality of gate trenches 22 and extending to cover at least one of the plurality of gate trenches 22. The semiconductor device 10 may include a plurality of conductive cap portions 38, each located between two contact conductive portions 42 in a plan view. In this embodiment, the plurality of conductive cap portions 38 may each cover a plurality of gate trenches 22. That is, the number of conductive cap portions 38 may be the same as the number of gate trenches 22.

[0046] The conductive cap portion 38 is connected to the gate electrode 36 located within the gate trench 22 covered by the conductive cap portion 38. The conductive cap portion 38 is also covered by an insulating layer 30. More specifically, the side and top surfaces of the conductive cap portion 38 are covered by a second insulating layer 34. The conductive cap portion 38 is separated from the semiconductor layer 12 (first surface 12A) by a first insulating layer 32.

[0047] The conductive cap portion 38 may have a width greater than each of the multiple gate electrodes 36 in a direction (second direction) that intersects (for example, perpendicular to) the direction in which the contact conductive portion 42 extends (first direction) in a plan view. In the example of Figure 5, the gate electrode 36 has a width W in the X-axis direction. Ｇ The conductive cap portion 38 has a width W in the X-axis direction. ＣＡＰ It has a width W ＣＡＰ is width W Ｇ It is larger than that. For example, the width W of the conductive cap portion 38. ＣＡＰ The width W of the gate electrode 36 is Ｇ It may be 1.5 times or more. Preferably, the width W of the conductive cap portion 38. ＣＡＰ The width W of the gate electrode 36 is Ｇ It may be more than twice that area. Therefore, in a plan view, the conductive cap portion 38 has a larger area than the area of ​​the gate electrode 36 to which the conductive cap portion 38 is connected.

[0048] Here, the width W of the gate electrode 36.Ｇ This may be the dimension of the widest part of the gate electrode 36 in the X-axis direction. Alternatively, it may be the width W of the gate electrode 36. Ｇ This could also be the X-axis dimension of the gate electrode 36 (the portion of the gate electrode 36 located at the open end of the gate trench 22) at the same Z-axis position as the first surface 12A of the semiconductor layer 12.

[0049] Furthermore, the width W of the conductive cap portion 38 ＣＡＰ This may be the dimension of the widest part of the conductive cap portion 38 in the X-axis direction. Alternatively, it may be the width W of the conductive cap portion 38. ＣＡＰ This could also be the X-axis dimension of the conductive cap portion 38 at a position immediately above the first surface 12A of the semiconductor layer 12 (the same Z-axis position as the upper surface of the first insulating layer 32 covering the first surface 12A).

[0050] In the example shown in Figure 4, the height of the conductive cap portion 38 (dimension in the Z-axis direction) is smaller than the height of the gate electrode 36 (dimension in the Z-axis direction), but the disclosure is not limited to this example. The height of the conductive cap portion 38 may be greater than, equal to, or less than the height of the gate electrode 36. In one example, the height of the conductive cap portion 38 may be 0.1 to 10 times the height of the gate electrode 36. If the height of the conductive cap portion 38 is not uniform (for example, it varies in the X-axis direction), the height of the conductive cap portion 38 may refer to the average and / or maximum height of the conductive cap portion 38. Similarly, if the height of the gate electrode 36 is not uniform (for example, it varies in the X-axis direction), the height of the gate electrode 36 may refer to the average and / or maximum height of the gate electrode 36.

[0051] Furthermore, the cross-sectional area of ​​the conductive cap portion 38 in the ZX plane may be larger than, equal to, or smaller than the cross-sectional area of ​​the gate electrode 36 in the ZX plane. In one example, the cross-sectional area of ​​the conductive cap portion 38 in the ZX plane may be 0.1 to 10 times the cross-sectional area of ​​the gate electrode 36 in the ZX plane. The ZX plane is a plane perpendicular to the direction in which the gate trench 22 extends (Y-axis direction) in a plan view.

[0052] The smaller the height and / or cross-sectional area of ​​the conductive cap portion 38, the easier it is to ensure the flatness of the source electrode 40. On the other hand, the larger the height and / or cross-sectional area of ​​the conductive cap portion 38, the lower the gate resistance (the resistance of the conductor to which the gate voltage is applied, i.e., the conductor including the gate electrode 36 and the conductive cap portion 38) can be.

[0053] The conductive cap portion 38 may extend more widely than the gate electrode 36 on both sides of the gate electrode 36 in the X-axis direction. In the example of Figure 4, the center of the conductive cap portion 38 in the X-axis direction is aligned with the center of the gate electrode 36 in the X-axis direction, and as a result, the conductive cap portion 38 and the gate electrode 36 can form a T-shaped cross-section in the ZX plane. However, the disclosure is not limited to this example. For example, the conductive cap portion 38 may be positioned off-center in the X-axis direction relative to the gate electrode 36. In one example, the conductive cap portion 38 may extend more widely than the gate electrode 36 on only one side of the gate electrode 36 in the X-axis direction. In this case, the conductive cap portion 38 and the gate electrode 36 can form an L-shaped cross-section in the ZX plane.

[0054] In another example, the conductive cap portion 38 does not have to extend wider than the gate electrode 36 on either side of the gate electrode 36 in the X-axis direction. In this case, the conductive cap portion 38 and the gate electrode 36 may form an I-shaped cross-section in the ZX plane.

[0055] The gate electrode 36 may contain conductive polysilicon. The gate electrode 36 may contain either or both of the following: polysilicon containing p-type impurities and polysilicon containing n-type impurities. Preferably, the gate electrode 36 may be formed from conductive polysilicon containing n-type impurities.

[0056] The conductive cap portion 38 may contain conductive polysilicon. The conductive cap portion 38 may contain either or both of the following: polysilicon containing p-type impurities and polysilicon containing n-type impurities. Preferably, the conductive cap portion 38 may be formed from conductive polysilicon containing n-type impurities.

[0057] The conductive cap portion 38 may be integrally formed with the gate electrode 36 to which the conductive cap portion 38 is connected. The conductive cap portion 38 and the gate electrode 36 may be formed from the same conductive material.

[0058] The semiconductor device 10 further comprises a source electrode 40 located on an insulating layer 30 and a plurality of contact conductive portions 42 connected to the source electrode 40. The plurality of contact conductive portions 42 are arranged so as to overlap with the source electrode 40 in a plan view. The source electrode 40 and the contact conductive portions 42 are electrically connected to the semiconductor layer 12 through a plurality of source openings 44 formed in the insulating layer 30.

[0059] As shown in Figure 4, the multiple source openings 44 penetrate the insulating layer 30 (second insulating layer 34 and first insulating layer 32). Each source opening 44 may be embedded by a source electrode 40 and a contact conductive portion 42. Each contact conductive portion 42 may be partially embedded in the semiconductor layer 12 from the first surface 12A of the semiconductor layer 12.

[0060] As shown in Figure 3, in this embodiment, the multiple contact conductive parts 42 may extend parallel to the multiple gate trenches 22 in a plan view (in the Y-axis direction in the example of Figure 3). Each gate trench 22 may be located between two contact conductive parts 42 that are spaced apart in the X-axis direction. That is, the multiple contact conductive parts 42 and the multiple gate trenches 22 may be arranged alternately in a plan view. In addition, some of the multiple contact conductive parts 42 may be arranged with a gap in the Y-axis direction between two gate trenches 22 that are spaced apart in the X-axis direction.

[0061] The source electrode 40 may contain at least one of titanium (Ti), titanium nitride (TiN), nickel (Ni), gold (Au), silver (Ag), copper (Cu), palladium (Pd), aluminum (Al), and alloys thereof (e.g., AlCu, AlSi, AlSiCu, etc.). Each of the plurality of contact conductive portions 42 may contain a silicide. Examples of silicides include nickel (Ni), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), and vanadium (V) silicides.

[0062] As shown in Figure 4, the semiconductor layer 12 may include a plurality of contact regions 46 that contact a plurality of contact conductive portions 42. The contact regions 46 are regions containing p-type impurities at a higher concentration than the body region 26. In one example, the p-type impurity concentration in the contact region 46 is 1 × 10⁻⁶. １８ cm －３ The above 2 x 10 ２１ cm －３ The following is acceptable:

[0063] Each of the multiple contact regions 46 may extend in the Y-axis direction in a plan view, similar to the contact conductive portion 42. In another example, the multiple contact regions 46 may be formed at intervals in the Y-axis direction. The multiple contact regions 46 may be in contact with the bottom of each contact conductive portion 42. The multiple contact regions 46 may be adjacent to the source region 28. The multiple contact regions 46 may be located away from the first surface 12A of the semiconductor layer 12.

[0064] The semiconductor layer 12 may further include a p-type extended region 48 that is adjacent to the body region 26 and separated from the gate trenches 22, between the gate trenches 22. In Figure 4, the extended region 48 is shown as a p-type region continuous with the body region 26. The extended region 48 extends more widely in the depth direction than the body region 26. The distance between the extended region 48 and the second surface 12B is smaller than the distance between the gate trench 22 (bottom wall 22B) and the second surface 12B. The extended region 48 is separated from the side wall 22A of the gate trench 22 by a drift region 24.

[0065] The extended region 48 is adjacent to the drift region 24. When a reverse bias is applied to the pn junction between the p-type extended region 48 and the n-type drift region 24, a depletion layer spreads between the extended region 48 and the drift region 24, and this depletion layer can reduce the leakage current.

[0066] The p-type impurity concentration in the extended region 48 may be smaller than that of the p-type impurity region in the contact region 46. The p-type impurity concentration in the extended region 48 may be the same as or different from that of the body region 26. For example, the p-type impurity concentration in the extended region 48 may be smaller than that of the body region 26. In this disclosure, the extended region 48 may be referred to as the fourth semiconductor region.

[0067] The semiconductor device 10 may include a drain electrode 50 located on the second surface 12B of the semiconductor layer 12. The drain electrode 50 is electrically connected to the first semiconductor layer 14 (drain region). The drain electrode 50 may be in ohmic contact with the first semiconductor layer 14. The drain electrode 50 may contain at least one of titanium (Ti), titanium nitride (TiN), nickel (Ni), gold (Au), silver (Ag), copper (Cu), palladium (Pd), aluminum (Al), and alloys thereof (e.g., AlCu, AlSi, AlSiCu, etc.).

[0068] The drain electrode 50 may cover the entire second surface 12B of the semiconductor layer 12. Alternatively, the drain electrode 50 may cover a portion of the second surface 12B of the semiconductor layer 12 (for example, spaced apart from the first surface 12C1, the second surface 12C2, the third surface 12C3, and the fourth surface 12C4).

[0069] (Details of the outer region) Next, with reference to Figures 2 and 6, the outer region 20 of the semiconductor device 10 will be described further. The semiconductor layer 12 may further include a p-type outer well region 52 that includes a part of the first surface 12A. The outer well region 52 may extend along the periphery of the active region 18 in a plan view. A source potential may be applied to the outer well region 52. The outer well region 52 may be covered by an insulating layer 30 (first insulating layer 32).

[0070] The outer well region 52 may extend more widely in the depth direction than the body region 26. That is, the thickness of the outer well region 52 may be greater than the thickness of the body region 26. Also, the outer well region 52 may extend more widely in the depth direction than the gate trench 22. The outer well region 52 may be included in the second semiconductor layer 16. Therefore, the outer well region 52 may be separated from the first semiconductor layer 14.

[0071] In one example, some of the multiple gate trenches 22 may be formed within the outer well region 52. More specifically, some of the multiple gate trenches 22 that are located relatively close to the outer peripheral region 20 may be included within the outer well region 52.

[0072] The outer well region 52 may be separated from the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12. The outer well region 52 may have a width greater than 0 μm and less than or equal to 300 μm.

[0073] The p-type impurity concentration in the outer well region 52 may be the same as or different from the p-type impurity concentration in the body region 26. The p-type impurity concentration in the outer well region 52 may be lower than the p-type impurity concentration in the contact region 46. The p-type impurity concentration in the outer well region 52 may be the same as or different from the p-type impurity concentration in the extended region 48.

[0074] The outer well region 52 forms a pn junction with the drift region 24. When a reverse bias is applied to the pn junction between the p-type outer well region 52 and the n-type drift region 24, a depletion layer spreads between the outer well region 52 and the drift region 24. This depletion layer integrates with the depletion layer that spreads between the body region 26 and the drift region 24, thereby reducing the electric field strength in the outer peripheral region 20 (mitigating electric field concentration).

[0075] As shown in Figure 6, the semiconductor device 10 may include a p-type outer contact region 54 adjacent to the outer well region 52. The outer contact region 54 may extend along the periphery of the active region 18 in a plan view. The outer contact region 54 may be covered at least partially by an insulating layer 30 (first insulating layer 32).

[0076] The outer contact region 54 may include a portion of the first surface 12A of the semiconductor layer 12. The thickness of the outer contact region 54 may be less than the thickness of the outer well region 52. The outer contact region 54 may be located within the outer well region 52.

[0077] The outer contact region 54 has a higher p-type impurity concentration than the outer well region 52. The p-type impurity concentration in the outer contact region 54 is higher than the p-type impurity concentration in the body region 26. In one example, the p-type impurity concentration in the outer contact region 54 may be the same as that of the contact region 46. In another example, the p-type impurity concentration in the outer contact region 54 may be different from that of the contact region 46.

[0078] As shown in Figures 2 and 6, the semiconductor device 10 may include one or more (three in the example of Figure 6) p-type field regions 56 between the outer well region 52 and the first side surface 12C1, second side surface 12C2, third side surface 12C3, and fourth side surface 12C4 of the semiconductor layer 12. In one example, the number of field regions 56 may be between one and eight. One or more field regions 56 may extend along the periphery of the outer well region 52 in a plan view. In one example, one or more field regions 56 may be electrically floating. In another example, one or more field regions 56 may be fixed to the source potential. Each field region 56 may be covered by an insulating layer 30 (first insulating layer 32).

[0079] Each field region 56 may include a portion of the first surface 12A of the semiconductor layer 12. Each field region 56 may extend more widely in the depth direction than the body region 26. That is, the thickness of each field region 56 may be greater than the thickness of the body region 26. Also, each field region 56 may extend more widely in the depth direction than the gate trench 22. One or more field regions 56 may be included in the second semiconductor layer 16. Therefore, each field region 56 may be separated from the first semiconductor layer 14.

[0080] In one example, the thickness of each field region 56 may be equal to the thickness of the outer well region 52. In another example, the thickness of each field region 56 may be different from the thickness of the outer well region 52.

[0081] In one example, the thicknesses of the multiple field regions 56 may be uniform. In another example, the thicknesses of the multiple field regions 56 may differ from one another. For example, the thickness of the multiple field regions 56 may be greater closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4. Alternatively, the thickness of the multiple field regions 56 may be smaller closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4.

[0082] One or more field regions 56 may be spaced apart from the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12. In one example, the widths of the multiple field regions 56 may be uniform. In another example, the widths of the multiple field regions 56 may differ from one another. For example, the widths of the multiple field regions 56 may be larger closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4. Alternatively, the widths of the multiple field regions 56 may be smaller closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4.

[0083] The p-type impurity concentration in the field region 56 may be the same as or different from the p-type impurity concentration in the body region 26. The p-type impurity concentration in the field region 56 may be the same as or different from the p-type impurity concentration in the outer well region 52. The p-type impurity concentration in the field region 56 can take any value depending on the electric field to be relaxed.

[0084] The field region 56 forms a pn junction with the drift region 24. When a reverse bias is applied to the pn junction between the p-type field region 56 and the n-type drift region 24, a depletion layer spreads between the field region 56 and the drift region 24. This depletion layer integrates with the depletion layer that spreads between the body region 26 and the outer well region 52 and the drift region 24, thereby reducing the electric field strength in the outer peripheral region 20 (mitigating electric field concentration).

[0085] In one example, the spacing between the multiple field regions 56 may be uniform. In another example, the spacing between the multiple field regions 56 may be different from one another. For example, the spacing between the multiple field regions 56 may be larger closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4. Alternatively, the spacing between the multiple field regions 56 may be smaller closer to the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, or the fourth side surface 12C4.

[0086] As shown in Figure 6, the semiconductor device 10 may include gate wiring 58 located on the first insulating layer 32. The gate wiring 58 may face the outer well region 52 via the first insulating layer 32.

[0087] The gate wiring 58 is electrically connected to a plurality of gate electrodes 36 to provide a gate potential. The gate wiring 58 may be connected to the gate electrodes 36 via a conductive cap portion 38 at the end of the gate trench 22 (not shown). The gate wiring 58 may be formed integrally with the conductive cap portion 38.

[0088] The gate wiring 58 may have approximately the same thickness as the conductive cap portion 38 on the semiconductor layer 12. The upper surface of the gate wiring 58 may be at approximately the same position as the upper surface of the conductive cap portion 38 in the Z-axis direction. The bottom surface of the gate wiring 58 may be at approximately the same position as the bottom surface of the conductive cap portion 38 in the Z-axis direction. In one example, the gate wiring 58 may be manufactured simultaneously with the conductive cap portion 38 in a manufacturing process common to both.

[0089] The gate wiring 58 may contain conductive polysilicon. The gate wiring 58 may contain either or both of the following: polysilicon containing p-type impurities and polysilicon containing n-type impurities. Preferably, the gate wiring 58 may be formed from conductive polysilicon containing impurities of the same conductivity type as the gate electrode 36. Furthermore, the gate wiring 58 and the conductive cap portion 38 may be formed from the same conductive material.

[0090] The gate wiring 58 may be covered by a second insulating layer 34. The second insulating layer 34 includes a gate opening 60 that exposes the gate wiring 58. The gate opening 60 may extend along the gate wiring 58 in a plan view.

[0091] The semiconductor device 10 may further include gate finger electrodes 62 located on an insulating layer 30 and connected to gate wiring 58 via a gate opening 60. The gate finger electrodes 62 may face the gate wiring 58 in the Z-axis direction via a second insulating layer 34, at least partially. In one example, a portion of the gate finger electrodes 62 may not face the gate wiring 58, but instead face the outer well region 52 via the insulating layer 30.

[0092] As shown in Figure 1, the gate finger electrode 62 may extend so as to at least partially surround the source electrode 40 in a plan view. The gate finger electrode 62 may include portions that extend along the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12, respectively, in a plan view. The gate finger electrode 62 is separated from the source electrode 40 on the insulating layer 30.

[0093] The semiconductor device 10 may further include a gate pad electrode 64 located on the insulating layer 30 and connected to the gate finger electrode 62. In the example shown in Figure 2, the gate pad electrode 64 is located relatively close to the central portion of the fourth side surface 12C4 of the semiconductor layer 12 in a plan view.

[0094] The gate pad electrode 64 is located on the insulating layer 30, separated from the source electrode 40. In the example shown in Figure 1, the source electrode 40 has a recess 40A that extends from the fourth side surface 12C4 toward the second side surface 12C2 of the semiconductor layer 12 in a plan view. The gate pad electrode 64 may be located within the recess 40A of the source electrode 40. The gate pad electrode 64 may have a smaller area than the source electrode 40.

[0095] The arrangement of the gate pad electrodes 64 shown in Figure 1 is just one example, and the gate pad electrodes 64 may be arranged in different positions. For example, the gate pad electrodes 64 may be located relatively close to the corners of the semiconductor layer 12 in a plan view.

[0096] As shown in Figure 2, the gate pad electrode 64 may face the outer well region 52 in the Z-axis direction via the insulating layer 30. The gate pad electrode 64 may be located in a position that overlaps with the outer peripheral region 20 in a plan view.

[0097] The gate pad electrode 64 is electrically connected to the gate wiring 58 (see Figure 6) via the gate finger electrode 62. In another example, the gate pad electrode 64 may be directly connected to the gate wiring 58 through an opening formed in the insulating layer 30.

[0098] As shown in Figure 1, the semiconductor device 10 may further include a source finger electrode 66 located on the insulating layer 30 and connected to the source electrode 40. The source finger electrode 66 may extend so as to surround the gate finger electrode 62 and the gate pad electrode 64 in a plan view. In a plan view, the source finger electrode 66 may include portions extending along the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12, respectively. On the insulating layer 30, the source finger electrode 66 is separated from the gate finger electrode 62 and the gate pad electrode 64. The source finger electrode 66 may be configured to transmit the source potential applied to the source electrode 40 to other regions.

[0099] As shown in Figure 6, the source finger electrode 66 may extend so as to overlap with the outer well region 52 in a plan view. The semiconductor device 10 may further include an outer contact conductive portion 68 connected to the source finger electrode 66. The source finger electrode 66 and the outer contact conductive portion 68 are electrically connected to the outer contact region 54 via an outer opening 70 formed in the insulating layer 30. The outer opening 70 may have a width smaller than the outer contact region 54. The outer opening 70 penetrates the insulating layer 30 (the second insulating layer 34 and the first insulating layer 32). The outer opening 70 may be filled by the source finger electrode 66 and the outer contact conductive portion 68. The outer contact conductive portion 68 may be partially embedded in the semiconductor layer 12 from the first surface 12A of the semiconductor layer 12. This allows the source finger electrode 66 to transmit the source potential applied to the source electrode 40 to the outer contact region 54 and the outer well region 52.

[0100] (Upper insulating layer) As shown in Figure 1, the semiconductor device 10 may include an upper insulating layer 72 located on the insulating layer 30 and covering at least partially the source electrode 40, source finger electrode 66, gate finger electrode 62, and gate pad electrode 64. In the example of Figure 1, the upper insulating layer 72 covers the entire source finger electrode 66 and gate finger electrode 62.

[0101] The upper insulating layer 72 may include a gate pad opening 74 that exposes the gate pad electrode 64. The gate pad opening 74 overlaps with the gate pad electrode 64 in a plan view. The gate pad opening 74 may have a smaller area than the gate pad electrode 64.

[0102] The upper insulating layer 72 may include a first source pad opening 76A, a second source pad opening 76B, and a third source pad opening 76C that expose the source electrode 40. The first source pad opening 76A, the second source pad opening 76B, and the third source pad opening 76C may overlap the source electrode 40 in a plan view. The combined area of ​​the first source pad opening 76A, the second source pad opening 76B, and the third source pad opening 76C may be smaller than the area of ​​the source electrode 40. In the example of Figure 1, the first source pad opening 76A has a larger area than the second source pad opening 76B and the third source pad opening 76C. The first source pad opening 76A is spaced apart from the gate pad opening 74, the second source pad opening 76B, and the third source pad opening 76C in the X-axis direction. The second source pad opening 76B and the third source pad opening 76C are spaced apart from the gate pad opening 74 in the Y-axis direction. The gate pad opening 74 is located between the second source pad opening 76B and the third source pad opening 76C.

[0103] The gate pad opening 74 can be used to connect the gate pad electrode 64 to an external connection terminal (not shown). The first source pad opening 76A, the second source pad opening 76B, and / or the third source pad opening 76C can be used to connect the source electrode 40 to an external connection terminal (not shown). The second source pad opening 76B and / or the third source pad opening 76C may be used to monitor the current flowing through the source electrode 40.

[0104] The number of openings formed in the upper insulating layer 72 is arbitrary. For example, there may be only one opening to expose the source electrode 40. The upper insulating layer 72 may be separated from the first side surface 12C1, the second side surface 12C2, the third side surface 12C3, and the fourth side surface 12C4 of the semiconductor layer 12 in a plan view. Therefore, the peripheral edge of the insulating layer 30 does not have to be covered by the upper insulating layer 72.

[0105] As shown in Figures 2 and 6, the upper insulating layer 72 may include a first upper insulating layer 78 and a second upper insulating layer 80 located on the first upper insulating layer 78. In one example, the first upper insulating layer 78 may be made of an inorganic material and the second upper insulating layer 80 may be made of an organic material.

[0106] The first upper insulating layer 78 may contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. Preferably, the first upper insulating layer 78 may contain an insulating material different from that of the insulating layer 30. The first upper insulating layer 78 may have a thickness less than that of the source electrode 40. The first upper insulating layer 78 may have a thickness greater than 0 μm and 2 μm or less.

[0107] The second upper insulating layer 80 may contain a resin. The second upper insulating layer 80 may contain a light-transmitting resin. The second upper insulating layer 80 may contain a negative-type or positive-type photosensitive resin. The second upper insulating layer 80 may contain at least one of polyimide, polyamide, and polybenzoxazole. The second upper insulating layer 80 may have a greater thickness than the first upper insulating layer 78. The second upper insulating layer 80 may have a thickness of 1 μm or more and 25 μm or less.

[0108] The upper insulating layer 72 does not necessarily have to have a laminated structure including the first upper insulating layer 78 and the second upper insulating layer 80, and may include only one of the first upper insulating layer 78 and the second upper insulating layer 80.

[0109] (Operation of the semiconductor device) The operation of the semiconductor device 10 will be described below. The semiconductor device 10 includes a plurality of gate electrodes 36, each located within a plurality of gate trenches 22, and a conductive cap portion 38 located outside the plurality of gate trenches 22 and extending to cover at least one of the plurality of gate trenches 22. The conductive cap portion 38 is connected to a gate electrode 36 located within at least one gate trench 22 covered by the conductive cap portion 38.

[0110] With this configuration, in addition to the gate electrode 36 inside the gate trench 22, there is also a conductive cap portion 38 connected to the gate electrode 36 outside the gate trench 22. Therefore, the cross-sectional area of ​​the conductor to which the gate voltage is applied can be increased without increasing the dimensions of the gate trench 22. Consequently, the gate resistance of the semiconductor device 10 can be reduced. By reducing the gate resistance of the semiconductor device 10, for example, the switching loss of the semiconductor device 10 can be reduced.

[0111] The semiconductor device 10 according to this embodiment has the following advantages: (1-1) The semiconductor device 10 includes a plurality of gate electrodes 36, each located within a plurality of gate trenches 22, and a conductive cap portion 38 located outside the plurality of gate trenches 22 and extending to cover at least one of the plurality of gate trenches 22. The conductive cap portion 38 is connected to a gate electrode 36 located within at least one gate trench 22 covered by the conductive cap portion 38.

[0112] With this configuration, in addition to the gate electrode 36 inside the gate trench 22, there is also a conductive cap portion 38 connected to the gate electrode 36 outside the gate trench 22. Therefore, the cross-sectional area of ​​the conductor to which the gate voltage is applied can be increased without increasing the dimensions of the gate trench 22. Consequently, the gate resistance of the semiconductor device 10 can be reduced.

[0113] (1-2) In a plan view, the conductive cap portion 38 has a larger area than the gate electrode 36 to which the conductive cap portion 38 is connected. With this configuration, the conductive cap portion 38, which has a larger area than the gate electrode 36, makes it possible to reduce the gate resistance without being constrained by the dimensions of the gate trench 22.

[0114] (1-3) The conductive cap portion 38 is integrally formed with the gate electrode 36 to which the conductive cap portion 38 is connected. With this configuration, the gate resistance can be reduced compared to the case where the gate electrode 36 and the conductive cap portion 38 are not integrally formed. In addition, the manufacturing process of the gate electrode 36 and the conductive cap portion 38 can be simplified.

[0115] (1-4) The semiconductor device 10 further comprises a source electrode 40 located on an insulating layer 30 and a plurality of contact conductive portions 42 connected to the source electrode 40, and the semiconductor layer 12 includes a plurality of p-type (second conductivity type) contact regions 46 adjacent to the plurality of contact conductive portions 42, and the plurality of contact regions 46 have a higher p-type (second conductivity type) impurity concentration than the body region 26 (second semiconductor region).

[0116] This configuration makes it possible to reduce the contact resistance between the multiple contact conductive parts 42 and the semiconductor layer 12. (1-5) The semiconductor layer 12 includes a first surface 12A provided with a plurality of gate trenches 22 and a second surface 12B opposite to the first surface 12A. The semiconductor layer 12 includes a p-type (second conductivity type) extended region 48 (fourth semiconductor region) between the plurality of gate trenches 22 that is adjacent to the body region (second semiconductor region) and separated from the plurality of gate trenches 22. The distance between the extended region 48 and the second surface 12B is smaller than the distance between the plurality of gate trenches 22 and the second surface 12B.

[0117] With this configuration, the extended region 48 extends relatively close to the second surface 12B of the semiconductor layer 12, so the depletion layer can be extended from the extended region 48 to relatively close to the second surface 12B of the semiconductor layer 12. Therefore, the leakage current of the semiconductor device 10 can be reduced.

[0118] <Second Embodiment> Next, an exemplary semiconductor device 100 according to the second embodiment will be described with reference to Figures 7 to 10. Figure 7 is a schematic plan view of the semiconductor device 100. Figure 8 is a schematic cross-sectional view of the semiconductor device 100 along the line F8-F8 in Figure 7. Figure 9 is a schematic plan cross-sectional view of the semiconductor device 100 along the line F9-F9 in Figure 8. Figure 10 is a schematic cross-sectional view of the semiconductor device 100 along the line F10-F10 in Figure 9. In Figures 7 to 10, the same reference numerals are used for components similar to those of the semiconductor device 10. Detailed explanations of components similar to those of the semiconductor device 10 will be omitted.

[0119] As shown in Figures 7, 9, and 10, the semiconductor layer 12 of the semiconductor device 100 includes a plurality of gate trenches 102 spaced apart from each other. When each of the plurality of contact conductive portions 42 extends in a first direction (the Y-axis direction in the example of Figure 7) in a plan view, the plurality of contact conductive portions 42 include a first contact conductive portion 42A and a second contact conductive portion 42B that face each other in a second direction (the X-axis direction in the example of Figure 7) that intersects the first direction in a plan view. At least a portion of the plurality of gate trenches 102 is spaced apart in the first direction between the first contact conductive portion 42A and the second contact conductive portion 42B.

[0120] Multiple gate trenches 102 are provided on the first surface 12A of the semiconductor layer 12. Each of the multiple gate trenches 102 is rectangular in shape in a plan view, having a first dimension D1 along a first direction and a second dimension D2 along a second direction (see Figure 7). Here, the first dimension D1 may be larger than the second dimension D2. In one example, some of the multiple gate trenches 102 may be arranged in the first direction at intervals smaller than the first dimension D1. In another example, the first dimension D1 may be equal to the second dimension D2. In the example of Figure 7, the first direction in which the multiple gate trenches 102 extend may coincide with the off-direction of the semiconductor layer 12, which is a SiC single crystal (for example, the a-axis direction of the SiC single crystal). For other features of the gate trenches 102, please refer to the description of the gate trenches 22.

[0121] As shown in Figures 8 to 10, the semiconductor device 100 further includes a conductive cap portion 104 located outside the plurality of gate trenches 102 and extending to cover at least one of the plurality of gate trenches 102. The semiconductor device 100 may include a plurality of conductive cap portions 104, each located between two contact conductive portions 42 in a plan view.

[0122] The conductive cap portion 104 may be connected to a gate electrode 36 located within at least one gate trench 102 covered by the conductive cap portion 104. In this embodiment, the conductive cap portion 104 extends to cover a plurality of gate trenches 102 and connects a plurality of gate electrode 36 to each other. Therefore, in this embodiment, the number of conductive cap portions 104 is less than the number of gate trenches 102.

[0123] As shown in Figure 8, the conductive cap portion 104 extends onto the first insulating layer 32 even in a position where no gate trench 102 exists (a position between two gate trenches 102 that are spaced apart in the first direction). The conductive cap portion 104 is covered by the insulating layer 30. More specifically, the side and top surfaces of the conductive cap portion 104 are covered by the second insulating layer 34. The conductive cap portion 104 is separated from the semiconductor layer 12 (first surface 12A) by the first insulating layer 32.

[0124] As shown in Figure 9, the conductive cap portion 104 may have a width greater than each of the multiple gate electrodes 36 in the second direction (X-axis direction). In the example in Figure 9, the gate electrode 36 has a width W in the X-axis direction. Ｇ The conductive cap portion 104 has a width W in the X-axis direction. ＣＡＰ It has a width W ＣＡＰ is width W Ｇ Larger than that. For example, the width W of the conductive cap portion 104. ＣＡＰ The width W of the gate electrode 36 is Ｇ It may be 1.5 times or more. Preferably, the width W of the conductive cap portion 104. ＣＡＰ The width W of the gate electrode 36 is ＧIt may be more than twice that area. In a plan view, the conductive cap portion 104 has a larger area than the area of ​​the gate electrode 36 to which the conductive cap portion 104 is connected (the sum of the areas of the multiple gate electrode 36).

[0125] Here, the width W of the gate electrode 36. Ｇ This may be the dimension of the widest part of the gate electrode 36 in the X-axis direction. Alternatively, it may be the width W of the gate electrode 36. Ｇ This could also be the X-axis dimension of the gate electrode 36 (the portion of the gate electrode 36 located at the open end of the gate trench 102) at the same Z-axis position as the first surface 12A of the semiconductor layer 12.

[0126] Furthermore, the width W of the conductive cap portion 104 ＣＡＰ This may be the dimension of the widest part of the conductive cap portion 104 in the X-axis direction. Alternatively, it may be the width W of the conductive cap portion 104. ＣＡＰ This could also be the X-axis dimension of the conductive cap portion 104 at a position immediately above the first surface 12A of the semiconductor layer 12 (the same Z-axis position as the upper surface of the first insulating layer 32 covering the first surface 12A).

[0127] In the example shown in Figure 10, the height of the conductive cap portion 104 (dimension in the Z-axis direction) is smaller than the height of the gate electrode 36 (dimension in the Z-axis direction), but the disclosure is not limited to this example. The height of the conductive cap portion 104 may be greater than, equal to, or less than the height of the gate electrode 36. In one example, the height of the conductive cap portion 104 may be 0.1 to 10 times the height of the gate electrode 36. If the height of the conductive cap portion 104 is not uniform (for example, it varies in the X-axis direction), the height of the conductive cap portion 104 may refer to the average and / or maximum height of the conductive cap portion 104. Similarly, if the height of the gate electrode 36 is not uniform (for example, it varies in the X-axis direction), the height of the gate electrode 36 may refer to the average and / or maximum height of the gate electrode 36.

[0128] Furthermore, the cross-sectional area of ​​the conductive cap portion 104 in the ZX plane may be larger than, equal to, or smaller than the cross-sectional area of ​​the gate electrode 36 in the ZX plane. In one example, the cross-sectional area of ​​the conductive cap portion 104 in the ZX plane may be 0.1 to 10 times the cross-sectional area of ​​the gate electrode 36 in the ZX plane. The ZX plane is a plane perpendicular to the direction in which the gate trench 102 extends (Y-axis direction) in a plan view.

[0129] The smaller the height and / or cross-sectional area of ​​the conductive cap portion 104, the easier it is to ensure the flatness of the source electrode 40. On the other hand, the larger the height and / or cross-sectional area of ​​the conductive cap portion 104, the lower the gate resistance (the resistance of the conductor to which the gate voltage is applied, i.e., the conductor including the multiple gate electrodes 36 and the conductive cap portion 104) can be.

[0130] The conductive cap portion 104 may extend more widely than the gate electrode 36 on both sides of the gate electrode 36 in the X-axis direction. In the example of Figure 9, the center of the conductive cap portion 104 in the X-axis direction is aligned with the center of the gate electrode 36 in the X-axis direction, and as a result, the conductive cap portion 104 and the gate electrode 36 can form a T-shaped cross-section in the ZX plane (similar to the cross-section of the conductive cap portion 38 and gate electrode 36 shown in Figure 4). However, the disclosure is not limited to this example. For example, the conductive cap portion 104 may be positioned off-center in the X-axis direction relative to the gate electrode 36. In one example, the conductive cap portion 104 may extend more widely than the gate electrode 36 on only one side of the gate electrode 36 in the X-axis direction. In this case, the conductive cap portion 104 and the gate electrode 36 can form an L-shaped cross-section in the ZX plane.

[0131] In another example, the conductive cap portion 104 does not have to extend wider than the gate electrode 36 on either side of the gate electrode 36 in the X-axis direction. In this case, the conductive cap portion 104 and the gate electrode 36 may form an I-shaped cross-section in the ZX plane.

[0132] As shown in Figures 7 and 8, in this embodiment, the source region 28 extends continuously around the multiple gate trenches 102 at least below the conductive cap portion 104. The multiple contact conductive portions 42 are in contact with the source region 28 at a position away from the conductive cap portion 104 in a plan view.

[0133] As shown in Figure 7, the source region 28 located between the first contact conductive portion 42A and the second contact conductive portion 42B extends continuously around the gate trenches 102, at least below the conductive cap portion 104, because the gate trenches 102 are spaced apart in the first direction. For example, if a single gate trench extended uninterrupted in the first direction between the first contact conductive portion 42A and the second contact conductive portion 42B in a plan view, the source region 28 located between the first contact conductive portion 42A and the second contact conductive portion 42B would be divided by that single gate trench. In this embodiment, since the gate trenches 102 located between the first contact conductive portion 42A and the second contact conductive portion 42B are spaced apart in the first direction, such division of the source region 28 does not occur. Therefore, the uniformity of the potential of the source region 28 between the first contact conductive portion 42A and the second contact conductive portion 42B can be ensured and / or improved.

[0134] As shown in Figure 10, the conductive cap portion 104 connects gate electrodes 36 embedded in separate gate trenches 102. The conductive cap portion 104 extends not only over the gate electrodes 36 but also between the gate trenches 102. The conductive cap portion 104 may be formed integrally with the plurality of gate electrodes 36 to which the conductive cap portion 104 is connected. The conductive cap portion 104 and the gate electrodes 36 may be formed from the same conductive material.

[0135] In the example shown in Figure 10, the p-shaped extension region 48 is formed adjacent to the body region 26 between the gate trenches 102 that are spaced apart in the first direction. The extension region 48 may be adjacent to the body region 26 and separated from the gate trenches 102 between the gate trenches 102. In another example, the extension region 48 may not be formed between the gate trenches 102 that are spaced apart in the first direction.

[0136] The semiconductor device 100 of this embodiment may have an outer peripheral region 20 and related components similar to those of the semiconductor device 10 of the first embodiment described with reference to Figures 1, 2, and 6. The gate wiring 58 shown in Figure 6 may have approximately the same thickness as the conductive cap portion 104 on the semiconductor layer 12. The upper surface of the gate wiring 58 may be in approximately the same position as the upper surface of the conductive cap portion 104 in the Z-axis direction. The bottom surface of the gate wiring 58 may be in approximately the same position as the bottom surface of the conductive cap portion 104 in the Z-axis direction. In one example, the gate wiring 58 may be manufactured simultaneously in a manufacturing process common to the conductive cap portion 104.

[0137] As described above, in this embodiment, the conductive cap portion 104 extends to cover a plurality of gate trenches 102 and connects a plurality of gate electrodes 36 to each other, so that the source region 28 is not interrupted and the gate electrodes 36 located in a plurality of gate trenches 102 that are spaced apart in the first direction can be electrically connected.

[0138] The semiconductor device 100 according to this embodiment has the following advantages: (2-1) The conductive cap portion 104 extends to cover a plurality of gate trenches 102 and connects a plurality of gate electrodes 36 to each other.

[0139] This configuration allows for the electrical connection of multiple gate electrodes 36 located within multiple gate trenches 102 that are spaced apart from each other. (2-2) The semiconductor layer 12 includes at least an n-type (first conductivity type) source region 28 (first semiconductor region) that extends continuously around the multiple gate trenches 102 below the conductive cap portion 104, and the multiple contact conductive portions 42 are in contact with the source region 28 (first semiconductor region) at a position away from the conductive cap portion 104 in a plan view.

[0140] With this configuration, since the source region 28 is not interrupted between the multiple contact conductive parts 42, the uniformity of the potential of the source region 28 can be ensured and / or improved.

[0141] (2-3) Each of the plurality of contact conductive portions 42 extends in a first direction in a plan view. The plurality of contact conductive portions 42 include a first contact conductive portion 42A and a second contact conductive portion 42B that face each other in a second direction intersecting the first direction in a plan view. At least a portion of the plurality of gate trenches 102 is spaced apart in the first direction between the first contact conductive portion 42A and the second contact conductive portion 42B.

[0142] With this configuration, the source region 28 between the first contact conductive portion 42A and the second contact conductive portion 42B can be prevented from being divided in the second direction by the gate trench 102. Therefore, the uniformity of the potential of the source region 28 between the first contact conductive portion 42A and the second contact conductive portion 42B can be ensured and / or improved.

[0143] In addition to the various advantages described above, the semiconductor device 100 also has the same advantages as the semiconductor device 10 of the first embodiment (1-1) to (1-5). <Third Embodiment> Next, an exemplary semiconductor device 200 according to the third embodiment will be described with reference to Figures 11 to 14. Figure 11 is a schematic plan view of the semiconductor device 200. Figure 12 is a schematic cross-sectional view of the semiconductor device 200 along the line F12-F12 in Figure 11. Figure 13 is a schematic cross-sectional view of the semiconductor device 200 along the line F13-F13 in Figure 11. Figure 14 is a schematic plan cross-sectional view of the semiconductor device 200 along the line F14-F14 in Figure 12. In Figures 11 to 14, the same reference numerals are used for components similar to those of the semiconductor device 10. Detailed explanations of components similar to those of the semiconductor device 10 will be omitted.

[0144] As shown in Figures 11, 12, and 14, the semiconductor layer 12 of the semiconductor device 200 includes a plurality of gate trenches 202 spaced apart from each other. When each of the plurality of contact conductive portions 42 extends in a first direction (the Y-axis direction in the example of Figure 11) in a plan view, the plurality of contact conductive portions 42 include a first contact conductive portion 42A and a second contact conductive portion 42B that face each other in a second direction (the X-axis direction in the example of Figure 11) that intersects the first direction in a plan view. A portion of the plurality of gate trenches 202 is spaced apart in the first direction between the first contact conductive portion 42A and the second contact conductive portion 42B. Also, a portion of the plurality of gate trenches 202 is spaced apart in the second direction between the first contact conductive portion 42A and the second contact conductive portion 42B. In this embodiment, the plurality of gate trenches 202 may be arranged in a matrix in a plan view. Each gate trench 202 faces another gate trench 202 in a first direction and yet another gate trench 202 in a second direction.

[0145] In the examples of Figures 11, 12, and 14, three rows of gate trenches 202 are arranged between the first contact conductive portion 42A and the second contact conductive portion 42B, spaced apart in the second direction, with each row of gate trenches 202 spaced apart in the first direction. Each of the gate trenches 202 in the rows located at both ends in the second direction is adjacent to either the first contact conductive portion 42A or the second contact conductive portion 42B. Each of the gate trenches 202 in the middle row of the three rows is not adjacent to either the first contact conductive portion 42A or the second contact conductive portion 42B, and is located between the two gate trenches 202 in the second direction.

[0146] In another example, four or more rows of gate trenches 202 may be arranged between the first contact conductive portion 42A and the second contact conductive portion 42B, spaced apart in the second direction. In this case, there may be multiple rows that are not adjacent to the first contact conductive portion 42A and the second contact conductive portion 42B.

[0147] In yet another example, there may be two rows of gate trenches 202 spaced apart in the second direction between the first contact conductive portion 42A and the second contact conductive portion 42B. In this case, each gate trench 202 in each row is adjacent to either the first contact conductive portion 42A or the second contact conductive portion 42B. On the other hand, in this example, there may not be a central row of gate trenches 202 that are not adjacent to the first contact conductive portion 42A and the second contact conductive portion 42B, as shown in Figure 11.

[0148] Multiple gate trenches 202 are provided on the first surface 12A of the semiconductor layer 12. In the example in Figure 11, the first direction in which the multiple gate trenches 202 extend may coincide with the off-direction of the semiconductor layer 12, which is a SiC single crystal (for example, the a-axis direction of the SiC single crystal). For other features of the gate trenches 202, please refer to the description of the gate trenches 22.

[0149] As shown in Figures 12 to 14, the semiconductor device 200 further comprises a conductive cap portion 204 located outside the plurality of gate trenches 202 and extending to cover at least one of the plurality of gate trenches 202. The semiconductor device 200 may comprise a plurality of conductive cap portions 204, each located between two contact conductive portions 42 in a plan view.

[0150] The conductive cap portion 204 may be connected to a gate electrode 36 located within at least one gate trench 202 covered by the conductive cap portion 204. In this embodiment, the conductive cap portion 204 extends to cover a plurality of gate trenches 202 and connects a plurality of gate electrode 36 to each other. Therefore, in this embodiment, the number of conductive cap portions 204 is less than the number of gate trenches 202.

[0151] As shown in Figure 12, a plurality of gate trenches 202, spaced apart in the second direction (X-axis direction), are positioned between the first contact conductive portion 42A and the second contact conductive portion 42B. The conductive cap portion 204 covers the plurality of gate trenches 202, which are spaced apart in the second direction. In this embodiment, it is not necessary to position the contact conductive portions 42 between the gate trenches 202 covered by the conductive cap portion 204.

[0152] In the example shown in Figure 12, the p-type extension region 48 is formed adjacent to the body region 26 between gate trenches 202 where the contact conductive portion 42 is not located. The extension region 48 may be adjacent to the body region 26 and separated from the gate trenches 202 between the gate trenches 202. In another example, the extension region 48 may not be formed between gate trenches 202 where the contact conductive portion 42 is not located.

[0153] As shown in Figure 13, the conductive cap portion 204 extends onto the first insulating layer 32 even in a position where no gate trench 202 exists (a position between two gate trenches 202 spaced apart in the first direction). The conductive cap portion 204 is covered by the insulating layer 30. More specifically, the side and top surfaces of the conductive cap portion 204 are covered by the second insulating layer 34. The conductive cap portion 204 is separated from the semiconductor layer 12 (first surface 12A) by the first insulating layer 32.

[0154] As shown in Figure 14, the conductive cap portion 204 may have a width greater than each of the multiple gate electrodes 36 in the second direction (X-axis direction). In the example in Figure 14, the gate electrode 36 has a width W in the X-axis direction. Ｇ The conductive cap portion 204 has a width W in the X-axis direction. ＣＡＰ It has a width W ＣＡＰ is width W Ｇ It is larger than. In this embodiment, the conductive cap portion 204 covers a plurality of gate trenches 202 that are spaced apart in the second direction, so the width W of the conductive cap portion 204 ＣＡＰ The width W of the gate electrode 36 is Ｇ It may be 3.0 times or more. In a plan view, the conductive cap portion 204 has a larger area than the area of ​​the gate electrode 36 to which the conductive cap portion 204 is connected (the sum of the areas of the multiple gate electrode 36).

[0155] Here, the width W of the gate electrode 36. Ｇ This may be the dimension of the widest part of the gate electrode 36 in the X-axis direction. Alternatively, it may be the width W of the gate electrode 36. Ｇ This could also be the X-axis dimension of the gate electrode 36 (the portion of the gate electrode 36 located at the open end of the gate trench 202) at the same Z-axis position as the first surface 12A of the semiconductor layer 12.

[0156] Furthermore, the width W of the conductive cap portion 204 ＣＡＰ This may be the dimension of the widest part of the conductive cap portion 204 in the X-axis direction. Alternatively, it may be the width W of the conductive cap portion 204. ＣＡＰThis could also be the X-axis dimension of the conductive cap portion 204 at a position immediately above the first surface 12A of the semiconductor layer 12 (the same Z-axis position as the upper surface of the first insulating layer 32 covering the first surface 12A).

[0157] In the example shown in Figure 12, the height of the conductive cap portion 204 (dimension in the Z-axis direction) is smaller than the height of the gate electrode 36 (dimension in the Z-axis direction), but the disclosure is not limited to this example. The height of the conductive cap portion 204 may be greater than, equal to, or less than the height of the gate electrode 36. In one example, the height of the conductive cap portion 204 may be 0.1 to 10 times the height of the gate electrode 36. If the height of the conductive cap portion 204 is not uniform (for example, it varies in the X-axis direction), the height of the conductive cap portion 204 may refer to the average and / or maximum height of the conductive cap portion 104. Similarly, if the height of the gate electrode 36 is not uniform (for example, it varies in the X-axis direction), the height of the gate electrode 36 may refer to the average and / or maximum height of the gate electrode 36.

[0158] The smaller the height and / or cross-sectional area of ​​the conductive cap portion 204, the easier it is to ensure the flatness of the source electrode 40. On the other hand, the larger the height and / or cross-sectional area of ​​the conductive cap portion 204, the lower the gate resistance (the resistance of the conductor to which the gate voltage is applied, i.e., the conductor including the multiple gate electrodes 36 and the conductive cap portion 204) can be.

[0159] As shown in Figure 12, the conductive cap portion 204 may include a portion extending toward the first contact conductive portion 42A from the gate electrode 36 closest to the first contact conductive portion 42A (the leftmost gate electrode 36 in Figure 12). Similarly, the conductive cap portion 204 may include a portion extending toward the second contact conductive portion 42B from the gate electrode 36 closest to the second contact conductive portion 42B (the rightmost gate electrode 36 in Figure 12). In the example in Figure 12, the center of the conductive cap portion 204 in the X-axis direction is aligned with the central row of the gate trench 202. However, the disclosure is not limited to this example. For example, the conductive cap portion 204 may be positioned offset in the X-axis direction with respect to the central row of the gate trench 202. In one example, the conductive cap portion 204 includes a portion extending from the gate electrode 36 closest to the first contact conductive portion 42A toward the first contact conductive portion 42A, but does not necessarily include a portion extending from the gate electrode 36 closest to the second contact conductive portion 42B toward the second contact conductive portion 42B.

[0160] In another example, the conductive cap portion 204 does not have to include both a portion extending toward the first contact conductive portion 42A from the gate electrode 36 closest to the first contact conductive portion 42A, and a portion extending toward the second contact conductive portion 42B from the gate electrode 36 closest to the second contact conductive portion 42B.

[0161] As shown in Figures 11 and 13, in this embodiment, the source region 28 extends continuously around the multiple gate trenches 202 at least below the conductive cap portion 204. The multiple contact conductive portions 42 are in contact with the source region 28 at a position away from the conductive cap portion 204 in a plan view.

[0162] The source region 28 located between the first contact conductive portion 42A and the second contact conductive portion 42B, as shown in Figure 11, extends continuously around the gate trenches 202, at least below the conductive cap portion 204, because the gate trenches 202 are spaced apart in the first and second directions. For example, if a single gate trench extended uninterrupted in the first direction between the first contact conductive portion 42A and the second contact conductive portion 42B in a plan view, the source region 28 located between the first contact conductive portion 42A and the second contact conductive portion 42B would be divided by that single gate trench. In this embodiment, since the gate trenches 202 located between the first contact conductive portion 42A and the second contact conductive portion 42B are spaced apart in the first and second directions, such division of the source region 28 does not occur. Therefore, the uniformity of the potential in the source region 28 between the first contact conductive portion 42A and the second contact conductive portion 42B can be ensured and / or improved.

[0163] In this embodiment, since the source region 28 is not divided as described above, it is not necessarily required to provide the contact conductive portion 42 between the gate trenches 202. On the other hand, in the first embodiment, for example, as shown in Figure 3, the gate trench 22 extends continuously in the Y-axis direction, so the source region 28 is divided, and therefore it is necessary to provide the contact conductive portion 42 between the two gate trenches 22. When providing the contact conductive portion 42 between the gate trenches 22, the spacing between the gate trenches 22 must be wide enough to accommodate the contact conductive portion 42. For this reason, in the semiconductor device 10 of the first embodiment, in which the gate trenches 22 and contact conductive portion 42 are arranged alternately, there is a limit to how closely the gate trenches 22 can be arranged.

[0164] In this respect, in this embodiment, the contact conductive portion 42 does not necessarily have to be placed between the gate trenches 202 which are spaced apart in the second direction, so the spacing between the gate trenches 202 can be made relatively small. For example, as shown in Figure 11, the contact conductive portion 42 has a width W in the second direction. ＣＯＮＴIf it has, the spacing S between the gate trenches 202 in the second direction is width W ＣＯＮＴ It is possible to make it even smaller. This makes it easier to miniaturize the semiconductor device 200 and increases the channel width per unit area (channel density) within the semiconductor layer 12. As a result, the on-resistance of the semiconductor device 200 can be reduced. Note that the width W of the contact conductive part 42 ＣＯＮＴ This may be the dimension of the widest part of the contact conductive portion 42 in the X-axis direction. Alternatively, it may be the width W of the contact conductive portion 42. ＣＯＮＴ This may be the X-axis dimension of the contact conductive portion 42 at the same Z-axis position as the first surface 12A of the semiconductor layer 12.

[0165] In addition, since the contact conductive portion 42 does not need to be placed between the two gate trenches 202, the dimensions (width and / or depth) of the contact conductive portion 42 can be made relatively large. For example, as shown in Figure 12, in this embodiment, the source region 28 may include an extended portion 206. The extended portion 206 is a part of the source region 28 that has a relatively large thickness in the depth direction. This makes it possible to increase the contact area between the source region 28 and the contact conductive portion 42, for example, when the contact conductive portion 42 has a relatively large depth dimension. Also, in this case, the distance between the multiple contact regions 46 and the second surface 12B of the semiconductor layer 12 may be smaller than the distance between the multiple gate trenches 202 and the second surface 12B. This makes it possible to efficiently pass current between the source electrode 40 and the drain electrode 50, thereby improving the reliability of the operation of the semiconductor device 200.

[0166] As shown in Figure 12, the conductive cap portion 204 connects gate electrodes 36 embedded in separate gate trenches 202. The conductive cap portion 204 extends not only over the gate electrodes 36 but also between the gate trenches 202. The conductive cap portion 204 may be formed integrally with the plurality of gate electrodes 36 to which the conductive cap portion 204 is connected. The conductive cap portion 204 and the gate electrodes 36 may be formed from the same conductive material.

[0167] The semiconductor device 200 of this embodiment may have an outer peripheral region 20 and related components similar to those of the semiconductor device 10 of the first embodiment described with reference to Figures 1, 2, and 6. The gate wiring 58 shown in Figure 6 may have approximately the same thickness as the conductive cap portion 204 on the semiconductor layer 12. The upper surface of the gate wiring 58 may be in approximately the same position as the upper surface of the conductive cap portion 204 in the Z-axis direction. The bottom surface of the gate wiring 58 may be in approximately the same position as the bottom surface of the conductive cap portion 204 in the Z-axis direction. In one example, the gate wiring 58 may be manufactured simultaneously in a manufacturing process common to the conductive cap portion 204.

[0168] As described above, in this embodiment, the conductive cap portion 204 extends to cover a plurality of gate trenches 202 and connects a plurality of gate electrodes 36 to each other, so that the source region 28 is not interrupted and the gate electrodes 36 located in a plurality of gate trenches 202 that are spaced apart in the first and second directions can be electrically connected.

[0169] The semiconductor device 200 according to this embodiment has the following advantages: (3-1) Some of the multiple gate trenches 202 are spaced apart in the second direction between the first contact conductive portion 42A and the second contact conductive portion 42B.

[0170] This configuration allows for an increase in the number of gate trenches 202 positioned between the first contact conductive portion 42A and the second contact conductive portion 42B. Furthermore, since the contact conductive portions 42 do not necessarily need to be positioned between the gate trenches 202 that are spaced apart in the second direction, the spacing between the gate trenches 202 can be made relatively small. This facilitates miniaturization of the semiconductor device 200 and increases the channel width per unit area (channel density) within the semiconductor layer 12. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0171] (3-2) The spacing S between the gate trenches 202 in the second direction is equal to the width W of the contact conductive portion 42 in the second direction. ＣＯＮＴ This configuration facilitates miniaturization of the semiconductor device 200 and increases the channel width per unit area (channel density) within the semiconductor layer 12. As a result, the on-resistance of the semiconductor device 200 can be reduced.

[0172] (3-3) The distance between the multiple contact areas 46 and the second surface 12B is smaller than the distance between the multiple gate trenches 202 and the second surface 12B. This configuration allows current to flow efficiently between the source electrode 40 and the drain electrode 50, thereby improving the reliability of the operation of the semiconductor device 200.

[0173] In addition to the various advantages described above, the semiconductor device 200 also has advantages similar to those of the semiconductor device 10 of the first embodiment (1-1) to (1-5) and the semiconductor device 100 of the second embodiment (2-1) to (2-3).

[0174] <Examples of Modifications to the Third Embodiment> Next, semiconductor devices 300, 400, 500, and 600 according to examples of modifications to the third embodiment will be described with reference to Figures 15 to 18. Figures 15 to 18 show examples of changes in the arrangement of gate trenches that can be covered by the conductive cap portion 204 of the semiconductor device 200.

[0175] Figure 15 shows a schematic plan view of the semiconductor device 300 on the first surface 12A of the semiconductor layer 12. As shown in Figure 15, the semiconductor layer 12 of the semiconductor device 300 includes a plurality of gate trenches 302 spaced apart from each other. The plurality of gate trenches 302 are spaced apart in the Y-axis direction and the X-axis direction. In this embodiment, the plurality of gate trenches 302 are arranged in a staggered pattern in plan view. In the example of Figure 15, the position of each gate trench 302 in the Y-axis direction is offset from the position of another gate trench 302 facing that gate trench 302 in the X-axis direction in the Y-axis direction.

[0176] The semiconductor device 300 allows for the current path through the source region 28 to be distributed. Figure 16 shows a schematic plan view of the semiconductor device 400 on the first surface 12A of the semiconductor layer 12. As shown in Figure 16, the semiconductor layer 12 of the semiconductor device 400 includes a plurality of gate trenches 402 that are spaced apart from each other. The plurality of gate trenches 402 are spaced apart in the Y-axis direction and the X-axis direction. In this embodiment, each of the plurality of gate trenches 402 has a hexagonal shape in plan view.

[0177] The semiconductor device 400 allows for the relatively dense arrangement of multiple gate trenches 402, thereby increasing the channel density of the semiconductor device 400. Figure 17 shows a schematic plan view of the semiconductor device 500 on the first surface 12A of the semiconductor layer 12. As shown in Figure 17, the semiconductor layer 12 of the semiconductor device 500 includes multiple gate trenches 502 spaced apart from each other. The multiple gate trenches 502 are spaced apart in the Y-axis and X-axis directions. In this embodiment, each of the multiple gate trenches 502 has a circular shape in plan view.

[0178] According to the semiconductor device 500, it is possible to arrange the gate trench 502 without considering the plane orientation (for example, the off-direction) of the semiconductor layer 12, which is a SiC single crystal, thereby improving the ease of manufacturing the semiconductor device 500.

[0179] Figure 18 shows a schematic plan view of the semiconductor device 600 on the first surface 12A of the semiconductor layer 12. As shown in Figure 18, the semiconductor layer 12 of the semiconductor device 600 includes a plurality of gate trenches 602 spaced apart from each other. The plurality of gate trenches 602 are spaced apart in the Y-axis direction and the X-axis direction. Each of the plurality of gate trenches 602 is rectangular in plan view, having a first dimension D1 along the first direction and a second dimension D2 along the second direction. In this embodiment, the first dimension D1 may be 10 times or more the second dimension D2.

[0180] According to the semiconductor device 600, by making the first dimension D1 of the gate trench 602 sufficiently larger than the second dimension D2, it is possible to reduce variations in the channel width of the semiconductor device 600 that may occur during the manufacturing process.

[0181] <Example Manufacturing Method of Semiconductor Device> Next, an example of a manufacturing method for a semiconductor device 10 will be described with reference to Figures 19 to 33. For ease of understanding, in Figures 19 to 33, components similar to those in Figure 4 are denoted by the same reference numerals. Generally, the manufacturing method for the semiconductor device 10 includes forming a semiconductor layer 12 made of SiC, which includes a plurality of gate trenches 22 spaced apart from each other; forming a plurality of gate electrodes 36, each located within the plurality of gate trenches 22; forming a conductive cap portion 38 located outside the plurality of gate trenches 22 and extending to cover at least one of the plurality of gate trenches 22; and forming an insulating layer 30 that covers the semiconductor layer 12 and the conductive cap portion 38.

[0182] As shown in Figure 19, the method for manufacturing the semiconductor device 10 includes forming a second semiconductor layer 16 on a first semiconductor layer 14 and forming a body region 26 on the second semiconductor layer 16. Here, the first semiconductor layer 14 may be an n-type SiC semiconductor substrate. The second semiconductor layer 16 may be an n-type SiC epitaxial layer formed on the first semiconductor layer 14. The first semiconductor layer 14 and the second semiconductor layer 16 together are called the semiconductor layer 12. The semiconductor layer 12 includes a first surface 12A and a second surface 12B opposite to the first surface 12A. The first surface 12A is included in the second semiconductor layer 16, and the second surface 12B is included in the first semiconductor layer 14. The first surface 12A and the second surface 12B may be formed by the c-plane (plane perpendicular to the c-axis) of a SiC single crystal. In one example, the first surface 12A may be formed by the (0001) plane (Si plane) of the SiC single crystal, and the second surface 12B may be formed by the (000-1) plane (C plane) of the SiC single crystal.

[0183] The body region 26 is formed by implanting p-type impurities into the second semiconductor layer 16. The body region 26 can be formed relatively close to the first surface 12A of the semiconductor layer 12. The n-type region of the second semiconductor layer 16 between the body region 26 and the first semiconductor layer 14 corresponds to the drift region 24.

[0184] As shown in Figure 20, the method for manufacturing the semiconductor device 10 involves placing a first dielectric layer 82 (for example, SiO2) on a second semiconductor layer 16. ２ This includes forming a layer, forming a resist layer 84 on the first dielectric layer 82, and patterning the resist layer 84.

[0185] As shown in Figure 21, the method for manufacturing the semiconductor device 10 includes selective etching of a first dielectric layer 82 and a second semiconductor layer 16. In this step, the first dielectric layer 82 and the second semiconductor layer 16 are etched using a patterned resist layer 84 (see Figure 20), resulting in the formation of an opening 82A in the first dielectric layer 82 and a gate trench 22 in the second semiconductor layer 16. The gate trench 22 may penetrate the body region 26 and reach the drift region 24. Next, the resist layer 84 is removed.

[0186] As shown in Figure 22, the method for manufacturing the semiconductor device 10 includes forming a first metal layer 86 in the opening 82A and gate trench 22 of the first dielectric layer 82. In one example, the first metal layer 86 may contain polysilicon.

[0187] As shown in Figure 23, the method for manufacturing the semiconductor device 10 includes removing the first dielectric layer 82 by etching. In this step, the first metal layer 86 remains embedded in the gate trench 22, with a portion of it protruding outward from the second semiconductor layer 16.

[0188] As shown in Figure 24, the method for manufacturing the semiconductor device 10 is to create a second dielectric layer 88 (for example, SiO ２ This step includes forming a second dielectric layer on the first metal layer 86. In this step, the second dielectric layer 88 is formed on the side surface of the first metal layer 86 that protrudes outward from the second semiconductor layer 16.

[0189] As shown in Figure 25, the manufacturing method of the semiconductor device 10 includes forming a p-type extended region 48. In this step, the extended region 48 is formed by injecting p-type impurities into the second semiconductor layer 16. At this time, p-type impurities are not injected into the portion of the second semiconductor layer 16 covered by the first metal layer 86 and the second dielectric layer 88. As a result, an extended region 48 separated from the gate trench 22 can be formed.

[0190] As shown in Figure 26, the method for manufacturing the semiconductor device 10 includes removing the second dielectric layer 88 and forming a source region 28. In this step, the source region 28 is selectively formed on the surface portion of the second semiconductor layer 16 by injecting n-type impurities into the second semiconductor layer 16.

[0191] As shown in Figure 27, the manufacturing method of the semiconductor device 10 includes removing the first metal layer 86 and forming a contact region 46. In this step, the gate trench 22 is exposed by removing the first metal layer 86. The side wall 22A of the gate trench 22 is formed by a source region 28, a body region 26, and a drift region 24. The bottom wall 22B of the gate trench 22 is formed by the drift region 24. Furthermore, by injecting p-type impurities into the second semiconductor layer 16, the contact region 46 is selectively formed in a portion of the region adjacent to the source region 28.

[0192] As shown in Figure 28, the method for manufacturing the semiconductor device 10 includes forming a first insulating layer 32 on the semiconductor layer 12. In this step, the first insulating layer 32 is formed to cover the first surface 12A of the semiconductor layer 12 and the side walls 22A and bottom wall 22B of the gate trench 22. The first insulating layer 32 may be formed relatively thin so that the second metal layer 90, which will be described later with reference to Figure 29, can be embedded in the gate trench 22 via the first insulating layer 32.

[0193] As shown in Figure 29, the manufacturing method of the semiconductor device 10 involves forming a second metal layer 90 on a first insulating layer 32, and forming a third dielectric layer 92 (for example, SiO2) on the second metal layer 90. ２ This includes forming a second metal layer. In this step, the second metal layer 90 is embedded in the gate trench 22. The second metal layer 90 may contain polysilicon.

[0194] As shown in Figure 30, the method for manufacturing the semiconductor device 10 may include selectively removing the third dielectric layer 92. In this step, the third dielectric layer 92 is selectively removed such that a portion of the third dielectric layer 92 that covers the gate trench 22 and its surroundings in a plan view remains.

[0195] As shown in Figure 31, the manufacturing method of the semiconductor device 10 includes selectively removing the second metal layer 90 to form the gate electrode 36 and the conductive cap portion 38. In this step, the portion of the second metal layer 90 that is not covered by the third dielectric layer 92 is removed. As a result, the gate electrode 36 located inside the gate trench 22 and the conductive cap portion 38 located outside the gate trench 22 are formed. In addition, the portion of the first insulating layer 32 that is not covered by the gate electrode 36 and the conductive cap portion 38 is exposed.

[0196] As shown in Figure 32, the method for manufacturing the semiconductor device 10 includes forming a second insulating layer 34 on a first insulating layer 32. In this step, the second insulating layer 34 is formed so as to cover the third dielectric layer 92 and the conductive cap portion 38 shown in Figure 31. In Figure 32, the third dielectric layer 92 is shown integrally as part of the second insulating layer 34.

[0197] As shown in Figure 33, the manufacturing method of the semiconductor device 10 includes forming a contact conductive portion 42 that contacts the contact area 46. Forming the contact conductive portion 42 may include forming a source opening 44 in the insulating layer 30 (first insulating layer 32 and second insulating layer 34) to expose the semiconductor layer 12 (second semiconductor layer 16), and forming a metal layer (not shown) and performing heat treatment. By heat treatment, the metal diffuses from the source opening 44 into the semiconductor layer 12, forming a silicide containing the metal, and this silicide can be used as the contact conductive portion 42. In another example, the contact conductive portion 42 may be formed by embedding any metal material in the source opening 44.

[0198] Although not shown in the figures, the manufacturing method of the semiconductor device 10 may further include forming a source electrode 40 on the insulating layer 30, forming a drain electrode 50 on the second surface 12B of the semiconductor layer 12, and forming an upper insulating layer 72. By a manufacturing method including these steps, the semiconductor device 10 shown in Figure 4 can be obtained. It will be understood by those skilled in the art that the above-described manufacturing method is also applicable to semiconductor devices of other embodiments or modifications.

[0199] <Other Modification Examples> The above embodiment can be implemented with the following modifications: The arrangement of impurity regions in the semiconductor layer 12 is not limited to the example described above. For example, the semiconductor layer 12 does not have to include the extended region 48. In yet another example, the semiconductor layer 12 may include a p-type well region (not shown) adjacent to the bottom wall 22B of the gate trench 22.

[0200] In the example shown in Figure 12, the source region 28 does not necessarily have to include the extension portion 206. Also, the semiconductor device 200 shown in Figure 12 may instead include the contact conductive portion 42 and contact region 46 shown in Figure 4.

[0201] - The gate trench 22 covered by the conductive cap portion 38 may be spaced apart only in a direction perpendicular to the direction in which the contact conductive portion 42 extends (second direction). - An example of a contact conductive portion 42 partially embedded in the semiconductor layer 12 is shown (see, for example, Figure 4), but in another example, the contact conductive portion 42 does not have to be embedded in the semiconductor layer 12. In that case, the contact conductive portion 42 may be in contact with the first surface 12A of the semiconductor layer 12.

[0202] In the example shown in Figure 6, several gate trenches 22 are formed within the outer well region 52, but in another example, gate trenches 22 may not be formed within the outer well region 52. For example, the outer well region 52 may be adjacent to the gate trenches 22.

[0203] The shape of the gate trench 22 in plan view is not limited to the examples shown in Figures 15 to 18. For example, the gate trench 22 may have an elliptical shape in plan view, or it may have any polygonal shape.

[0204] A structure in which the conductivity types of each region within the semiconductor layer 12 are inverted may be adopted. That is, a p-type region may become an n-type region, and an n-type region may become a p-type region. One or more of the various examples described herein can be combined to the extent that they do not contradict the technical specifications.

[0205] In this specification, “at least one of A and B” should be understood to mean “A only, or B only, or both A and B.” The term “on” as used in this disclosure may mean both “on” and “above” unless the context clearly indicates otherwise. Thus, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with the second layer and directly placed on the second layer, while in other embodiments the first layer may be placed above the second layer without contact with the second layer. In other words, the term “on” does not preclude structures in which another layer is formed between the first layer and the second layer.

[0206] The terms indicating direction, such as “vertical,” “horizontal,” “upward,” “downward,” “up,” “down,” “forward,” “backward,” “longitudinal,” “lateral,” “left,” “right,” “front,” and “rear,” as used in this disclosure depend on the specific orientation of the described and illustrated apparatus. Various alternative orientations can be assumed in this disclosure, and therefore these terms indicating direction should not be interpreted narrowly.

[0207] For example, the Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures according to this disclosure (e.g., the structure shown in Figure 1) are not limited to the Z-axis direction "up" and "down" being described herein being vertical "up" and "down". For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0208] The terms "first," "second," "third," etc., used in this disclosure are used simply to distinguish between objects and do not rank them. <Note> The technical ideas that can be grasped from this disclosure are described below. Not with the intention of limiting, but for the purpose of aiding understanding, the components described in the note are denoted by the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples for the purpose of aiding understanding, and the components described in each note should not be limited to the components indicated by the reference numerals.

[0209] (Note 1) A semiconductor layer (12) made of SiC, comprising a plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) spaced apart from each other; a plurality of gate electrodes (36) each located within the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602); and conductive cap portions (38, 104, 204) located outside the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) and extending to cover at least one of the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602). A semiconductor device comprising the semiconductor layer (12) and an insulating layer (30) covering the conductive cap portions (38, 104, 204), wherein the conductive cap portions (38, 104, 204) are connected to a gate electrode (36) located within the at least one gate trench (22, 102, 202, 302, 402, 502, 602) covered by the conductive cap portions (38, 104, 204).

[0210] (Note 2) The semiconductor device according to Note 1, wherein the conductive cap portions (104, 204) extend to cover the plurality of gate trenches (102, 202, 302, 402, 502, 602) and connect the plurality of gate electrodes (36) to each other.

[0211] (Note 3) The semiconductor device according to Note 2, further comprising a source electrode (40) located on the insulating layer (30), and a plurality of contact conductive portions (42) connected to the source electrode (40), wherein the semiconductor layer (12) includes at least a first semiconductor region (28) of a first conductivity type that extends continuously around the plurality of gate trenches (102, 202, 302, 402, 502, 602) below the conductive cap portions (104, 204), and the plurality of contact conductive portions (42) are in contact with the first semiconductor region (28) at a position away from the conductive cap portions (104, 204) in a plan view.

[0212] (Note 4) The semiconductor device according to Note 3, wherein each of the plurality of contact conductive portions (42) extends in a first direction in a plan view, and the plurality of contact conductive portions (42) include a first contact conductive portion (42A) and a second contact conductive portion (42B) that face each other in a second direction intersecting the first direction in a plan view, and at least a portion of the plurality of gate trenches (102, 202, 302, 402, 502, 602) are spaced apart in the first direction between the first contact conductive portion (42A) and the second contact conductive portion (42B).

[0213] (Note 5) The semiconductor device according to Note 4, wherein some of the plurality of gate trenches (202, 302, 402, 502, 602) are arranged at intervals in the second direction between the first contact conductive portion (42A) and the second contact conductive portion (42B).

[0214] (Note 6) The spacing (S) between the gate trenches (202, 302, 402, 502, 602) in the second direction is equal to the width (W) of the contact conductive portion (42) in the second direction. ＣＯＮＴ A semiconductor device described in Appendix 5, smaller than ).

[0215] (Note 7) The semiconductor device according to Note 5 or 6, wherein the plurality of gate trenches (202) are arranged in a matrix in a plan view.

[0216] (Note 8) The semiconductor device according to Note 5 or 6, wherein the plurality of gate trenches (302) are arranged in a staggered pattern in a plan view.

[0217] (Note 9) The semiconductor device according to Note 5 or 6, wherein each of the plurality of gate trenches (602) is rectangular in shape in a plan view, having a first dimension (D1) along the first direction and a second dimension (D2) along the second direction, and the first dimension (D1) is 10 times or more the second dimension (D2).

[0218] (Note 10) The semiconductor device according to Note 5 or 6, wherein each of the plurality of gate trenches (402) has a hexagonal shape in plan view.

[0219] (Note 11) The semiconductor device according to Note 5 or 6, wherein each of the plurality of gate trenches (502) has a circular shape in plan view.

[0220] (Note 12) The semiconductor device according to any one of Notes 1 to 11, wherein the conductive cap portion (38, 104, 204) has a larger area in a plan view than the area of ​​the gate electrode (36) to which the conductive cap portion (38, 104, 204) is connected.

[0221] (Note 13) The semiconductor device according to any one of Notes 1 to 12, wherein the conductive cap portion (38, 104, 204) is integrally formed with the gate electrode (36) to which the conductive cap portion (38, 104, 204) is connected.

[0222] (Note 14) The semiconductor device according to any one of Notes 3 to 11, wherein each of the plurality of contact conductive parts (42) includes a silicide.

[0223] (Note 15) The semiconductor device according to any one of Notes 3 to 11, wherein the semiconductor layer (12) includes a second semiconductor region (26) of a second conductivity type adjacent to the first semiconductor region (28) and a third semiconductor region (24) of a first conductivity type adjacent to the second semiconductor region (26), and each of the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) penetrates the first semiconductor region (28) and the second semiconductor region (26) to reach the third semiconductor region (24).

[0224] (Note 16) The semiconductor device according to Note 15, further comprising a source electrode (40) located on the insulating layer (30), and a plurality of contact conductive portions (42) connected to the source electrode (40), wherein the semiconductor layer (12) includes a plurality of contact regions (46) of a second conductivity type adjacent to each of the plurality of contact conductive portions (42), and the plurality of contact regions (46) have a higher concentration of impurities of the second conductivity type than the second semiconductor region (26).

[0225] (Note 17) The semiconductor layer (12) includes a first surface (12A) on which the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) are provided, and a second surface (12B) opposite to the first surface (12A). The semiconductor device according to Appendix 16, wherein the semiconductor layer (12) includes a fourth semiconductor region (48) of a second conductivity type that is adjacent to the second semiconductor region (26) and separated from the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) between the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602), and the distance between the fourth semiconductor region (48) and the second surface (12B) is smaller than the distance between the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) and the second surface (12B).

[0226] (Note 18) The semiconductor device according to Note 17, wherein the distance between the plurality of contact regions (46) and the second surface (12B) is smaller than the distance between the plurality of gate trenches (202) and the second surface (12B).

[0227] (Note 19) The semiconductor device according to any one of Notes 1 to 18, further comprising: a source electrode (40) located on the insulating layer (30); a plurality of contact conductive portions (42) connected to the source electrode (40); and a plurality of conductive cap portions (38, 104, 204), each corresponding to one of the conductive cap portions (38, 104, 204), wherein each of the plurality of conductive cap portions (38, 104, 204) is located between two of the plurality of contact conductive portions (42) in a plan view.

[0228] (Note 20) The semiconductor device described in Note 19, wherein the number of conductive cap portions (104, 204) is less than the number of gate trenches (102, 202, 302, 402, 502, 602).

[0229] (Note 21) Forming a semiconductor layer (12) made of SiC, which includes a plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) spaced apart from each other; forming a plurality of gate electrodes (36) each located within the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602); forming conductive cap portions (38, 104, 204) located outside the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602) and extending to cover at least one of the plurality of gate trenches (22, 102, 202, 302, 402, 502, 602); A method for manufacturing a semiconductor device, comprising forming an insulating layer (30) that covers the semiconductor layer (12) and the conductive cap portions (38, 104, 204), wherein the conductive cap portions (38, 104, 204) are connected to a gate electrode (36) located within the at least one gate trench (22, 102, 202, 302, 402, 502, 602) covered by the conductive cap portions (38, 104, 204).

[0230] Various modifications in form and detail can be made to the above-described examples without departing from the claims and their equivalents. The above-described examples are for illustrative purposes only and are not intended to be limiting. The descriptions of features in each example should be considered applicable to similar features or embodiments in other examples. Preferred results can be achieved when consecutive events occur in a different order, and / or when components within the described systems, architectures, devices, or circuits are combined in different ways and / or replaced or complemented by other components or their equivalents. The scope of this disclosure is defined not by the detailed description, but by the claims and their equivalents. All variations of the claims and their equivalents are included in this disclosure.

[0231] 10, 100, 200, 300, 400, 500, 600... Semiconductor device, 12... Semiconductor layer, 12A... First surface, 12B... Second surface, 12C1... First side, 12C2... Second side, 12C3... Third side, 12C4... Fourth side, 14... First semiconductor layer, 16... Second semiconductor layer, 18... Active region, 20... Outer periphery region, 22, 102, 202, 302, 402, 502, 602...Gate trench, 22A...Side wall, 22B...Bottom wall, 24...Drift region, 26...Body region, 28...Source region, 30...Insulating layer, 32...First insulating layer, 34...Second insulating layer, 36...Gate electrode, 38, 104, 204...Conductive cap portion, 40...Source electrode, 42...Contact conductive portion, 42A...First contact conductive portion, 42B...Second contact conductive portion, 4 4...Source opening, 46...Contact region, 48...Expansion region, 50...Drain electrode, 52...Outer well region, 54...Outer contact region, 56...Field region, 58...Gate wiring, 60...Gate opening, 62...Gate finger electrode, 64...Gate pad electrode, 66...Source finger electrode, 68...Outer contact conductive part, 70...Outer opening, 72...Upper insulating layer, 74...Gate pad opening, 76A...First source pad opening, 76B...Second source pad opening, 76C...Third source pad opening, 78...First upper insulating layer, 80...Second upper insulating layer, 82...First dielectric layer, 82A...Opening, 84...Resist layer, 86...First metal layer, 88...Second dielectric layer, 90...Second metal layer, 92...Third dielectric layer, 206...Expansion portion.

Claims

1. A semiconductor device comprising: a semiconductor layer made of SiC and including a plurality of gate trenches spaced apart from each other; a plurality of gate electrodes each located within the plurality of gate trenches; a conductive cap portion located outside the plurality of gate trenches and extending to cover at least one of the plurality of gate trenches; and an insulating layer covering the semiconductor layer and the conductive cap portion, wherein the conductive cap portion is connected to a gate electrode located within the at least one gate trench covered by the conductive cap portion.

2. The semiconductor device according to claim 1, wherein the conductive cap portion extends to cover the plurality of gate trenches and connects the plurality of gate electrodes to each other.

3. The semiconductor device according to claim 2, further comprising a source electrode located on the insulating layer and a plurality of contact conductive portions connected to the source electrode, wherein the semiconductor layer includes a first semiconductor region of a first conductivity type that extends continuously around the plurality of gate trenches at least below the conductive cap portion, and the plurality of contact conductive portions are in contact with the first semiconductor region at a position away from the conductive cap portion in a plan view.

4. The semiconductor device according to claim 3, wherein each of the plurality of contact conductive portions extends in a first direction in a plan view, the plurality of contact conductive portions includes a first contact conductive portion and a second contact conductive portion that face each other in a second direction intersecting the first direction in a plan view, and at least a portion of the plurality of gate trenches is arranged at an interval in the first direction between the first contact conductive portion and the second contact conductive portion.

5. The semiconductor device according to claim 4, wherein a portion of the plurality of gate trenches is arranged at an interval in the second direction between the first contact conductive portion and the second contact conductive portion.

6. The semiconductor device according to claim 5, wherein the spacing between the gate trenches in the second direction is smaller than the width of the contact conductive portion in the second direction.

7. The semiconductor device according to claim 5 or 6, wherein the plurality of gate trenches are arranged in a matrix in a plan view.

8. The semiconductor device according to claim 5 or 6, wherein the plurality of gate trenches are arranged in a staggered pattern in a plan view.

9. The semiconductor device according to claim 5 or 6, wherein each of the plurality of gate trenches is rectangular in plan view, having a first dimension along the first direction and a second dimension along the second direction, and the first dimension is 10 times or more the second dimension.

10. The semiconductor device according to claim 5 or 6, wherein each of the plurality of gate trenches has a hexagonal shape in plan view.

11. The semiconductor device according to claim 5 or 6, wherein each of the plurality of gate trenches has a circular shape in plan view.

12. The semiconductor device according to any one of claims 1 to 11, wherein the conductive cap portion has a larger area in a plan view than the area of ​​the gate electrode to which the conductive cap portion is connected.

13. The semiconductor device according to any one of claims 1 to 12, wherein the conductive cap portion is integrally formed with the gate electrode to which the conductive cap portion is connected.

14. The semiconductor device according to any one of claims 3 to 11, wherein each of the plurality of contact conductive parts includes a silicide.

15. The semiconductor device according to any one of claims 3 to 11, wherein the semiconductor layer includes a second semiconductor region of a second conductivity type adjacent to the first semiconductor region and a third semiconductor region of a first conductivity type adjacent to the second semiconductor region, and each of the plurality of gate trenches penetrates the first semiconductor region and the second semiconductor region to reach the third semiconductor region.

16. The semiconductor device according to claim 15, further comprising a source electrode located on the insulating layer and a plurality of contact conductive portions connected to the source electrode, wherein the semiconductor layer includes a plurality of contact regions of a second conductivity type adjacent to the plurality of contact conductive portions, and the plurality of contact regions have a higher impurity concentration of the second conductivity type than the second semiconductor region.

17. The semiconductor device according to claim 16, wherein the semiconductor layer includes a first surface on which the plurality of gate trenches are provided and a second surface opposite to the first surface, and the semiconductor layer includes a fourth semiconductor region of a second conductivity type adjacent to the second semiconductor region and separated from the plurality of gate trenches between the plurality of gate trenches, and the distance between the fourth semiconductor region and the second surface is smaller than the distance between the plurality of gate trenches and the second surface.

18. The semiconductor device according to claim 17, wherein the distance between the plurality of contact regions and the second surface is smaller than the distance between the plurality of gate trenches and the second surface.

19. The semiconductor device according to any one of claims 1 to 18, further comprising: a source electrode located on the insulating layer; a plurality of contact conductive portions connected to the source electrode; and a plurality of conductive cap portions, each corresponding to the conductive cap portion, wherein each of the plurality of conductive cap portions is located between two of the plurality of contact conductive portions in a plan view.

20. The semiconductor device according to claim 19, wherein the number of conductive cap portions is less than the number of gate trenches.

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