Semiconductor device

Abstract

This semiconductor device (10) comprises: a semiconductor layer (20) including a main surface (20S) and composed of SiC; a body region (23) provided on a surface layer part of the semiconductor layer (20); a source region (35) provided on a surface layer part of the body region (23); an insulating layer (40) having a main surface insulating film (41) covering the main surface (20S) and a source opening (40A) exposing the semiconductor layer (20); a source electrode (51) provided on the insulating layer (40); and a contact part (60) that is provided so as to be exposed through the source opening (40A) in a plan view seen from a thickness direction (Z) of the semiconductor layer (20) and is in contact with both the source electrode (51) and the source region (35). The contact part (60) extends completely through the source region (35).

Description

Semiconductor equipment

[0001] This disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device comprising a SiC substrate and a SiC epitaxial layer. In the inner cell region, a plurality of transistor cells formed on the surface of the SiC epitaxial layer include a body region, a source region selectively formed inside the body region, and a body contact region selectively formed inside the source region. The semiconductor device also includes a source metal and a source contact for making contact from the source metal to the source region and the body contact region.

[0003] Japanese Patent Publication No. 2015-220334

[0004] [Overview] The source contact is in contact with the source region and body contact region on the surface of the SiC epitaxial layer. It is desirable to suppress the increase in contact resistance between the source contact and the source region caused by the miniaturization of transistor cells in semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer made of SiC and including a main surface; a body region provided on the surface of the semiconductor layer; a source region provided on the surface of the body region; an insulating layer having a main surface insulating film covering the main surface and a source opening that exposes the semiconductor layer; a source electrode provided on the insulating layer; and a contact portion provided so as to be exposed from the source opening in a plan view taken from the thickness direction of the semiconductor layer and in contact with both the source electrode and the source region, wherein the contact portion penetrates the source region.

[0006] Figure 1 is a schematic plan view of an exemplary semiconductor device according to the first embodiment. Figure 2 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F2-F2 in Figure 1. Figure 3 is a schematic plan view showing an enlarged portion of the active region in the semiconductor device of Figure 1. Figure 4 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F4-F4 in Figure 3. Figure 5 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F5-F5 in Figure 3. Figure 6 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F6-F6 in Figure 3. Figure 7 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F7-F7 in Figure 3. Figure 8 is a schematic perspective cross-sectional view obtained by enlarging a portion of the semiconductor device of Figure 5. Figure 9 is a schematic perspective cross-sectional view obtained by removing the insulating layer from Figure 8. Figure 10 is a schematic perspective cross-sectional view obtained by enlarging a portion of the semiconductor device other than that in Figure 8. Figure 11 is a schematic perspective cross-sectional view obtained by enlarging a portion of the semiconductor device other than that in Figure 10. Figure 12 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F12-F12 in Figure 4. Figure 13 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F13-F13 in Figure 4. Figure 14 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F14-F14 in Figure 1. Figure 15 is a schematic plan view obtained by adding a contact portion to Figure 3. Figure 16 is a schematic cross-sectional view obtained by enlarging a part of Figure 5. Figure 17 is a schematic cross-sectional view obtained by enlarging the contact portion and its surroundings in Figure 16. Figure 18 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F18-F18 in Figure 15. Figure 19 is a schematic cross-sectional view obtained by enlarging the end of the contact portion and its surroundings in Figure 18. Figure 20 is a schematic cross-sectional view obtained by showing an example of the manufacturing process of a semiconductor device according to the first embodiment. Figure 21 is a schematic cross-sectional view obtained by continuing the manufacturing process of a semiconductor device from Figure 20. Figure 22 is a schematic cross-sectional view obtained by continuing the manufacturing process of a semiconductor device from Figure 21. Figure 23 is a schematic cross-sectional view obtained by continuing the manufacturing process of a semiconductor device from Figure 22. Figure 24 is a schematic cross-sectional view obtained by continuing the manufacturing process of a semiconductor device from Figure 23. Figure 25 is a schematic cross-sectional view obtained by continuing the manufacturing process of a semiconductor device from Figure 24. Figure 26 is a schematic cross-sectional view showing the manufacturing process of a semiconductor device following Figure 25. Figure 27 is a schematic cross-sectional view showing the manufacturing process of a semiconductor device following Figure 26. Figure 28 is a schematic cross-sectional view of a part of a comparative example semiconductor device. Figure 29 is an enlarged schematic plan view of a part of the active region in the semiconductor device of the second embodiment.Figure 30 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F30-F30 in Figure 29. Figure 31 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F31-F31 in Figure 29. Figure 32 is a schematic cross-sectional view obtained by enlarging a part of Figure 31. Figure 33 is a schematic cross-sectional view obtained by enlarging a contact portion and its surroundings in Figure 32. Figure 34 is a schematic plan view obtained by enlarging a part of the active region in the semiconductor device of the third embodiment. Figure 35 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F35-F35 in Figure 34. Figure 36 is a schematic cross-sectional view obtained by enlarging a contact portion and its surroundings in Figure 35. Figure 37 is a schematic plan view obtained by enlarging a part of the active region in the semiconductor device of the fourth embodiment. Figure 38 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F38-F38 in Figure 37. Figure 39 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F39-F39 in Figure 37. Figure 40 is a schematic cross-sectional view obtained by cutting the semiconductor device along the line F40-F40 in Figure 38. Figure 41 is a schematic cross-sectional view of the contact area and its surroundings in the modified semiconductor device. Figure 42 is a schematic cross-sectional view of the contact area and its surroundings in the modified semiconductor device. Figure 43 is a schematic cross-sectional view of the contact area and its surroundings in the modified semiconductor device. Figure 44 is a schematic cross-sectional view of a part of the modified semiconductor device. Figure 45 is a schematic cross-sectional view of a part of the modified semiconductor device. Figure 46 is a schematic plan view of a part of the active region in the modified semiconductor device. Figure 47 is a schematic cross-sectional view of a part of the modified semiconductor device. Figure 48 is a schematic cross-sectional view of the contact area and its surroundings in the modified semiconductor device. Figure 49 is a schematic cross-sectional view of a part of the modified semiconductor device. Figure 50 is a schematic plan view of a part of the active region in the modified semiconductor device. Figure 51 is a schematic plan view of a part of the active region in the modified semiconductor device. Figure 52 is a schematic plan view of a part of the active region in the modified semiconductor device.

[0007] [Detailed Description] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. It should be noted that, for the sake of simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to a constant scale. In addition, to facilitate understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be construed as limiting the present disclosure.

[0008] The following detailed description includes apparatuses, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is inherently for illustrative purposes only, and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0009] Terms such as "first", "second", and "third" in the present disclosure are merely used for labeling, and are not necessarily intended to impose an order on the objects they refer to. As used in the present disclosure, the expression "at least one" means "one or more" of the desired options. For example, as used in the present disclosure, if there are two options, the expression "at least one" means "only one option" or "both of the two options". As another example, as used in the present disclosure, if there are three or more options, the expression "at least one" means "only one option" or "any combination of two or more options".

[0010] As used in the present disclosure, the statements "the dimension (distance) of A is equal to the dimension (distance) of B" or "the dimension (distance) of A and the dimension (distance) of B are equal to each other" also include the relationship where the difference between the dimension (distance) of A and the dimension (distance) of B is within 10% of the dimension (distance) of A, for example. Here, the dimension refers to, for example, width, depth, thickness, and the like.

[0011] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type". "p-type" may be referred to as "first conductivity type" and "n-type" may be referred to as "second conductivity type". Alternatively, "n-type" may be referred to as "first conductivity type" and "p-type" may be referred to as "second conductivity type". "p-type" is a conductivity type derived from a trivalent element, and "n-type" is a conductivity type derived from a pentavalent element. The trivalent element is at least one selected from the group consisting of boron (B), aluminum (Al), gallium (Ga), and indium (In). The pentavalent element is at least one selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0012] <First Embodiment> [Overall Configuration of Semiconductor Device] An overall configuration of a semiconductor device 10 according to the first embodiment will be described with reference to FIG. 1 and FIG. 2. FIG. 1 schematically shows a planar structure of the semiconductor device 10. FIG. 2 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 along line F2-F2 in FIG. 1.

[0013] In the present disclosure, constituent members may be described based on mutually orthogonal XYZ axes shown in the drawings. Here, a direction along the X-axis is defined as an "X direction", a direction along the Y-axis is defined as a "Y direction", and a direction along the Z-axis is defined as a "Z direction". The term "plan view" as used in the present disclosure refers to viewing the semiconductor device 10 in the Z direction. In the first embodiment, the X direction is an example of a "second direction", and the Y direction is an example of a "first direction".

[0014] As shown in FIG. 1, the semiconductor device 10 includes a flat plate-shaped chip 20 having a thickness direction in the Z direction. The chip 20 has a quadrangular shape in plan view. The semiconductor device 10 is a semiconductor switching device having an insulated gate transistor structure Tr as an example of a device structure. In the first embodiment, the transistor structure Tr has a trench gate type vertical structure. Note that the shape of the chip 20 in plan view can be arbitrarily changed.

[0015] The semiconductor device 10 contains a single crystal of a wide-bandgap semiconductor. Therefore, the semiconductor device 10 can also be called a "wide-bandgap semiconductor device." The chip 20 can be called a "semiconductor chip," a "wide-bandgap semiconductor chip," etc.

[0016] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). Chip 20 is a "SiC chip" containing a hexagonal SiC single crystal as an example of a wide-bandgap semiconductor. Therefore, semiconductor device 10 can also be called a "SiC semiconductor device."

[0017] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, and so on. In the first embodiment, the chip 20 contains a 4H-SiC single crystal. The chip 20 may also contain other polytypes. Furthermore, the chip 20 may contain cubic or polycrystalline materials. In one example, the chip 20 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0018] The chip 20 includes a first main surface 20S, a second main surface 20R (see Figure 2) opposite to the first main surface 20S, and first to fourth side surfaces 20A to 20D. The first to fourth side surfaces 20A to 20D are connected to the first main surface 20S and the second main surface 20R. The first side surface 20A and the second side surface 20B constitute both end faces of the chip 20 in the Y direction, and the third side surface 20C and the fourth side surface 20D constitute both end faces of the chip 20 in the X direction. Thus, the first to fourth side surfaces 20A to 20D constitute the periphery of the first main surface 20S. The first main surface 20S is an example of a "main surface".

[0019] The first main surface 20S and the second main surface 20R are composed of c-planes of a SiC single crystal. The first main surface 20S may be composed of a silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 20R may be composed of a carbon plane ((000-1) plane) of the SiC single crystal. In the following description, the direction from the second main surface 20R toward the first main surface 20S may be referred to as "upward," and the direction from the first main surface 20S toward the second main surface 20R may be referred to as "downward."

[0020] In the first embodiment, the X direction is the m-axis direction ([1-100] direction) of the SiC single crystal, and the Y direction is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the X direction may be the a-axis direction of the SiC single crystal, and the Y direction may be the m-axis direction of the SiC single crystal. Hereafter, the direction extending along the first principal surface 20S may be referred to as the "horizontal direction". The horizontal direction can be said to be the direction along the XY plane (horizontal plane) formed by the X and Y directions. The horizontal direction can also be said to be the direction perpendicular to the Z direction.

[0021] The chip 20 (first main surface 20S and second main surface 20R) has an off-angle θ that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle θ from a straight line along the Z direction in the off-direction. Also, the c-plane of the SiC single crystal is inclined by the off-angle θ with respect to the horizontal plane.

[0022] The off-direction is, for example, the a-axis direction (Y-direction) of a SiC single crystal. The off-angle θ can be greater than 0° and 10° or less. The off-angle θ may have a value that falls within at least one of the following ranges: greater than 0° and 1° or less, 1° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, and 7.5° or more and 10° or less.

[0023] The off-angle θ is preferably 5° or less. The off-angle θ is more preferably 2° or more and 4.5° or less. Typically, the off-angle θ is set in the range of 4° ± 0.1°. However, this specification does not exclude the form in which the off-angle θ is 0° (the form in which the first main surface 20S is a just surface with respect to the c surface).

[0024] As shown in FIG. 2, the chip 20 includes an n-type first semiconductor layer 21. The first semiconductor layer 21 constitutes part of the second main surface 20R of the chip 20 and the first to fourth side surfaces 20A to 20D (see FIG. 1). The first semiconductor layer 21 comprises a single crystal of a wide bandgap semiconductor. In the first embodiment, an SiC substrate including a hexagonal SiC single crystal may be used for the first semiconductor layer 21. The first semiconductor layer 21 includes a 4H-SiC single crystal and has the aforementioned off direction and off angle θ. Note that the first semiconductor layer 21 may include other polytypes. In one example, the first semiconductor layer 21 may include 3C-SiC polycrystal. In this case, the second main surface 20R may be constituted by a crystal plane of the 3C-SiC polycrystal.

[0025] A thickness T1 of the first semiconductor layer 21 may be greater than 0 μm and not greater than 500 μm. The thickness T1 may have a value falling within at least one range selected from the group consisting of: greater than 0 μm and not greater than 50 μm, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or less, 400 μm or more and 450 μm or less, and 450 μm or more and 500 μm or less.

[0026] The first semiconductor layer 21 may have a uniform n-type impurity concentration in the thickness direction (Z direction). The impurity concentration of the first semiconductor layer 21 is 1×10 １７ cm －３ or more and 1×10 ２１ cm －３ or less. The impurity concentration of the first semiconductor layer 21 is 1×10 １７ cm －３ or more and 5×10 １７ cm －３ or less, 5×10 １７ cm －３ or more and 1×10 １８ cm －３ or less, 1×10 １８ cm －３ or more and 5×10 １８ cm －３ or less, 5×10 １８ cm －３ or more and 1×10１９ cm －３ Below, 1 x 10 １９ cm －３ The above 5 x 10 １９ cm －３ Below, 5 x 10 １９ cm －３ The above 1 x 10 ２０ cm －３ Below, 1 x 10 ２０ cm －３ The above 5 x 10 ２０ cm －３ The following, and 5 x 10 ２０ cm －３ The above 1 x 10 ２１ cm －３ The value may be within at least one of the following ranges. Here, the impurity concentration of the first semiconductor layer 21 may be adjusted by a single or multiple pentavalent elements. Preferably, the impurity concentration of the first semiconductor layer 21 is adjusted by a single pentavalent element. The impurity concentration of the first semiconductor layer 21 may be adjusted by, for example, nitrogen.

[0027] The chip 20 includes an n-type second semiconductor layer 22 provided on a first semiconductor layer 21. The second semiconductor layer 22 constitutes a portion of the first main surface 20S and the first to fourth side surfaces 20A to 20D of the chip 20. The second semiconductor layer 22 includes a single crystal of a wide-bandgap semiconductor. In the first embodiment, the second semiconductor layer 22 is a SiC semiconductor layer containing a hexagonal SiC single crystal. The second semiconductor layer 22 is composed of an epitaxial layer (SiC epitaxial layer). The second semiconductor layer 22 includes a 4H-SiC single crystal and has the off-direction and off-angle θ described above. The second semiconductor layer 22 may also include other polytypes. Furthermore, the chip 20 is an example of a "semiconductor layer," and the first main surface 20S is an example of a "main surface." Also, "plan view" refers to viewing the chip 20 from the thickness direction.

[0028] The second semiconductor layer 22 has a thickness T2 that is thinner than the first semiconductor layer 21. The thickness T2 may be greater than 0 μm and 50 μm or less. The thickness T2 may have a value that falls within at least one of the following ranges: greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or more and 50 μm or less.

[0029] The second semiconductor layer 22 may have a uniform n-type impurity concentration in the thickness direction (Z direction). The second semiconductor layer 22 may have an impurity concentration of n-type impurities that is lower than that of the first semiconductor layer 21. The impurity concentration of the second semiconductor layer 22 is 1 × 10⁻⁶. １５ cm －３ The above 1 x 10 １９ cm －３ The following may apply: The impurity concentration of the second semiconductor layer 22 is 1 × 10⁻⁶. １５ cm －３ The above 5 x 10 １５ cm －３ Below, 5 x 10 １５ cm －３ The above 1 x 10 １６ cm －３ Below, 1 x 10 １６ cm －３ The above 5 x 10 １６ cm －３ Below, 5 x 10 １６ cm －３ The above 1 x 10 １７ cm －３ Below, 1 x 10 １７ cm －３ The above 5 x 10 １７ cm －３ Below, 5 x 10 １７ cm －３ The above 1 x 10 １８ cm －３ Below, 1 x 10 １８ cm －３ The above 5 x 10 １８ cm －３ The following, and 5 x 10 １８ cm －３ The above 1 x 10 １９ cm －３The second semiconductor layer 22 may have a value that falls within at least one of the following ranges. Here, the impurity concentration of the second semiconductor layer 22 may be adjusted by a single or multiple pentavalent elements. Preferably, the impurity concentration of the second semiconductor layer 22 is adjusted by a single pentavalent element. The impurity concentration of the second semiconductor layer 22 may be adjusted by, for example, nitrogen. The second semiconductor layer 22 may have an n-type impurity concentration that gradually increases from the first semiconductor layer 21 toward the first main surface 20S.

[0030] The semiconductor device 10 includes an active region 11 provided in the second semiconductor layer 22. The active region 11 is a region containing a device structure (transistor structure Tr). Therefore, the active region 11 is a region in which an output current (drain current) is generated by the transistor structure Tr. The active region 11 is provided in the inner part of the second semiconductor layer 22, spaced apart from the periphery (first to fourth side surfaces 20A to 20D) of the first main surface 20S. The active region 11 may also be a region covered by a source electrode 51, which will be described later.

[0031] The active region 11 is provided as a polygonal shape having four sides parallel to the periphery of the first main surface 20S in a plan view. In the first embodiment, the shape of the active region 11 in a plan view includes a quadrilateral shape. The active region 11 includes a quadrilateral recess that is recessed in the X direction from the first side surface 20A toward the second side surface 20B in a plan view. This recess is provided at the center of the first side surface 20A in the Y direction.

[0032] The ratio of the surface area of ​​the active region 11 to the surface area of ​​the first main surface 20S (area ratio) may be 0.5 or more and 0.95 or less. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0033] The semiconductor device 10 includes an outer peripheral region 12 provided outside the active region 11 in the second semiconductor layer 22. The outer peripheral region 12 is a region that does not include the device structure (transistor structure Tr). The outer peripheral region 12 is provided at the periphery of the second semiconductor layer 22. In other words, the outer peripheral region 12 is provided as the region between the periphery of the first main surface 20S and the active region 11 in a plan view. The outer peripheral region 12 is provided in a polygonal ring shape surrounding the active region 11 in a plan view. In the first embodiment, the outer peripheral region 12 is provided in a quadrilateral ring shape in a plan view. The outer peripheral region 12 extends in a band shape along the active region 11 in a plan view.

[0034] [Active Region] The configuration of the active region 11 of the chip 20 will be described with reference to Figures 3 to 13. Figure 3 schematically shows a magnified planar structure of a part of the active region 11 on the first main surface 20S of the chip 20. Figure 4 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 along the line F4-F4 in Figure 3. Figure 5 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 along the line F5-F5 in Figure 3. Figure 6 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 along the line F6-F6 in Figure 3. Figure 7 schematically shows a cross-sectional structure obtained by cutting the semiconductor device 10 along the line F7-F7 in Figure 3. Figure 8 schematically shows a magnified cross-sectional perspective view of a part of the active region 11. Figure 9 schematically shows a cross-sectional perspective view obtained by removing the insulating layer 40, which will be described later, from Figure 8. Figure 10 schematically shows a magnified cross-sectional perspective view of a part of the active region 11 different from that in Figure 9. Figure 11 schematically shows a cross-sectional perspective view of the portion closer to the gate structure 25, which will be described later, compared to Figure 10. Figure 12 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F12-F12 in Figure 4. Figure 13 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F13-F13 in Figure 4.

[0035] As shown in Figures 4 and 5, the active region 11 includes a p-type body region 23 provided on the surface of the first main surface 20S (second semiconductor layer 22) of the chip 20. The body region 23 is not provided in the outer peripheral region 12 (see Figure 2). In one example, the body region 23 is provided over the entire area of ​​the active region 11 in a plan view. It can also be said that the body region 23 is provided on the surface of the second semiconductor layer 22. The body region 23 extends in layers along the first main surface 20S. The body region 23 is provided with a gap from the depth position of the middle part of the second semiconductor layer 22 toward the first main surface 20S. Here, the "depth position of the middle part" indicates the position of the center in the thickness direction (Z direction) of the target component (target region).

[0036] A source potential is applied to the body region 23. The source potential may be a reference potential that serves as the basis for circuit operation. The reference potential may also be the ground potential. The body region 23 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 22. The body region 23 replaces the conductivity type of the second semiconductor layer 22 from n-type to p-type.

[0037] As shown in Figure 5, the body region 23 includes a portion that forms a pn junction with the second semiconductor layer 22. This forms a body diode structure (pn junction diode structure) as a diode structure Di having the body region 23 as the anode region and the second semiconductor layer 22 (second pillar region 32, described later) as the cathode region. When a reverse bias voltage is applied, the body region 23 expands a depletion layer in the second semiconductor layer 22. The depletion layer, starting from the body region 23, expands within the second semiconductor layer 22 in the horizontal direction (X direction, Y direction) and the thickness direction (Z direction).

[0038] The semiconductor device 10 includes a plurality of trench-type gate structures 25 provided in the inner part of the first main surface 20S. The gate structures 25 can also be called "trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 25 as a control potential. The plurality of gate structures 25 control the inversion and non-inversion of channels Ch1 and Ch2 within the body region 23 in response to the gate potential.

[0039] Multiple gate structures 25 are provided in the active region 11, but not in the outer peripheral region 12. As shown in Figure 3, the multiple gate structures 25 are arranged at intervals in the Y direction (a-axis direction) in a plan view. Each gate structure 25 extends in the X direction (m-axis direction) in a plan view. The multiple gate structures 25 can be said to be arranged in a stripe pattern extending in the X direction in a plan view. The extension direction of the multiple gate structures 25 intersects (specifically orthogonal to) the off-direction of the SiC single crystal. Both ends of each gate structure 25 in the X direction are located inward from the periphery of the body region 23 in the X direction.

[0040] The range in which the gate structure 25 is provided and the arrangement of the multiple gate structures 25 can be arbitrarily changed. In one example, both ends of each gate structure 25 in the X direction may be located outward from the periphery of the body region 23 in the X direction (closer to the periphery of the first main surface 20S). The multiple gate structures 25 may be arranged with spacing in the X direction in a plan view. In this case, each gate structure 25 may extend in the Y direction in a plan view.

[0041] As shown in Figures 4 and 5, each gate structure 25 penetrates the body region 23 so as to reach the second semiconductor layer 22. Each gate structure 25 may be provided at a distance from the depth position in the middle of the second semiconductor layer 22 toward the first main surface 20S. In one example, each gate structure 25 extends along the Z direction. Each gate structure 25 may be provided in a tapered shape as it moves from the first main surface 20S toward the first semiconductor layer 21.

[0042] The sidewalls of each gate structure 25 are composed of the a-plane ((11-20) plane) of the SiC single crystal. The sidewalls of each gate structure 25 may also be composed of the m-plane ((1-100) plane) of the SiC single crystal, depending on the direction of extension of the gate structure 25. The sidewalls of each gate structure 25, together with the first main surface 20S, define the arc-shaped (circular arc-shaped) curved open end.

[0043] The bottom wall of each gate structure 25 is made of the c-plane (Si plane) of a SiC single crystal. The bottom wall of each gate structure 25 may include a portion that extends flat along the horizontal direction. In this case, the corner portion between the bottom wall and the side wall of each gate structure 25 may be provided in a curved shape that is convex outward. Furthermore, the bottom wall of each gate structure 25 may be provided in a curved shape that is convex toward the first semiconductor layer 21 as a whole.

[0044] The absolute value of the inclination angle of the side wall of the gate structure 25 with respect to the Z direction may be 85° or more and 95° or less. The inclination angle may have a value that falls within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. Preferably, the inclination angle is 87° or more and 93° or less.

[0045] The gate structure 25 may have a width (dimension in the X direction) of 0.1 μm or more and 2 μm or less. The width of the gate structure 25 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. Preferably, the width of the gate structure 25 is 1 μm or less.

[0046] The gate structure 25 may have a depth (dimension in the Z direction) of 0.1 μm or more and 3 μm or less. The depth of the gate structure 25 can be defined by the dimension in the Z direction from the first main surface 20S to the bottom wall. The depth of the gate structure 25 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the gate structure 25 is 0.5 μm or more and 1.5 μm or less.

[0047] The gate structure 25 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 25 can be defined by the ratio of the depth of the gate structure 25 to the width of the gate structure 25. The aspect ratio of the gate structure 25 may have a value that falls within at least one of the following ranges: 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3. Preferably, the aspect ratio of the gate structure 25 is 1.5 to 2.5.

[0048] Multiple gate structures 25 may be arranged at intervals of 0.1 μm or more and 2 μm or less. The spacing of the gate structures 25 can be defined by the horizontal (Y-direction) distance between the multiple gate structures 25. The spacing of the gate structures 25 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, and 1.75 μm or more and 2 μm or less. Preferably, the spacing of the gate structures 25 is 1 μm or less.

[0049] The spacing between gate structures 25 may be greater than the width of the gate structures 25. The spacing between gate structures 25 can be between 2 and 10 times the width of the gate structures 25. The spacing between gate structures 25 may be a value that falls within at least one of the following ranges: between 2 and 3 times the width of the gate structures 25, between 3 and 4 times, between 4 and 5 times, between 5 and 6 times, between 6 and 7 times, between 7 and 8 times, between 8 and 9 times, and between 9 and 10 times the width of the gate structures 25. In the first embodiment, the width of the gate structures 25 is 0.4 μm, and the spacing between gate structures 25 is 1.2 μm. Therefore, in the first embodiment, the spacing between gate structures 25 is 4 times the width of the gate structures 25.

[0050] Each gate structure 25 includes a trench 26, an insulating film 27, and an embedded electrode 28. The trench 26 can be called a "gate trench," and the insulating film 27 can be called a "gate insulating film." In the first embodiment, the embedded electrode 28 can be called a "gate electrode."

[0051] The trench 26 is provided on the first main surface 20S and extends in the Z direction toward the first semiconductor layer 21. The trench 26 extends from the first main surface 20S through the body region 23. The trench 26 demarcates the side walls and bottom walls of the gate structure 25. In a plan view, the trench 26 extends in the Y direction and is provided in multiple locations spaced apart in the X direction.

[0052] The insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 27 may include a silicon oxide film containing the oxide of the second semiconductor layer 22. In addition, the insulating film 27 may include a silicon oxide film containing oxides other than the oxide of the second semiconductor layer 22.

[0053] The insulating film 27 is provided within the trench 26. More specifically, the insulating film 27 covers the side walls and bottom walls of the trench 26. The side wall thickness of the portion of the insulating film 27 that covers the side walls of the trench 26 may be greater than the bottom wall thickness of the portion of the insulating film 27 that covers the bottom wall of the trench 26. The relationship between the side wall thickness and the bottom wall thickness can be arbitrarily changed. In one example, the side wall thickness may be equal to the bottom wall thickness. In another example, the bottom wall thickness may be thicker than the side wall thickness.

[0054] The thickness of the insulating film 27 can be 10 nm or more and 250 nm or less. The thickness of the insulating film 27 may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or less, and 225 nm or more and 250 nm or less.

[0055] The embedded electrode 28 may contain either p-type conductive polysilicon or n-type conductive polysilicon, or both. In one example, the embedded electrode 28 may be made of n-type conductive polysilicon. The embedded electrode 28 is embedded in the trench 26 with the insulating film 27 in between. In other words, the embedded electrode 28 can be said to be embedded in the insulating film 27 within the trench 26. As a result, the embedded electrode 28 faces both the second semiconductor layer 22 and the body region 23 with the insulating film 27 in between.

[0056] The embedded electrode 28 has an electrode surface exposed from the trench 26. The electrode surface is positioned at a distance from the height of the first main surface 20S, closer to the bottom wall of the trench 26. The electrode surface is positioned closer to the first main surface 20S than the depth of the middle part of the trench 26. The electrode surface may also be positioned closer to the bottom wall of the trench 26 than the depth of the middle part of the trench 26. The electrode surface may have a recess that is indented toward the bottom wall of the trench 26.

[0057] As shown in Figure 3, the semiconductor device 10 includes a plurality of mesa portions 29 provided in the active region 11. The plurality of mesa portions 29 are partitioned on the first main surface 20S. That is, the plurality of mesa portions 29 are partitioned as regions between adjacent gate structures 25. The plurality of mesa portions 29 are partitioned with spacing in the Y direction, following the layout of the gate structures 25, and each extends in the X direction. It can also be said that the plurality of mesa portions 29 extend in a stripe-like pattern in the X direction. The width of each mesa portion 29 corresponds to the spacing between adjacent gate structures 25 on the first main surface 20S.

[0058] As shown in Figures 4 and 5, the semiconductor device 10 includes a plurality of p-type well regions 30 provided in the second semiconductor layer 22. Each well region 30 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 22. Each well region 30 replaces the conductivity type of the second semiconductor layer 22 from n-type to p-type. A source potential is applied to each well region 30.

[0059] Multiple well regions 30 are provided in the second semiconductor layer 22, spaced apart from each other in the horizontal direction (Y direction). Each of the multiple well regions 30 is provided in the region below (specifically directly below) each of the multiple gate structures 25. Each well region 30 is provided between the gate structure 25 and the first semiconductor layer 21 in the Z direction. In a plan view, the multiple well regions 30 are provided so as to overlap with the multiple gate structures 25 in a one-to-one correspondence.

[0060] Each well region 30 extends in the X direction in a plan view, corresponding to the extension direction of the corresponding gate structure 25. Multiple well regions 30 are arranged in a stripe pattern extending in the X direction in a plan view. The extension direction of each well region 30 intersects the off-direction of the SiC single crystal. The X-direction ends of each well region 30 may be positioned closer to the inside of the gate structure 25 than the X-direction ends of the corresponding gate structure 25.

[0061] Furthermore, the X-direction ends of each well region 30 may be positioned closer to the periphery of the active region 11 than the X-direction ends of the corresponding gate structure 25. Also, each well region 30 may extend in the Y-direction in a plan view. In this case, each well region 30 coincides with the off-direction in a plan view.

[0062] Each well region 30 is provided with a gap between it and the bottom wall of the gate structure 25, closer to the first semiconductor layer 21, and faces the first semiconductor layer 21 with a portion of the second semiconductor layer 22 in between. Each well region 30 includes an upper end provided closer to the bottom wall of the corresponding gate structure 25 and a bottom provided closer to the first semiconductor layer 21.

[0063] The upper end of each well region 30 is connected to the bottom wall of the corresponding gate structure 25 and faces the embedded electrode 28 across the insulating film 27. The position of the upper end of each well region 30 can be arbitrarily changed. In one example, the upper end of each well region 30 may include a portion along the side wall of the corresponding gate structure 25. That is, the upper end of each well region 30 may face the embedded electrode 28 across the insulating film 27 at the side wall of the corresponding gate structure 25. In another example, the upper end of each well region 30 may be provided at a distance closer to the first semiconductor layer 21 than the bottom wall of the corresponding gate structure 25.

[0064] The bottom of each well region 30 may be located between the depth position of the intermediate part of the second semiconductor layer 22 and the first semiconductor layer 21 in the Z direction. The bottom of each well region 30 may be located between the depth position of the intermediate part of the second semiconductor layer 22 and the bottom wall of the gate structure 25 in the Z direction. The bottom of each well region 30 is directly connected to the second semiconductor layer 22.

[0065] The depth of the well region 30 is, for example, less than the depth of the gate structure 25. The depth of the well region 30 can be defined by the distance in the Z direction between the bottom wall of the corresponding gate structure 25 and the bottom of the well region 30. The depth of the well region 30 can be between 0.5 μm and 5 μm. The depth of the well region 30 may have a value that falls within at least one of the following ranges: 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm. The depth of the well region 30 can be arbitrarily changed. In one example, the depth of the well region 30 may be greater than the depth of the gate structure 25.

[0066] The semiconductor device 10 includes n-type first pillar regions 31 provided within the second semiconductor layer 22. Multiple first pillar regions 31 are provided in the active region 11. On the other hand, the first pillar regions 31 are not provided in the outer peripheral region 12. The multiple first pillar regions 31 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 22. Each first pillar region 31 may be considered as a part of the second semiconductor layer 22 as a high-concentration portion of the second semiconductor layer 22. The n-type impurity concentration of each first pillar region 31 is lower than the p-type impurity concentration of the well region 30. The n-type impurity concentration of each first pillar region 31 is higher than the p-type impurity concentration of the body region 23. Note that the n-type impurity concentration of each first pillar region 31 can be arbitrarily changed. In one example, the n-type impurity concentration of each first pillar region 31 may be less than or equal to the p-type impurity concentration of the body region 23. Furthermore, the first pillar region 31 may also be provided in the outer peripheral region 12.

[0067] Multiple first pillar regions 31 are arranged at intervals in the X direction (m-axis direction) in a plan view. Each first pillar region 31 extends in the Y direction (a-axis direction) in a plan view. In other words, multiple first pillar regions 31 are arranged in a stripe-like pattern extending in the Y direction in a plan view. Each first pillar region 31 intersects (specifically orthogonally) with the gate structure 25 in a plan view. The extension direction of each first pillar region 31 coincides with the off-direction of the SiC single crystal.

[0068] The width (dimension in the X direction) of the first pillar region 31 may be greater than the width of the gate structure 25. The width of the first pillar region 31 may be greater than 0 μm and 3 μm or less. The width of the first pillar region 31 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The width of the first pillar region 31 can be changed arbitrarily. In one example, the width of the first pillar region 31 may be less than or equal to the width of the gate structure 25. In another example, the width of the first pillar region 31 may be less than or equal to the spacing of the gate structure 25.

[0069] Multiple first pillar regions 31 may be provided at intervals greater than the width of the first pillar region 31. The interval of the first pillar regions 31 can be defined by the distance between adjacent first pillar regions 31 in the X direction. The interval of the first pillar regions 31 may be greater than the width of the gate structure 25. The interval of the first pillar regions 31 may be greater than 0 μm and 3 μm or less. The interval of the first pillar regions 31 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or more and 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Note that the interval of the first pillar regions 31 can be arbitrarily changed. In one example, the spacing of the first pillar regions 31 may be less than or equal to the width of the first pillar regions 31. In another example, the spacing of the first pillar regions 31 may be less than or equal to the width of the gate structure 25. In yet another example, the spacing of the first pillar regions 31 may be less than or equal to the spacing of the gate structure 25.

[0070] Each first pillar region 31 is located in a region closer to the first semiconductor layer 21 than the bottom of the body region 23. Each first pillar region 31 is a vertically elongated columnar shape along the Z direction. Each first pillar region 31 is located at a distance from the bottom of the second semiconductor layer 22 closer to the first main surface 20S. Each first pillar region 31 faces the first semiconductor layer 21 across the second semiconductor layer 22. Here, the bottom of the second semiconductor layer 22 refers to the surface portion of the second semiconductor layer 22 closer to the first semiconductor layer 21, including the boundary between the first semiconductor layer 21 and the second semiconductor layer 22.

[0071] In the first embodiment, each first pillar region 31 is composed of a single n-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 22). The axial channel is a region (channel) with relatively wide interatomic distances in the SiC single crystal and is surrounded by rows of atoms that constitute the crystal axis extending in the stacking direction. In other words, the axial channel is a region in which a region with sparse interatomic distances (atomic density) in the horizontal direction extends in the Z direction.

[0072] The axial channel is preferably a region surrounded by atomic rows along the low-index crystal axes among the crystal axes. The low-index crystal axes are crystal axes in which the absolute values ​​of "a1", "a2", "a3", and "c" are all between 0 and 2 (preferably between 0 and 1) with respect to Miller indices (a1, a2, a3, c). In the first embodiment, the axial channel is composed of a region surrounded by atomic rows along the c axis ((0001) axis) of the SiC single crystal. That is, each first pillar region 31 extends along the c axis as an axial channel and has the off direction and off angle θ described above. In other words, each first pillar region 31 is inclined with respect to the Z direction by an off angle θ in the off direction.

[0073] In the first embodiment, the extension direction (a-axis direction) of each first pillar region 31 coincides with the off-direction of the off-angle θ. Therefore, each first pillar region 31 extends perpendicularly in a cross-sectional view along a direction (Y-direction, m-axis direction) perpendicular to the off-direction (X-direction, a-axis direction).

[0074] As shown in Figure 10, the first pillar region 31 has a depth greater than the depth of the gate structure 25. The depth of the first pillar region 31 can be defined by the distance in the Z direction between the bottom of the body region 23 and the first bottom 31B of the first pillar region 31. The depth of the first pillar region 31 is less than the thickness of the second semiconductor layer 22. Here, the bottom of the body region 23 refers to the surface layer of the body region 23 that is closer to the first pillar region 31 (second pillar region 32), including the boundary between the first pillar region 31 (second pillar region 32) and the body region 23.

[0075] The depth of the first pillar region 31 can be greater than 0 μm and 5 μm or less. The depth of the first pillar region 31 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the first pillar region 31 is 1 μm or more.

[0076] The aspect ratio of the first pillar region 31 can be between 1 and 10. The aspect ratio of the first pillar region 31 is the ratio of the depth of the first pillar region 31 to the width of the first pillar region 31. The aspect ratio of the first pillar region 31 may have a value that belongs to at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0077] Each first pillar region 31 includes a first upper region 31U and a first lower region 31L. The first upper region 31U is the region of the first pillar region 31 located closer to the first main surface 20S than the bottom wall of the corresponding gate structure 25. The first lower region 31L is the region of the first pillar region 31 located closer to the bottom of the second semiconductor layer 22 than the bottom wall of the corresponding gate structure 25. The n-type impurity concentration in each first pillar region 31 is lower than the p-type impurity concentration in the well region 30 in both the first upper region 31U and the first lower region 31L.

[0078] As shown in Figures 3 and 4, the first upper region 31U is interposed in the region between the multiple gate structures 25. The first upper region 31U is connected to the side walls of the multiple gate structures 25. As a result, the first upper region 31U faces the embedded electrode 28 across the insulating film 27 of the multiple gate structures 25. The first upper region 31U includes a first upper end connected to the body region 23.

[0079] As shown in Figures 6 and 10, in the first embodiment, the first upper region 31U includes a first constriction that is narrowed in the X direction and a first bulge that bulges in the X direction. The first bulge is provided in the region between the bottom walls of the plurality of gate structures 25 and the bottom of the body region 23 in the Z direction. The first bulge is a portion in which the width in the X direction gradually increases from the first constriction toward the bottom of the body region 23. The first bulge includes a first upper end connected to the body region 23. The first constriction is provided in the region between the first bulge and the bottom of the body region 23 in the Z direction. The first constriction is a portion in which the width in the X direction gradually decreases from the bottom wall of the gate structure 25 toward the body region 23.

[0080] The first lower region 31L is located closer to the bottom of the second semiconductor layer 22 than the bottom walls of the multiple gate structures 25. The first lower region 31L extends in the Y direction. Therefore, the first lower region 31L intersects with the multiple gate structures 25 in a three-dimensional manner. In this way, the multiple first pillar regions 31 (first lower region 31L) are provided in the region directly below the gate structures 25, spaced apart in the X direction according to the extending direction of the gate structures 25.

[0081] As shown in Figure 12, in the first embodiment, the first lower region 31L intersects with and is connected to a plurality of well regions 30 in the region directly below the plurality of gate structures 25. The p-type impurity concentration in the well region 30 at the first intersection Cr1 between the well region 30 and the first lower region 31L is offset (reduced) by the amount of the n-type impurity concentration (pentavalent element concentration) in the first lower region 31L.

[0082] As shown in Figures 7 to 11, the first lower region 31L includes a first bottom portion 31B located closer to the bottom of the second semiconductor layer 22 than the depth position of the bottom walls of the multiple gate structures 25. The first bottom portion 31B is located closer to the bottom of the second semiconductor layer 22 than the multiple well regions 30. The first bottom portion 31B includes a first portion extending in the Y direction in a first region directly below the multiple well regions 30, and a second portion extending in the Y direction in a second region outside the first region. The first bottom portion 31B faces the bottom walls of the multiple gate structures 25 across the multiple well regions 30.

[0083] The distance in the Z direction between the bottom of the well region 30 and the first bottom 31B is less than the distance in the Z direction between the bottom of the second semiconductor layer 22 and the first bottom 31B. The distance in the Z direction between the bottom wall of the gate structure 25 and the first bottom 31B is less than the distance in the Z direction between the bottom of the second semiconductor layer 22 and the first bottom 31B. In the first embodiment, the distance in the Z direction between the bottom wall of the gate structure 25 and the first bottom 31B is smaller than the depth of the gate structure 25. Note that the distance in the Z direction between the bottom wall of the gate structure 25 and the first bottom 31B can be arbitrarily changed, and may be larger than the depth of the gate structure 25, for example.

[0084] The configuration of the first pillar region 31 can be arbitrarily changed. In one example, the first pillar region 31 may have a first constriction but not a first bulge. In another example, the first pillar region 31 may have a first bulge but not a first constriction. In this case, the first bulge may be connected to the body region 23 as a first upper end. In yet another example, the first pillar region 31 may not have both a first constriction and a first bulge. In this case, the first pillar region 31 may extend along the Z direction with a constant width. The first pillar region 31 may also have a tapered or tapered shape along the Z direction.

[0085] As shown in Figure 5, the semiconductor device 10 includes a plurality of p-type second pillar regions 32 provided within the second semiconductor layer 22. Each second pillar region 32 is provided in the active region 11, but not in the outer peripheral region 12. Each second pillar region 32 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 22. The p-type impurity concentration of each second pillar region 32 is lower than the p-type impurity concentration of the well region 30. The p-type impurity concentration of each second pillar region 32 may be higher than the p-type impurity concentration of the body region 23. Note that the p-type impurity concentration of each second pillar region 32 can be arbitrarily changed, and for example, it may be less than or equal to the p-type impurity concentration of the body region 23. Furthermore, each second pillar region 32 may also be provided in the outer peripheral region 12 (see Figure 2).

[0086] As shown in Figure 3, the multiple second pillar regions 32 may be arranged with spacing in the X direction (m-axis direction) in a plan view. Each second pillar region 32 extends in the Y direction in a plan view. In other words, the multiple second pillar regions 32 are arranged in a stripe-like pattern extending in the Y direction in a plan view. For this reason, each second pillar region 32 intersects (specifically orthogonally) with the multiple gate structures 25. The extension direction of each second pillar region 32 coincides with the off-direction of the SiC single crystal.

[0087] As shown in Figures 3, 6, and 7, the multiple second pillar regions 32 are arranged alternately with the multiple first pillar regions 31 in the X direction. As a result, the multiple second pillar regions 32 form pn junctions with the multiple first pillar regions 31. Consequently, a bipolar diode is formed that includes multiple first pillar regions 31 as cathode regions and multiple second pillar regions 32 as anode regions. The multiple second pillar regions 32 have a charge balance with respect to the multiple first pillar regions 31 and also constitute a superjunction structure with the multiple first pillar regions 31. Here, charge balance means a state in which the depletion layer extending from the multiple second pillar regions 32 is connected within the multiple first pillar regions 31.

[0088] The second pillar region 32 has a width (dimension in the X direction) corresponding to the spacing of the first pillar regions 31. The width of the second pillar region 32 may be equal to the width of the first pillar region 31. The width of the second pillar region 32 may be greater than the width of the gate structure 25. The width of the second pillar region 32 can be greater than 0 μm and 3 μm or less. The width of the second pillar region 32 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0089] The width of the second pillar region 32 can be changed arbitrarily. In one example, the width of the second pillar region 32 may be greater than or less than the width of the first pillar region 31. In another example, the width of the second pillar region 32 may be less than or equal to the width of the gate structure 25. In yet another example, the width of the second pillar region 32 may be less than or equal to the spacing between the gate structures 25.

[0090] Multiple second pillar regions 32 are provided at intervals corresponding to the width of the first pillar region 31. The spacing of the second pillar regions 32 may be equal to the width of the second pillar region 32. The spacing of the second pillar regions 32 may be greater than the spacing of the first pillar region 31. The spacing of the second pillar regions 32 may be greater than the width of the gate structure 25. The spacing of the second pillar regions 32 may be greater than 0 μm and 3 μm or less. The spacing of the second pillar regions 32 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0091] The spacing of the second pillar regions 32 can be arbitrarily changed. In one example, the spacing of the second pillar regions 32 may be greater than or less than the width of the first pillar region 31. In another example, the spacing of the second pillar regions 32 may be less than or equal to the spacing of the first pillar region 31. In yet another example, the spacing of the second pillar regions 32 may be less than or equal to the width of the gate structure 25. In yet another example, the spacing of the second pillar regions 32 may be less than or equal to the spacing of the gate structure 25.

[0092] Multiple second pillar regions 32 are provided in a region closer to the bottom of the second semiconductor layer 22 than to the bottom of the body region 23. Each second pillar region 32 is a vertically elongated columnar shape along the Z direction. Each second pillar region 32 is provided with a gap between it and the first main surface 20S, closer to the bottom of the second semiconductor layer 22. Each second pillar region 32 faces the first semiconductor layer 21 with a portion of the second semiconductor layer 22 in between.

[0093] In the first embodiment, each second pillar region 32 is composed of a single p-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 22). That is, each second pillar region 32 extends along the c-axis as the axial channel and has the off-direction and off-angle θ described above. In other words, each second pillar region 32 is inclined with respect to the Z-direction by an off-angle θ in the off-direction. In the first embodiment, the extension direction (a-axis direction) of each second pillar region 32 coincides with the off-direction of the off-angle θ. Therefore, each second pillar region 32 extends perpendicularly in a cross-sectional view along a direction (Y-direction, m-axis direction) perpendicular to the off-direction (X-direction, a-axis direction).

[0094] The second pillar region 32 has a depth greater than the depth of the gate structure 25. The depth of the second pillar region 32 can be defined by the distance in the Z direction between the bottom of the body region 23 and the bottom of the second pillar region 32. The depth of the second pillar region 32 is less than the thickness of the second semiconductor layer 22. The depth of the second pillar region 32 may be equal to the depth of the first pillar region 31.

[0095] The depth of the second pillar region 32 can be greater than 0 μm and 5 μm or less. The depth of the second pillar region 32 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the second pillar region 32 is 1 μm or more.

[0096] The depth of the second pillar region 32 can be arbitrarily changed. In one example, the depth of the second pillar region 32 may be greater than the depth of the first pillar region 31. In another example, the depth of the second pillar region 32 may be less than the depth of the first pillar region 31.

[0097] The aspect ratio of the second pillar region 32 may be equal to the aspect ratio of the first pillar region 31. The aspect ratio of the second pillar region 32 is the ratio of the depth of the second pillar region 32 to the width of the second pillar region 32. The aspect ratio of the second pillar region 32 can be between 1 and 10. The aspect ratio of the second pillar region 32 may have a value that belongs to at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10. Note that the aspect ratio of the second pillar region 32 can be arbitrarily changed and may differ from the aspect ratio of the first pillar region 31.

[0098] Each second pillar region 32 includes a second upper region 32U and a second lower region 32L. The second upper region 32U is a region of the second pillar region 32 located closer to the first main surface 20S than the bottom wall of the corresponding gate structure 25. The second lower region 32L is a region of the second pillar region 32 located closer to the bottom of the second semiconductor layer 22 than the bottom wall of the corresponding gate structure 25. The p-type impurity concentration in each second pillar region 32 is lower than the p-type impurity concentration in the well region 30 in both the second upper region 32U and the second lower region 32L.

[0099] As shown in Figures 3 and 5, the second upper region 32U is interposed in the region between the multiple gate structures 25. The second upper region 32U is connected to the side walls of the multiple gate structures 25. As a result, the second upper region 32U faces the embedded electrode 28 across the insulating film 27 of the multiple gate structures 25. The second upper region 32U includes a second upper end connected to the body region 23.

[0100] As shown in Figures 6 and 8 to 12, the second pillar region 32 forms a pn joint with the first upper region 31U of the multiple first pillar regions 31 in the region between the multiple gate structures 25. The second upper region 32U has a charge balance with the first upper region 31U in the region between the multiple gate structures 25. The second upper region 32U forms a superjunction structure with the first upper region 31U.

[0101] In the first embodiment, the second upper region 32U includes a second bulge that protrudes in the X direction and a second constriction that narrows in the X direction. The second bulge is provided in the region between the bottom walls of the plurality of gate structures 25 and the bottom of the body region 23 in the Z direction. The second bulge is formed along the first constriction of the first pillar region 31. The second bulge is a portion in which the width in the X direction gradually increases from the bottom wall of the gate structure 25 toward the bottom of the body region 23. The second bulge includes a second upper end connected to the body region 23. The second constriction is provided in the region between the second bulge and the bottom of the body region 23 in the Z direction. The second constriction is formed along the first bulge of the first pillar region 31. The second constriction is a portion in which the width in the X direction gradually decreases from the bottom wall of the gate structure 25 toward the body region 23. Thus, the irregularities of the second upper region 32U interlock with the irregularities of the first upper region 31U.

[0102] The second lower region 32L is located closer to the bottom of the second semiconductor layer 22 than the bottom walls of the multiple gate structures 25. The second lower region 32L extends in the Y direction. Therefore, the second lower region 32L intersects with the multiple gate structures 25 in a three-dimensional manner. In this way, the multiple second pillar regions 32 (second lower region 32L) are provided at intervals in the X direction according to the extending direction of the gate structures 25 in the region directly below the gate structures 25. The multiple second pillar regions 32 are provided alternately with the multiple first pillar regions 31 in the X direction in the region directly below the gate structures 25.

[0103] As shown in Figure 12, in the first embodiment, the second lower region 32L intersects with and connects to the multiple well regions 30 in the region directly below the multiple gate structures 25. In other words, the multiple second pillar regions 32 are interposed between the body region 23 and the multiple well regions 30, and electrically connect the multiple well regions 30 and the body region 23. The multiple second pillar regions 32 are electrically interlocked with the body region 23 and the multiple well regions 30. The p-type impurity concentration in the well region 30 at the second intersection Cr2 between the well region 30 and the second lower region 32L is increased by the amount of the p-type impurity concentration (trivalent element concentration) in the second lower region 32L. In other words, the p-type impurity concentration in the second intersection Cr2 is higher than the p-type impurity concentration in the first intersection Cr1.

[0104] As shown in Figures 6 to 11, the second lower region 32L forms a pn joint with the first lower region 31L of the multiple first pillar regions 31. More specifically, the second lower region 32L includes a first joint that forms a pn joint with the first lower region 31L in a first region directly below the multiple gate structures 25, and a second joint that forms a pn joint with the first lower region 31L in a second region outside the first region. The second lower region 32L has a charge balance with the first lower region 31L. The second lower region 32L constitutes a superjunction structure with the first lower region 31L.

[0105] The second lower region 32L includes a second bottom portion 32B located closer to the bottom of the second semiconductor layer 22 than the depth position of the bottom walls of the multiple gate structures 25. The second bottom portion 32B is located closer to the bottom of the second semiconductor layer 22 than the multiple well regions 30. The second bottom portion 32B includes a first portion extending in the Y direction in a first region directly below the multiple well regions 30, and a second portion extending in the Y direction in a second region outside the first region. The second bottom portion 32B faces the bottom walls of the multiple gate structures 25 across the multiple well regions 30.

[0106] The second bottom portion 32B may be located at the same position in the Z-direction as the first bottom portion 31B of the first pillar region 31 in the region directly below the multiple gate structures 25. The position of the second bottom portion 32B in the Z-direction can be arbitrarily changed. In one example, the second bottom portion 32B may be located closer to the bottom of the second semiconductor layer 22 than the first bottom portion 31B of the first pillar region 31 in the region directly below the multiple gate structures 25. In another example, the second bottom portion 32B may be located closer to the bottom wall of the gate structure 25 than the first bottom portion 31B of the first pillar region 31 in the region directly below the multiple gate structures 25.

[0107] The distance in the Z direction between the bottom of the well region 30 and the second bottom 32B is less than the distance in the Z direction between the bottom of the second semiconductor layer 22 and the second bottom 32B. The distance in the Z direction between the bottom wall of the gate structure 25 and the second bottom 32B is less than the distance in the Z direction between the bottom of the second semiconductor layer 22 and the second bottom 32B. In the first embodiment, the distance in the Z direction between the bottom wall of the gate structure 25 and the second bottom 32B is smaller than the depth of the gate structure 25. Note that the distance in the Z direction between the bottom wall of the gate structure 25 and the second bottom 32B can be arbitrarily changed, and may be larger than the depth of the gate structure 25, for example.

[0108] The configuration of the second pillar region 32 can be arbitrarily changed. In one example, the second pillar region 32 may have a second constriction but not a second bulge. In this case, the second constriction may be connected to the body region 23 as a second upper end. In another example, the second pillar region 32 may have a second bulge but not a second constriction. In yet another example, the second pillar region 32 may not have both a second constriction and a second bulge. In this case, the second pillar region 32 may extend along the Z direction with a constant width. The second pillar region 32 may also have a tapered or tapered shape along the Z direction.

[0109] As shown in Figures 12 and 13, the semiconductor device 10 includes a p-type mesh region 33 provided within the second semiconductor layer 22 in a horizontal cross-sectional view. The mesh region 33 extends in a mesh-like manner in the X direction (m-axis direction) and Y direction (a-axis direction) along the first main surface 20S at a position separated from the first main surface 20S within the second semiconductor layer 22. The mesh region 33 aims to improve short-circuit withstand capability by narrowing the current when the device is ON. This mesh region 33 demarcates a plurality of n-type intermesh regions 34 within the second semiconductor layer 22. The plurality of intermesh regions 34 form a plurality of current paths.

[0110] As shown in Figure 12, the mesh region 33 is located closer to the bottom of the second semiconductor layer 22 than the bottom of the body region 23 (see Figure 5). The mesh region 33 is located closer to the bottom of the second semiconductor layer 22 than the bottom wall of the gate structure 25. The mesh region 33 includes a plurality of p-shaped well regions 30 as a plurality of first stripe regions extending in the X direction, and a plurality of p-shaped second pillar regions 32 as a plurality of second stripe regions extending in the Y direction. The plurality of well regions 30 and the plurality of second pillar regions 32 are integrated.

[0111] Since each second lower region 32L is connected to a plurality of well regions 30, the plurality of second lower regions 32L form a mesh region 33 with the plurality of well regions 30 and also form an intermesh region 34. As shown in Figure 13, since each second upper region 32U is connected to the body region 23, each second upper region 32U is formed as a connection part that electrically connects the mesh region 33 to the body region 23.

[0112] As shown in Figure 12, the multiple intermesh regions 34 are partitioned in a row along the X direction in a plan view according to the extension direction of the multiple well regions 30 (multiple gate structures 25). The multiple intermesh regions 34 are partitioned in a row along the Y direction in a plan view according to the extension direction of the multiple second pillar regions 32 (multiple first pillar regions 31). In this way, the multiple intermesh regions 34 are partitioned in a matrix with spacing in the X and Y directions in a plan view. The multiple intermesh regions 34 are composed of, for example, first pillar regions 31. As a result, the multiple intermesh regions 34 extend in a vertical columnar shape along the Z direction. Because the n-type impurity concentration of the first pillar regions 31 is higher than the n-type impurity concentration of the second semiconductor layer 22, the multiple intermesh regions 34 form current paths with a resistance value lower than the resistance value of the second semiconductor layer 22.

[0113] Each of the multiple intermesh regions 34 includes a first portion partitioned in a region closer to the body region 23 than the bottom walls of the multiple gate structures 25, and a second portion partitioned in a region closer to the bottom of the second semiconductor layer 22 than the bottom walls of the multiple gate structures 25. The first portion is composed of a first upper region 31U, and the second portion is composed of a first lower region 31L. The first portion (first upper region 31U) is partitioned by multiple gate structures 25 and multiple second pillar regions 32 (second upper region 32U). The second portion (first lower region 31L) is partitioned by a mesh region 33, in other words, multiple well regions 30 and multiple second pillar regions 32 (second lower region 32L).

[0114] As shown in Figures 4 and 5, the semiconductor device 10 includes an n-type source region 35 provided on the surface of the body region 23. Multiple source regions 35 are provided in the active region 11. The source regions 35 have an n-type impurity concentration higher than the p-type impurity concentration of the body region 23. The source regions 35 replace the conductivity type of the body region 23 from p-type to n-type. The n-type impurity concentration of the source regions 35 is higher than the n-type impurity concentration of the second semiconductor layer 22.

[0115] As shown in Figure 3, each source region 35 is adjacent to two gate structures 25 that constitute the mesa portion 29. Two source regions 35, positioned on either side of a single gate structure 25 in the X direction, are positioned at the same location relative to each other in the Y direction. In other words, the multiple source regions 35 are arranged in a line in the X direction in a plan view. Multiple source regions 35 are provided, for example, spaced apart in the Y direction relative to the corresponding mesa portion 29. In other words, the source regions 35 are provided in a one-to-many correspondence with respect to the mesa portion 29. Thus, the multiple source regions 35 are arranged in a matrix with spacing in both the X and Y directions in a plan view. Each source region 35 extends in the Y direction in a plan view according to the extending direction of the gate structure 25.

[0116] The arrangement of the multiple source regions 35 can be arbitrarily changed. In one example, the multiple source regions 35 may be arranged in a staggered pattern with spacing in the X and Y directions in a plan view. That is, two source regions 35 placed on either side of a single gate structure 25 in the X direction may be offset in the Y direction.

[0117] As shown in Figure 4, multiple source regions 35 are provided in multiple mesa portions 29 on the surface of the body region 23. Each source region 35 has a depth less than the depth of the body region 23. The depth of each source region 35 is greater than the distance in the Z direction between the bottom of the body region 23 and the bottom of the source region 35. Here, the depth of the body region 23 can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the body region 23. The depth of the source region 35 can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the source region 35. Note that the depth of each source region 35 can be arbitrarily changed. In one example, the depth of each source region 35 may be less than the distance in the Z direction between the bottom of the body region 23 and the bottom of the source region 35.

[0118] Each source region 35 is provided with a gap between it and the first main surface 20S, closer to the bottom of the body region 23. Each source region 35 faces the second semiconductor layer 22 across the bottom of the body region 23. Each source region 35 includes a portion located closer to the bottom wall of the trench 26 than the electrode surface of the embedded electrode 28, and a portion located closer to the first main surface 20S than the electrode surface. Each source region 35 includes a portion that faces the embedded electrode 28 horizontally across the insulating film 27.

[0119] As shown in Figures 4, 5, and 8 to 11, the semiconductor device 10 includes a plurality of n-type cap regions 36 provided within the second semiconductor layer 22. The plurality of cap regions 36 are provided in the active region 11.

[0120] The cap region 36 has an n-type impurity concentration higher than that of the second semiconductor layer 22. The n-type impurity concentration of the cap region 36 is higher than that of the p-type impurity concentration of the body region 23. The n-type impurity concentration of the cap region 36 is higher than that of the p-type impurity concentration of the well region 30. The n-type impurity concentration of the cap region 36 may also be higher than that of the source region 35. However, the n-type impurity concentration of the cap region 36 may be less than or equal to the n-type impurity concentration of the source region 35.

[0121] The multiple cap regions 36 are provided in the region between the multiple gate structures 25 (mesa portion 29) in a region closer to the bottom wall of the gate structure 25 than the body region 23. The multiple cap regions 36 are provided at intervals closer to the first main surface 20S than the bottom wall of the multiple gate structures 25. The multiple cap regions 36 include a plurality of first cap regions 36A and a plurality of second cap regions 36B.

[0122] The multiple first cap regions 36A are provided at intervals in the X direction according to the extending direction of the multiple gate structures 25. Each first cap region 36A is adjacent to the corresponding gate structure 25 in the Y direction. The multiple first cap regions 36A are provided in a one-to-one correspondence with the multiple first pillar regions 31.

[0123] As shown in Figure 4, each first cap region 36A is provided across the entire region (mesa portion 29) between adjacent gate structures 25 in the Y direction. Multiple first cap regions 36A are connected to the first upper regions 31U of multiple first pillar regions 31. This increases the n-type impurity concentration in the first upper regions 31U.

[0124] Each first cap region 36A is positioned closer to the bottom wall of the trench 26 with respect to the electrode surface of the embedded electrode 28. Each first cap region 36A faces the embedded electrode 28 across the insulating film 27. Each first cap region 36A faces a plurality of source regions 35 in the Z direction, with a portion of the body region 23 in between. As a result, each first cap region 36A, together with the plurality of source regions 35, forms a first channel Ch1 along the gate structure 25 within the body region 23.

[0125] As shown in Figures 5, 10, and 11, the multiple second cap regions 36B are interposed in the regions between the multiple first cap regions 36A that are adjacent in the X direction in the region (mesa portion 29) between the multiple gate structures 25. Each second cap region 36B extends in a band shape in the X direction along the side wall of the corresponding gate structure 25. The multiple second cap regions 36B are spaced apart from each other in the Y direction in a cross-sectional view along the Y direction. Each second cap region 36B faces each other in the Y direction via a part of the corresponding second pillar region 32 (second upper region 32U). In other words, each second cap region 36B is interposed between the side wall of the corresponding gate structure 25 and the corresponding second pillar region 32 in a cross-sectional view along the Y direction.

[0126] Multiple second cap regions 36B are provided in portions of the second upper region 32U of the multiple second pillar regions 32 that are interposed between the multiple first cap regions 36A. In the first embodiment, each second cap region 36B extends in the X direction from the first cap region 36A along the side wall of the gate structure 25, and replaces the conductivity type of a part of the second upper region 32U from p type to n type.

[0127] The multiple second cap regions 36B face the multiple source regions 35 in the Z direction, with a portion of the body region 23 in between. As a result, the multiple second cap regions 36B, together with the multiple source regions 35, form a second channel Ch2 within the body region 23 along the multiple gate structures 25.

[0128] In this way, the multiple cap regions 36 extend the current path connecting the multiple first pillar regions 31 and the multiple source regions 35 through the first channel Ch1 originating from the first cap region 36A and the second channel Ch2 originating from the second cap region 36B.

[0129] [Peripheral Region] The configuration of the peripheral region 12 of the chip 20 will be described with reference to Figures 2 and 14. Figure 14 is a cross-sectional structure obtained by cutting the semiconductor device 10 along the line F14-F14 in Figure 1, and schematically shows the cross-sectional structure of the peripheral region 12.

[0130] As shown in Figures 2 and 14, the semiconductor device 10 includes a p-type outer well region 37 provided on the surface of the chip 20 (second semiconductor layer 22) in the outer peripheral region 12. A source potential is applied to the outer well region 37. The outer well region 37 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 22. The p-type impurity concentration of the outer well region 37 may be higher than the p-type impurity concentration of the body region 23. The p-type impurity concentration of the outer well region 37 is lower than the p-type impurity concentration of the well region 30. Note that the p-type impurity concentration of the outer well region 37 can be arbitrarily changed. In one example, the p-type impurity concentration of the outer well region 37 may be less than or equal to the p-type impurity concentration of the body region 23. In another example, the p-type impurity concentration of the outer well region 37 may be greater than or equal to the p-type impurity concentration of the well region 30.

[0131] The outer well region 37 extends in layers along the first main surface 20S. The outer well region 37 is spaced closer to the gate structures 25 than to the periphery of the first main surface 20S. In plan view, the outer well region 37 extends in a band shape along the periphery of the active region 11. In one example, the outer well region 37 is a polygonal ring having four sides parallel to the periphery of the first main surface 20S in plan view. In the first embodiment, the outer well region 37 is a quadrilateral ring in plan view. The outer well region 37 surrounds the active region 11 in plan view. Therefore, the outer well region 37 surrounds the gate structures 25 in plan view. In the outer well region 37, the corner portions that form the four corners of the quadrilateral ring in plan view may be curved arcs that are convex outward.

[0132] The outer well region 37 includes an inner edge portion closer to the plurality of gate structures 25 and an outer edge portion closer to the periphery of the first main surface 20S. The inner edge portion of the outer well region 37 demarcates the boundary between the active region 11 and the outer peripheral region 12. The portion of the inner edge portion of the outer well region 37 extending in the X direction is connected to the ends of the plurality of gate structures 25. The inner edge portion of the outer well region 37 faces the embedded electrode 28 across the insulating film 27. The inner edge portion of the outer well region 37 may be located closer to the interior of the plurality of gate structures 25 than to the ends of the plurality of gate structures 25. The inner edge portion of the outer well region 37 may have a portion located in the region between the plurality of gate structures 25 and may be connected to the body region 23. The outer edge portion of the outer well region 37 is provided at a distance from the periphery of the first main surface 20S. The outer edge portion of the outer well region 37 extends parallel to the inner edge portion of the outer well region 37.

[0133] The outer well region 37 may have a width greater than 0 μm and less than or equal to 300 μm. Here, the width of the outer well region 37 can be defined by the dimension in the direction perpendicular to the direction in which the outer well region 37 extends in a plan view. The width of the outer well region 37 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 25 μm, 25 μm to 50 μm, 50 μm to 75 μm, 75 μm to 100 μm, 100 μm to 125 μm, 125 μm to 150 μm, 150 μm to 175 μm, 175 μm to 200 μm, 200 μm to 225 μm, 225 μm to 250 μm, 250 μm to 275 μm, and 275 μm to 300 μm.

[0134] The outer well region 37 is provided at a distance from the first semiconductor layer 21, closer to the first main surface 20S. The outer well region 37 faces the first semiconductor layer 21, with a portion of the second semiconductor layer 22 in between. In one example, the outer well region 37 is provided at a distance from the first main surface 20S, closer to the depth position of the middle portion of the second semiconductor layer 22. In another example, the outer well region 37 may include a portion located closer to the first semiconductor layer 21 than the depth position of the middle portion of the second semiconductor layer 22.

[0135] In the first embodiment, the outer well region 37 includes a portion located closer to the bottom of the second semiconductor layer 22 than the depth position of the bottom walls of the multiple gate structures 25. Therefore, the depth of the outer well region 37 is greater than the depth of the gate structures 25. The depth of the outer well region 37 is greater than the depth of the body region 23. Here, the depth of the outer well region 37 can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the outer well region 37. Note that the depth of the outer well region 37 can be arbitrarily changed. In one example, the depth of the outer well region 37 may be less than or equal to the depth of the gate structures 25. In another example, the depth of the outer well region 37 may be less than or equal to the depth of the body region 23.

[0136] The outer well region 37 forms a pn junction with the second semiconductor layer 22. When a reverse bias voltage is applied, the outer well region 37 expands a depletion layer in the second semiconductor layer 22. The depletion layer of the outer well region 37 expands in the horizontal direction (X direction, Y direction) and the thickness direction (Z direction), and integrates with the depletion layer expanding from the body region 23 and the well region 30. The outer well region 37 extends the depletion layer expanding from the body region 23 and the well region 30 toward the periphery of the first main surface 20S. This reduces the electric field strength (electric field concentration) in the outer peripheral region 12, which is the periphery of the first main surface 20S.

[0137] The semiconductor device 10 includes a p-type outer contact region 38 provided on the surface of the outer well region 37. The outer contact region 38 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 37. The outer contact region 38 is provided at a distance from the bottom of the outer well region 37, closer to the first main surface 20S. The outer contact region 38 faces the second semiconductor layer 22 across a portion of the outer well region 37. In plan view, the outer contact region 38 extends in a strip shape along the outer well region 37. That is, in plan view, the outer contact region 38 is a polygonal ring (a quadrilateral ring in the first embodiment) having four sides parallel to the periphery of the first main surface 20S. In plan view, the outer contact region 38 surrounds a plurality of gate structures 25. In the outer contact region 38, the corner portions that form the four corners of the quadrilateral ring in plan view may be curved arcs that are convex outwards.

[0138] Multiple outer contact regions 38 may be provided. In this case, the multiple outer contact regions 38 may be spaced apart from each other in the extending direction of the outer well region 37. Each outer contact region 38 may extend in a strip shape along the extending direction of the outer well region 37.

[0139] The outer contact region 38 has a width less than the width of the outer well region 37. For this reason, the outer contact region 38 is located within the outer well region 37. The outer contact region 38 is spaced apart from both the inner and outer edges of the outer well region 37. In one example, the outer contact region 38 is located towards the outer edge of the outer well region 37. The position of the outer contact region 38 can be arbitrarily changed; for example, it may be located in the middle of the outer well region 37 in the width direction.

[0140] The semiconductor device 10 includes at least one p-type field region 39 provided in the outer peripheral region 12. Each field region 39 is provided on the surface of the chip 20 (second semiconductor layer 22). In one example, each field region 39 may be electrically floating. In another example, each field region 39 may be assigned a source potential.

[0141] The number of field regions 39 can be arbitrarily changed. The number of field regions 39 can be between 1 and 20. The number of field regions 39 may have a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 39 is between 1 and 8. In the first embodiment, the number of field regions 39 is 3.

[0142] Multiple field regions 39 are arranged at intervals from one another. Each field region 39 is located in the region between the periphery of the first main surface 20S and the multiple gate structures 25 (active regions 11). More specifically, each field region 39 is located in the region between the periphery of the first main surface 20S and the outer well region 37. Each field region 39 is located at an interval from the periphery of the first main surface 20S.

[0143] Multiple field regions 39 extend in a strip-like manner along the outer well region 37 in a plan view. Each field region 39 includes a portion that extends in a strip-like manner in the X direction and a portion that extends in a strip-like manner in the Y direction. In one example, each field region 39 is a polygonal ring (a quadrilateral ring in the first embodiment) surrounding multiple gate structures 25 in a plan view. Each field region 39 may be an arc-shaped curve in a plan view such that the corner portions that form the four corners of the quadrilateral ring are convex outwards.

[0144] Each field region 39 is provided with a gap between it and the first main surface 20S, closer to the first semiconductor layer 21. Each field region 39 faces the first semiconductor layer 21 with a portion of the second semiconductor layer 22 in between. In one example, each field region 39 is provided with a gap between it and the first semiconductor layer 21, closer to the depth position of the middle part of the second semiconductor layer 22. In another example, each field region 39 may include a portion closer to the first main surface 20S than the depth position of the middle part of the second semiconductor layer 22.

[0145] In the first embodiment, the field region 39 includes a portion located closer to the bottom of the second semiconductor layer 22 than the depth position of the bottom walls of the multiple gate structures 25. Therefore, the depth of the field region 39 is greater than the depth of the gate structures 25. The depth of the field region 39 is greater than the depth of the body region 23. Here, the depth of the field region 39 can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the field region 39. Note that the depth of the field region 39 can be arbitrarily changed. In one example, the depth of the field region 39 may be less than or equal to the depth of the gate structures 25. In another example, the depth of the field region 39 may be less than or equal to the depth of the body region 23.

[0146] Each field region 39 forms a pn junction with the second semiconductor layer 22. Each field region 39 expands a depletion layer in the second semiconductor layer 22 when a reverse bias voltage is applied. The depletion layer of each field region 39 expands in the horizontal direction (X direction, Y direction) and the thickness direction (Z direction) and integrates with the depletion layer expanding from the body region 23 and the outer well region 37. Each field region 39 extends the depletion layer expanding from the body region 23 and the outer well region 37 toward the periphery of the first main surface 20S. This reduces the electric field strength (electric field concentration) in the outer peripheral region 12, which is the periphery of the first main surface 20S.

[0147] The width, depth, and spacing of the multiple field regions 39 can be arbitrarily changed and can take various values ​​depending on the electric field to be mitigated. The widths of the multiple field regions 39 may be equal to each other or different. In one example, the widths of the multiple field regions 39 may gradually increase toward the periphery of the first main surface 20S. In another example, the widths of the multiple field regions 39 may gradually decrease toward the periphery of the first main surface 20S. The depths of the multiple field regions 39 may be equal to each other or different. In one example, the depths of the multiple field regions 39 may gradually increase toward the periphery of the first main surface 20S. In another example, the depths of the multiple field regions 39 may gradually decrease toward the periphery of the first main surface 20S. The spacing of the multiple field regions 39 may be equal to each other or different. In one example, the spacing of the multiple field regions 39 may gradually increase toward the periphery of the first main surface 20S. In another example, the spacing between the multiple field regions 39 may gradually decrease toward the periphery of the first main surface 20S.

[0148] The p-type impurity concentrations in the multiple field regions 39 can be arbitrarily changed and can take various values ​​depending on the electric field to be relaxed. The p-type impurity concentrations in the multiple field regions 39 may be equal to the p-type impurity concentrations in the multiple body regions 23. The p-type impurity concentrations in the multiple field regions 39 may be equal to the p-type impurity concentrations in the outer well region 37. The p-type impurity concentrations in the multiple field regions 39 may be higher or lower than the p-type impurity concentrations in the body region 23. The p-type impurity concentrations in the multiple field regions 39 may be higher or lower than the p-type impurity concentrations in the outer well region 37.

[0149] [Insulating layer and electrodes] Referring to Figures 4 to 14, the insulating layer 40 provided on the first main surface 20S of the chip 20 and the electrodes provided on the insulating layer 40 will be described.

[0150] The insulating layer 40 selectively covers the first main surface 20S of the chip 20. The insulating layer 40 includes a main surface insulating film 41 in contact with the first main surface 20S and an interlayer film 42 provided on the main surface insulating film 41.

[0151] The main surface insulating film 41 selectively covers the first main surface 20S in the active region 11 and the peripheral region 12. The main surface insulating film 41 coats the first main surface 20S in a film-like manner in the active region 11. The main surface insulating film 41 is connected to the insulating film 27 of each gate structure 25. Therefore, the main surface insulating film 41 does not cover the embedded electrode 28. The main surface insulating film 41 covers each of the outer well region 37, the outer contact region 38, and the multiple field regions 39 in the peripheral region 12. The main surface insulating film 41 covers the periphery of the first main surface 20S. The main surface insulating film 41 may be provided with a gap inward from the periphery of the first main surface 20S so as to expose the periphery of the first main surface 20S.

[0152] The thickness of the main surface insulating film 41 can be 10 nm or more and 250 nm or less. The thickness of the main surface insulating film 41 may have a value that falls within at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, 175 nm or more and 200 nm or less, 200 nm or more and 225 nm or more and 250 nm or less.

[0153] The main surface insulating film 41 may contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. In one example, the main surface insulating film 41 may contain silicon oxide including the oxide of the second semiconductor layer 22. In another example, the main surface insulating film 41 may contain silicon oxide including an oxide other than the oxide of the second semiconductor layer 22.

[0154] The interlayer film 42 selectively covers the first main surface 20S via the main surface insulating film 41 in the active region 11 and the peripheral region 12. The interlayer film 42 covers the embedded electrode 28 in the active region 11. Therefore, it can be said that the embedded electrode 28 is embedded in the insulating layer 40. In the peripheral region 12, the interlayer film 42 covers the outer well region 37, the outer contact region 38, and a plurality of field regions 39 via the main surface insulating film 41. The interlayer film 42 covers the periphery of the first main surface 20S. The interlayer film 42 may be provided with a gap inward from the periphery of the first main surface 20S so as to expose the periphery of the first main surface 20S.

[0155] The interlayer film 42 has a thickness greater than the thickness of the main surface insulating film 41. The thickness of the interlayer film 42 can be 0.1 μm or more and 5 μm or less. The thickness of the interlayer film 42 may have a value that falls within at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0156] The interlayer film 42 may be composed of a single insulating film or a laminated structure of multiple insulating films. In the first embodiment, the interlayer film 42 is a laminated structure of multiple insulating films made of different materials. In one example, the interlayer film 42 includes a first insulating film and a second insulating film provided on the first insulating film. The first insulating film contains silicon oxide. In one example, the first insulating film may be USG (Undoped Silicate Glass), that is, an insulating film made of silicon oxide that does not contain either phosphorus or boron. The second insulating film has both boron and phosphorus added to the silicon oxide. In other words, the second insulating film may be BPSG (Boro-Phospho Silicate Glass). In another example, the second insulating film has phosphorus added to the silicon oxide. In other words, the second insulating film may be PSG (Phospho Silicate Glass). Thus, the first insulating film and the second insulating film can be said to be composed of different materials because the elements added to the silicon oxide are different, or no elements are added to the silicon oxide. The interlayer film 42 may be composed of three or more insulating films.

[0157] As shown in Figure 14, the semiconductor device 10 may include at least one gate wiring 43 embedded in the insulating layer 40. The gate wiring 43 is located in the outer peripheral region 12. The gate wiring 43 provides a gate potential to a plurality of gate structures 25. More specifically, the gate wiring 43 is electrically and mechanically connected to the embedded electrodes 28 of the plurality of gate structures 25. The gate wiring 43 may include a lead portion integrated with the embedded electrodes 28. The gate wiring 43 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 43 has the same conductivity type as the embedded electrodes 28.

[0158] The gate wiring 43 is positioned on the main surface insulating film 41 and covered by the interlayer film 42. The gate wiring 43 is selectively routed on the main surface insulating film 41, spaced closer to the multiple gate structures 25 than to the periphery of the first main surface 20S. The gate wiring 43 faces the outer well region 37 across the main surface insulating film 41.

[0159] The gate wiring 43 includes portions that extend along the plurality of gate structures 25. The gate wiring 43 includes portions that extend in a strip shape in the X direction and portions that extend in a strip shape in the Y direction. The gate wiring 43 includes portions that extend so as to intersect (specifically, perpendicular to) the ends of the plurality of gate structures 25 in a plan view. In a plan view, the gate wiring 43 is an endless polygonal ring (e.g., a quadrilateral ring) having four sides parallel to the periphery of the first main surface 20S. In a plan view, the gate wiring 43 surrounds the plurality of gate structures 25 (active regions 11). In one example, the gate wiring 43 may be arc-shaped, with the corner portions that form the four corners of the quadrilateral ring in a plan view curving outward. The inner edge of the gate wiring 43 is positioned closer to the periphery of the first main surface 20S than the outermost source region 35.

[0160] The outer edge of the gate wiring 43 is positioned closer to the gate structure 25 than the multiple field regions 39. This configuration suppresses the blocking of the electric field dispersion path by the gate wiring 43, allowing the electric field (electric field lines) to be appropriately dispersed by the multiple field regions 39.

[0161] The outer edge of the gate wiring 43 is positioned closer to the gate structure 25 than the outer edge of the outer well region 37. The outer edge of the gate wiring 43 is positioned closer to the gate structure 25 than the inner edge of the outer contact region 38.

[0162] The semiconductor device 10 may include a plurality of gate wirings 43. In this case, the plurality of gate wirings 43 may be arranged at both ends of at least a plurality of gate structures 25. In one example, one gate wiring 43 may include a portion that extends in a strip shape in the X direction and intersect (specifically, orthogonally) with one end of the plurality of gate structures 25. The other gate wiring 43 may include a portion that extends in a strip shape in the X direction and intersect (specifically, orthogonally) with the other end of the plurality of gate structures 25. Furthermore, the plurality of gate wirings 43 may include portions that extend in a strip shape in the Y direction.

[0163] As shown in Figures 4 and 5, the insulating layer 40 includes a plurality of source openings 40A that expose the first main surface 20S in the active region 11. Each source opening 40A can also be said to expose the second semiconductor layer 22 in the active region 11. Each source opening 40A exposes a plurality of mesa portions 29 by penetrating both the main surface insulating film 41 and the interlayer film 42. The plurality of source openings 40A are provided in a one-to-one correspondence with the plurality of mesa portions 29. Each source opening 40A extends in the Y direction according to the extending direction of the corresponding mesa portion 29. Both ends of each source opening 40A in the Y direction may include an arc-shaped curved opening end.

[0164] The portion of the insulating layer 40 between adjacent source openings 40A is curved in an arc shape, becoming convex upwards (away from the first main surface 20S and the second main surface 20R). Therefore, each source opening 40A is provided such that the opening width WS (dimension in the X direction, see Figure 16) increases as it moves upwards from the first main surface 20S.

[0165] In the first embodiment, the multiple source openings 40A are provided in a one-to-many correspondence with respect to the corresponding mesa portion 29. In this case, the multiple source openings 40A may be provided at intervals along the extending direction of the corresponding mesa portion 29. Each source opening 40A may be square, rectangular (strip-shaped), circular, etc., in plan view. In the first embodiment, each source opening 40A is strip-shaped in plan view.

[0166] As shown in Figure 14, the insulating layer 40 includes at least one (or more in the first embodiment) gate openings 40B that selectively expose the gate wiring 43 in the outer peripheral region 12. The gate openings 40B expose the gate wiring 43 by penetrating the interlayer film 42 that covers the gate wiring 43.

[0167] Multiple gate openings 40B extend in a strip-like shape along the direction of extension of the gate wiring 43. Multiple gate openings 40B are provided at intervals along the direction of extension of the gate wiring 43. Multiple gate openings 40B may include portions extending in the X direction and portions extending in the Y direction in a plan view. Multiple gate openings 40B may have arc shapes that curve outward, with the corner portions forming the four corners of a rectangular ring in a plan view being convex.

[0168] Furthermore, the shape of the gate opening 40B in plan view is not limited to a strip shape and can be changed as desired. For example, the gate opening 40B may be polygonal or circular in plan view. In this case, the gate opening 40B may be square or hexagonal in plan view.

[0169] The insulating layer 40 includes at least one (one in the first embodiment) outer opening 40C in the outer peripheral region 12 that exposes the outer contact region 38. The outer opening 40C is spaced further towards the periphery of the first main surface 20S than the gate opening 40B. The outer opening 40C penetrates both the main surface insulating film 41 and the interlayer film 42.

[0170] The outer opening 40C has a width less than the width of the outer contact region 38. In a plan view, the outer opening 40C is provided at a distance from both the inner and outer edges of the outer contact region 38. The outer opening 40C may expose the outer well region 37.

[0171] The outer opening 40C extends in a band shape along the extending direction of the outer contact region 38. In a plan view, the outer opening 40C is a polygonal annular shape (a quadrilateral annular shape in the first embodiment) having four sides parallel to the periphery of the first main surface 20S. In a plan view, the outer opening 40C surrounds a plurality of gate structures 25 (active regions 11). In the plurality of outer openings 40C, the corner portions that form the four corners of the quadrilateral annular shape in a plan view may be curved in an arc shape that is convex outward.

[0172] The insulating layer 40 may have a plurality of outer openings 40C. In this case, the plurality of outer openings 40C may be spaced apart along the extending direction of the outer contact region 38. The plurality of outer openings 40C may extend in a strip shape along the extending direction of the outer contact region 38.

[0173] As shown in Figures 4 and 5, the semiconductor device 10 includes a first electrode 50 disposed on a first main surface 20S. The first electrode 50 may include a laminated structure of multiple metal films. In the first embodiment, the first electrode 50 includes a laminated structure of a first metal film 50A, a second metal film 50B, and a third metal film 50C.

[0174] The first metal film 50A is in contact with the interlayer film 42. The first metal film 50A is a titanium (Ti)-based metal film (barrier electrode film). The first metal film 50A contains a titanium film. The second metal film 50B is provided on the first metal film 50A. The second metal film 50B is a titanium-based metal film (barrier electrode film). The second metal film 50B contains a titanium nitride (TiN) film. In one example, the thickness of the second metal film 50B is greater than the thickness of the first metal film 50A.

[0175] The third metal film 50C is provided on the second metal film 50B. The third metal film 50C includes an aluminum-based metal film. The aluminum-based metal film may include at least one of an aluminum film and an aluminum alloy film. In one example, the aluminum-based alloy film may include at least one of an aluminum-silicon (AlSi) alloy film, an aluminum-copper (AlCu) alloy film, and an aluminum-silicon-copper (AlSiCu) alloy film. In one example, the third metal film 50C includes an aluminum-based alloy film. In the first embodiment, the third metal film 50C includes an aluminum-copper film.

[0176] As shown in Figure 1, the first electrode 50 includes a source electrode 51, a source finger electrode 52, a gate electrode 53, and a gate finger electrode 54. The source electrode 51 is provided on an insulating layer 40. That is, the source electrode 51 is positioned on the first main surface 20S via the insulating layer 40. The source electrode 51 includes a main source electrode 51A, a first sub-source electrode 51B, and a second sub-source electrode 51C. In the first embodiment, the main source electrode 51A, the first sub-source electrode 51B, and the second sub-source electrode 51C are integrated.

[0177] The main source electrode 51A constitutes the body of the source electrode 51 by having a relatively large planar area. In a plan view, the main source electrode 51A has a polygonal shape (a quadrilateral shape in the first embodiment) with four sides parallel to the periphery of the first main surface 20S.

[0178] Both the first sub-source electrode 51B and the second sub-source electrode 51C have a planar area less than that of the main source electrode 51A. Each sub-source electrode 51B, 51C is drawn out from the main source electrode 51A in the Y direction. The first sub-source electrode 51B and the second sub-source electrode 51C are spaced apart in the X direction and face each other in the X direction. The planar area of ​​the second sub-source electrode 51C may be equal to that of the first sub-source electrode 51B. Either or both of the first sub-source electrode 51B and the second sub-source electrode 51C may be used as monitor electrodes for current monitoring. The planar areas of each sub-source electrode 51B, 51C can be arbitrarily changed. In one example, the planar area of ​​the first sub-source electrode 51B may be larger or smaller than the planar area of ​​the second sub-source electrode 51C.

[0179] The configuration of the source electrode 51 can be arbitrarily changed. In one example, one of the first sub-source electrode 51B and the second sub-source electrode 51C may be omitted from the source electrode 51. In another example, each of the sub-source electrodes 51B and 51C may be omitted from the source electrode 51.

[0180] As shown in Figures 4 and 5, the source electrode 51 includes an embedded portion that fits into a plurality of source openings 40A and a covering portion that covers the insulating layer 40 (interlayer film 42). The source electrode 51 is electrically connected from a plurality of gate structures 25 by the insulating layer 40 and is also electrically connected to the chip 20 through the plurality of source openings 40A.

[0181] As shown in Figure 14, the peripheral edge of the source electrode 51 may extend from the active region 11 to the outer peripheral region 12 and face a portion of the gate wiring 43 across the interlayer film 42. The peripheral edge of the source electrode 51 may include a portion facing the outer well region 37 across the gate wiring 43 and the main surface insulating film 41. The peripheral edge of the source electrode 51 is spaced further closer to the gate structures 25 than to the field regions 39. The peripheral edge of the source electrode 51 is spaced further closer to the gate structures 25 than to the outer edge of the outer well region 37. The peripheral edge of the source electrode 51 is spaced further closer to the gate structures 25 than to the inner edge of the outer contact region 38. The peripheral edge of the source electrode 51 is spaced further closer to the inner edge of the gate wiring 43 than to the outer edge of the gate wiring 43. The peripheral portion of the source electrode 51 may be positioned closer to the inner edge of the gate wiring 43 than to the middle portion of the gate wiring 43, with a gap between them.

[0182] As shown in Figure 1, the source finger electrode 52 is an electrode drawn out from the source electrode 51 onto the first main surface 20S. The source finger electrode 52 transmits the source potential applied to the source electrode 51 to other regions. The source finger electrode 52 is drawn out from the source electrode 51 onto the portion of the interlayer film 42 that covers the outer contact region 38. The source finger electrode 52 may be integrated with the source electrode 51.

[0183] The source finger electrode 52 is routed in a band shape in the region between the periphery of the first main surface 20S and the source electrode 51 in a plan view. The source finger electrode 52 includes a portion extending in the X direction and a portion extending in the Y direction in a plan view. In the first embodiment, the source finger electrode 52 is a polygonal ring (quadrilateral ring) having four sides parallel to the periphery of the first main surface 20S in a plan view. The source finger electrode 52 surrounds the source electrode 51 in a plan view. In the source finger electrode 52, the corner portions that form the four corners of the quadrilateral ring in a plan view may be curved in an arc shape so as to be convex outward.

[0184] As shown in Figure 14, the source finger electrode 52 enters the outer opening 40C from above the interlayer film 42 and is electrically connected to the outer contact region 38 through the outer opening 40C. The source finger electrode 52 includes an inner edge portion on the inner side of the first main surface 20S and an outer edge portion on the peripheral side of the first main surface 20S. The inner edge portion of the source finger electrode 52 is positioned closer to the periphery of the first main surface 20S than the middle portion of the outer contact region 38. The inner edge portion of the source finger electrode 52 may be positioned on the outer well region 37 or on the outer contact region 38. The outer edge portion of the source finger electrode 52 is drawn out from above the outer contact region 38 towards the periphery of the first main surface 20S and is positioned on the interlayer film 42 in a region closer to the periphery of the first main surface 20S than the outer contact region 38. The outer edge of the source finger electrode 52 is positioned at a distance from the outer edge of the outer well region 37, closer to the interior of the first main surface 20S, and faces the outer well region 37 across the insulating layer 40. Alternatively, the outer edge of the source finger electrode 52 may be positioned closer to the periphery of the first main surface 20S than the outer edge of the outer well region 37, and may face the second semiconductor layer 22 across the insulating layer 40.

[0185] As shown in Figure 1, the gate electrode 53 is positioned at a distance from the source electrode 51 in a plan view. The gate electrode 53 is positioned on the first main surface 20S. The gate electrode 53 is positioned in the region between the first sub-source electrode 51B and the second sub-source electrode 51C, and faces each of the sub-source electrodes 51B and 51C in the X direction.

[0186] The gate electrode 53 has a polygonal shape (a quadrilateral shape in the first embodiment) with four sides parallel to the periphery of the first main surface 20S in a plan view. The gate electrode 53 has a planar area less than the planar area of ​​the source electrode 51. The planar area of ​​the gate electrode 53 is less than the planar area of ​​the main source electrode 51A. The planar area of ​​the gate electrode 53 may also be less than the planar area of ​​the first sub-source electrode 51B (second sub-source electrode 51C).

[0187] Although not shown in the figures, the gate electrode 53 faces the outer well region 37 across the insulating layer 40. In the first embodiment, the gate electrode 53 is positioned at a distance from the ends of the multiple gate structures 25 in a plan view. That is, the gate electrode 53 does not face the multiple gate structures 25 in the Z direction. The gate electrode 53 may include a portion that faces a part of the gate structure 25 across the insulating layer 40.

[0188] The gate finger electrode 54 is drawn out from the gate electrode 53 onto the first main surface 20S and transmits the gate potential applied to the gate electrode 53 to other regions. The gate finger electrode 54 is drawn out onto the portion of the interlayer film 42 that covers the gate wiring 43. In a plan view, the gate finger electrode 54 extends in a strip shape in the region between the periphery of the first main surface 20S and the source electrode 51. More specifically, in a plan view, the gate finger electrode 54 extends in a strip shape in the region between the source electrode 51 and the source finger electrode 52. The gate finger electrode 54 is integrated with the gate electrode 53.

[0189] The gate finger electrode 54 includes a portion extending in a band shape in the X direction and a portion extending in a band shape in the Y direction in a plan view. In the first embodiment, the gate finger electrode 54 is a band with ends having four sides parallel to the periphery of the first main surface 20S in a plan view. The gate finger electrode 54 surrounds the source electrode 51 in a plan view. In a plan view, the gate finger electrode 54 is positioned closer to the periphery of the first main surface 20S than the ends of the plurality of gate structures 25. In the gate finger electrode 54, the corner portions that form the four corners of a rectangular ring in a plan view may be arc-shaped, curving outward.

[0190] As shown in Figure 14, the gate finger electrode 54 enters a plurality of gate openings 40B from above the interlayer film 42 and is mechanically and electrically connected to the gate wiring 43 through each gate opening 40B. As a result, the gate finger electrode 54 transmits the gate potential applied to the gate electrode 53 to the plurality of gate structures 25.

[0191] The gate finger electrode 54 includes an inner edge portion on the inner side of the first main surface 20S and an outer edge portion on the peripheral side of the first main surface 20S. The inner edge portion of the gate finger electrode 54 is positioned closer to the periphery of the first main surface 20S than the ends of the plurality of gate structures 25. In other words, the gate finger electrode 54 does not face the plurality of gate structures 25 in the Z direction. The inner edge portion of the gate finger electrode 54 is positioned on the gate wiring 43 and faces the periphery of the source electrode 51 in the horizontal direction. The outer edge portion of the gate finger electrode 54 is drawn out from above the gate wiring 43 towards the periphery of the first main surface 20S and is positioned on the interlayer film 42 in a region closer to the periphery of the first main surface 20S than the gate wiring 43. In other words, the outer edge portion of the gate finger electrode 54 does not face the gate wiring 43 in the Z direction. The outer edge of the gate finger electrode 54 is positioned at a distance from the innermost field region 39, closer to the interior of the first main surface 20S. The outer edge of the gate finger electrode 54 is positioned at a distance from the outer edge of the outer well region 37, closer to the interior of the first main surface 20S, and faces the outer well region 37 across the insulating layer 40. Alternatively, the outer edge of the gate finger electrode 54 may be positioned closer to the periphery of the first main surface 20S than the outer edge of the outer well region 37, and may face the second semiconductor layer 22 across the insulating layer 40.

[0192] As shown in Figure 1, the semiconductor device 10 includes an uppermost film 44 that selectively covers the first main surface 20S. In Figure 1, the uppermost film 44 is indicated by dots. The uppermost film 44 includes portions that selectively cover the source electrode 51, portions that selectively cover the source finger electrode 52, portions that selectively cover the gate electrode 53, portions that selectively cover the gate finger electrode 54, and portions that selectively cover the interlayer film 42. In the first embodiment, the uppermost film 44 covers the entire area of ​​the source finger electrode 52 and the entire area of ​​the gate finger electrode 54.

[0193] The uppermost film 44 includes the source inner edge on the source electrode 51 side, the gate inner edge on the gate electrode 53 side, and the outer edge on the peripheral side of the first main surface 20S. The source inner edge covers the peripheral and inner portions of the source electrode 51, while defining one or more (multiple in the first embodiment) source pad openings 44A that selectively expose the source electrode 51.

[0194] The multiple source pad openings 44A include a first source pad opening 44AA that selectively exposes the main source electrode 51A, a second source pad opening 44AB that selectively exposes the first sub-source electrode 51B, and a third source pad opening 44AC that selectively exposes the second sub-source electrode 51C. Each of the first to third source pad openings 44AA to 44AC is partitioned into a rectangular shape in plan view. Each of the second source pad opening 44AB and the third source pad opening 44AC has a planar area smaller than that of the first source pad opening 44AA.

[0195] The inner edge of the gate covers the peripheral edge of the gate electrode 53 and defines a gate pad opening 44B that selectively exposes the inner portion of the gate electrode 53. The gate pad opening 44B is divided into a rectangular shape in plan view. The gate pad opening 44B has a planar area smaller than the planar area of ​​the first source pad opening 44AA. The planar area of ​​the gate pad opening 44B may be larger or smaller than the planar area of ​​the second source pad opening 44AB (third source pad opening 44AC).

[0196] As shown in Figure 14, the outer edge of the top layer 44 is positioned on the interlayer 42 with a gap from the periphery of the first main surface 20S. In other words, the outer edge of the top layer 44 exposes the periphery of the interlayer 42. The top layer 44 faces multiple field regions 39 across the insulating layer 40.

[0197] The top layer 44 has a laminated structure including an inorganic film 45 and an organic film 46 stacked in this order. The configuration of the top layer 44 can be arbitrarily changed. In one example, the top layer 44 may be a single layer structure composed of an inorganic film 45. In another example, the top layer 44 may be a single layer structure composed of an organic film 46.

[0198] Both the inorganic film 45 and the organic film 46 include portions that selectively cover the source electrode 51, the source finger electrode 52, the gate electrode 53, the gate finger electrode 54, and the interlayer film 42. In the first embodiment, the inorganic film 45 covers the entire area of ​​the source finger electrode 52 and the entire area of ​​the gate finger electrode 54.

[0199] The inorganic film 45 is in contact with the source electrode 51, the source finger electrode 52, the gate electrode 53, the gate finger electrode 54, and the interlayer film 42. The inorganic film 45 may contain at least one of silicon oxide, silicon nitride, and silicon oxynitride. The inorganic film 45 may contain an insulating material different from the insulating material of the interlayer film 42. The inorganic film 45 may have a thickness less than the thickness of the first electrode 50.

[0200] The thickness of the inorganic film 45 can be greater than 0 μm and 2 μm or less. The thickness of the inorganic film 45 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, and 1.5 μm or more and 2 μm or less.

[0201] The organic film 46 is provided on the inorganic film 45. The organic film 46 may contain a transparent resin or a light-transmitting resin. The organic film 46 may contain a negative-type or positive-type photosensitive resin. The organic film 46 may contain at least one of polyimide, polyamide, and polybenzoxazole.

[0202] The thickness of the organic film 46 is greater than the thickness of the inorganic film 45. The thickness of the organic film 46 can be 1 μm or more and 25 μm or less. The thickness of the organic film 46 may have a value that falls within at least one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, and 20 μm or more and 25 μm or less.

[0203] As shown in Figure 2, the semiconductor device 10 includes a drain electrode 55 as a second electrode provided on the second main surface 20R. The drain electrode 55 may cover the entire area of ​​the second main surface 20R. The coverage area of ​​the drain electrode 55 can be arbitrarily changed. In one example, the drain electrode 55 may cover the second main surface 20R with a gap from the periphery of the second main surface 20R. In this case, the periphery of the second main surface 20R is exposed.

[0204] The drain electrode 55 has a single-layer or multilayer structure comprising at least one of the following: an aluminum-based metal film, a copper-based metal film, a titanium-based metal film, a nickel (Ni)-based metal film, a palladium (Pd)-based metal film, a gold (Au)-based metal film, and a silver (Ag)-based metal film. The aluminum-based metal film may comprise at least one of an aluminum film and an aluminum alloy film. In one example, the aluminum-based metal film may comprise at least one of an aluminum-silicon alloy film, an aluminum-copper alloy film, and an aluminum-silicon-copper alloy film. The titanium-based alloy film may comprise at least one of a titanium film and a titanium alloy film. The nickel-based alloy film may comprise at least one of a nickel film and a nickel alloy film. The palladium-based alloy film may comprise at least one of a palladium film and a palladium alloy film. The gold-based alloy film may comprise at least one of a gold film and a gold alloy film. The silver-based alloy film may comprise at least one of a silver film and a silver alloy film.

[0205] If the drain electrode 55 has a layered metal film structure, at least two of the following are provided on the second main surface 20R in any order and combination: an aluminum-based metal film, a copper-based metal film, a titanium-based metal film, a nickel-based metal film, a palladium-based metal film, a gold-based metal film, and a silver-based metal film. In one example, the drain electrode 55 may have a layered structure including an aluminum-based metal film, a titanium-based metal film, a nickel-based metal film, a palladium-based metal film, a gold-based metal film, and a silver-based metal film, layered in this order from the second main surface 20R side.

[0206] Referring to Figures 4 and 5, the semiconductor device 10 includes a contact portion 60 that is mechanically and electrically connected to both the source electrode 51 and the second semiconductor layer 22, and a contact region 65 that is in contact with the contact portion 60.

[0207] The contact portion 60 is provided in each of the multiple source openings 40A. The contact portion 60 is positioned to be exposed from the corresponding source opening 40A in a plan view. The contact portion 60 penetrates the source region 35 in the Z direction. The contact portion 60 is made of, for example, silicide. The contact portion 60 is made of a different material from, for example, the source electrode 51 (first electrode 50). In one example, the contact portion 60 may include at least one of nickel, titanium, molybdenum (Mo), tantalum (Ta), tungsten (W), and vanadium (V). In the first embodiment, the contact portion 60 includes nickel. That is, the contact portion 60 is made of nickel silicide.

[0208] The contact region 65 is provided at a distance from the first main surface 20S in the Z direction. More specifically, the contact region 65 is provided at a distance closer to the second semiconductor layer 22 than the first main surface 20S in the Z direction. The contact region 65 is provided within the second semiconductor layer 22. The contact region 65 is provided at a distance closer to the first main surface 20S than the bottom of the body region 23. The p-type impurity concentration in the contact region 65 is higher than the p-type impurity concentration in the body region 23. The p-type impurity concentration in the contact region 65 may be higher than the p-type impurity concentration in the well region 30. The p-type impurity concentration in the contact region 65 may be higher than the n-type impurity concentration in the source region 35. The detailed configuration of the contact portion 60 and the contact region 65 will be described later.

[0209] The breakdown voltage that can be applied between the source electrode 51 and the drain electrode 55 (between the first main surface 20S and the second main surface 20R) can be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1650V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or less, 2250V or more and 2500V or less, 2500V or more and 2750V or more and 3000V or less.

[0210] [Contact portion and contact area] The detailed configuration of the contact portion 60 and the contact area 65 will be described with reference to Figures 15 to 19.

[0211] Figure 15 schematically shows the planar structure of a part of the active region 11 with the contact portion 60 added to Figure 3. Figure 16 schematically shows an enlarged cross-sectional structure of a part of Figure 4. Figure 17 schematically shows an enlarged cross-sectional structure of one contact portion 60 and its surroundings in Figure 16. Figure 18 schematically shows the cross-sectional structure of the semiconductor device 10 cut along the line F18-F18 in Figure 15. Figure 19 schematically shows an enlarged cross-sectional structure of the end of the contact portion 60 and its surroundings in Figure 18.

[0212] (Planar structure of the contact portion and contact area) The planar structure of the contact portion 60 and the contact area 65 will be described with reference to Figures 3 and 15.

[0213] As shown in Figure 15, multiple contact portions 60 are provided spaced apart from each other in a direction (X direction) that intersects (specifically orthogonal to) the extending direction of the gate structure 25 in a plan view. Each contact portion 60 is provided between multiple trenches 26 in the X direction. Each of the multiple contact portions 60 is provided in the region (mesa portion 29) between the multiple gate structures 25.

[0214] The contact portion 60 extends in a strip shape along the extending direction (X direction) of the gate structure 25. Multiple contact portions 60 are provided at intervals in the X direction. In the first embodiment, the length of the contact portion 60 in the extending direction is greater than the width of the gate structure 25. The length of the contact portion 60 is greater than the spacing of the gate structure 25. The length of the contact portion 60 is greater than the distance between adjacent contact portions 60 in the X direction (length LR of the inter-contact region 66 in the X direction). The length of the contact portion 60 is greater than the width WC of the contact portion 60 (see Figure 17). The length of the contact portion 60 is greater than the thickness TC of the contact portion 60 (see Figure 17). The length of the contact portion 60 is less than the length of the gate structure 25 in the extending direction. The contact portion 60 extends so as to span both the first pillar region 31 and the second pillar region 32. In one example, the contact portion 60 extends across a plurality of first pillar regions 31 and a plurality of second pillar regions 32.

[0215] As shown in Figures 3 and 15, multiple contact regions 65 are provided spaced apart from each other in a direction (X direction) that intersects (specifically orthogonal to) the extending direction of the gate structure 25 in a plan view. Each contact region 65 is provided between multiple trenches 26 in the X direction. Each of the multiple contact regions 65 is provided in the region (mesa portion 29) between the multiple gate structures 25. Each of the multiple contact regions 65 is provided in a one-to-one correspondence with each of the multiple mesa portions 29.

[0216] The contact region 65 extends in a strip shape along the extending direction (X direction) of the gate structure 25. The length of the contact region 65 in the extending direction is greater than the length of the contact portion 60. In one example, the length of the contact region 65 may be equal to the length of the gate structure 25 in the extending direction. In another example, the length of the contact region 65 may be less than the length of the gate structure 25 in the extending direction.

[0217] (Cross-sectional structure of the contact portion and its surroundings) Next, the detailed configuration of the contact portion 60 and its surroundings will be described with reference to Figures 16 to 18.

[0218] As shown in Figure 16, the contact portion 60 includes a contact body 61 provided inside the tip 20 and a projection 62 provided on the first main surface 20S of the tip 20. The contact body 61 and the projection 62 are integrated. Thus, it can be said that the contact portion 60 penetrates the first main surface 20S.

[0219] The contact body 61 is provided such that, in the Y direction, its width WS is greater than the opening width WS of the source opening 40A that corresponds to the first main surface 20S. In other words, the contact body 61 includes a bulge portion 63 that bulges out closer to the gate structure 25 than the source opening 40A. The bulge portion 63 is provided on both sides of the source opening 40A in the Y direction. Thus, the width WC of the contact portion 60 is greater than the opening width WS of the source opening 40A.

[0220] The bulge portion 63 is in contact with the lower surface of the main surface insulating film 41. The bulge portion 63 is spaced apart from adjacent gate structures 25 in the Y direction. A source region 35 is provided between the bulge portion 63 and the gate structure 25 in the Y direction. In other words, the source region 35 is located outward (closer to the gate structure 25) than the source opening 40A in a plan view. The source region 35 is in contact with both the bulge portion 63 and the gate structure 25 (insulating film 27). The thickness TS of the source region 35 is at least half the opening width WS of the source opening 40A. The thickness TS of the source region 35 is about two-thirds the opening width WS of the source opening 40A. The thickness TS of the source region 35 may be less than or equal to the width WE of the source region 35. The maximum value of the thickness TS of the source region 35 may be greater than the minimum value of the width WE of the source region 35. Here, the maximum value of the thickness TS of the source region 35 is the thickness at the position in the Y direction of the source region 35 that is in contact with the gate structure 25. The minimum value of the width WE of the source region 35 is the width of the source region 35 that is exposed to the first main surface 20S.

[0221] As shown in Figure 17, the bulge width WA of the bulge portion 63 is smaller than the opening width WS of the source opening 40A. The bulge width WA is smaller than the thickness TB of the contact body 61. The bulge width WA is smaller than the thickness TP of the projection portion 62. The bulge width WA is smaller than the width WE of the source region 35. The bulge width WA is smaller than the thickness TS of the source region 35. Here, the bulge width WA can be defined by the distance in the Y direction between the periphery of the first main surface 20S of the source opening 40A and the tip of the bulge portion 63 in the Y direction. The thickness TB of the contact body 61 can be defined by the distance in the Z direction between the first main surface 20S and the bottom surface 61B of the contact body 61, which will be described later. The thickness TP of the projection portion 62 can be defined by the distance in the Z direction between the first main surface 20S and the upper surface 62A of the projection portion 62.

[0222] The contact body 61 includes a side surface 61A, a bottom surface 61B, and a corner portion 61C. The corner portion 61C is provided between the side surface 61A and the bottom surface 61B and connects the bottom surface 61B and the side surface 61A. The corner portion 61C is curved and convex outward.

[0223] The bottom surface 61B is located closer to the first main surface 20S than the bottom of the body region 23. In one example, the bottom surface 61B may be located closer to the first main surface 20S than the bottom of the source region 35. In the example shown in Figure 17, the bottom surface 61B is located closer to the bottom wall of the gate structure 25 (see Figure 16) than the bottom of the source region 35 closer to the contact body 61. The bottom surface 61B is located closer to the first main surface 20S than the bottom of the source region 35 closer to the gate structure 25. In the first embodiment, the bottom surface 61B is a flat surface perpendicular to the Z direction.

[0224] As shown in Figure 17, the side surface 61A constitutes a bulge 63. The side surface 61A is connected to the insulating film 27 of the gate structure 25 at the first main surface 20S. The side surfaces 61A of the contact body 61 (contact portion 60) are tapered in shape, inclined to move away from each other from the corner portion 61C toward the first main surface 20S. Each side surface 61A is inclined to move closer to the opposing gate structure 25 as it moves from the corresponding corner portion 61C toward the first main surface 20S. In one example, each side surface 61A is positioned closer to the gate structure 25 than the portion of the source opening 40A corresponding to the first main surface 20S in a plan view. Each side surface 61A is in contact with the source region 35. The source region 35 may be in contact with a part of the corner portion 61C.

[0225] The protrusion 62 extends upward from the first main surface 20S. The protrusion 62 is in contact with the insulating side surface 40AA that constitutes the source opening 40A of the insulating layer 40. The protrusion 62 is in contact with both the main surface insulating film 41 and the interlayer film 42.

[0226] The protruding portion 62 includes an upper surface 62A, a side surface 62B, and a corner portion 62C provided between the upper surface 62A and the side surface 62B. The upper surface 62A includes, for example, a flat surface perpendicular to the Z direction. The side surface 62B includes, for example, a plane along the Z direction. The corner portion 62C is curved and convex outward. The corner portion 62C is located, for example, above the main surface insulating film 41, that is, on the opposite side of the first main surface 20S from the main surface insulating film 41 in the Z direction. Therefore, the thickness TP of the protruding portion 62 is greater than the thickness of the main surface insulating film 41. Both the upper surface 62A and the corner portion 62C of the protruding portion 62 are in contact with the source electrode 51. The protruding portion 62 can be said to be in contact with the first metal film 50A.

[0227] The thickness TC of the contact portion 60 may be greater than or equal to the width WC of the contact portion 60. The width WC of the contact portion 60 may be greater than the thickness TB of the contact body 61, i.e., the distance in the Z direction between the first main surface 20S and the bottom surface 61B of the contact body 61. The thickness TB of the contact body 61 is greater than the thickness TP of the protruding portion 62. The thickness TB of the contact body 61 may be less than the width WC of the contact portion 60. The thickness TB of the contact body 61 can be 0.01 μm or more and 0.5 μm or less. The thickness TP of the protruding portion 62 can be 0.01 μm or more and 0.5 μm or less. The thickness TC of the contact portion 60 can be 0.02 μm or more and 1.0 μm or less. Note that the thickness TC of the contact portion 60 is not limited to the above range and may be 0.01 μm or more and 0.5 μm or less.

[0228] The contact area 65 is in contact with both the bottom surface 61B and the corner portion 61C of the contact body 61. The contact area 65 is provided in the body area 23. The contact area 65 is in contact with the source area 35. The contact area 65 is in contact with the entire bottom surface 61B. The width WD of the contact area 65 is greater than the opening width WS of the source opening 40A. In one example, the width WD of the contact area 65 is smaller than the width WC of the contact portion 60. For this reason, the outer edge of the contact area 65 is provided in a position that overlaps with the bulge portion 63 in a plan view. As shown in Figure 16, the contact area 65 includes a portion of the gate structure 25 closer to the bottom wall than the source area 35. The contact area 65 is provided closer to the first main surface 20S than the cap area 36. The width WD of the contact area 65 is greater than the width (dimension in the Y direction) of one source area 35 adjacent to the contact area 65.

[0229] (Cross-sectional structure of the inter-contact region and its surrounding area) The cross-sectional structure of the inter-contact region 66 and the contact portion 60 and source electrode 51 corresponding to the inter-contact region 66 will be described with reference to Figures 18 and 19.

[0230] As shown in Figure 18, the source electrode 51 is inserted into the intercontact region 66 between adjacent contact portions 60 in the X direction. Therefore, the source electrode 51 is in contact with the first main surface 20S of the tip 20. Here, the source region 35 is exposed in the intercontact region 66. Thus, the source electrode 51 is mechanically and electrically connected to the source region 35. The source electrode 51 is in contact with the side surfaces 62B of the protrusions 62 of both adjacent contact portions 60 in the X direction. As a result, the movement of the source electrode 51 in the X direction relative to the contact portions 60 is restricted.

[0231] The inter-contact region 66 may be provided, for example, in the first pillar region 31. The length LR of the inter-contact region 66 in the X direction may be smaller than the length of the first pillar region 31 in the X direction. The length LR of the inter-contact region 66 may be smaller than the length of the second pillar region 32 in the X direction.

[0232] The position of the inter-contact region 66 can be arbitrarily changed. In one example, the inter-contact region 66 may be provided in the second pillar region 32. In another example, the inter-contact region 66 may be provided so as to straddle the boundary between the first pillar region 31 and the second pillar region 32. The length LR of the inter-contact region 66 can also be arbitrarily changed. In one example, the inter-contact region 66 may be greater than or equal to the length of the first pillar region 31 in the X direction. In another example, the inter-contact region 66 may be greater than or equal to the length of the second pillar region 32 in the X direction. In another example, the inter-contact region 66 may extend so as to straddle both the first pillar region 31 and the second pillar region 32.

[0233] As shown in Figure 19, the X-direction end 64 of the contact portion 60 includes an end bulge 64A that bulges in the X direction. The end bulge 64A is provided within the second semiconductor layer 22. The end bulge 64A includes an upper surface exposed from the first main surface 20S. The end bulge 64A is in contact with the source electrode 51 on the first main surface 20S. The end bulge 64A includes a side surface 64AA and a corner portion 64AB. The corner portion 64AB is provided between the bottom surface 61B and the side surface 64AA of the contact body 61 and connects the bottom surface 61B and the side surface 64AA.

[0234] The side surface 64AA is inclined away from the contact body 61 as it moves from the corner portion 64AB toward the first main surface 20S. The side surface 64AA is in contact with the source region 35. The corner portion 64AB is curved and convex outward. The corner portion 64AB is in contact with the source region 35. The source electrode 51 (first metal film 50A) is in contact with the end face 64B in the X direction of the end portion 64 and the upper surface 64AC of the end bulge portion 64A. Here, the end face 64B is formed by the side surface 62B of the protruding portion 62. The corner portion 64AB may also be in contact with the contact region 65.

[0235] [Contact portion in the outer peripheral region] As shown in Figure 14, the outer peripheral region 12 is provided with an outer contact portion 67 that is mechanically and electrically connected to both the source finger electrode 52 and the second semiconductor layer 22. The outer contact portion 67 is provided in the outer opening 40C. In a plan view, the outer contact portion 67 is provided so as to be exposed from the outer opening 40C. The outer contact portion 67 is made of, for example, silicide. The outer contact portion 67 is made of a different material than, for example, the source finger electrode 52 (first electrode 50). In one example, the outer contact portion 67 may contain at least one of nickel, titanium, molybdenum, tantalum, tungsten, and vanadium. In the first embodiment, the outer contact portion 67 contains nickel. That is, the outer contact portion 67 is made of nickel silicide. Therefore, in the first embodiment, it can be said that the outer contact portion 67 is made of the same material as the contact portion 60.

[0236] The outer contact portion 67 is in contact with the outer contact region 38. As shown in Figure 14, the outer contact portion 67 has the same shape as the contact portion 60 in a cross-sectional view obtained by cutting the outer contact portion 67 in the YZ plane. In one example, the size of the outer contact portion 67 may be larger than that of the contact portion 60. In another example, the size of the outer contact portion 67 may be the same as that of the contact portion 60.

[0237] [Method for Manufacturing a Semiconductor Device] An example of a method for manufacturing the semiconductor device 10 of the first embodiment will be described with reference to Figures 20 to 27.

[0238] As shown in Figure 20, the method for manufacturing the semiconductor device 10 includes preparing a wafer 800. The wafer 800 is the substrate for the first semiconductor layer 21 (see Figure 2) and contains a SiC single crystal. The wafer 800 includes a first wafer main surface (not shown) and a second wafer main surface (not shown) opposite to the first wafer main surface. The first and second wafer main surfaces are formed by the c-planes of the SiC single crystal. The first wafer main surface is formed by the silicon plane of the SiC single crystal, and the second wafer main surface is formed by the carbon plane of the SiC single crystal.

[0239] Next, the method for manufacturing the semiconductor device 10 includes forming a second semiconductor layer 22. The second semiconductor layer 22 is formed by epitaxial growth of the wafer 800. This forms a first main surface 20S as the surface of the second semiconductor layer 22.

[0240] Next, the manufacturing method of the semiconductor device 10 includes forming a body region 23. In this step, a p-type impurity is introduced throughout the second semiconductor layer 22. As a result, a body region 23 is formed throughout the surface layer of the second semiconductor layer 22.

[0241] Next, the manufacturing method of the semiconductor device 10 includes forming a source region 35. In this step, an n-type impurity is introduced into the second semiconductor layer 22 (the surface layer of the body region 23). As a result, the source region 35 is formed on the surface layer of the body region 23.

[0242] Next, the manufacturing method of the semiconductor device 10 includes forming a contact region 65. In this step, p-type impurities are selectively introduced into the surface layer of the body region 23 (the boundary between the body region 23 and the source region 35). As a result, a contact region 65 is formed at the boundary between the body region 23 and the source region 35.

[0243] As shown in Figure 21, the manufacturing method of the semiconductor device 10 includes forming a plurality of trenches 26. In this step, unnecessary portions of the second semiconductor layer 22 are removed by an etching method using a mask (not shown) of a predetermined pattern. The etching method may be either a wet etching method or a dry etching method, or both. The etching method may be a Reactive Ion Etching (RIE) method. As a result, a plurality of trenches 26 are formed on the surface of the second semiconductor layer 22, and mesa portions 29 are formed between adjacent trenches 26.

[0244] As shown in Figure 22, the manufacturing method of the semiconductor device 10 includes forming a cap region 36. In this step, n-type impurities are selectively introduced into the second semiconductor layer 22 through each trench 26. As a result, a cap region 36 is formed at the bottom of the body region 23.

[0245] Next, the manufacturing method of the semiconductor device 10 includes forming well regions 30. In this step, p-type impurities are selectively introduced into the second semiconductor layer 22 through a mask (not shown) while the first main surface 20S is covered with the mask. As a result, well regions 30 are formed at the bottom of each trench 26.

[0246] As shown in Figure 23, the method for manufacturing the semiconductor device 10 includes forming an insulating film 27. The insulating film 27 may be formed by either a CVD (Chemical Vapor Deposition) method or an oxidation treatment method, or both. In one example, the insulating film 27 is formed by the CVD method. The insulating film 27 is formed in a film-like manner on the walls of each trench 26 and also over the entire area of ​​the first main surface 20S. That is, a main surface insulating film 41 is formed on the first main surface 20S. The wafer 800 may be subjected to thermal oxidation treatment after the formation of the insulating film 27.

[0247] Next, the manufacturing method of the semiconductor device 10 includes forming an embedded electrode 28. In this step, conductive polysilicon is embedded by CVD, and then any unnecessary portions of the conductive polysilicon are removed by etching. This forms a trench-type gate structure 25.

[0248] Next, the manufacturing method of the semiconductor device 10 includes the formation of an interlayer film 42. In this step, an insulating material film is laminated on the first main surface 20S by CVD, and then any unnecessary portions of the insulating material film are removed by etching. The CVD method may be, for example, LPTEOS (Low Pressure Tetra Ethyl Ortho Silicate). At this time, openings corresponding to the source opening 40A, etc., are formed in the insulating material film. Subsequently, an annealing treatment is performed to form a first insulating film that is curved so as to be convex upward. Subsequently, an insulating material film is laminated on the first insulating film and the first main surface 20S by CVD, and then any unnecessary portions of the insulating material film are removed by etching. The CVD method may be, for example, LPTEOS. This forms the interlayer film 42. In other words, an insulating layer 40 including openings such as the source opening 40A is formed.

[0249] As shown in Figures 24 to 26, the manufacturing method of the semiconductor device 10 includes forming a contact portion 60. In this step, as shown in Figure 24, a metal film 810 is first formed on the interlayer film 42 and the first main surface 20S by sputtering. The metal film 810 contains at least one of nickel, titanium, molybdenum, tantalum, tungsten, and vanadium. In the first embodiment, the metal film 810 contains nickel. The thickness of the metal film 810 is, for example, greater than the thickness of the main surface insulating film 41 of the insulating layer 40. The thickness of the metal film 810 can be 0.01 μm or more and 0.5 μm or less. Subsequently, as shown in Figure 25, a first heat treatment (sintering) is performed. As a result, the metal film 810 is diffused into the second semiconductor layer 22 through the first main surface 20S. As a result, a contact body 61 is formed in the second semiconductor layer 22. As a result, the contact body 61 penetrates the source region 35 and contacts the contact region 65. Next, as shown in Figure 26, the unwanted portion of the metal film 810 is removed by etching. This forms the protruding portion 62. Finally, a second heat treatment (sintering) is performed. In this way, the contact portion 60 is made of nickel silicide.

[0250] As shown in Figure 27, the method for manufacturing the semiconductor device 10 includes forming a first electrode 50 including a source electrode 51. This step includes forming a first metal film 50A, a second metal film 50B, and a third metal film 50C.

[0251] In forming the first metal film 50A, for example, by sputtering, the first metal film 50A is formed on the insulating layer 40 and the contact portion 60. The first metal film 50A contains, for example, titanium. Subsequently, in forming the second metal film 50B, for example, by sputtering, the second metal film 50B is formed on the first metal film 50A. The second metal film 50B contains, for example, titanium nitride. Subsequently, in forming the third metal film 50C, for example, the third metal film 50C is formed on the second metal film 50B by sputtering. The third metal film 50C contains aluminum copper.

[0252] Although not shown in the figures, the manufacturing method of the semiconductor device 10 includes forming a drain electrode 55, forming a top layer 44, and framing. In forming the drain electrode 55, for example, the drain electrode 55 is formed on the second main surface 20R by a sputtering method. In forming the top layer 44, first, an inorganic film 45 is formed on the insulating layer 40 and the first electrode 50 by either a thermal oxidation method or a CVD method, or both. Subsequently, an organic film 46 is formed by, for example, coating a photosensitive organic film on the inorganic film 45. Subsequently, the organic film 46 and the inorganic film 45 are selectively removed by an etching method. In framing, for example, the wafer 800 is cut into units of semiconductor device 10 using a dicing blade. Through these steps, the semiconductor device 10 is manufactured.

[0253] [Operation of the First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to Figures 17 and 28. Figure 28 schematically shows an enlarged cross-sectional structure of the contact portion 60X and its surroundings of the semiconductor device 10X of the comparative example.

[0254] As shown in Figure 28, the semiconductor device 10X of the comparative example differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the contact portion 60X, the source region 35X, and the contact region 65X. In the following, with respect to the semiconductor device 10X, components common to the semiconductor device 10 of the first embodiment are denoted by the same reference numerals, and their descriptions are omitted.

[0255] More specifically, the contact portion 60X is in contact with the first main surface 20S. In other words, the contact portion 60X does not penetrate the first main surface 20S. As a result, both the source region 35X and the contact region 65X are exposed from the first main surface 20S through the source opening 40A. The contact portion 60X is in contact with the source region 35X and the contact region 65X on the first main surface 20S.

[0256] Incidentally, in order to reduce the on-resistance of a semiconductor device, the transistor structure Tr in the active region 11 is sometimes miniaturized. As a result of this miniaturization, the region between adjacent gate structures 25 (mesa region 29) becomes smaller. Due to the reduction in this region, the opening width WS of the source opening 40A becomes smaller. In the semiconductor device 10X, the exposed area of ​​the source region 35X becomes smaller as the opening width of the source opening 40A becomes smaller. As a result, the contact area between the source region 35X and the contact portion 60X becomes smaller, and the contact resistance increases. Consequently, the on-resistance of the semiconductor device 10X increases.

[0257] In this regard, in the semiconductor device 10 of the first embodiment, the contact portion 60 penetrates the source region 35. As a result, the contact portion 60 contacts the source region 35 within the chip 20, rather than on the first main surface 20S exposed from the source opening 40A. In addition, the side surface 61A of the contact portion 60 (contact body 61) contacts the source region 35. As a result, the contact area between the contact portion 60 and the source region 35 is less dependent on the opening width WS of the source opening 40A. In other words, it is less dependent on the area of ​​the source region 35X exposed from the source opening 40A. As a result, even if the opening width WS of the source opening 40A becomes smaller due to the miniaturization of the transistor structure Tr, the contact area between the contact portion 60 and the source region 35 can be secured, and the increase in contact resistance can be suppressed. Therefore, the on-resistance of the semiconductor device 10 can be reduced.

[0258] [Effects of the First Embodiment] The semiconductor device 10 of the first embodiment provides the following effects. (1-1) The semiconductor device 10 includes a second semiconductor layer 22 including a first main surface 20S, a body region 23 provided on the surface of the second semiconductor layer 22, a source region 35 provided on the surface of the body region 23, an insulating layer 40 having a main surface insulating film 41 covering the first main surface 20S and a source opening 40A that exposes the second semiconductor layer 22, a source electrode 51 provided on the insulating layer 40, and a contact portion 60 provided so as to be exposed from the source opening 40A in a plan view and in contact with both the source electrode 51 and the source region 35. The contact portion 60 penetrates the source region 35.

[0259] In this configuration, the contact portion 60 penetrates the source region 35, causing the side surface 61A of the contact portion 60 to contact the source region 35. Therefore, even if the opening width WS of the source opening 40A becomes smaller due to miniaturization, the contact area between the contact portion 60 and the source region 35 can be secured. This suppresses an increase in contact resistance between the contact portion 60 and the source region 35. Consequently, the on-resistance of the semiconductor device 10 can be reduced.

[0260] (1-2) The contact portion 60 is made of silicide. With this configuration, the process of forming the contact portion 60 can be simplified compared to a configuration in which a trench for providing the contact portion 60 is formed in the second semiconductor layer 22 and then a metal layer is embedded in the trench. In addition, there is a possibility that the source opening 40A and the trench may be misaligned. In this respect, when the contact portion 60 is made of silicide, no misalignment with the source opening 40A occurs, so the contact portion 60 can be formed without aligning the contact portion 60 with respect to the source opening 40A.

[0261] (1-3) The width WC of the contact portion 60 is greater than the opening width WS of the source opening 40A. With this configuration, the contact portion 60 in the second semiconductor layer 22 is more likely to come into contact with the source region 35. This makes it easier to secure a contact area between the contact portion 60 and the source region 35.

[0262] (1-4) The source region 35 is located outward from the source aperture 40A in a plan view. When the source region is exposed from the first main surface through the source aperture, the precision of the formation position of the source region relative to the source aperture needs to be increased as the transistor structure becomes smaller. In this respect, in the semiconductor device 10 of the first embodiment, the side surface 61A of the contact portion 60 is in contact with the source region 35, that is, the source region 35 does not need to be exposed from the first main surface 20S through the source aperture 40A, so it is possible to suppress the need to make the precision of the formation position of the source region 35 excessively high.

[0263] (1-5) The thickness TC of the contact portion 60 is greater than or equal to the width WC of the contact portion 60. This configuration makes it easier to secure the contact area between the contact portion 60 and the source region 35.

[0264] (1-6) The width WC of the contact portion 60 is greater than the distance between the first main surface 20S of the second semiconductor layer 22 and the bottom surface 61B of the contact portion 60. With this configuration, the contact portion 60 in the second semiconductor layer 22 is more likely to come into contact with the source region 35. This makes it easier to secure a contact area between the contact portion 60 and the source region 35.

[0265] (1-7) The contact portion 60 includes a side surface 61A, a bottom surface 61B, and a corner portion 61C provided between the side surface 61A and the bottom surface 61B. The corner portion 61C is curved and convex outward.

[0266] With this configuration, since the corner portion 61C is curved, the thickness of the body region 23 between the corner portion 61C and the second semiconductor layer 22 can be secured compared to, for example, the case where the corner portion 61C is formed at a right angle in cross-sectional view. This suppresses the occurrence of punch-through.

[0267] (1-8) The side surface 61A of the contact portion 60 is tapered, so that it moves away from each other as it moves from the corner portion 61C toward the first main surface 20S of the second semiconductor layer 22. With this configuration, the contact area between the side surface 61A and the source region 35 can be increased compared to a configuration in which the side surface 61A extends along the Z direction.

[0268] (1-9) The thickness TS of the source region 35 is 1 / 2 or more of the opening width WS of the source opening 40A. With this configuration, as the thickness TS of the source region 35 increases, the contact area between the contact portion 60 and the source region 35 increases, making it easier to secure a contact area between the contact portion 60 and the source region 35.

[0269] (1-10) The semiconductor device 10 includes a contact region 65 that is in contact with the bottom surface 61B of the contact portion 60. The p-type impurity concentration in the contact region 65 is higher than the p-type impurity concentration in the body region 23.

[0270] With this configuration, the contact region 65 reduces the resistance in the current path passing through the body region 23, the contact region 65, and the contact portion 60. This reduces the on-resistance of the semiconductor device 10.

[0271] (1-11) In a plan view, the width WD of the contact area 65 is greater than the opening width WS of the source opening 40A. With this configuration, the contact area between the contact portion 60 and the contact area 65 can be increased, thereby reducing the resistance in the current path passing through the body area 23, the contact area 65, and the contact portion 60.

[0272] (1-12) The contact area 65 is in contact with both the bottom surface 61B and the corner portion 61C of the contact part 60. With this configuration, the contact area between the contact part 60 and the contact area 65 can be increased, thereby reducing the resistance in the current path passing through the body area 23, the contact area 65, and the contact part 60.

[0273] (1-13) The contact region 65 is provided with a gap in the Z direction relative to the first main surface 20S. In a configuration in which the contact region is exposed from the first main surface through the source opening, both the contact region and the source region must be exposed on the first main surface. For this reason, as the opening width of the source opening decreases with the miniaturization of the transistor structure, it becomes necessary to reduce the area of ​​the contact region.

[0274] In this regard, in the semiconductor device 10 of the first embodiment, the contact area 65 is provided at a position away from the first main surface 20S, so the above-mentioned constraint on the area of ​​the contact area 65 is eliminated. As a result, the area of ​​the contact area 65 can be made larger in a plan view, making it easier to secure the contact area between the contact portion 60 and the contact area 65.

[0275] (1-14) The contact portion 60 includes a contact body 61 provided within the second semiconductor layer 22 and a protrusion 62 provided on the first main surface 20S. The thickness TB of the contact body 61 is greater than the thickness TP of the protrusion 62. With this configuration, the contact body 61 provided within the second semiconductor layer 22 is formed to be large, making it easier to secure a contact area between the contact body 61 and the source region 35.

[0276] (1-15) Multiple contact portions 60 are provided spaced apart from each other in the X direction in a plan view. Each contact portion 60 extends in the X direction. The source electrode 51 is located in the intercontact region 66, which is the area between adjacent contact portions 60 in the X direction.

[0277] With this configuration, the movement of the source electrode 51 relative to the contact portion 60 is restricted by the source electrode 51 entering the intercontact region 66. This prevents the source electrode 51 from detaching from the contact portion 60, for example, when an external force is applied to the source electrode 51.

[0278] (1-16) The X-direction end 64 of the contact portion 60 includes an end bulge 64A. The end bulge 64A is provided within the second semiconductor layer 22 and is exposed from the first main surface 20S. The source electrode 51 is in contact with the portion of the end bulge 64A that is exposed from the first main surface 20S.

[0279] This configuration allows for a larger contact area between the contact portion 60 and the source electrode 51 at the end 64 of the contact portion 60. This reduces the resistance between the contact portion 60 and the source electrode 51.

[0280] <Second Embodiment> The semiconductor device 10 of the second embodiment will be described with reference to Figures 29 to 33. In the semiconductor device 10 of the second embodiment, the configuration within the chip 20 is mainly different from that of the semiconductor device 10 of the first embodiment. The following will explain the differences from the first embodiment, and will omit the explanation of parts that are common with the first embodiment. Also, in the second embodiment, the X direction is an example of the "first direction", and the Y direction is an example of the "second direction".

[0281] Figure 29 schematically shows the planar structure of a part of the active region 11 of the semiconductor device 10 of the second embodiment. Figure 30 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F30-F30 in Figure 29. Figure 31 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F31-F31 in Figure 29. Figure 32 schematically shows an enlarged cross-sectional structure of a part of Figure 31. Figure 33 schematically shows an enlarged cross-sectional structure of one contact portion 60 and its surroundings in Figure 32.

[0282] As shown in Figures 30 and 31, the configuration of the well region 30 in the second embodiment differs from that of the first embodiment. More specifically, each well region 30 extends vertically, for example, in the thickness direction (Z direction) of the second semiconductor layer 22. Each well region 30 may form a superjunction structure together with the second semiconductor layer 22 in the region of the gate structure 25 closer to the first semiconductor layer 21. In this case, the depletion layers starting from each well region 30 are connected to each other in the regions between the multiple well regions 30. Each well region 30 includes a first well region 30A and a second well region 30B. The first well region 30A includes the upper end of the well region 30. The second well region 30B includes the bottom of the well region 30.

[0283] The first well region 30A is located closer to the bottom wall of the gate structure 25 than the depth position of the middle part of the well region 30. The ends of the first well region 30A in the Y direction may be located further inward from the gate structure 25 than the ends of the gate structure 25 in the Y direction. The first well region 30A may face the embedded electrode 28 across the insulating film 27. The first well region 30A may have a portion that runs along the side wall of the gate structure 25. In other words, the first well region 30A may face the embedded electrode 28 across the insulating film 27 on the side wall of the gate structure 25. The ends of the first well region 30A in the Y direction may be located closer to the periphery of the active region 11 than the ends of the gate structure 25 in the Y direction.

[0284] The first depth ratio, which is the ratio of the depth of the first well region 30A to the depth of the well region 30, can be greater than 0 and less than or equal to 0.5. The first depth ratio may have a value that belongs to at least one of the following ranges: greater than 0 and less than or equal to 0.1, 0.1 to less than or equal to 0.2, 0.2 to less than or equal to 0.3, 0.3 to less than or equal to 0.4, and 0.4 to less than or equal to 0.5. Preferably, the first depth ratio is less than 0.5. Here, the depth of the well region 30 can be defined by the distance in the Z direction between the bottom wall of the corresponding gate structure 25 and the bottom of the well region 30 (the bottom of the second well region 30B). The depth of the first well region 30A can be defined by the distance in the Z direction between the bottom wall of the corresponding gate structure 25 and the bottom of the first well region 30A.

[0285] The depth of the first well region 30A is less than the depth of the gate structure 25. The depth of the first well region 30A can be greater than 0 μm and 1 μm or less. The depth of the first well region 30A may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, 0.4 μm or more and 0.5 μm or less, 0.5 μm or more and 0.6 μm or less, 0.6 μm or more and 0.7 μm or less, 0.7 μm or more and 0.8 μm or less, 0.8 μm or more and 0.9 μm or less, and 0.9 μm or more and 1 μm or less. Preferably, the depth of the first well region 30A is 0.5 μm or less.

[0286] The second well region 30B is located closer to the first semiconductor layer 21 than the first well region 30A. The second well region 30B extends in the Y direction according to the extending direction of the gate structure 25. The ends of the second well region 30B in the Y direction may be located further inward from the gate structure 25 than the ends of the gate structure 25 in the Y direction. Furthermore, the ends of the second well region 30B in the Y direction may be located closer to the periphery of the active region 11 than the ends of the gate structure 25 in the Y direction.

[0287] The second well region 30B includes, for example, a first portion located closer to the bottom wall of the gate structure 25 than the depth position of the middle part of the well region 30, and a second portion located closer to the first semiconductor layer 21 than the depth position of the middle part of the well region 30. The first portion is in contact with the first well region 30A. The second portion includes the bottom of the second well region 30B.

[0288] The depth of the second well region 30B is obtained by subtracting the depth of the first well region 30A from the depth of the well region 30. The depth of the second well region 30B can be defined by the distance in the Z direction between the bottom of the first well region 30A and the bottom of the second well region 30B. The second depth ratio, which is the ratio of the depth of the second well region 30B to the depth of the well region 30, is obtained by "1 - first depth ratio".

[0289] The second depth ratio can be 0.5 or greater. Preferably, the second depth ratio is greater than 0.5. The depth of the second well region 30B is, for example, less than the depth of the gate structure 25. The depth of the second well region 30B can be arbitrarily changed. In one example, the depth of the second well region 30B may be greater than or equal to the depth of the gate structure 25.

[0290] The depth of the second well region 30B can be 0.5 μm or more and 5 μm or less. The depth of the second well region 30B may have a value that falls within at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0291] Each source region 35, together with the second semiconductor layer 22, demarcates a channel region 24 that serves as a current path near the bottom of the body region 23. The channel region 24 may have a channel length greater than 0 nm and less than or equal to 500 nm. The channel length can be defined by the distance in the Z direction between the bottom of the body region 23 and the bottom of the source region 35. The channel length may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 50 nm, 50 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm. Preferably, the channel length is 300 nm or less.

[0292] As shown by the dashed lines in Figure 29, the multiple contact portions 60 are arranged with spacing in the X direction. Each contact portion 60 extends in the Y direction in a plan view. The multiple contact portions 60 are arranged with spacing in the Y direction within one mesa portion 29.

[0293] As shown in Figures 32 and 33, the cross-sectional structure obtained by cutting the contact portion 60 along the X direction is the same as the cross-sectional structure obtained by cutting the contact portion 60 along the Y direction in the first embodiment. On the other hand, the semiconductor device 10 of the second embodiment has a different configuration of the contact region 65.

[0294] As shown in Figure 29, the multiple contact regions 65 of the second embodiment are provided at intervals in the Y direction in a one-to-many correspondence with respect to the multiple gate structures 25. More specifically, the multiple contact regions 65 are interposed in the regions between the multiple source regions 35. In other words, the contact regions 65 of the second embodiment are exposed from the first main surface 20S.

[0295] Each contact region 65 may be connected to an adjacent source region 35 in the Y direction. Alternatively, each contact region 65 may be spaced apart from the source region 35 in the Y direction. In this case, a body region 23 is interposed between the contact region 65 and the source region 35 in the Y direction. Therefore, the contact region 65 faces the source region 35 with a portion of the body region 23 in between.

[0296] In a plan view, the portion of each contact region 65 that aligns with one gate structure 25 faces the portion that aligns with the other gate structure 25 in the X direction. Thus, the multiple contact regions 65 are arranged in a matrix with spacing in the X and Y directions in a plan view.

[0297] The arrangement of the multiple contact regions 65 can be arbitrarily changed. In one example, the multiple contact regions 65 may be arranged in a staggered pattern with spacing in the X and Y directions in a plan view. That is, one contact region 65 may face in the X direction the portion in the Y direction between two other adjacent contact regions 65 in the Y direction in a plan view.

[0298] Each contact region 65 may extend in a strip-like shape in the Y direction along the extending direction of the gate structure 25 in a plan view. The lengths of multiple contact regions 65 in the Y direction may be equal to each other. The length of each contact region 65 in the Y direction may be adjusted according to the channel area. The lengths of multiple contact regions 65 in the Y direction may be different from each other.

[0299] The channel area is the total area of ​​the portion of the multiple source regions 35 that is exposed from the region between the multiple gate structures 25. In other words, the channel area increases or decreases in proportion to the increase or decrease in the total planar area of ​​the multiple contact regions 65. It is preferable that the total planar area of ​​the multiple contact regions 65 is less than the channel area. That is, in the region between the multiple gate structures 25, it is preferable that the total planar area of ​​the multiple contact regions 65 is less than the total planar area of ​​the multiple source regions 35.

[0300] The length of the contact area 65 (dimension in the Y direction) may be greater than the width of the gate structure 25 (dimension in the X direction). The length of the contact area 65 may be greater than the spacing between the multiple gate structures 25 (width of the mesa portion 29). The spacing between the multiple contact areas 65 may be greater than the width of the gate structure 25. The spacing between the contact areas 65 may be greater than the spacing between the multiple gate structures 25. Here, the spacing between the contact areas 65 can be defined by the dimension of the inter-contact area 66 in the X direction.

[0301] The length of the contact area 65 can be arbitrarily changed. For example, the length of the contact area 65 may be less than or equal to the width of the gate structure 25, or less than or equal to the spacing between multiple gate structures 25. Also, the spacing between multiple contact areas 65 can be arbitrarily changed. For example, the spacing between multiple contact areas 65 may be less than or equal to the width of the gate structure 25, or less than or equal to the spacing between multiple gate structures 25.

[0302] The p-type impurity concentration in the contact region 65 may be the same as in the first embodiment, for example. The p-type impurity concentration in the contact region 65 may be higher than the p-type impurity concentration in the first well region 30A. The p-type impurity concentration in the contact region 65 may be higher than the p-type impurity concentration in the second well region 30B. The p-type impurity concentration in the contact region 65 may be less than or equal to the p-type impurity concentration in the first well region 30A.

[0303] As shown in Figure 31, the multiple contact regions 65 include a first region 65A, a second region 65B, and a third region 65C. The first region 65A is a region along the bottom wall of the corresponding gate structure 25. The first region 65A is interposed between the bottom wall of the corresponding gate structure 25 and the bottom of the corresponding well region 30, and is connected to the bottom wall of the corresponding gate structure 25 and the corresponding well region 30. The first region 65A faces the embedded electrode 28 across the insulating film 27.

[0304] The first region 65A includes a bottom that is located closer to the bottom of the second well region 30B than the bottom of the first well region 30A (see Figure 30). Therefore, the thickness of the first region 65A is greater than the thickness of the first well region 30A. Here, the thickness of the first region 65A can be defined by the distance in the Z direction between the bottom wall of the gate structure 25 and the bottom of the first region 65A.

[0305] The bottom of the first region 65A is positioned closer to the bottom wall of the gate structure 25 than the bottom of the second well region 30B. Therefore, the first region 65A faces the second semiconductor layer 22 with a portion of the second well region 30B in between. In one example, the bottom of the first region 65A may be located closer to the bottom wall of the gate structure 25 than the depth position of the middle part of the second well region 30B. In another example, the bottom of the first region 65A may be located closer to the bottom of the second well region 30B than the depth position of the middle part of the second well region 30B.

[0306] The first region 65A has a width greater than the width of the gate structure 25. The first region 65A extends horizontally from the region directly below the corresponding gate structure 25 to both sides of the corresponding gate structure 25. The first region 65A covers the bottom wall of the trench 26 (gate structure 25). By connecting the first region 65A to both the first well region 30A and the second well region 30B, the p-type impurity concentration in the first well region 30A and the p-type impurity concentration in the second well region 30B are increased.

[0307] The thickness of the first region 65A may be less than the thickness of the first well region 30A. In this case, the first region 65A may be provided at a distance closer to the bottom wall of the gate structure 25 than the depth position of the bottom of the first well region 30A. In this case, the first region 65A may face the second well region 30B with a portion of the first well region 30A in between.

[0308] The second region 65B is in contact with the side wall of the gate structure 25. The second region 65B is a region that extends along the side wall of the gate structure 25. The second region 65B faces the embedded electrode 28 across the insulating film 27. The second region 65B has a thickness less than the thickness of the first region 65A. The thickness of the second region 65B is the thickness in the horizontal direction (X direction) with respect to the side wall of the gate structure 25. The second region 65B connects the first region 65A and the body region 23. In other words, the second region 65B electrically connects the corresponding well region 30 to the body region 23. This suppresses the well region 30 from becoming electrically floating, thereby improving the electrical response characteristics of the well region 30.

[0309] The third region 65C extends in layers along the first main surface 20S on the surface of the tip 20. The third region 65C is exposed from the first main surface 20S. In other words, the third region 65C constitutes the upper end of the contact region 65. In one example, the third region 65C is exposed from the side wall of the trench 26 at the opening end of the trench 26.

[0310] The third region 65C is connected to the second region 65B of the adjacent contact region 65. In one example, the third region 65C is integrated with the second region 65B of the adjacent contact region 65. In other words, multiple contact regions 65 are electrically connected to each other via multiple third regions 65C. The third region 65C has a thickness less than the thickness of the body region 23. The third region 65C faces the second semiconductor layer 22 with a portion of the body region 23 in between. The thickness of the third region 65C can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the third region 65C.

[0311] The bottom of the third region 65C is located closer to the bottom of the body region 23 than the height of the electrode surface of the embedded electrode 28. Therefore, the third region 65C has a portion located closer to the bottom wall of the trench 26 than the electrode surface of the embedded electrode 28, and a portion located closer to the first main surface 20S than the electrode surface. The third region 65C has a portion that faces the embedded electrode 28 across the insulating film 27.

[0312] The thickness of the third region 65C is greater than the thickness of the second region 65B. The thickness of the third region 65C may be equal to the thickness of the first region 65A. The thickness of the third region 65C may be less than the thickness of the first region 65A. The thickness of the third region 65C is less than the thickness of the source region 35. For this reason, the bottom of the third region 65C is located closer to the first main surface 20S than the bottom of the source region 35.

[0313] The thickness of the third region 65C can be arbitrarily changed. In one example, the thickness of the third region 65C may be greater than or equal to the thickness of the source region 35. In another example, the thickness of the third region 65C may be greater than the distance in the Z direction between the bottom of the body region 23 and the bottom of the third region 65C. In yet another example, the thickness of the third region 65C may be less than or equal to the distance in the Z direction between the bottom of the body region 23 and the bottom of the third region 65C.

[0314] As shown in Figure 30, the portion of the contact portion 60 that overlaps with the source region 35 in a plan view is in contact with the source region 35. In the second embodiment, the bottom surface 61B of the contact portion 60 is located at a distance closer to the first main surface 20S than the bottom of the source region 35. In other words, the contact portion 60 does not penetrate the source region 35 in the Z direction. For this reason, the thickness TB of the contact body 61 is less than the thickness TS of the source region 35. Thus, the bottom surface 61B, the side surface 61A, and the corner portion 61C (see Figure 33) of the contact portion 60 (contact body 61) are in contact with the source region 35.

[0315] On the other hand, as shown in Figure 29, the contact portion 60 penetrates the source region 35 in the Y direction. In other words, the length of the contact portion 60 in the extending direction is longer than the length of the source region 35 in the Y direction.

[0316] As shown in Figures 31 to 33, the portion of the contact portion 60 that overlaps with the contact area 65 in a plan view is in contact with the contact area 65. More specifically, the contact portion 60 is in contact with the third area 65C. The contact portion 60 does not penetrate the third area 65C in the Z direction. In other words, the bottom surface 61B of the contact portion 60 is located closer to the first main surface 20S than the bottom of the third area 65C. For this reason, the thickness TB of the contact body 61 is less than the thickness TD of the third area 65C. Thus, the bottom surface 61B, side surface 61A, and corner portion 61C of the contact portion 60 (contact body 61) are in contact with the third area 65C (contact area 65).

[0317] As shown in Figure 29, the intercontact region 66 is positioned to overlap with the source region 35 in a plan view. Since the source region 35 is exposed on the first main surface 20S, the source electrode 51 that enters the intercontact region 66 is mechanically and electrically connected to the source region 35. The length of the intercontact region 66 in the Y direction may be smaller than the length of the source region 35 in the Y direction.

[0318] The position of the inter-contact region 66 can be arbitrarily changed. In one example, the inter-contact region 66 may be located in a position that overlaps with the contact region 65 in a plan view. In another example, the inter-contact region 66 may be located so as to straddle the boundary between the source region 35 and the contact region 65. The length LR of the inter-contact region 66 can also be arbitrarily changed. In one example, the inter-contact region 66 may be longer than or equal to the length LS of the source region 35. In another example, the inter-contact region 66 may be longer than or equal to the length of the contact region 65. Although not shown in the figures, the cross-sectional structure of the contact portion 60 in the inter-contact region 66 is the same as in the first embodiment.

[0319] [Effects of the Second Embodiment] The semiconductor device 10 of the second embodiment provides the same effects as the semiconductor device 10 of the first embodiment.

[0320] <Third Embodiment> The semiconductor device 10 of the third embodiment will be described with reference to Figures 34 to 36. The main difference between the semiconductor device 10 of the third embodiment and the semiconductor device 10 of the first embodiment is that the gate structure has been changed from a trench structure to a planar structure. In the following, the differences from the first embodiment will be mainly described, and components common to both the first and third embodiments will be denoted by the same reference numerals, and their descriptions will be omitted. Also, in the third embodiment, the X direction is an example of the "first direction," and the Y direction is an example of the "second direction."

[0321] Figure 34 schematically shows the planar structure of a part of the active region 11 in the semiconductor device 10 of the third embodiment. Figure 35 shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F35-F35 in Figure 34. Figure 36 schematically shows an enlarged cross-sectional structure of one contact portion 60 and its surroundings in Figure 35.

[0322] (Active Region) As shown in Figure 35, the transistor structure Tr of the semiconductor device 10 of the third embodiment has a planar gate type vertical structure. The semiconductor device 10 of the third embodiment is provided with multiple body regions 23 and multiple source regions 35.

[0323] Multiple body regions 23 are provided at intervals from the periphery of the first main surface 20S of the chip 20. Multiple body regions 23 are provided in the active region 11 (see Figure 2), while they are not provided in the outer peripheral region 12 (see Figure 2). In the third embodiment, the multiple body regions 23 are provided at intervals in the X direction in a plan view and extend in the Y direction. That is, the multiple body regions 23 are stripe-shaped and extend in the Y direction in a plan view. The extension direction of each body region 23 coincides with the off-direction of the SiC single crystal. The arrangement of the multiple body regions 23 can be arbitrarily changed. In one example, the multiple body regions 23 may be strip-shaped and provided at intervals in the Y direction and extend in the X direction.

[0324] Multiple source regions 35 are provided on the surface of each of the multiple body regions 23. The multiple source regions 35 are provided at intervals in the X direction, extending inward from both ends of the corresponding body regions 23. The multiple source regions 35 are provided at intervals in the X direction on the surface of the corresponding body regions 23 and extend in a strip-like manner in the Y direction. The multiple source regions 35 may also be provided at intervals in the Y direction according to the extending direction of the corresponding body regions 23.

[0325] The multiple source regions 35 are spaced apart in the Y direction, extending inward from both ends of the corresponding body region 23. The multiple source regions 35 are spaced further towards the first main surface 20S than the bottom of the corresponding body region 23. Therefore, the multiple source regions 35 face the second semiconductor layer 22 with a portion of the body region 23 in between.

[0326] The semiconductor device 10 of the third embodiment includes a plurality of contact portions 60 and a plurality of contact regions 65. The plurality of contact portions 60 are spaced apart in the X direction. The plurality of contact portions 60 are provided corresponding to a plurality of body regions 23. As shown in Figure 34, each contact portion 60 extends in the Y direction in a plan view. The plurality of contact portions 60 are spaced apart in the Y direction.

[0327] As shown in Figure 35, the contact portion 60 is provided so as to penetrate the source region 35, similar to the first embodiment. As a result, it can be said that multiple source regions 35 are provided in the body region 23. As shown in Figure 36, the shape of the contact portion 60 is the same as in the first embodiment.

[0328] As shown in Figure 34, the multiple contact regions 65 are spaced apart in the X direction and extend in a strip shape in the Y direction. As shown in Figure 35, the multiple contact regions 65 are spaced apart closer to the bottom of the second semiconductor layer 22 than the first main surface 20S. The contact regions 65 are in contact with the bottom surface 61B and corner portion 61C of the contact portion 60, similar to the first embodiment.

[0329] As shown in Figure 34, in the inter-contact region 66, the source region 35 is exposed on the first main surface 20S. Therefore, in the inter-contact region 66, the source regions 35, which are spaced apart in the X direction, are connected in the X direction. Although not shown, the cross-sectional structure of the contact portion 60 in the inter-contact region 66 is the same as in the first embodiment.

[0330] As shown in Figure 35, the multiple well regions 30 are each provided in the region below (specifically, directly below) the multiple body regions 23. Each well region 30 is connected to the bottom of the corresponding body region 23. The multiple well regions 30 are provided within the second semiconductor layer 22 with spacing between them in the horizontal direction (X direction). The multiple well regions 30 are provided in a one-to-one correspondence with the multiple body regions 23. Note that each well region 30 may be provided with spacing between it and the bottom of the second semiconductor layer 22, both closer to the corresponding body region 23 and closer to the bottom.

[0331] Each well region 30 extends in the Y direction in a plan view, corresponding to the extension direction of the body region 23. Multiple well regions 30 form a stripe shape extending in the Y direction in a plan view. The extension direction of each well region 30 coincides with the off-direction of the SiC single crystal. In one example, both ends of each well region 30 in the Y direction are located closer to the inside of the body region 23 than both ends of each body region 23 in the Y direction. Alternatively, both ends of each well region 30 in the Y direction may be located closer to the periphery of the active region 11 than both ends of each body region 23 in the Y direction. If the body region 23 extends in the X direction, the well regions 30 may extend in the X direction. In this case, multiple well regions 30 intersect (specifically, orthogonal) in the off-direction.

[0332] Each well region 30 has a width less than the width of the corresponding body region 23. Each well region 30 is provided spaced inward from both ends in the X direction of the corresponding body region 23. The width of each well region 30 can be arbitrarily changed. In one example, the width of the well region 30 may be greater than or equal to the width of the body region 23.

[0333] The bottom of each well region 30 may be located closer to the bottom of the body region 23 with respect to the depth position of the intermediate portion of the second semiconductor layer 22. Each well region 30 may form a superjunction structure with the second semiconductor layer 22 in the region below the corresponding body region 23. In this case, the depletion layers starting from each well region 30 are connected to each other in the regions between the multiple well regions 30. The position of the bottom of each well region 30 can be arbitrarily changed.

[0334] The thickness of the well region 30 is greater than the thickness of the body region 23. Here, the thickness of the well region 30 can be defined by the distance in the Z direction between the bottom of the body region 23 and the bottom of the well region 30. The thickness of the body region 23 can be defined by the distance in the Z direction between the first main surface 20S and the bottom of the body region 23. The thickness of the well region 30 can be between 0.5 μm and 5 μm. The thickness of the well region 30 may have a value that belongs to at least one of the following ranges: 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm, and 4.5 μm to 5 μm.

[0335] The semiconductor device 10 of the third embodiment includes a plurality of surface drift regions 71 and a plurality of p-type channel regions 72 provided on the surface of the second semiconductor layer 22. Since the plurality of surface drift regions 71 are composed of the second semiconductor layer 22, they have the same n-type impurity concentration as the second semiconductor layer 22. The n-type impurity concentration of each surface drift region 71 can be arbitrarily changed. In one example, the n-type impurity concentration of the surface drift region 71 may be higher or lower than the n-type impurity concentration of the second semiconductor layer 22.

[0336] Multiple surface drift regions 71 are each demarcated in the region between adjacent body regions 23 on the surface of the second semiconductor layer 22. Therefore, the multiple surface drift regions 71 are spaced apart in the X direction and extend in the Y direction. In a plan view, the multiple surface drift regions 71 form a stripe shape extending in the Y direction.

[0337] The multiple channel regions 72 are each demarcated in the surface portion of the multiple body regions 23, between the multiple source regions 35 and the multiple surface drift regions 71. Each channel region 72 forms a current path that extends horizontally along the first main surface 20S.

[0338] The semiconductor device 10 of the third embodiment includes a plurality of planar gate structures 73 arranged on the first main surface 20S in the active region 11 (see Figure 1), instead of a trench-type gate structure 25 (see Figure 4). The plurality of gate structures 73 are arranged with spacing in the X direction and each extends in a strip-like manner in the Y direction. In a plan view, the plurality of gate structures 73 are stripes extending in the Y direction. The direction of extension of each gate structure 73 coincides with the off-direction of the SiC single crystal.

[0339] Each of the multiple gate structures 73 is positioned on at least one channel region 72 (the periphery of the body region 23). Each of the multiple gate structures 73 covers at least one periphery of the body region 23, at least one source region 35, and one surface drift region 71. In the third embodiment, the multiple gate structures 73 span across one surface drift region 71 and the peripheries of two adjacent body regions 23, and cover the multiple channel regions 72.

[0340] Each gate structure 73 has a stacked structure including a planar insulating film 74 and a planar electrode 75. Here, the planar insulating film 74 is an example of a "planar insulating film," and the planar electrode 75 is an example of a "planar gate electrode."

[0341] The planar insulating film 74 may contain at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In the third embodiment, the planar insulating film 74 has a single-layer structure composed of a silicon oxide film. Preferably, the planar insulating film 74 contains a silicon oxide film including the oxide of the second semiconductor layer 22.

[0342] The planar insulating film 74 is provided on the first main surface 20S. The planar insulating film 74 covers the first main surface 20S in a film-like manner. The planar insulating film 74 extends in a strip shape in the Y direction. The planar insulating film 74 is positioned on at least one channel region 72 (periphery of the body region 23). The planar insulating film 74 covers at least one periphery of the body region 23, at least one source region 35, and one surface drift region 71, respectively. In the third embodiment, the planar insulating film 74 spans across one surface drift region 71 and the peripheries of two adjacent body regions 23, and covers a plurality of channel regions 72.

[0343] As shown in Figure 36, the planar insulating film 74 is in contact with the contact portion 60. More specifically, the planar insulating film 74 is in contact with the upper surface of the bulging portion 63 of the contact body 61. In other words, the planar insulating film 74 covers the bulging portion 63. The planar insulating film 74 is also in contact with the side surface 62B of the protruding portion 62.

[0344] As shown in Figure 35, the planar electrode 75 is placed on the planar insulating film 74. A gate potential is applied to the planar electrode 75 as a control potential. The planar electrode 75 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0345] The planar electrode 75 covers the first main surface 20S in a film-like manner via the planar insulating film 74 and faces at least one channel region 72. The planar electrode 75 extends in a strip shape in the Y direction. In the third embodiment, the planar electrode 75 is positioned in the X direction at a distance inward from both ends of the planar insulating film 74. Both ends of the planar insulating film 74 are covered by the interlayer film 42.

[0346] The planar electrode 75 covers the periphery of at least one body region 23, at least one source region 35, and one surface drift region 71 via the planar insulating film 74. In the third embodiment, the planar electrode 75 spans the periphery of two adjacent body regions 23 across one surface drift region 71 and faces a plurality of channel regions 72 across the planar insulating film 74. The planar electrode 75 is located at a different position from the contact portion 60 in a plan view. In other words, the contact portion 60 is located at a different position from the planar electrode 75 in a plan view, that is, at a distance from the planar electrode 75.

[0347] (Peripheral Region) Although not shown in the figures, the semiconductor device 10 of the third embodiment includes an outer well region 37, an outer contact region 38, and a plurality of field regions 39, similar to the first embodiment.

[0348] The outer well region 37 extends in layers along the first main surface 20S. The inner edge of the outer well region 37 is connected to the body region 23. The inner edge of the outer well region 37 may be located inward of the first main surface 20S beyond the outermost body region 23. The outer edge of the outer well region 37 may be located inward from the periphery of the first main surface 20S.

[0349] The outer well region 37 has a width greater than the width of the body region 23. The width of the outer well region 37 is the dimension in the direction perpendicular to the extending direction of the outer well region 37 in a plan view. The width of the outer well region 37 may be equal to the width of the body region 23. The ratio of the width of the outer well region 37 to the width of the body region 23 can be between 1 and 50. This width ratio may have a value that falls within at least one of the following ranges: between 1 and 10, between 10 and 20, between 20 and 30, between 30 and 40, and between 40 and 50. The other configurations of the outer well region 37 are the same as in the first embodiment.

[0350] (Insulating layer and gate wiring) As shown in Figure 36, the main surface insulating film 41 of the insulating layer 40 selectively covers the first main surface 20S and is connected to a plurality of planar insulating films 74. The main surface insulating film 41 may be integrated with the plurality of planar insulating films 74. For this reason, it can be said that the main surface insulating film 41 includes a plurality of planar insulating films 74.

[0351] Although not shown, the gate wiring 43 (see Figure 14) extends in a strip-like shape along the multiple gate structures 73. In a plan view, the gate wiring 43 is a polygonal annular shape (a quadrilateral annular shape in the third embodiment) surrounding the multiple gate structures 73. The inner edge of the gate wiring 43 is mechanically and electrically connected to the multiple planar electrodes 75 (gate structures 73). In one example, the gate wiring 43 is integrated with the planar electrodes 75. The arrangement of the gate wiring 43 is the same as in the first embodiment.

[0352] The width of the gate wiring 43 is greater than the width of the planar electrode 75. Here, the width of the gate wiring 43 can be defined by the dimension in the direction perpendicular to the extending direction of the gate wiring 43 in a plan view. The width of the gate wiring 43 may also be equal to the width of the planar electrode 75. The ratio of the width of the gate wiring 43 to the width of the planar electrode 75 can be between 1 and 50. This width ratio may have a value that falls within at least one of the following ranges: 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.

[0353] The gate wiring 43 preferably has the same conductivity type as the planar electrode 75. The thickness of the gate wiring 43 is equal to the thickness of the planar electrode 75. The thickness of the gate wiring 43 can be arbitrarily changed.

[0354] The gate wiring 43 is covered by the interlayer film 42, as in the first embodiment. In other words, the interlayer film 42 covers multiple gate structures 73. The other configurations of the interlayer film 42 are the same as in the first embodiment.

[0355] [Effects of the Third Embodiment] The semiconductor device 10 of the third embodiment provides the same effects as the semiconductor device 10 of the first embodiment.

[0356] <Fourth Embodiment> The semiconductor device 10 of the fourth embodiment will be described with reference to Figures 37 to 40. The semiconductor device 10 of the fourth embodiment differs from the semiconductor device 10 of the first embodiment mainly in the configuration of the gate structure. The differences from the first embodiment will be described below, and components common to the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted. In the fourth embodiment, the X direction is an example of the "first direction", and the Y direction is an example of the "second direction".

[0357] Figure 37 schematically shows the planar structure of a part of the active region 11 in the semiconductor device 10 of the fourth embodiment. Figure 38 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F38-F38 in Figure 37. Figure 39 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F39-F39 in Figure 37. Figure 40 schematically shows the cross-sectional structure obtained by cutting the semiconductor device 10 along the line F40-F40 in Figure 38.

[0358] As shown in Figures 37 and 40, the semiconductor device 10 of the fourth embodiment includes a plurality of gate structures 80 instead of the gate structure 25 (see Figure 4). The plurality of gate structures 80 are spaced apart in the X direction and each extends in a strip shape in the Y direction. The plurality of gate structures 80 and the plurality of contact portions 60 are arranged alternately one by one in the X direction. Each gate structure 80 includes a plurality of trenches 81, an insulating film 82, and a gate electrode 83.

[0359] Each trench 81 is excavated in a columnar shape from the first main surface 20S. In the fourth embodiment, each trench 81 is rectangular in shape, with the Y direction being the longitudinal direction and the X direction being the short direction in a plan view. Multiple trenches 81 are provided between adjacent contact portions 60 in the X direction.

[0360] In one gate structure 80, multiple trenches 81 are provided at intervals in the X direction (three in the fourth embodiment). Multiple trenches 81 are provided at intervals in the extending direction (Y direction) of the gate structure 80. Thus, the multiple trenches 81 are arranged at intervals from each other in both the X and Y directions. In the fourth embodiment, the multiple trenches 81 are arranged in a matrix in a plan view. In one example, the distance DX between adjacent trenches 81 in the X direction is greater than the distance DY between adjacent trenches 81 in the Y direction. The distance DX is less than the distance DG between adjacent gate structures 80 in the X direction. The distance DX is less than the distance DA between adjacent trenches 81 in the X direction with a contact portion 60 in between.

[0361] As shown in Figure 38, the insulating film 82 is provided in a film-like manner within the trench 81 and along the first main surface 20S. The insulating film 82 provided within the trench 81 constitutes the side walls and bottom walls of the trench 81. The insulating film 82 is connected to the main surface insulating film 41. In one example, the insulating film 82 is integrated with the main surface insulating film 41. That is, the main surface insulating film 41 may include the insulating film 82. The insulating film 82 may be made of the same material as the main surface insulating film 41. That is, it can be said that the main surface insulating film 41 includes the insulating film 82.

[0362] The gate electrode 83 includes embedded electrode portions 83A, each provided in a plurality of trenches 81, and an electrode connection portion 83B located on the first main surface 20S. The electrode connection portion 83B connects the plurality of embedded electrode portions 83A. In one example, the electrode connection portion 83B is integrated with the plurality of embedded electrode portions 83A. The electrode connection portion 83B is positioned on an insulating film 82 (main surface insulating film 41). The embedded electrode portions 83A face the pillar region 91 across the insulating film 82. The electrode connection portion 83B faces the source region 35 across the insulating film 82 (main surface insulating film 41). The electrode connection portion 83B is positioned between adjacent contact portions 60 in the X direction. As shown in Figure 39, the electrode connection portion 83B extends in the Y direction. The material of the gate electrode 83 may be the same as, for example, the material of the embedded electrode 28 in the first embodiment (see Figure 4).

[0363] The interlayer film 42 covers the electrode connection portion 83B. Due to the electrode connection portion 83B, the shape of the interlayer film 42 differs from that of the first embodiment. The upper surface of the interlayer film 42 includes a flat surface. As shown in Figures 38 and 39, in the fourth embodiment, the configuration of the body region 23 provided on the chip 20 differs from that of the first embodiment. Specifically, the bottom of the body region 23 in the fourth embodiment is located closer to the bottom of the second semiconductor layer 22 than the bottom wall of the gate structure 80. In other words, the thickness of the body region 23 is greater than the depth of the trench 81.

[0364] The semiconductor device 10 of the fourth embodiment includes a plurality of n-type pillar regions 91 instead of the first pillar region 31 and the second pillar region 32 of the first embodiment (see Figures 4 and 5). The plurality of pillar regions 91 are elongated columnar in shape. The pillar regions 91 and the body region 23 form a pn junction.

[0365] As shown by the dashed line in Figure 40, the multiple pillar regions 91 are provided in the region that overlaps with the gate structure 80 in a plan view. In one example, multiple pillar regions 91 are provided in the overlapping region RA that overlaps with one gate structure 80. The multiple pillar regions 91 are arranged with spacing in the X and Y directions in the overlapping region RA. In one example, the multiple pillar regions 91 are arranged in a matrix in a plan view. In a plan view, each pillar region 91 is rectangular in shape, with the Y direction being the longitudinal direction and the X direction being the short direction, according to the plan view shape of the trench 81.

[0366] Multiple pillar regions 91 are provided corresponding to multiple trenches 81. In one example, multiple pillar regions 91 are provided in a one-to-one correspondence with multiple trenches 81. Therefore, body regions 23 (see Figure 38) are provided between multiple pillar regions 91 in the X direction. As shown in Figure 39, no pillar regions 91 are provided between adjacent trenches 81 in the Y direction. In other words, body regions 23 are provided between trenches 81 in the Y direction.

[0367] As shown in Figure 38, the pillar region 91 reduces the thickness of the body region 23, so each trench 81 penetrates both the source region 35 and the body region 23 in the Z direction. The portion of the side wall of the trench 81 closer to the bottom wall of each trench 81 than to the body region 23, and the bottom wall of the trench 81 are surrounded by the pillar region 91. In a plan view, the pillar region 91 surrounds the entire circumference of the portion of the side wall of the trench 81 closer to the bottom wall of each trench 81 than to the body region 23. For this reason, the pillar region 91 faces the gate electrode 83 (embedded electrode portion 83A) across the insulating film 82. Each source region 35, together with the pillar region 91, demarcates a channel region 92 in the body region 23 directly above the pillar region 91, which serves as a current path. In other words, the channel region 92 is demarcated around the entire circumference of the trench 81 in a plan view.

[0368] In the fourth embodiment, the configuration of the source region 35 provided on the chip 20 differs from that of the first embodiment. Specifically, the source region 35 of the fourth embodiment extends continuously around a plurality of trenches 81, at least below the electrode connection portion 83B. In one example, the source region 35 extends across the entire area between adjacent contact portions 60 in the X direction.

[0369] (Contact portion and contact area) As shown in Figures 38 and 39, the contact portion 60 is provided at a position away from the electrode connection portion 83B of the gate electrode 83. Specifically, the contact portion 60 is provided at a distance from the electrode connection portion 83B in the X direction. Similar to the first embodiment, the contact portion 60 is in contact with both the source area 35 and the contact area 65.

[0370] In the fourth embodiment, the cross-sectional structure obtained by cutting the contact portion 60 along the X direction is the same as the cross-sectional structure obtained by cutting the contact portion 60 along the Y direction in the first embodiment. The width WC of the contact portion 60 is greater than the width WT of the trench 81. The width WC of the contact portion 60 is less than the length LT of the trench 81 (see Figure 40).

[0371] The shape of the contact region 65 differs from that of the first embodiment. More specifically, the thickness of the contact region 65 in the fourth embodiment is greater than that of the contact region 65 in the first embodiment. In one example, the thickness of the contact region 65 increases from both ends in the X direction of the contact body 61 towards the center. The bottom of the contact region 65 may be located closer to the bottom of the second semiconductor layer 22 than the bottom wall of the trench 81.

[0372] [Effects of the Fourth Embodiment] According to the semiconductor device 10 of the fourth embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.

[0373] (4-1) Multiple contact portions 60 are provided spaced apart in the X direction. The semiconductor device 10 includes a plurality of trenches 81 extending from the first main surface 20S of the second semiconductor layer 22 through the body region 23, an insulating film 82 provided in each trench 81, and a gate electrode 83 embedded in the insulating film 82 in each trench 81. The plurality of trenches 81 are provided between adjacent contact portions 60 in the X direction. The plurality of trenches 81 are arranged spaced apart in the X direction. The gate electrode 83 includes embedded electrode portions 83A provided in each of the plurality of trenches 81, and an electrode connection portion 83B located on the first main surface 20S and connecting the plurality of embedded electrode portions 83A. The source region 35 extends continuously around the plurality of trenches 81 at least below the electrode connection portion 83B. The contact portions 60 are in contact with the source region 35 at a position away from the electrode connection portion 83B.

[0374] With this configuration, the source region 35 extends continuously around the multiple trenches 81 at least below the electrode connection portion 83B, so there is no need to provide contact portions 60 between the multiple trenches 81. Therefore, miniaturization of the semiconductor device 10 can be facilitated, and the channel width per unit area within the second semiconductor layer 22 can be increased. As a result, the on-resistance of the semiconductor device 10 can be reduced.

[0375] (4-2) The distance DX between adjacent trenches 81 in the X direction is smaller than the distance DA between adjacent trenches 81 in the X direction that are separated by a contact portion 60. With this configuration, multiple trenches 81 can be densely arranged. Therefore, miniaturization of the semiconductor device 10 can be facilitated, and the channel width per unit area within the second semiconductor layer 22 can be increased.

[0376] <Examples of Modifications> Each of the above embodiments can be modified and implemented as follows. Furthermore, each of the above embodiments and each of the following examples of modifications can be combined with each other to the extent that they do not contradict each other technically.

[0377] [Examples of changes to the contact portion] In each embodiment, the configuration of the contact portion 60 can be changed as desired. For example, the contact portion 60 may be changed as shown in the first to fifth examples of changes in Figures 41 to 45.

[0378] As shown in Figure 41, in the first modified example, the bottom surface 61B of the contact portion 60 is curved so as to be convex toward the body region 23. In this case, the bottom surface 61B is smoothly connected to the corner portion 61C.

[0379] As shown in Figure 42, in the second modified example, the side surface 61A of the contact portion 60 is curved so as to be convex outward (towards the source region 35). In this case, the side surface 61A is smoothly connected to the corner portion 61C. In one example, the curvature of the side surface 61A may be equal to the curvature of the corner portion 61C. In another example, the curvature of the side surface 61A may be different from the curvature of the corner portion 61C.

[0380] As shown in Figure 43, in the third modification, the entire contact body 61 of the contact portion 60 is formed in a curved shape that is convex downwards. As shown in Figure 44, in the fourth modification, the contact portion 60 may be rectangular in cross-sectional view when the contact portion 60 is cut in the YZ plane. In this case, the side surface 61A extends along the Z direction. The bottom surface 61B is formed by a flat surface perpendicular to the Z direction. The side surface 61A is connected to the bottom surface 61B. In this case, the width WC of the contact portion 60 is equal to the opening width WS of the source opening 40A.

[0381] As shown in Figure 45, in the fifth modified example, the contact body 61 of the contact portion 60 may be trapezoidal in a cross-sectional view obtained by cutting the contact portion 60 in the YZ plane. In this case, the side surfaces 61A may be tapered, becoming closer to each other as they approach the body region 23. The bottom surface 61B is composed of a flat surface perpendicular to the Z direction.

[0382] In each embodiment, the shape of the contact portion 60 in plan view can be arbitrarily changed. In one example, as shown in Figure 46, the length of the contact portion 60 in the X direction may be shorter than in each embodiment. In this case, the number of inter-contact regions 66 will increase compared to each embodiment. In one example, the length of the contact portion 60 in the X direction is greater than the length of the first pillar region 31 in the X direction and less than twice the length of the first pillar region 31 in the X direction. Note that the length of the contact portion 60 in the X direction can be arbitrarily changed, and for example, it may be less than or equal to the length of the first pillar region 31 in the X direction. In this case, the contact portion 60 may be provided in each of the multiple first pillar regions 31.

[0383] - In each embodiment, the protruding portion 62 from the contact portion 60 may be omitted. - In each embodiment, the position of the bottom surface 61B of the contact portion 60 can be arbitrarily changed. In one example, the bottom surface 61B may be located closer to the bottom of the body region 23 than the source region 35.

[0384] In each embodiment, the contact portion 60 is not limited to being composed of silicide and can be changed as desired. In one example, the contact portion 60 may be composed of a metal film embedded in a trench formed from the first main surface 20S to the second semiconductor layer 22.

[0385] In each embodiment, the contact portion 60 may be made of the same material as the source electrode 51. In one example, the contact portion 60 may be integrated with the source electrode 51.

[0386] In each embodiment, the width WC of the contact portion 60 may be smaller than the opening width WS of the source opening 40A. In other words, the contact portion 60 may be spaced apart from the insulating layer 40. In this case, the source electrode 51 may be embedded between the contact portion 60 and the insulating layer 40. The source electrode 51 may be in contact with the first main surface 20S between the contact portion 60 and the insulating layer 40.

[0387] - In each embodiment, the thickness TC of the contact portion 60 may be less than the width WC of the contact portion 60. - In each embodiment, the width WC of the contact portion 60 may be less than or equal to the distance in the Z direction between the first main surface 20S and the bottom surface 61B of the contact portion 60 (contact body 61).

[0388] - In each embodiment, the thickness TP of the protrusion 62 may be greater than or equal to the thickness TB of the contact body 61. - In each embodiment, the end bulge 64A from the contact portion 60 may be omitted.

[0389] (Examples of changes to the insulating layer) In each embodiment, the shape of the insulating layer 40 can be arbitrarily changed. In one example, as shown in Figure 47, the source opening 40A provided in the insulating layer 40 may be tapered, with the opening width decreasing towards the first main surface 20S. In this case, the inclination angle θ1 of the side surface 61A of the contact portion 60 may be greater than the inclination angle θ2 of the insulating side surface 40AA that constitutes the source opening 40A of the insulating layer 40. Note that the insulating side surface 40AA is not limited to the tapered insulating side surface 40AA shown in Figure 47, and may extend along the Z direction.

[0390] (Examples of semiconductor layer modification) In the first, third, and fourth embodiments, the shape of the source region 35 can be arbitrarily changed. In one example, as shown in Figure 48, the source region 35 includes a first source region 35A that is in contact with the contact portion 60, and a second source region 35B that is spaced apart from the contact portion 60 in the X direction. The first source region 35A is in contact with the side surface 61A and corner portion 61C of the contact body 61 of the contact portion 60. The second source region 35B is provided on the opposite side from the contact body 61 to the first source region 35A. The second source region 35B is the region in contact with the insulating film 27 (see Figure 4) of the gate structure 25.

[0391] The bottom of the first source region 35A is located closer to the bottom of the body region 23 than the bottom of the second source region 35B. The bottom of the second source region 35B may be located closer to the first main surface 20S than the bottom surface 61B of the contact body 61. The bottom of the first source region 35A may be located closer to the bottom of the body region 23 than the bottom surface 61B of the contact body 61.

[0392] The contact area 65 is in contact with the bottom surface 61B and a part of the corner portion 61C of the contact body 61. The contact area 65 is in contact with the first source area 35A and is spaced apart from the second source area 35B.

[0393] - In the first, third, and fourth embodiments, the width WD of the contact area 65 may be less than or equal to the opening width WS of the source opening 40A. - In the first, third, and fourth embodiments, the contact area 65 may be in contact only with the bottom surface 61B of the contact portion 60 (contact body 61). In this case, the corner portion 61C and the side surface 61A of the contact portion 60 are in contact with the source area 35.

[0394] - In the third embodiment, the configuration of the chip 20 can be arbitrarily changed. For example, as shown in Figure 49, multiple well regions 30 may be omitted from the chip 20. - In the first, third, and fourth embodiments, the contact region 65 may be omitted from the chip 20.

[0395] In the first, third, and fourth embodiments, the configuration of the contact area 65 can be arbitrarily changed. For example, the contact area 65 may be in contact with a part of the side surface 61A in addition to the bottom surface 61B and corner portion 61C of the contact portion 60.

[0396] (Examples of gate structure modification) In the fourth embodiment, the configuration of the gate structure 80 can be arbitrarily changed. The gate structure 80 may be modified as shown in the first to third modification examples in Figures 50 to 52, for example.

[0397] As shown in Figure 50, in the gate structure 80 of the first modified example, the multiple trenches 81 may be arranged in a single row with spacing in the Y direction. In other words, in one gate structure 80, the multiple trenches 81 are not arranged with spacing in the X direction. In this case, the multiple embedded electrode portions 83A of the gate electrode 83 are arranged in a single row with spacing in the Y direction.

[0398] As shown in Figure 51, in the gate structure 80 of the second modified example, the multiple trenches 81 may be arranged in a staggered pattern in a plan view. In this case, the multiple embedded electrode portions 83A are arranged in a staggered pattern in a plan view. Also, as shown in Figure 51, multiple adjacent trenches 81 in the X direction may include portions that overlap each other when viewed from the X direction. Although not shown, multiple adjacent trenches 81 in the X direction may be arranged with a gap in the Y direction so that they do not overlap each other when viewed from the X direction.

[0399] As shown in Figure 52, in the gate structure 80 of the third modified example, each trench 81 may be circular in shape in plan view. In the example shown in Figure 52, the multiple trenches 81 are arranged in a staggered pattern in plan view. In this case, each embedded electrode portion 83A is circular in shape in plan view. Note that the shape of each trench 81 in plan view can be arbitrarily changed. In one example, each trench 81 may be elliptical, a polygon with more than one triangle, or an oval in shape in plan view. Also, in the gate structure 80 of the third modified example, the multiple trenches 81 may be arranged in a matrix in plan view.

[0400] As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, for example, the expression “the first element is positioned on the second element” is intended to mean that in one embodiment the first element may be in contact with and directly positioned on the second element, while in other embodiments the first element may be positioned above the second element without contact. In other words, the term “on” does not preclude structures in which other elements are formed between the first and second elements.

[0401] The Z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to perfectly coincide with the vertical. Therefore, the various structures described herein are not limited to the "up" and "down" in the Z-axis direction being the same as the "up" and "down" in the vertical direction. For example, the X-direction may be vertical, or the Y-direction may be vertical.

[0402] <Note> The technical concepts that can be grasped from this disclosure are described below. Not intended to be limiting, but to aid understanding, the components described in this note are denoted by the corresponding reference numerals of the components in the embodiments described above. The reference numerals are provided as examples to aid understanding, and the components described in each note should not be limited to those indicated by the reference numerals.

[0403] [Note 1] A semiconductor device (10) comprising: a semiconductor layer (20) made of SiC and including a main surface (20S); a body region (23) provided on the surface of the semiconductor layer (20); a source region (35) provided on the surface of the body region (23); an insulating layer (40) having a main surface insulating film (41) covering the main surface (20S) and a source opening (40A) that exposes the semiconductor layer (20); a source electrode (51) provided on the insulating layer (40); and a contact portion (60) provided so as to be exposed from the source opening (40A) in a plan view viewed from the thickness direction (Z) of the semiconductor layer (20), and in contact with both the source electrode (51) and the source region (35), wherein the contact portion (60) penetrates the source region (35).

[0404] [Note 2] The semiconductor device described in Note 1, wherein the contact portion (60) is made of silicide.

[0405] [Note 3] The semiconductor device according to Note 1 or 2, wherein the contact portion (60) is made of a different material from the source electrode (51).

[0406] [Note 4] The semiconductor device according to any one of Notes 1 to 3, wherein the width (WC) of the contact portion (60) is greater than the opening width (WS) of the source aperture (40A).

[0407] [Note 5] The semiconductor device according to Note 4, wherein the source region (35) is located outward from the source aperture (40A) in the plan view.

[0408] [Note 6] The semiconductor device according to any one of Notes 1 to 5, wherein the thickness (TC) of the contact portion (60) is equal to or greater than the width (WC) of the contact portion (60).

[0409] [Note 7] The semiconductor device according to any one of Notes 1 to 6, wherein the width (WC) of the contact portion (60) is greater than the distance between the main surface (20S) of the semiconductor layer (20) and the bottom surface (61B) of the contact portion (60).

[0410] [Note 8] The contact portion (60) includes a side surface (61A), a bottom surface (61B), and a corner portion (61C) provided between the side surface (61A) and the bottom surface (61B), wherein the corner portion (61C) is curved and convex outward, as described in any one of Notes 1 to 7.

[0411] [Note 9] The semiconductor device according to any one of Notes 1 to 8, wherein the side surface (61A) of the contact portion (60) is tapered so as it approaches the main surface (20S) of the semiconductor layer (20) so as to move away from each other.

[0412] [Supplementary Note 10] The semiconductor device according to any one of Supplementary Notes 1 to 9, wherein the contact portion (60) contains at least one selected from the group consisting of nickel, titanium, molybdenum, tantalum, tungsten, and vanadium.

[0413] [Supplementary Note 11] The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein a thickness (TS) of the source region (35) is ½ or more of an opening width (WS) of the source opening (40A).

[0414] [Supplementary Note 12] The semiconductor device according to any one of Supplementary Notes 1 to 11, further comprising a contact region (65) provided in the semiconductor layer (20) and in contact with a bottom surface (61B) of the contact portion (60), wherein an impurity concentration of the contact region (65) is higher than an impurity concentration of the body region (23).

[0415] [Supplementary Note 13] The semiconductor device according to Supplementary Note 12, wherein in the planar view, a width (WD) of the contact region (65) is larger than the opening width (WS) of the source opening (40A).

[0416] [Supplementary Note 14] The semiconductor device according to Supplementary Note 12 or 13, wherein the contact region (65) is in contact with both the bottom surface (61B) and a corner portion (61C) of the contact portion (60).

[0417] [Supplementary Note 15] The semiconductor device according to Supplementary Note 14, wherein the contact region (65) is further in contact with a side surface (61A) of the contact portion (60).

[0418] [Supplementary Note 16] The semiconductor device according to any one of Supplementary Notes 12 to 15, wherein the contact region (65) is provided spaced apart from the main surface (20S) in the thickness direction (Z).

[0419] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 1 to 16, wherein the contact portion (60) includes: a contact body (61) provided in the semiconductor layer (20); and a protruding portion (62) provided on the main surface (20S).

[0420] [Note 18] The semiconductor device according to Note 17, wherein the thickness (TB) of the contact body (61) is greater than the thickness (TP) of the protrusion (62).

[0421] [Note 19] The semiconductor device according to any one of Notes 1 to 18, wherein the contact portions (60) are provided in a plurality of locations spaced apart from each other in a first direction in the plan view, and the contact portions (60) extend in a second direction perpendicular to the first direction in the plan view.

[0422] [Note 20] The semiconductor device according to Note 19, wherein the contact portions (60) are provided in a plurality of locations separated from each other in the second direction in the plan view, and the source electrode (51) is inserted into the intercontact region (66), which is the region between adjacent contact portions (60) in the second direction.

[0423] [Note 21] The semiconductor device according to Note 20, wherein the end (64) of the contact portion (60) in the second direction includes an end bulge (64A), the end bulge (64A) is provided within the semiconductor layer (20) and is exposed from the main surface (20S), and the source electrode (51) is in contact with the portion of the end bulge (64A) that is exposed from the main surface (20S).

[0424] [Note 22] The insulating layer (40) includes an insulating side surface (40AA) that constitutes the source opening (40A), the insulating side surface (40AA) is tapered such that the opening width (WS) of the source opening (40A) decreases as it approaches the main surface (20S) of the semiconductor layer (20), and the inclination angle (θ1) of the side surface (61A) of the contact portion (60) is greater than the inclination angle (θ2) of the insulating side surface (40AA), the semiconductor device according to any one of Notes 1 to 21.

[0425] [Note 23] The semiconductor device according to Note 17 or 18, wherein the thickness (TB) of the contact body (61) is 0.01 μm or more and 0.5 μm or less.

[0426] [Note 24] The semiconductor device according to any one of Notes 1 to 23, wherein the thickness (TC) of the contact portion (60) is 0.01 μm or more and 0.5 μm or less.

[0427] [Note 25] The semiconductor device according to any one of Notes 1 to 23, wherein the source electrode (51) includes a first metal film (50A) in contact with the contact portion (60), a second metal film (50B) provided on the first metal film (50A), and a third metal film (50C) provided on the second metal film (50B), the first metal film (50A) contains titanium, the second metal film (50B) contains titanium nitride, and the third metal film (50C) contains aluminum copper.

[0428] [Note 26] A semiconductor device according to any one of Notes 1 to 25, comprising: a trench (26) extending from the main surface (20S) of the semiconductor layer (20) so as to penetrate the body region (23); an insulating film (27) provided within the trench (26); and a gate electrode (28) embedded within the insulating film (27) in the trench (26), wherein a plurality of trenches (26) are provided spaced apart in a first direction in the plan view, the plurality of trenches (26) extend in a second direction perpendicular to the first direction in the plan view, and the contact portion (60) is provided between each of the plurality of trenches (26) in the first direction.

[0429] [Note 27] A semiconductor device according to any one of Notes 1 to 25, comprising a planar structure including an insulating film (74) provided on the main surface (20S) and a gate electrode (75) provided on the insulating film (74), wherein a plurality of source regions (35) are provided spaced apart in a first direction in the plan view, the plurality of source regions (35) extend in a second direction perpendicular to the first direction in the plan view, and the contact portion (60) is provided at a position different from the gate electrode (75) in the plan view and extends in the second direction.

[0430] [Note 28] The contact portion (60) is provided in a plurality of locations spaced apart in the first direction in the plan view, and is provided between adjacent contact portions (60) in the first direction, and includes a plurality of trenches (81) extending from the main surface (20S) of the semiconductor layer (20) to penetrate the body region (23), an insulating film (82) provided in each of the trenches (81), and a gate electrode (83) embedded in the insulating film (82) in each of the trenches (81), wherein the plurality of trenches (81) are arranged spaced apart in the first direction, and the gate electrode (83) includes embedded electrode portions (83A) provided in each of the plurality of trenches (81), and an electrode connection portion (83B) located on the main surface (20S) and connecting the plurality of embedded electrode portions (83A), The semiconductor device according to any one of the appendices 1 to 25, wherein the source region (35) extends continuously around the plurality of trenches (81) at least below the electrode connection portion (83B), and the contact portion (60) is in contact with the source region (35) at a position away from the electrode connection portion (83B).

[0431] [Note 29] The semiconductor device according to Note 28, wherein the distance (DX) between adjacent trenches (81) in the first direction is smaller than the distance (DA) between adjacent trenches (81) in the first direction with the contact portion (60) in between.

[0432] [Note 30] The semiconductor device according to Note 28 or 29, wherein the plurality of trenches (81) are arranged with spacing between them in both the first and second directions, with the direction perpendicular to the first direction in the plan view being the second direction.

[0433] [Note 31] The semiconductor device according to any one of Notes 28 to 30, wherein the plurality of trenches (81) extend in the direction perpendicular to the first direction in the plan view, with respect to the second direction.

[0434] [Note 32] The contact portion (60) is provided in a plurality of locations spaced apart in a first direction in the plan view, and is provided between adjacent contact portions (60) in the first direction, and includes a plurality of trenches (81) extending from the main surface (20S) of the semiconductor layer (20) to penetrate the body region (23), an insulating film (82) provided in each of the trenches (81), and a gate electrode (83) embedded in the insulating film (82) in each of the trenches (81), wherein the plurality of trenches (81) are spaced apart in a second direction perpendicular to the first direction in the plan view, and the gate electrode (83) includes embedded electrode portions (83A) provided in each of the plurality of trenches (81), and an electrode connection portion (83B) located on the main surface (20S) and connecting the plurality of embedded electrode portions (83A), The semiconductor device according to any one of the appendices 1 to 25, wherein the source region (35) extends continuously around the plurality of trenches (81) at least below the electrode connection portion (83B), and the contact portion (60) is in contact with the source region (35) at a position away from the electrode connection portion (83B).

[0435] [Note 33] A semiconductor layer (20) made of SiC, including a main surface (20S); a body region (23) provided on the surface of the semiconductor layer (20); a source region (35) provided on the surface of the body region (23) and exposed from the main surface (20S); a trench (26) extending from the main surface (20S) through the body region (23); a contact region (65) surrounding the side and bottom walls of the trench (26) and partially exposed to the main surface (20S); an insulating film (27) provided in the trench (26); a gate electrode (28) embedded in the insulating film (27) in the trench (26); an insulating layer (40) covering the main surface (20S) and having a source opening (40A) that opens to the source region (35); a source electrode (51) provided on the insulating layer (40), A semiconductor device (10) comprising: a contact portion (60) provided in an exposed area from the source opening (40A) in a plan view as seen from the thickness direction (Z) of the semiconductor layer (20), and in contact with both the source electrode (51) and the source region (35) and the contact region (65), wherein the contact portion (60) extends from the main surface (20S) toward the body region (23) and includes a side surface (61A) in contact with both the source region (35) and the contact region (65).

[0436] [Note 34] The semiconductor device according to Note 33, wherein the contact region (65) includes: a first region (65A) covering the bottom wall of the trench (26); a second region (65B) in contact with the side wall of the trench (26) and extending along the side wall; and a third region (65C) exposed from the main surface (20S), wherein the second region (65B) connects the first region (65A) and the body region (23), the third region (65C) is connected to the second region (65B), and the side surface (61A) of the contact portion (60) is in contact with the third region (65C).

[0437] [Note 35] The semiconductor device according to Note 34, wherein the source region (35) and the third region (65C) are arranged side by side in the direction of extension of the contact portion (60) in the plan view.

[0438] [Note 36] The semiconductor device according to any one of Notes 33 to 35, wherein the bottom surface (61B) of the contact portion (60) is in contact with the source region (35).

[0439] [Note 37] The method comprises: forming a body region (23) on a semiconductor layer (20 / 800) made of SiC, including a main surface (20S); forming a source region (35) on the surface of the body region (23); forming an insulating layer (40) having a main surface insulating film (41) covering the main surface (20S) and a source opening (40A) that exposes the semiconductor layer (20 / 800); forming a contact portion (60) so as to be exposed from the source opening (40A) in a plan view viewed from the thickness direction (Z) of the semiconductor layer (20 / 800); and forming a source electrode (51) on the insulating layer (40) so as to be in contact with the contact portion (60), wherein the formation of the contact portion (60) involves forming a metal film (810) on the insulating layer (40) and within the source opening (40A); and diffusing the metal film (810) into the semiconductor layer (20 / 800). A method for manufacturing a semiconductor device, comprising the diffused contact portion (60) being in contact with both the source electrode (51) and the source region (35).

[0440] [Note 38] The method for manufacturing a semiconductor device according to Note 37, wherein diffusing the metal film (810) into the semiconductor layer (20 / 800) includes: performing a first heat treatment on the metal film (810); removing unnecessary portions of the metal film (810); and performing a second heat treatment on the metal film (810).

[0441] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims.

[0442] 10...Semiconductor device, 11...Active region, 12...Peripheral region, 20...Chip, 20S...First main surface, 20R...Second main surface, 20A-20D...First to fourth side surfaces, 21...First semiconductor layer, 22...Second semiconductor layer, 23...Body region, 24...Channel region, 25...Gate structure, 26...Trench, 27...Insulating film, 28...Buried electrode, 29...Mesa region, 30...Well region, 30A...First well region, 30B...Second well region, 31...First pillar region, 31U...First upper region, 31L...First lower region, 31B...First bottom, 32...Second pillar region, 32U...Second upper region, 32L...Second lower region Region, 32B...Second bottom, 33...Mesh region, 34...Intermesh region, 35...Source region, 35A...First source region, 35B...Second source region, 36...Cap region, 36A...First cap region, 36B...Second cap region, 37...Outer well region, 38...Outer contact region, 39...Field region, 40...Insulating layer, 41...Main surface insulating film, 42...Interlayer film, 40A...Source opening, 40AA...Insulating side, 40B...Gate opening, 40C...Outer opening, 43...Gate wiring, 44...Uppermost film, 44A...Source pad opening, 44AA...First source pad opening, 44AB ...Second source pad opening, 44AC...Third source pad opening, 44B...Gate pad opening, 45...Inorganic film, 46...Organic film, 50...First electrode, 50A...First metal film, 50B...Second metal film, 50C...Third metal film, 51...Source electrode, 51A...Main source electrode, 51B...First sub-source electrode, 51C...Second sub-source electrode, 52...Source finger electrode, 53...Gate electrode, 54...Gate finger electrode, 55...Drain electrode, 60...Contact part, 61...Contact body, 61A...Side, 61B...Bottom, 61C...Corner part, 62...Protruding part, 62A...Top, 6 2B...side, 62C...corner portion, 63...bulge portion, 64...end, 64A...end bulge portion, 64AA...side, 64AB...corner portion, 64AC...top, 64B...end face, 65...contact region, 65A...first region, 65B...second region, 65C...third region, 66...inter-contact region, 67...outer contact portion, 71...surface drift region, 72...channel region, 73...gate structure, 74...planar insulating film, 75...gate electrode, 80...gate structure, 81...trench, 82...insulating film, 83...gate electrode, 83A...embedded electrode portion, 83B...electrode connection portion, 91...pillar region92...Channel region, 800...Wafer, 810...Metal film, Tr...Transistor structure, Cr1...First intersection, Cr2...Second intersection, Ch1...First channel, Ch2...Second channel, RA...Overlap region, LR...Length of inter-contact region, LT...Trench length, T1...Thickness of first semiconductor layer, T2...Thickness of second semiconductor layer, TC...Thickness of contact portion, TB...Thickness of contact body, TP...Thickness of protrusion, TS...Thickness of source region, TD...Thickness of third region, WC...Width of contact portion, WD...Con Cycle width, WE... Source width, WS... Source opening width, WA... Bulge width of bulge, WT... Trench width, T1... First thickness of the first semiconductor layer, T2... Second thickness of the second semiconductor layer, DA... Distance between adjacent trenches in the X direction across the contact area, DG... Distance between adjacent gate structures in the X direction, DX... Distance between adjacent trenches in the X direction, DY... Distance between adjacent trenches in the Y direction, θ1... Inclination angle of the side surface of the contact area, θ2... Inclination angle of the insulating side surface constituting the source opening.

Claims

1. A semiconductor device comprising: a semiconductor layer made of SiC and including a main surface; a body region provided on the surface of the semiconductor layer; a source region provided on the surface of the body region; an insulating layer having a main surface insulating film covering the main surface and a source opening that exposes the semiconductor layer; a source electrode provided on the insulating layer; and a contact portion provided so as to be exposed from the source opening in a plan view taken from the thickness direction of the semiconductor layer, and in contact with both the source electrode and the source region, wherein the contact portion penetrates the source region.

2. The semiconductor device according to claim 1, wherein the contact portion is made of silicide.

3. The semiconductor device according to claim 1 or 2, wherein the contact portion is made of a different material from the source electrode.

4. The semiconductor device according to any one of claims 1 to 3, wherein the width of the contact portion is greater than the opening width of the source aperture.

5. The semiconductor device according to claim 4, wherein the source region is located outward from the source aperture in the plan view.

6. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the contact portion is equal to or greater than the width of the contact portion.

7. The semiconductor device according to any one of claims 1 to 6, wherein the width of the contact portion is greater than the distance between the main surface of the semiconductor layer and the bottom surface of the contact portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein the contact portion includes a side surface, a bottom surface, and a corner portion provided between the side surface and the bottom surface, and the corner portion is curved in a convex shape outward.

9. The semiconductor device according to any one of claims 1 to 8, wherein the side surfaces of the contact portion are tapered in shape so as they move away from each other toward the main surface of the semiconductor layer.

10. The semiconductor device according to any one of claims 1 to 9, wherein the contact portion comprises at least one of nickel, titanium, molybdenum, tantalum, tungsten, and vanadium.

11. The semiconductor device according to any one of claims 1 to 10, wherein the thickness of the source region is 1 / 2 or more of the opening width of the source aperture.

12. The semiconductor device according to any one of claims 1 to 11, comprising a contact region provided within the semiconductor layer and in contact with the bottom surface of the contact portion, wherein the impurity concentration of the contact region is higher than that of the body region.

13. The semiconductor device according to claim 12, wherein, in the plan view, the width of the contact region is greater than the aperture width of the source aperture.

14. The semiconductor device according to claim 12 or 13, wherein the contact area is in contact with both the bottom surface and the corner portion of the contact part.

15. The semiconductor device according to claim 14, wherein the contact area is further in contact with the side surface of the contact portion.

16. The semiconductor device according to any one of claims 12 to 15, wherein the contact area is provided at a distance from the main surface in the thickness direction.

17. The semiconductor device according to any one of claims 1 to 16, wherein the contact portion includes a contact body provided in the semiconductor layer and a protruding portion provided on the main surface.

18. The semiconductor device according to claim 17, wherein the thickness of the contact body is greater than the thickness of the protruding portion.

19. The semiconductor device according to any one of claims 1 to 18, wherein a plurality of contact portions are provided spaced apart from each other in a first direction in a plan view, and the contact portions extend in a second direction perpendicular to the first direction in a plan view.

20. The semiconductor device according to claim 19, wherein a plurality of contact portions are provided spaced apart from each other in the second direction in the plan view, and the source electrode is inserted into the intercontact region, which is the region between adjacent contact portions in the second direction.

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