Electronic component and method for manufacturing same

Abstract

This electronic component includes: a coating body; and a metal film which is disposed on the coating body, which includes a metal surface formed by a plurality of metal crystal grains, and in which the median value of the planar area per unit area of the plurality of metal crystal grains is less than 10 μm2.

Description

Electronic components and methods for manufacturing the same

[0001] This application claims priority under Japanese Patent Application No. 2025-032303, filed with the Japan Patent Office on 28 February 2025, the entire contents of which are incorporated herein by reference. This disclosure relates to an electronic component and a method for manufacturing the same.

[0002] Patent document 1 (US2015 / 206967A1) discloses a semiconductor device comprising a semiconductor substrate, an interlayer insulating film, a gate electrode pad, and a source electrode pad. The interlayer insulating film covers the semiconductor substrate. The gate electrode pad is located on the interlayer insulating film. The source electrode pad is located on the interlayer insulating film at a distance from the gate electrode pad.

[0003] U.S. Patent Application Publication No. 2015 / 206967

[0004] [Summary] This disclosure provides an electronic component having a metal film with excellent surface condition and a method for manufacturing the same.

[0005] This disclosure includes a coating body and a metal surface disposed on the coating body and formed by a plurality of metal crystal grains, wherein the median flat area per unit area of ​​the plurality of metal crystal grains is 10 μm ２ The present invention provides an electronic component comprising a metal film that is less than [amount missing].

[0006] This disclosure provides an electronic component comprising a coating body and a metal film covering the coating body and having a metal surface extending along the coating body, wherein the metal film comprises a first metal film formed on the coating body side having a first metal crystal density per unit area and a second metal film formed on the metal surface side having a second metal crystal density higher than the first metal crystal density per unit area.

[0007] This disclosure describes a method in which the median planar area per unit area of ​​multiple metal crystal grains is 10 μm by sputtering at a temperature of 300°C or less. ２ The present invention provides a method for manufacturing electronic components, which includes a step of forming a metal film having a metal surface less than 1 / 2 on a film-forming substrate.

[0008] This disclosure provides a method for manufacturing an electronic component, comprising the steps of: forming a first base metal film having a first metal crystal density per unit area on a workpiece by sputtering at a first temperature; forming a second base metal film having a second metal crystal density higher than the first metal crystal density per unit area on the first base metal film by sputtering at a second temperature below the first temperature; and removing unnecessary portions of the first base metal film and the second base metal film to form a metal film having a laminated structure including a first metal film made from a part of the first base metal film and a second metal film made from a part of the second base metal film.

[0009] The aforementioned or any other purposes, features, and effects will be revealed in the detailed description with reference to the attached drawings.

[0010] Figure 1 is a plan view showing a semiconductor device (electronic component) according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface. Figure 4 is an enlarged plan view showing a key part of the active region. Figure 5 is a cross-sectional view along the line VV shown in Figure 4. Figure 6 is an enlarged cross-sectional view of a key part shown in Figure 5. Figure 7 is a plan view showing an example of the layout of the gate wiring. Figure 8 is a plan view showing an example of the layout of the interlayer film. Figure 9 is a plan view showing an example of the layout of the gate metal film, source metal film, and gate wiring metal film. Figure 10 is an enlarged plan view showing an example of the layout of the gate metal film. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 10. Figure 13 is an enlarged cross-sectional view showing a key part of the gate metal film shown in Figure 12. Figure 14 is a graph to explain the relationship between crystal density and temperature. Figure 15 is a diagram to explain the relationship between crystal density and temperature. Figure 16 is a cross-sectional view illustrating the gate metal film. Figure 17 is a diagram illustrating the relationship between crystal density and the surface state of the gate upper metal film. Figure 18 is a schematic diagram showing a wafer structure used in the manufacture of a semiconductor device. Figure 19A is a cross-sectional view showing an example of a manufacturing method for the semiconductor device shown in Figure 1. Figure 19B is a cross-sectional view showing a process after Figure 19A. Figure 19C is a cross-sectional view showing a process after Figure 19B. Figure 19D is a cross-sectional view showing a process after Figure 19C. Figure 19E is a cross-sectional view showing a process after Figure 19D. Figure 19F is a cross-sectional view showing a process after Figure 19E. Figure 19G is a cross-sectional view showing a process after Figure 19F. Figure 19H is a cross-sectional view showing a process after Figure 19G. Figure 19I is a cross-sectional view showing a process after Figure 19H. Figure 19J is a cross-sectional view showing a process after Figure 19I. Figure 19K is a cross-sectional view showing a process after Figure 19J. Figure 19L is a cross-sectional view showing a process after Figure 19K. Figure 20 is an enlarged cross-sectional view showing the process of forming the first metal film. Figure 21 is an enlarged cross-sectional view showing the process of forming the second metal film. Figure 22 is an enlarged cross-sectional view showing the process of forming the oxide film. Figure 23 is an enlarged cross-sectional view showing the process of removing the oxide film. Figure 24 is an enlarged cross-sectional view showing the process of forming the upper electrode. Figure 25 is an enlarged cross-sectional view showing the process of forming the oxide film according to a reference example.Figure 26 is an enlarged cross-sectional view showing the oxide film removal process according to a reference example. Figure 27 is an enlarged cross-sectional view showing the upper electrode formation process according to a reference example. Figure 28 is an enlarged plan view showing the pad area of ​​the semiconductor device according to the second embodiment. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 28. Figure 30 is a cross-sectional view showing the semiconductor device according to the third embodiment. Figure 31 is an enlarged cross-sectional view of a key part shown in Figure 30. Figure 32 is a plan view showing the semiconductor device according to the fourth embodiment. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. Figure 34 is a plan view showing the layout of the first main metal film shown in Figure 33. Figure 35 is an enlarged cross-sectional view showing a key part of the first main metal film shown in Figure 33.

[0011] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0012] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0013] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0014] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0015] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0016] Figure 1 is a plan view showing a semiconductor device 1A according to the present disclosure. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface 3. Figure 4 is an enlarged plan view showing a key part of the active region 8. Figure 5 is a cross-sectional view taken along the line VV shown in Figure 4. Figure 6 is an enlarged cross-sectional view of a key part shown in Figure 5. Figure 7 is a plan view showing an example of the layout of the gate wiring 23.

[0017] Referring to Figures 1 to 7, semiconductor device 1A is a semiconductor switching device as an example of an electronic component having an insulated gate type transistor structure T as an example of a device structure (functional device). In this embodiment, the transistor structure T is a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure and has a trench gate type vertical structure.

[0018] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). The chip 2 includes either a single crystal of Si (silicon) or a single crystal of a wide-bandgap semiconductor, or both. A wide-bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si. Examples of wide-bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).

[0019] In this embodiment, chip 2 includes a single crystal of a wide-bandgap semiconductor. Chip 2 may also be referred to as a "semiconductor chip," a "wide-bandgap semiconductor chip," etc. Semiconductor device 1A may also be referred to as a "wide-bandgap semiconductor device." In this embodiment, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device."

[0020] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0021] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a rectangular shape when viewed in plan from the thickness direction Z of the chip 2 (hereinafter simply referred to as "plan view"). The thickness direction Z is also the normal direction (vertical direction) to the first main surface 3 and the second main surface 4.

[0022] The first main surface 3 and the second main surface 4 are formed by the c-planes of the SiC single crystal. The first main surface 3 may be formed by the silicon plane ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by the carbon plane ((000-1) plane) of the SiC single crystal.

[0023] The first side surface 5A extends in the first direction X. The second side surface 5B is connected to the first side surface 5A and extends in the second direction Y, which intersects (specifically, is perpendicular to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0024] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Alternatively, the first direction X may be the a-axis direction and the second direction Y may be the m-axis direction. Alternatively, the first direction X may be a direction that intersects both the a-axis and m-axis directions, and the second direction Y may be a direction that intersects both the a-axis and m-axis directions.

[0025] The chip 2 (first main surface 3 and second main surface 4) has an off-angle that is inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. In other words, the c-axis ((0001) axis) of the SiC single crystal is inclined by the amount of the off-angle from the thickness direction Z (vertical line) toward the off-direction. The off-direction is preferably the a-axis direction (i.e., the second direction Y) of the SiC single crystal. The off-direction may also be the m-axis direction of the SiC single crystal.

[0026] The off-angle may be greater than 0° and less than or equal to 10°. The off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.

[0027] The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less. The off-angle is typically set in the range of 4° ± 0.1°. This specification does not exclude a configuration in which the off-angle is 0° (i.e., a configuration in which the first principal surface 3 is just plane to the c-plane).

[0028] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in the region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as the "first layer (region)," the "drain layer (region)," etc. The first semiconductor layer 6 extends in layers along the second main surface 4 and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D. The n-type impurity concentration of the first semiconductor layer 6 may be approximately constant in the thickness direction Z.

[0029] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0030] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 100 μm or less, 100 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0031] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)", "drain layer (region)", "drift layer (region)", etc.

[0032] The second semiconductor layer 7 has a lower n-type impurity concentration than the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z. The n-type impurity concentration of the second semiconductor layer 7 may increase from the first semiconductor layer 6 side toward the first main surface 3 side.

[0033] The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0034] The second semiconductor layer 7 contains a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a semiconductor layer (SiC layer) containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0035] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or more and 25 μm or less.

[0036] The semiconductor device 1A includes an active region 8 provided on the first main surface 3. The active region 8 includes a transistor structure T (device structure) and is a region where drain current (output current) is generated. The active region 8 is provided in the inner part of the first main surface 3, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.

[0037] In this configuration, the active region 8 is set to have a polygonal shape with four sides parallel to the periphery of the first main surface 3 in a plan view. Specifically, the active region 8 is set to have a polygonal shape with a rectangular recess that curves toward the third side surface 5C in a portion along the center of the first side surface 5A in a plan view.

[0038] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0039] The semiconductor device 1A includes a non-active region 9 located outside the active region 8 on the first main surface 3. The non-active region 9 is a region that does not include the transistor structure T (device structure) and is located around the active region 8. In this embodiment, the non-active region 9 includes a pad region 9a and an outer region 9b. The pad region 9a may be referred to as the "first non-active region," and the outer region 9b may be referred to as the "second non-active region."

[0040] The pad area 9a is located in the area on the first side surface 5A side in a plan view. Specifically, the pad area 9a is located along the central part of the first side surface 5A, is demarcated by a recess in the active area 8, and is sandwiched from both sides in the first direction X by the ends of the active area 8. In a plan view, the pad area 9a is demarcated in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.

[0041] The outer region 9b extends in a band shape along the first to fourth sides 5A to 5D in a plan view and is provided in a polygonal ring shape (a quadrilateral ring in this form) surrounding the active region 8. The outer region 9b is connected to the pad region 9a on the side of the first side 5A.

[0042] The semiconductor device 1A includes a p-type body region 10 formed in the second semiconductor layer 7 in the inner part of the first main surface 3. The body region 10 may also be called an "impurity region," etc. The body region 10 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0043] The body region 10 is formed in the active region 8, spaced apart from the periphery of the first main surface 3, and is not formed in the inactive region 9. In this configuration, the body region 10 is formed on the surface layer of the first main surface 3 across the entire area of ​​the active region 8.

[0044] The body region 10 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The body region 10 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0045] The semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 11 formed in the inner portion (active region 8) of the first main surface 3. The gate structures 11 may also be referred to as "trench structures," "trench gate structures," etc.

[0046] Multiple gate structures 11 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but not in the inactive region 9. Multiple gate structures 11 penetrate the body region 10 and are formed at intervals from the bottom of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3. Multiple gate structures 11 are formed at intervals from an intermediate depth position in the second semiconductor layer 7 toward the first main surface 3.

[0047] The multiple gate structures 11 each extend in a strip-like manner in the first direction X when viewed from above, and are arranged with gaps in the second direction Y. In other words, the multiple gate structures 11 extend in a strip-like manner in the first direction X when viewed from above, and divide the first main surface 3 (second semiconductor layer 7) into multiple mesa portions 12. The multiple mesa portions 12 each extend in a strip-like manner in the first direction X, following the layout of the multiple gate structures 11, and are divided with gaps in the second direction Y.

[0048] The multiple gate structures 11 have long sides (sides) formed by the m-plane ((1-100) plane) of the SiC single crystal, and short sides (sides) formed by the a-plane ((11-20) plane) of the SiC single crystal. Depending on the extension direction of the multiple gate structures 11, the long sides may be formed by the m-plane and the short sides may be formed by the a-plane.

[0049] The sides of the multiple gate structures 11 are formed almost perpendicular to the first main surface 3. The sides of the multiple gate structures 11 may be inclined at an angle to the first main surface 3. In other words, the multiple gate structures 11 may be formed in a tapered shape toward the second main surface 4.

[0050] The bottom surfaces of the multiple gate structures 11 are formed by the c-planes (Si planes) of the SiC single crystal. The bottom surfaces of the multiple gate structures 11 may extend in a nearly flat manner. The bottom surfaces of the multiple gate structures 11 may be curved in an arc shape toward the second main surface 4.

[0051] The gate structure 11 may have a depth greater than 0 μm and 3 μm or less. The depth of the gate structure 11 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0052] The depth of the gate structure 11 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0053] The gate structure 11 may have a width greater than 0 μm and 3 μm or less. The width of the gate structure 11 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0054] The width of the gate structure 11 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0055] The spacing between the multiple gate structures 11 (the width of the mesa portion 12) may be greater than the width of the gate structure 11. The spacing between the gate structures 11 may be less than the width of the gate structure 11. The spacing between the gate structures 11 may be greater than 0 μm and 3 μm or less. The spacing between the gate structures 11 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0056] The spacing of the gate structure 11 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0057] The multiple gate structures 11 each include a trench 13, an insulating film 14, and an embedded electrode 15. The trench 13 may be referred to as a "gate trench," the insulating film 14 as a "gate insulating film," and the embedded electrode 15 as a "gate embedded electrode." The trench 13 is formed on the first main surface 3 and demarcates the wall surfaces (sides and bottom surfaces) of the gate structure 11.

[0058] The insulating film 14 may have a single-layer structure or a multilayer structure comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 14 may also include at least one of the oxide film of the chip 2 (second semiconductor layer 7) and oxide films other than the oxide film of the chip 2.

[0059] The insulating film 14 coats the walls (sides and bottom) of the trench 13 in a film-like manner. The insulating film 14 may cover the walls of the trench 13 with a uniform thickness. The thickness of the insulating film 14 covering the bottom of the trench 13 may be greater than the thickness of the insulating film 14 covering the sides of the trench 13.

[0060] The thickness of the insulating film 14 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 14 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 250 nm or less.

[0061] The embedded electrode 15 includes either a metal or a non-metallic conductor (a conductor other than metal), or both. In this embodiment, the embedded electrode 15 includes conductive polysilicon. The embedded electrode 15 may include either a p-type conductive polysilicon or an n-type conductive polysilicon, or both.

[0062] The embedded electrode 15 is embedded in the trench 13 via an insulating film 14. The embedded electrode 15 has an electrode surface located on the bottom side of the trench 13 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 13. The electrode surface may have a recess toward the bottom side.

[0063] The semiconductor device 1A includes a plurality of n-type source regions 16 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The source regions 16 may also be referred to as "impurity regions," etc. The source regions 16 have an n-type impurity concentration higher than the p-type impurity concentration of the body region 10. The n-type impurity concentration of the source regions 16 is higher than the n-type impurity concentration of the second semiconductor layer 7.

[0064] In this configuration, the multiple source regions 16 are each formed in the surface layer of the body region 10, along the multiple gate structures 11. Specifically, the multiple source regions 16 are formed on both sides of the multiple gate structures 11, spaced apart from the bottom of the body region 10 toward the first main surface 3, and each demarcates a channel along the multiple gate structures 11 within the body region 10.

[0065] In this configuration, the multiple source regions 16 each extend in a strip-like manner in the first direction X, following the direction of extension of the multiple gate structures 11. The multiple source regions 16 are connected to the multiple gate structures 11 in the second direction Y and face the embedded electrodes 15 via an insulating film 14.

[0066] Of course, the multiple source regions 16 may be formed at intervals in the first direction X in the region (mesa portion 12) between the multiple gate structures 11. In this case, the multiple source regions 16 may each extend in a strip shape in the first direction X.

[0067] The semiconductor device 1A includes a plurality of p-type contact regions 17 formed in the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The contact regions 17 may also be referred to as "impurity regions," etc. The contact regions 17 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10.

[0068] In this configuration, the multiple contact regions 17 are each interposed in the regions between multiple adjacent source regions 16 in the second direction Y, and each extends in a strip-like manner in the first direction X, following the direction of extension of the multiple gate structures 11. The multiple contact regions 17 face a corresponding gate structure 11 via a single source region 16 corresponding to the second direction Y.

[0069] If multiple source regions 16 are formed at intervals in the first direction X, multiple contact regions 17 may be formed alternately with the multiple source regions 16 in the first direction X. In this case, the multiple contact regions 17 may each extend in a strip-like shape in the first direction X.

[0070] In this embodiment, the multiple contact regions 17 are formed on the surface of the body region 10 at intervals from the multiple gate structures 11. The multiple contact regions 17 may have portions connected to the multiple gate structures 11.

[0071] Multiple contact regions 17 are formed at intervals from the bottom of the body region 10 toward the first main surface 3, and face the second semiconductor layer 7 via a portion of the body region 10. In this configuration, the multiple contact regions 17 are formed deeper than the multiple source regions 16. The multiple contact regions 17 may also be formed shallower than the multiple source regions 16.

[0072] The semiconductor device 1A includes a p-type well region 18 formed in the second semiconductor layer 7 at the peripheral edge (inactive region 9) of the first main surface 3. The well region 18 may also be referred to as an "impurity region," "pn junction," etc. The well region 18 has a p-type impurity concentration lower than that of the contact region 17. The p-type impurity concentration of the well region 18 may be higher or lower than that of the body region 10.

[0073] The well region 18 is formed on the surface of the first main surface 3 and forms a pn junction with the second semiconductor layer 7. The well region 18 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3 and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The well region 18 is formed with a gap from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0074] In this embodiment, the well region 18 has a depth greater than the depth of the body region 10. The depth of the well region 18 may be less than the depth of the body region 10, or it may be approximately equal to the depth of the body region 10. In this embodiment, the depth of the well region 18 is greater than the depth of the gate structure 11. The depth of the well region 18 may be less than the depth of the gate structure 11.

[0075] In this embodiment, the well region 18 includes a pad well region 18a (pad pn joint) and an outer well region 18b (outer pn joint). The pad well region 18a is formed in the surface layer of the first main surface 3 in the pad region 9a and extends along the first main surface 3.

[0076] The pad well region 18a is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the pad well region 18a has a planar shape that is substantially similar to the planar shape of the pad region 9a.

[0077] The pad well region 18a is drawn out from the pad region 9a to the active region 8 and connected (electrically connected) to the body region 10 at the surface of the first main surface 3. The pad well region 18a may have portions that are along the bottom surfaces of the ends of the multiple gate structures 11.

[0078] The outer well region 18b is formed in the outer region 9b on the surface of the first main surface 3. The outer well region 18b is formed at a distance from the periphery of the first main surface 3 inward and extends in a band shape along the active region 8. In a plan view, the outer well region 18b has a portion extending in a first direction X and a portion extending in a second direction Y, and divides the active region 8 from multiple directions.

[0079] In this embodiment, the outer well region 18b is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The outer well region 18b may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter-circular arc shape) in a plan view.

[0080] The outer well region 18b is connected to the pad well region 18a on the first side surface 5A side. The outer well region 18b is drawn into the active region 8 and connected (electrically connected) to the body region 10 at the surface layer of the first main surface 3. The outer well region 18b may have portions that follow the bottom surfaces of the ends of the multiple gate structures 11.

[0081] The semiconductor device 1A includes an insulating interlayer film 20 that selectively covers the first main surface 3. The interlayer film 20 may be referred to as "coating," "film-forming body," "film-forming target," or the like. In this embodiment, the interlayer film 20 has a laminated structure including a first interlayer film 21 and a second interlayer film 22. The first interlayer film 21 may be referred to as "main surface insulating film," "lower insulating film," or the like, and the second interlayer film 22 may be referred to as "upper insulating film," or the like.

[0082] The first interlayer film 21 may have a single-layer structure or a multilayer structure comprising at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 21 may also include at least one of the oxide film of the chip 2 (second semiconductor layer 7) and an oxide film other than the oxide film of the chip 2. In this embodiment, the first interlayer film 21 is made of the same insulating film as the insulating film 14.

[0083] The first interlayer film 21 selectively covers the first main surface 3 in an active region 8 and an inactive region 9. On the active region 8 side, the first interlayer film 21 covers multiple source regions 16 and multiple contact regions 17 with multiple mesa portions 12, exposing multiple gate structures 11. The first interlayer film 21 is connected to multiple insulating films 14, exposing multiple embedded electrodes 15. In this configuration, the first interlayer film 21 forms a single insulating film integral with the multiple insulating films 14.

[0084] The first interlayer membrane 21 covers the well region 18 on the inactive region 9 side. The first interlayer membrane 21 is continuous with the first to fourth side surfaces 5A to 5D. The first interlayer membrane 21 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0085] The first interlayer film 21 may have a thickness approximately equal to the thickness of the insulating film 14. The thickness of the first interlayer film 21 may be greater than or less than the thickness of the insulating film 14. The thickness of the first interlayer film 21 may be greater than 0 nm and 250 nm or less.

[0086] The thickness of the first interlayer film 21 may be greater than 0 nm and fall within at least one of the following ranges: 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 250 nm or less.

[0087] The second interlayer film 22 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 22 may have a single-layer structure or a multilayer structure including at least one of an NSG film (Nondoped Silicate Glass film), a PSG film (Phosphorus Silicon Glass film), a BSG film (Boron Silicon Glass film), a BPSG film (Boron Phosphorus Silicon Glass film), and a TEOS film (tetraethyl orthosilicate film).

[0088] NSG film is a silicon oxide film without impurities, PSG film is a silicon oxide film containing phosphorus, BSG film is a silicon oxide film containing boron, and BPSG film is a silicon oxide film containing both phosphorus and boron.

[0089] The second interlayer film 22 preferably has a single-layer structure or a multilayer structure including at least an NSG film. If the second interlayer film 22 has a multilayer structure including multiple insulating films, the types and stacking order of the multiple insulating films are arbitrary. For example, the second interlayer film 22 may have a multilayer structure including an NSG film and a PSG film stacked in this order from the chip 2 side.

[0090] The second interlayer membrane 22 covers the first interlayer membrane 21 in a film-like manner in the active region 8 and the inactive region 9. On the active region 8 side, the second interlayer membrane 22 covers a plurality of gate structures 11 and a plurality of mesa portions 12 via the first interlayer membrane 21.

[0091] Specifically, the second interlayer membrane 22 covers multiple source regions 16 and multiple contact regions 17 via the first interlayer membrane 21 through multiple mesa portions 12. The second interlayer membrane 22 extends from above the first interlayer membrane 21 into multiple trenches 13 and covers multiple embedded electrodes 15 within the multiple trenches 13.

[0092] The second interlayer membrane 22 covers the first main surface 3 via the first interlayer membrane 21 on the side of the inactive region 9. Specifically, the second interlayer membrane 22 covers the well region 18 via the first interlayer membrane 21. The second interlayer membrane 22 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the second interlayer membrane 22 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the first interlayer membrane 21.

[0093] The second interlayer membrane 22 has a thickness greater than the thickness of the first interlayer membrane 21. The thickness of the second interlayer membrane 22 may be greater than 0 μm and 5 μm or less. The thickness of the second interlayer membrane 22 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0094] The semiconductor device 1A includes gate wiring 23 selectively routed to the peripheral edge (inactive region 9) of the first main surface 3. The gate wiring 23 is electrically connected to a plurality of gate structures 11 and applies a gate potential to the plurality of gate structures 11.

[0095] The gate wiring 23 includes either a metallic conductor or a non-metallic conductor (a conductor other than metal), or both. In this embodiment, the gate wiring 23 includes conductive polysilicon. The gate wiring 23 may include either a p-type conductive polysilicon or an n-type conductive polysilicon, or both. Preferably, the gate wiring 23 includes the same conductive material as the conductive material of the embedded electrode 15.

[0096] The gate wiring 23 is located within the interlayer film 20. Specifically, the gate wiring 23 is located on the first interlayer film 21 and covered by the second interlayer film 22. The gate wiring 23 is located at a distance from the periphery of the first main surface 3 inward. The gate wiring 23 is located at a distance from the outer edge of the well region 18 inward and faces the well region 18 in the thickness direction Z.

[0097] The gate wiring 23 is electrically connected to multiple gate structures 11 in the active region 8. Specifically, the gate wiring 23 enters multiple trenches 13 from above the first interlayer membrane 21 and is mechanically and electrically connected to multiple embedded electrodes 15 within the multiple trenches 13.

[0098] In this configuration, the gate wiring 23 is formed integrally with the multiple buried electrodes 15 as the lead-out portion of the multiple buried electrodes 15. The connection portion of the gate wiring 23 to the multiple buried electrodes 15 may be considered as part of the multiple buried electrodes 15, or as part of the gate wiring 23.

[0099] The gate wiring 23 includes a pad portion 23a and a line portion 23b. The pad portion 23a is positioned on the pad region 9a and faces the well region 18 (pad well region 18a) via the first interlayer film 21. The pad portion 23a is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the pad portion 23a has a planar shape that is substantially similar to the planar shape of the pad region 9a.

[0100] In this configuration, the pad portion 23a is positioned at a distance from the multiple gate structures 11. The pad portion 23a may be drawn into the active region 8 and mechanically and electrically connected to the ends of the multiple gate structures 11.

[0101] The line portion 23b is positioned on the outer region 9b and faces the well region 18 (outer well region 18b) via the first interlayer membrane 21. In a plan view, the line portion 23b extends in a band shape along the active region 8.

[0102] The line portion 23b has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view, and divides the active region 8 from multiple directions. The line portion 23b may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter arc shape) in a plan view.

[0103] In this embodiment, the line portion 23b is formed as an ended or endless (ended in this embodiment) polygonal ring (a quadrangular ring in this embodiment) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. The line portion 23b has a pair of ends in the portion that extends in the first direction X along the third side surface 5C.

[0104] The line portion 23b has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the line portion 23b extends into the active region 8 in the second direction Y and is mechanically and electrically connected to the ends of the multiple gate structures 11. Specifically, the inner edge of the line portion 23b enters into the multiple trenches 13 from above the first interlayer membrane 21 and is mechanically and electrically connected to the multiple embedded electrodes 15 within the multiple trenches 13.

[0105] The inner edge of the line portion 23b covers the first main surface 3 via the first interlayer film 21 with a plurality of mesa portions 12. The inner edge of the line portion 23b may overlap either or both of the body region 10 and the well region 18 with the plurality of mesa portions 12.

[0106] The configuration of semiconductor device 1A will be described below with reference to Figures 8 to 13. Figure 8 is a plan view showing an example of the layout of the interlayer film 20. Figure 9 is a plan view showing an example of the layout of the source metal film 50, gate metal film 30, and gate wiring metal film 40.

[0107] Figure 10 is an enlarged plan view showing an example layout of the gate metal film 30. Figure 11 is a cross-sectional view along the line XI-XI shown in Figure 10. Figure 12 is a cross-sectional view along the line XII-XII shown in Figure 10. Figure 13 is an enlarged cross-sectional view showing the main part of the gate metal film 30 shown in Figure 12.

[0108] The interlayer film 20 has an insulating surface that extends along the first main surface 3. The interlayer film 20 is formed by a second interlayer film 22. The interlayer film 20 includes an uneven region 26 on the insulating surface that contains a plurality of source openings 25. The uneven region 26 (plural source openings 25) is formed in the active region 8 but not in the inactive region 9.

[0109] Multiple source openings 25 penetrate the interlayer membrane 20 at intervals from multiple gate structures 11, exposing multiple mesa portions 12. In this configuration, each of the multiple source openings 25 is formed in a one-to-one correspondence with each of the multiple mesa portions 12. Each of the multiple source openings 25 has a bottom wall demarcated by the first main surface 3 (corresponding to the mesa portion 12) and side walls demarcated by the interlayer membrane 20.

[0110] The bottom walls of the multiple source openings 25 may be demarcated by bottom wall recesses that are recessed from the height position of the first main surface 3 toward the second main surface 4. The bottom wall recesses may be formed at a distance from the bottom of the body region 10 toward the first main surface 3. In this embodiment, the bottom wall recesses are formed at a distance from the depth position of the bottom of the source region 16 and the depth position of the bottom of the contact region 17 toward the first main surface 3.

[0111] The multiple source openings 25 each extend in a strip-like shape in a first direction X, following the direction of extension of the multiple gate structures 11, and are formed with gaps in the second direction Y. The multiple source openings 25 expose the corresponding source region 16 and the corresponding contact region 17.

[0112] Multiple source openings 25 may be formed in a one-to-many correspondence with respect to a single mesa portion 12. In this case, the multiple source openings 25 may be formed spaced apart from each other in the first direction X and may extend in a strip-like manner in the first direction X. The multiple source openings 25 may expose corresponding source regions 16 and corresponding contact regions 17.

[0113] Each of the multiple source openings 25 has an opening width less than or equal to the spacing of the gate structure 11 (the width of the mesa portion 12). The opening width may be greater than 0 μm and less than or equal to 3 μm. The opening width may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0114] The aperture width may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0115] The spacing between the multiple source openings 25 may be greater than or less than the opening width of the source opening 25. The spacing between the source openings 25 may be greater than 0 μm and 3 μm or less. The spacing between the source openings 25 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0116] The spacing of the source openings 25 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0117] The semiconductor device 1A includes one or more (in this embodiment, more than one) gate openings 27 formed in the interlayer film 20 in an inactive region 9. The multiple gate openings 27 penetrate the interlayer film 20 from the uneven region 26 (multiple source openings 25) toward the peripheral edge of the first main surface 3, leaving gaps between them and exposing the gate wiring 23. Each of the multiple gate openings 27 has a bottom wall partitioned by the gate wiring 23 and a side wall partitioned by the interlayer film 20.

[0118] In this configuration, the multiple gate openings 27 penetrate the portion of the interlayer film 20 that covers the line portion 23b, exposing the line portion 23b. In this configuration, the multiple gate openings 27 are formed at intervals in a direction perpendicular to the extending direction of the line portion 23b, and each extends in a strip shape following the extending direction of the line portion 23b.

[0119] The multiple gate openings 27 may each have a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y when viewed from above. The multiple gate openings 27 may each have an edge portion that connects the portion that extends in the first direction X and the portion that extends in the second direction Y in an arc shape (preferably a quarter-circular arc shape) when viewed from above.

[0120] Of course, the multiple gate openings 27 may be formed at intervals in the direction of extension of the gate wiring 23 and / or in a direction perpendicular to the direction of extension. In this case, the multiple gate openings 27 may each extend in a strip shape following the direction of extension of the line portion 23b in a plan view. Of course, the multiple gate openings 27 may each be formed in a polygonal shape (for example, a square or hexagonal shape), a circular shape, etc. in a plan view.

[0121] Each of the gate openings 27 has an opening width approximately equal to the opening width of the source opening 25. The opening width of the gate openings 27 may be larger or smaller than the opening width of the source opening 25. The opening width may be greater than 0 μm and 3 μm or less. The opening width may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0122] The aperture width may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0123] The spacing between the multiple gate openings 27 may be greater or less than the opening width of the gate openings 27. The spacing between the gate openings 27 may be approximately equal to the opening width of the source openings 25. The spacing between the gate openings 27 may be greater or less than the spacing between the source openings 25.

[0124] The spacing of the gate openings 27 may be greater than 0 μm and 3 μm or less. The spacing of the gate openings 27 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0125] The spacing of the gate openings 27 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0126] Of course, the semiconductor device 1A may include a single gate opening 27. In this case, the single gate opening 27 may extend in a strip shape following the direction of extension of the line portion 23b. Alternatively, the semiconductor device 1A may include one or more gate openings 27 that selectively expose the pad portion 23a.

[0127] It is preferable that one or more gate openings 27 for the pad portion 23a are formed with a density (occupied area per unit area) less than the density (occupied area per unit area) of the plurality of source openings 25. For example, one or more gate openings 27 for the pad portion 23a may be formed along the periphery of the pad portion 23a at the periphery of the pad portion 23a.

[0128] The interlayer film 20 has a flat region 28 outside the uneven region 26 on its insulating surface. The flat region 28 has an unevenness density less than that of the uneven region 26 and a flatness higher than that of the uneven region 26. In this embodiment, the flat region 28 is a region that does not have a plurality of source openings 25 and a plurality of gate openings 27, and is formed by a flat insulating surface.

[0129] If one or more gate openings 27 for the pad portion 23a are formed, the flat region 28 is a region that does not have a plurality of source openings 25 and is formed by an insulating surface that is flatter than the uneven region 26.

[0130] The flat region 28 is formed in the inactive region 9 but not in the active region 8. Specifically, the flat region 28 is formed in the pad region 9a and is surrounded by a plurality of source openings 25 and a plurality of gate openings 27 in a plan view. In this configuration, the flat region 28 is also formed in the outer region 9b on the peripheral side of the first main surface 3 beyond the plurality of gate openings 27, but the flat portion formed in the pad region 9a is defined as the "flat region 28".

[0131] The semiconductor device 1A includes a metallic gate film 30 as a gate pad electrode, which is placed on an interlayer film 20, which is an example of a coating. The gate metal film 30 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "gate electrode," etc. A gate potential is applied to the gate metal film 30.

[0132] The gate metal film 30 is positioned on the interlayer film 20 in the pad region 9a. Specifically, the gate metal film 30 is positioned on the flat region 28, spaced apart from the uneven region 26. In other words, the gate metal film 30 is positioned spaced apart from the multiple source openings 25 and the multiple gate openings 27, and has a gate metal surface 30s that extends flat along the insulating surface of the interlayer film 20.

[0133] The gate metal film 30 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. In this embodiment, the gate metal film 30 has a planar shape that is substantially similar to the planar shape of the pad region 9a (pad portion 23a). Of course, the gate metal film 30 may also be formed in a polygonal shape with the four corners recessed in a quadrilateral shape in a plan view.

[0134] The gate metal film 30 faces the pad portion 23a of the gate wiring 23 via a part of the interlayer film 20 (second interlayer film 22). The gate metal film 30 faces the pad well region 18a (well region 18) via the interlayer film 20 and the gate wiring 23. In other words, the gate metal film 30 overlaps the pn junction portion of the surface layer of the first main surface 3 in the thickness direction Z.

[0135] In this embodiment, the gate metal film 30 is positioned at a distance from the multiple gate structures 11 in a plan view. The gate metal film 30 may extend into the active region 8 in a plan view and have portions that face the ends of the multiple gate structures 11 via a part of the interlayer film 20 (second interlayer film 22).

[0136] The gate metal film 30 may be positioned at a distance from the periphery of the pad portion 23a, inward. In other words, the entire area of ​​the gate metal film 30 may face the pad portion 23a. Of course, the gate metal film 30 may have a portion that protrudes outward from the periphery of the pad portion 23a.

[0137] In this embodiment, the gate metal film 30 has a laminated structure including a gate underlayment metal film 31 and a gate body metal film 32, which are laminated in this order from the interlayer film 20 side. The gate underlayment metal film 31 is formed as a barrier electrode and has a single-layer structure consisting of a single metal film or a laminated structure including multiple metal films.

[0138] In this embodiment, the gate base metal film 31 has a laminated structure including a first gate base metal film 33 and a second gate base metal film 34. Of course, the gate base metal film 31 may also have a single-layer structure consisting of the first gate base metal film 33 or the second gate base metal film 34.

[0139] The first gate base metal film 33 covers the insulating surface of the interlayer film 20 in a film-like manner. In this embodiment, the first gate base metal film 33 consists of a titanium film, which is an example of a titanium-based metal film. The first gate base metal film 33 has a thickness less than the thickness of the interlayer film 20.

[0140] The thickness of the first gate base metal film 33 may be greater than 0 nm and 200 nm or less. The thickness of the first gate base metal film 33 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0141] The second gate base metal film 34 covers the first gate base metal film 33 in a film-like manner. In this embodiment, the second gate base metal film 34 consists of a titanium alloy film (in this embodiment, a titanium nitride film) as an example of a titanium-based metal film. The second gate base metal film 34 has a thickness less than the thickness of the interlayer film 20. The thickness of the second gate base metal film 34 is greater than the thickness of the first gate base metal film 33.

[0142] The thickness of the second gate underlay metal film 34 may be greater than 0 nm and 300 nm or less. The thickness of the second gate underlay metal film 34 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0143] The gate body metal film 32 forms the main body of the gate metal film 30. The gate body metal film 32 is made of a different metal from the first gate base metal film 33 and the second gate base metal film 34. The gate body metal film 32 contains a reducing active metal. In this embodiment, the gate body metal film 32 is made of an aluminum-based metal (pure aluminum or aluminum alloy with a purity of 99% or more). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0144] The gate body metal film 32 has a thickness greater than the thickness of the gate base metal film 31 (the total thickness of the first gate base metal film 33 and the second gate base metal film 34). In this embodiment, the thickness of the gate body metal film 32 is greater than the thickness of the interlayer film 20. The thickness of the gate body metal film 32 may be less than the thickness of the interlayer film 20.

[0145] The thickness of the gate body metal film 32 may be greater than 0 μm and 5 μm or less. The thickness of the gate body metal film 32 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0146] The gate body metal film 32 is laminated in a film-like manner on the gate base metal film 31 (interlayer film 20) and forms the main body of the gate metal film 30. The gate body metal film 32 contains a plurality of metal crystal grains MG (aluminum-based metal crystal grains) made of aluminum-based metal. The plurality of metal crystal grains MG are laminated on the gate base metal film 31 at a predetermined metal crystal grain density (hereinafter simply referred to as "crystal density") per unit area.

[0147] The metal crystal grain MG will be specifically described below with reference to Figures 14, 15, and Table 1. Figure 14 is a graph illustrating the relationship between crystal density per unit area (the planar area of ​​multiple metal crystal grains MG) and temperature. In Figure 14, the planar area of ​​the metal crystal grain MG is shown on the horizontal axis, and the normal quantile of the planar area of ​​the metal crystal grain MG is shown on the vertical axis. In this configuration, the unit area is 150 μm². ２ That is the case.

[0148] Figure 15 is a diagram illustrating the relationship between crystal density per unit area (the planar area of ​​multiple metal crystal grains MG) and temperature. The four images shown in Figure 15 are traces of analytical images of multiple metal crystal grains MG.

[0149] The analysis image in Figure 15 was obtained by EBSP (Electron Backscatter Diffraction Pattern) analysis per unit area on the gate metal surface 30s. EBSP analysis is a known analysis method for evaluating crystal orientation distribution, grain size, grain boundary orientation difference, phase distribution, orientation relationships, etc., observed by SEM (Scanning Electron Microscope). In Figure 15, crystal boundaries are indicated by black grid lines, and metal crystal grains MG are indicated by white areas surrounded by black grid lines.

[0150] The gate body metal film 32 (aluminum-based metal) is deposited on the interlayer film 20 (film to be deposited) by sputtering, and the crystal density of the gate body metal film 32 depends on the sputtering temperature. Figures 14 and 15 show four results when the gate body metal film 32 is formed by sputtering at 400°C, 350°C, 300°C, and 200°C.

[0151] Referring to Figures 14 and 15, the crystal density per unit area (i.e., the area of ​​metal crystal grains MG) decreases as the precipitation temperature is set lower. The area of ​​metal crystal grains MG at the major quantiles for each precipitation temperature is shown in Table 1.

[0152]

[0153] At 400°C, the planar area of the metal crystal grains MG is 0 µm at the minimum quantile ２ greater than 0.1 µm ２ or less, 0.3 µm at the 10% quantile ２ or more and 0.6 µm ２ or less, 4.5 µm at the 25% quantile ２ or more and 5.0 µm ２ or less, 12 µm at the 50% quantile ２ or more and 15 µm ２ or less, 35 µm at the 75% quantile ２ or more and 40 µm ２ or less, 65 µm at the 90% quantile ２ or more and 70 µm ２ or less, and 200 µm at the maximum quantile ２ or more and 205 µm ２ or less.

[0154] At 350°C, the planar area of the metal crystal grains MG is 0 µm at the minimum quantile ２ greater than 0.1 µm ２ or less, 1.5 µm at the 10% quantile ２ or more and 2.0 µm ２ or less, 4 µm at the 25% quantile ２ or more and 4.5 µm ２ or less, 10 µm at the 50% quantile ２ or more and 13 µm ２ or less, 20 µm at the 75% quantile ２ or more and 25 µm ２ or less, 37 µm at the 90% quantile ２ or more and 43 µm ２ or less, and 140 µm at the maximum quantile ２ or more and 145 µm ２ or less.

[0155] At 300°C, the planar area of the metal crystal grains MG is 0 µm at the minimum quantile ２ greater than 0.1 µm ２ or less, 0.5 µm at the 10% quantile ２ or more and 1.0 µm ２ or less, 2.5 µm at the 25% quantile ２ or more and 3.0 µm ２ or less, 5.0 µm at the 50% quantile ２ or more and 8.0 µm ２Below, the 75th percentile is 10 μm. ２ 13 μm or more ２ Below, the 90th percentile is 22 μm. ２ 26 μm or more ２ Below, and at the largest quantile, 100 μm ２ 105 μm or more ２ The results were as follows:

[0156] At 200°C, the planar area of ​​the metal crystal grain MG is 0 μm at the smallest quantile. ２ Larger than 0.1 μm ２ Below, the 10% quantile is 0.3 μm. ２ The above 0.5 μm ２ Below, the 25th percentile is 1.0 μm. ２ 1.3 μm or more ２ Below, the 50th percentile is 2.0 μm. ２ 3.0 μm or more ２ Below, the 75th percentile is 4.0 μm. ２ 6.0 μm or more ２ Below, the 90th percentile is 7.0 μm. ２ 10 μm or more ２ Below, and at the largest quantile, 25 μm ２ 30 μm or more ２ The results were as follows:

[0157] Based on these results, when the sputtering method with a deposition temperature of 400°C is used, the median area of ​​multiple metal crystal grains MG is 20 μm. ２ A gate body metal film 32 (aluminum-based metal) with a thickness of less than 15 μm is formed. Specifically, when the deposition temperature is 400°C, the median of the planar area of ​​multiple metal crystal grains MG is 15 μm. ２ The following applies:

[0158] When a sputtering method with a deposition temperature of 350°C is used, the median area of ​​multiple metal crystal grains MG is 15 μm, compared to when the deposition temperature is 400°C. ２ A gate body metal film 32 with a size less than 13 μm is formed. Specifically, when the deposition temperature is 350°C, the median of the planar area of ​​multiple metal crystal grains MG is 13 μm. ２ The following applies:

[0159] When a sputtering method with a deposition temperature of 300°C is used, the median area of ​​multiple metal crystal grains MG is 10 μm, compared to when the deposition temperature is 350°C. ２ A gate body metal film 32 with a size less than 9 μm is formed. Specifically, when the deposition temperature is 300°C, the median of the planar area of ​​multiple metal crystal grains MG is 9 μm. ２ The following, and more specifically 8 μm ２ The following applies:

[0160] At a deposition temperature of 300°C, the planar area of ​​metal crystal grains MG per unit area at the maximum quantile is 140 μm². ２ The following, specifically 110 μm ２ The following, and more specifically, 105 μm ２ The following applies:

[0161] At a precipitation temperature of 300°C, the planar area of ​​the metal crystal grain MG at the 90th percentile is 35 μm². ２ The following, specifically 30 μm ２ The following, and more specifically, 26 μm ２ The following applies: At a precipitation temperature of 300°C, the planar area of ​​the metal crystal grain MG at the 75th percentile is 20 μm². ２ The following, specifically 15 μm ２ The following, and more specifically, 13 μm ２ The following applies:

[0162] At a precipitation temperature of 300°C, the planar area of ​​the metal crystal grain MG at the 25th percentile is 4 μm². ２ The following, specifically 3.5 μm ２ The following, and more specifically 3 μm ２ The following applies: At a precipitation temperature of 300°C, the planar area of ​​the metal crystal grain MG at the 10% quantile is 1.5 μm². ２ The following, specifically 1 μm ２ The following applies:

[0163] When a sputtering method with a deposition temperature of 200°C is used, the median area of ​​multiple metal crystal grains MG is 5 μm compared to when the deposition temperature is 300°C. ２ A gate body metal film 32 with a thickness of less than 4 μm is formed. Specifically, when the deposition temperature is 200°C, the median of the planar area of ​​multiple metal crystal grains MG is 4 μm.２ or less, more specifically 3 μm ２ or less.

[0164] When the precipitation temperature is 200°C, the plane area of metal crystal grains MG per unit area at the maximum quantile (that is, the maximum plane area among a plurality of metal crystal grains MG) is 100 μm ２ or less, specifically 50 μm ２ or less, more specifically 30 μm ２ or less.

[0165] When the precipitation temperature is 200°C, the plane area of the metal crystal grains MG at the 90% quantile is 20 μm ２ or less, specifically 15 μm ２ or less, more specifically 10 μm ２ or less. When the precipitation temperature is 200°C, the plane area of the metal crystal grains MG at the 75% quantile is 10 μm ２ less than, specifically 8 μm ２ or less, more specifically 6 μm ２ or less.

[0166] When the precipitation temperature is 200°C, the plane area of the metal crystal grains MG at the 25% quantile is 2.5 μm ２ or less, specifically 2 μm ２ or less, more specifically 1.5 μm ２ or less. When the precipitation temperature is 200°C, the plane area of the metal crystal grains MG at the 10% quantile is 1 μm ２ or less, specifically 0.5 μm ２ or less.

[0167] From the above, it can be understood that the sputtering method with a relatively high precipitation temperature (>300°C) is effective in reducing crystal density, and the sputtering method with a relatively low precipitation temperature (≦300°C) is effective in increasing crystal density. At a relatively high precipitation temperature (>300°C), the kinetic energy of atoms and molecules increases, which facilitates the formation of metal crystals with an amorphous structure, and is also effective in forming metal crystal grains MG excellent in embedding property.

[0168] On the other hand, at relatively low deposition temperatures (≤300°C), the surface condition of the gate metal surface 30s improves because the crystal density per unit area increases, leading to an increase in crystal boundaries per unit area. The surface condition of the gate metal surface 30s will be explained below with reference to Figure 16.

[0169] Figure 16 is a cross-sectional view illustrating a gate metal film 30 according to a reference example. In Figure 16, as one reference example, a cross-sectional view is shown of a case where a single-layer gate metal film 30 (first gate metal film 35) is formed by a sputtering method at a deposition temperature higher than 300°C. In other words, the gate metal surface 30s according to the reference example is formed by a first gate metal film 35 having a relatively low first crystal density.

[0170] Referring to Figure 16, the gate metal film 30 according to the reference example has a residual oxide ROx made of the oxide (aluminum oxide in this embodiment) of the gate metal film 30 (first metal crystal grain MG1) on the gate metal surface 30s.

[0171] Residual oxide ROx is a film-like or particle-like residue resulting from the oxide film formed on the gate metal surface 30s during the manufacturing process of the semiconductor device 1A. The oxide film includes, for example, unwanted oxide films and native oxide films resulting from the manufacturing process.

[0172] In the case of the gate metal film 30 according to the reference example, the gate metal surface 30s is formed by a plurality of first metal crystal grains MG1 having a relatively low first crystal density. In other words, in the gate metal surface 30s according to the reference example, the contact area of ​​residual oxide ROx with the gate metal surface 30s is large, and the residual oxide ROx is difficult to remove by the removal process (chemical treatment process).

[0173] On the other hand, when the crystal density (density of multiple grain boundaries) of the gate metal surface 30s is increased by a sputtering method with a deposition temperature of less than 300°C, the multiple grain boundaries function as delamination starting points for residual oxide ROx. As a result, residual oxide ROx is properly removed by the removal process (chemical treatment process), and the remaining residual oxide ROx is suppressed. This improves the surface condition of the gate metal surface 30s and reduces the influence of residual oxide ROx on the electrical properties (e.g., resistance) of the gate metal film 30.

[0174] In light of the above properties, the gate body metal film 32 in this embodiment is formed with different crystal densities in the thickness direction Z. Specifically, the gate body metal film 32 has a laminated structure including a first gate metal film 35 and a second gate metal film 36 that are laminated in this order from the interlayer film 20 (gate base metal film 31) side.

[0175] The first gate metal film 35 is laminated in a film-like manner on the gate base metal film 31 (interlayer film 20) and contains a plurality of first metal crystal grains MG1 (aluminum-based metal crystal grains) made of aluminum-based metal. The plurality of first metal crystal grains MG1 have relatively large planar area and cross-sectional area with respect to the median (or average) value per unit area and are laminated on the gate base metal film 31 with a relatively low first crystal density per unit area (see Figure 13).

[0176] Multiple first metal crystal grains MG1 are adjacent to each other with irregular planar area, planar shape, and cross-sectional shape, and they demarcate each other by first grain boundaries that extend irregularly in the thickness direction Z. In other words, multiple first metal crystal grains MG1 are defined by multiple metal crystal regions demarcated by first grain boundaries that extend in a network-like pattern in a planar view.

[0177] In the first gate metal film 35, the median (first value) of the planar area of ​​the multiple first metal crystal grains MG1 is 8 μm ２ Larger than that, specifically 10 μm ２ That concludes the report. The median area of ​​the multiple first metal crystal grains MG1 is 50 μm. ２ Below, 45μm ２ Below, 40 μm ２ Below, 35μm ２ Below, 30μm ２ Below, 25μm ２ Below, 20μm ２ The following, or 15 μm ２ The following is also acceptable.

[0178] The first gate metal film 35 is formed by sputtering at a first deposition temperature. The first deposition temperature is preferably higher than 300°C and 500°C or lower. The first deposition temperature may have a value that falls within at least one of the following ranges: higher than 300°C and 350°C or lower, 350°C or higher and 400°C or lower, 400°C or higher and 450°C or lower, and 450°C or higher and 500°C or lower.

[0179] The first gate metal film 35 has a thickness greater than the thickness of the gate base metal film 31. In this embodiment, the thickness of the first gate metal film 35 is greater than the thickness of the interlayer film 20 (the depth of the source opening 25 and the depth of the gate opening 27). The thickness of the first gate metal film 35 may be less than the thickness of the interlayer film 20.

[0180] The ratio of the thickness of the first gate metal film 35 to the thickness of the gate body metal film 32 (first thickness ratio) may be 0.7 or more and less than 1. The first thickness ratio may have a value that falls within at least one of the following ranges: 0.7 or more and 0.75 or less, 0.75 or more and 0.8 or less, 0.8 or more and 0.85 or less, 0.85 or more and 0.95 or less, and 0.95 or more and less than 1.

[0181] The second gate metal film 36 is laminated in a film-like manner on the first gate metal film 35, forming the gate metal surface 30s. The second gate metal film 36 contains a plurality of second metal crystal grains MG2 (aluminum-based metal crystal grains) made of the same type of aluminum-based metal as the first gate metal film 35. Of course, the second gate metal film 36 may be made of a different aluminum-based metal than the first gate metal film 35.

[0182] Multiple second metal crystal grains MG2 are stacked on top of multiple first metal crystal grains MG1 (first gate metal film 35) at a second crystal density higher than the first crystal density per unit area (see Figure 13). In other words, with respect to the median (or average) value per unit area, the multiple second metal crystal grains MG2 have a smaller planar area and cross-sectional area than the multiple first metal crystal grains MG1.

[0183] Multiple second metal crystal grains MG2 are adjacent to each other with irregular planar area, planar shape, and cross-sectional shape, and they demarcate each other by second grain boundaries that extend irregularly in the thickness direction Z. In other words, the second metal crystal grains MG2 are defined by metal crystal regions demarcated by second grain boundaries that extend in a network-like pattern in a planar view.

[0184] The second gate metal film 36, together with the first gate metal film 35, forms a metal crystal boundary MB resulting from the density difference between the first crystal density of a plurality of first metal crystal grains MG1 and the second crystal density of a plurality of second metal crystal grains MG2 (see Figure 13). In other words, the gate metal film 30 has a boundary MB between the first gate metal film 35 and the second gate metal film 36, resulting from the density difference between the first and second crystal densities. The boundary MB extends horizontally along the insulating surface of the interlayer film 20 and the gate metal surface 30s.

[0185] The median (second value) of the planar area of ​​multiple second metal crystal grains MG2 is less than the median of the planar area of ​​multiple first metal crystal grains MG1. The median of the planar area of ​​multiple second metal crystal grains MG2 is 0 μm. ２ Larger than 10 μm ２ It is less than.

[0186] The median area of ​​multiple second metal crystal grains MG2 is 9 μm. ２ Below, 8 μm ２ Below, 7 μm ２ Below, 6 μm ２ Below, 5 μm ２ Below, 4μm ２ Below, 3μm ２ Below, 2μm ２ The following, or 1 μm ２ Preferably the following (10 μm at 300°C) ２ It is less than 5 μm at 200°C. ２ (Less than) The median planar area of ​​multiple second metal crystal grains MG2 is 0.5 μm ２ More than 1μm ２ More than 2 μm ２ or greater than 3 μm ２ That's fine too.

[0187] The second gate metal film 36 is formed by a sputtering method at a second deposition temperature lower than the first deposition temperature. The second deposition temperature may be between 0°C and 300°C. The second deposition temperature may have a value that falls within at least one of the following ranges: 0°C to 50°C, 50°C to 100°C, 100°C to 150°C, 150°C to 200°C, 200°C to 250°C, and 250°C to 300°C.

[0188] The second precipitation temperature is preferably less than 300°C. The second precipitation temperature is preferably 250°C or lower. The second precipitation temperature is preferably 200°C or lower. The second precipitation temperature may be 50°C or higher, 75°C or higher, 100°C or higher, 125°C or higher, 150°C or higher, or 175°C or higher.

[0189] The second gate metal film 36 has a thickness less than that of the first gate metal film 35 and forms the surface layer of the gate metal surface 30s. In this embodiment, the thickness of the second gate metal film 36 is less than the thickness of the interlayer film 20 (the depth of the source opening 25 and the depth of the gate opening 27).

[0190] The thickness of the second gate metal film 36 may be greater than the thickness of the interlayer film 20. In this embodiment, the thickness of the second gate metal film 36 is greater than the thickness (total thickness) of the gate base metal film 31. The thickness of the second gate metal film 36 may be less than the thickness of the gate base metal film 31.

[0191] The ratio of the thickness of the second gate metal film 36 to the thickness of the gate body metal film 32 (second thickness ratio) may be greater than 0 and 0.3 or less. The second thickness ratio may have a value that belongs to at least one of the following ranges: greater than 0 and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.2 or more and 0.25 or less, and 0.25 or more and 0.3 or less.

[0192] The thickness of the second gate metal film 36 may be greater than 0 nm and 1000 nm or less. The thickness of the second gate metal film 36 may have a value that falls within at least one of the following ranges: greater than 0 nm and 100 nm or less, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, and 900 nm to 1000 nm.

[0193] In this embodiment, the gate body metal film 32 had a laminated structure including a first gate metal film 35 and a second gate metal film 36. However, the gate body metal film 32 may also have a single-layer structure consisting of the second gate metal film 36.

[0194] The semiconductor device 1A includes a metallic gate wiring metal film 40 as a wiring electrode, which is placed on the interlayer film 20 in an inactive region 9. The gate wiring metal film 40 may also be called a "gate finger," "gate wiring," etc. The gate wiring metal film 40 is a metallic film. The gate wiring metal film 40 is drawn out from the gate metal film 30 onto the interlayer film 20 and transmits the gate potential applied to the gate metal film 30 to other regions.

[0195] The gate wiring metal film 40 covers a plurality of gate openings 27 on the interlayer film 20 in the outer region 9b and is electrically connected to the line portion 23b of the gate wiring 23 via the plurality of gate openings 27. The gate wiring metal film 40 faces the outer well region 18b (pn junction) via the interlayer film 20 and the gate wiring 23.

[0196] The gate wiring metal film 40 extends in a strip shape along the active region 8. The gate wiring metal film 40 has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view, and divides the active region 8 from multiple directions. The gate wiring metal film 40 may have corners that connect the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (for example, a quarter arc shape) in a plan view.

[0197] In this embodiment, the gate wiring metal film 40 is formed in an endowed or endless (endowed in this embodiment) polygonal annular shape (a quadrangular annular shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8. In this embodiment, the gate wiring metal film 40 has a pair of ends in the portion extending in the first direction X along the third side surface 5C.

[0198] The gate wiring metal film 40 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate wiring metal film 40 is positioned on the gate wiring 23 with a gap between it and the multiple gate structures 11 on the peripheral side of the first main surface 3, and does not face the multiple gate structures 11 in the thickness direction Z.

[0199] The outer edge of the gate wiring metal film 40 extends substantially parallel to the inner edge of the gate wiring metal film 40. The outer edge of the gate wiring metal film 40 is drawn out from above the gate wiring 23 towards the peripheral edge of the first main surface 3 and does not face the gate wiring 23 in the thickness direction Z.

[0200] The outer edge of the gate wiring metal film 40 is formed with a gap between it and the outer edge of the outer well region 18b, on the inward side of the first main surface 3. The outer edge of the gate wiring metal film 40 may be located closer to the periphery of the first main surface 3 than the outer edge of the outer well region 18b.

[0201] The gate wiring metal film 40, like the gate metal film 30, has a laminated structure including a gate base metal film 31 and a gate body metal film 32, which are laminated in this order from the first main surface 3 side. The gate base metal film 31 has a laminated structure including a first gate base metal film 33 and a second gate base metal film 34. The gate body metal film 32 has a laminated structure including a first gate metal film 35 and a second gate metal film 36.

[0202] The first gate base metal film 33 penetrates into the multiple gate openings 27 from above the interlayer film 20. The first gate base metal film 33 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner, a portion that covers the wall surfaces of the multiple gate openings 27 in a film-like manner, and a portion that covers the gate wiring 23 (line portion 23b) in a film-like manner. The first gate base metal film 33 is mechanically and electrically connected to the gate wiring 23 (line portion 23b) within the multiple gate openings 27.

[0203] The second gate base metal film 34 covers the first gate base metal film 33 in a film-like manner and penetrates the multiple gate openings 27 from above the interlayer film 20. The second gate base metal film 34 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner via the first gate base metal film 33, a portion that covers the wall surfaces of the multiple gate openings 27 in a film-like manner via the first gate base metal film 33, and a portion that covers the gate wiring 23 in a film-like manner via the first gate base metal film 33. The second gate base metal film 34 is electrically connected to the gate wiring 23 via the first gate base metal film 33 within the multiple gate openings 27.

[0204] The first gate metal film 35 covers the gate base metal film 31 in a film-like manner and penetrates the multiple gate openings 27 from above the interlayer film 20. The first gate metal film 35 has a portion that covers the interlayer film 20 in a film-like manner via the gate base metal film 31, and a portion that is embedded in the multiple gate openings 27 via the gate base metal film 31. In this configuration, the first gate metal film 35 backfills the multiple gate openings 27 and is electrically connected to the gate wiring 23 via the gate base metal film 31 within the multiple gate openings 27.

[0205] The second gate metal film 36 covers the first gate metal film 35 in a film-like manner. The second gate metal film 36 is located above the opening ends of the multiple gate openings 27 (the insulating surfaces of the interlayer film 20). In other words, the second gate metal film 36 has a portion that faces the insulating surface of the interlayer film 20 via the first gate metal film 35, and a portion that faces the multiple gate openings 27 via the first gate metal film 35. The second gate metal film 36 is electrically connected to the gate wiring 23 via the first gate metal film 35.

[0206] Thus, the gate wiring metal film 40 has a laminated structure that includes a first gate metal film 35 having a relatively low first crystal density per unit area, and a second gate metal film 36 having a second crystal density higher than the first crystal density per unit area.

[0207] The first gate metal film 35 is embedded in the multiple gate openings 27 and covers the insulating surface of the interlayer film 20. As a result, the embedding ability of the gate wiring metal film 40 into the multiple gate openings 27 is enhanced by the first gate metal film 35.

[0208] On the other hand, the second gate metal film 36 is positioned above the opening ends of the multiple gate openings 27 (the insulating surfaces of the interlayer film 20) and forms the gate metal surface 30s. This improves the surface condition of the gate wiring metal film 40 and reduces the influence of residual oxide ROx on the electrical properties (e.g., resistance) of the gate wiring metal film 40.

[0209] In this embodiment, the gate body metal film 32 had a laminated structure including a first gate metal film 35 and a second gate metal film 36. However, the gate body metal film 32 may also have a single-layer structure consisting of the second gate metal film 36. This configuration also improves the surface condition of the gate metal surface 30s.

[0210] The semiconductor device 1A includes a source metal film 50 as a source pad electrode, which is placed on an interlayer film 20, which is an example of a coating. The source metal film 50 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "source electrode," etc. A source potential is applied to the source metal film 50.

[0211] The source metal film 50 is positioned on the uneven region 26 (multiple source openings 25) of the interlayer film 20 in the active region 8. Specifically, the source metal film 50 covers the entire area of ​​the uneven region 26, spaced apart from the gate metal film 30 and the gate wiring metal film 40. The source metal film 50 penetrates the multiple source openings 25 from above the interlayer film 20 and is electrically connected to the multiple source regions 16 and the multiple contact regions 17 within the multiple source openings 25.

[0212] The source metal film 50 has a source metal surface 50s that extends along the insulating surface of the interlayer film 20. The source metal surface 50s has multiple electrode recesses ER resulting from the multiple source openings 25 (see also Figures 5 and 7). In other words, the source metal surface 50s has multiple electrode recesses ER (uneven surfaces) corresponding to the multiple source openings 25 (uneven regions 26).

[0213] The spacing between the multiple electrode recesses ER may be greater than 0 μm and 3 μm or less, similar to the spacing between the multiple source openings 25 (multiple mesa portions 12). The spacing between the electrode recesses ER may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0214] The spacing of the electrode recess ER may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0215] The source metal film 50 has a peripheral portion that extends from the active region 8 to the inactive region 9. The peripheral portion of the source metal film 50 faces the ends of the multiple gate structures 11 via the interlayer film 20. The peripheral portion of the source metal film 50 faces the gate wiring 23 via a portion of the interlayer film 20.

[0216] In this embodiment, the source metal film 50 has a first electrode portion 50a, a second electrode portion 50b, and a third electrode portion 50c. The first electrode portion 50a has a relatively large planar area and forms the main body of the source metal film 50. The planar area of ​​the first electrode portion 50a is larger than the planar area of ​​the gate metal film 30.

[0217] In this configuration, the first electrode portion 50a is formed in a polygonal shape (a quadrilateral shape in this configuration) having four sides parallel to the periphery of the first main surface 3 in a plan view, and is positioned on the third side surface 5C side with respect to the pad region 9a of the inactive region 9.

[0218] The second electrode portion 50b is drawn out in a strip shape (square shape) from one end of the first electrode portion 50a in the first direction X (the end on the second side surface 5B side) toward the first side surface 5A, and faces the pad region 9a in the first direction X. The second electrode portion 50b has a planar area less than the planar area of ​​the first electrode portion 50a. The planar area of ​​the second electrode portion 50b is larger than the planar area of ​​the gate metal film 30. The planar area of ​​the second electrode portion 50b may be smaller than the planar area of ​​the gate metal film 30.

[0219] The third electrode portion 50c is drawn out in a strip-like (square-shaped) manner from the other end of the first electrode portion 50a in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A, and faces the second electrode portion 50b in the first direction X via a pad area 9a. The third electrode portion 50c has a planar area less than that of the first electrode portion 50a.

[0220] The planar area of ​​the third electrode portion 50c is larger than the planar area of ​​the gate metal film 30. The planar area of ​​the third electrode portion 50c may be smaller than the planar area of ​​the gate metal film 30. The planar area of ​​the third electrode portion 50c may be approximately equal to the planar area of ​​the second electrode portion 50b. The planar area of ​​the third electrode portion 50c may be larger or smaller than the planar area of ​​the second electrode portion 50b.

[0221] Either the second electrode portion 50b or the third electrode portion 50c, or both, may be used as terminal portions for current monitoring. The source metal film 50 may have only one of the second electrode portion 50b or the third electrode portion 50c. The source metal film 50 may consist only of the first electrode portion 50a and may not have both the second electrode portion 50b and the third electrode portion 50c.

[0222] The area ratio of the surface area of ​​the source metal film 50 to the surface area of ​​the gate metal film 30 may be between 1 and 100. The area ratio may have a value that falls within at least one of the following ranges: 1 to 5, 5 to 10, 10 to 20, 20 to 40, 40 to 60, 60 to 80, and 80 to 100.

[0223] In this embodiment, the source metal film 50, like the gate metal film 30, has a laminated structure including a source base metal film 51 and a source body metal film 52 that are laminated in this order from the first main surface 3 side. The source base metal film 51 is formed as a barrier electrode and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0224] In this embodiment, the source base metal film 51 has a laminated structure including a first source base metal film 53 and a second source base metal film 54. Of course, the source base metal film 51 may also have a single-layer structure consisting of the first source base metal film 53 or the second source base metal film 54.

[0225] The first source base metal film 53 covers the insulating surface of the interlayer film 20 in a film-like manner and penetrates the multiple source openings 25 from above the interlayer film 20. Specifically, the first source base metal film 53 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 25 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner. The first source base metal film 53 is mechanically and electrically connected to the multiple source regions 16 and the multiple contact regions 17 within the multiple source openings 25.

[0226] The first source base metal film 53 is formed from the same metallic material as the first gate base metal film 33. In this embodiment, the first source base metal film 53 consists of a titanium film, which is an example of a titanium-based metal film. The first source base metal film 53 has a thickness approximately equal to the thickness of the first gate base metal film 33. The thickness of the first source base metal film 53 is less than the thickness of the interlayer film 20.

[0227] The thickness of the first source base metal film 53 may be greater than 0 nm and 200 nm or less. The thickness of the first source base metal film 53 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, and 150 nm or more and 200 nm or less.

[0228] The second source base metal film 54 covers the first source base metal film 53 in a film-like manner and penetrates the multiple source openings 25 from above the interlayer film 20. Specifically, the second source base metal film 54 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner via the first source base metal film 53, a portion that covers the wall surfaces of the multiple source openings 25 in a film-like manner via the first source base metal film 53, and a portion that covers the first main surface 3 in a film-like manner via the first source base metal film 53. The second source base metal film 54 is electrically connected to the multiple source regions 16 and the multiple contact regions 17 via the first source base metal film 53.

[0229] In this embodiment, the second source base metal film 54 is made of a different metal material than the first source base metal film 53. The second source base metal film 54 is formed of the same metal material as the second gate base metal film 34. The second source base metal film 54 is made of a titanium alloy film (titanium nitride film in this embodiment) as an example of a titanium-based metal film.

[0230] The second source base metal film 54 has a thickness approximately equal to the thickness of the second gate base metal film 34. The thickness of the second source base metal film 54 is less than the thickness of the interlayer film 20. In this embodiment, the thickness of the second source base metal film 54 is greater than the thickness of the first source base metal film 53. In this embodiment, the thickness of the second source base metal film 54 may be less than the thickness of the first source base metal film 53.

[0231] The thickness of the second source base metal film 54 may be greater than 0 nm and 300 nm or less. The thickness of the second source base metal film 54 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0232] The source body metal film 52 is laminated in a film-like manner on the source base metal film 51 (interlayer film 20), forming the main body of the source metal film 50. The source body metal film 52 penetrates into multiple source openings 25 from above the interlayer film 20. Specifically, the source body metal film 52 has a portion that covers the interlayer film 20 in a film-like manner via the source base metal film 51, and a portion that is embedded in the multiple source openings 25 via the source body metal film 52.

[0233] The source body metal film 52 is made of a different conductor than the first source underlay metal film 53 and the second source underlay metal film 54. The source body metal film 52 contains a reducing active metal. The source body metal film 52 is formed of the same metallic material as the gate body metal film 32.

[0234] In this embodiment, the source body metal film 52 is made of an aluminum-based metal (pure aluminum or an aluminum alloy having a purity of 99% or more). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0235] The source body metal film 52 is formed from the same metal material as the gate body metal film 32 and has approximately the same thickness as the gate body metal film 32. The thickness of the source body metal film 52 is greater than the thickness of the source underlay metal film 51 (the total thickness of the first source underlay metal film 53 and the second source underlay metal film 54). In this embodiment, the thickness of the source body metal film 52 is greater than the thickness of the interlayer film 20. The thickness of the source body metal film 52 may be less than the thickness of the interlayer film 20.

[0236] The thickness of the source body metal film 52 may be greater than 0 μm and 5 μm or less. The thickness of the source body metal film 52 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0237] In this embodiment, the source body metal film 52 is formed with different crystal densities in the thickness direction Z, similar to the gate body metal film 32. Specifically, the source body metal film 52 has a laminated structure that includes the first source metal film 55 and the second source metal film 56, which are laminated in this order from the interlayer film 20 (source base metal film 51) side, similar to the first gate metal film 35 and the second gate metal film 36.

[0238] The first source metal film 55 is laminated in a film-like manner on the interlayer film 20 (source base metal film 51). The first source metal film 55 covers the source base metal film 51 in a film-like manner and penetrates into the multiple source openings 25 from above the interlayer film 20. The first source metal film 55 has a portion that covers the interlayer film 20 in a film-like manner via the source base metal film 51, and a portion that is embedded in the multiple source openings 25 via the source base metal film 51.

[0239] In this configuration, the first source metal film 55 backfills the multiple source openings 25 and is electrically connected to the multiple source regions 16 and the multiple contact regions 17 within the multiple source openings 25 via the source base metal film 51.

[0240] The first source metal film 55 has multiple electrode recesses that are recessed above the multiple source openings 25 and toward the bottom walls of the multiple source openings 25. In other words, the first source metal film 55 has multiple electrode recesses (uneven surfaces) resulting from the multiple source openings 25 (uneven regions 26).

[0241] The first source metal film 55 contains a plurality of first metal crystal grains MG1 (aluminum-based metal crystal grains) made of the same type of aluminum-based metal as the first gate metal film 35. In other words, the plurality of first metal crystal grains MG1 are laminated on the interlayer film 20 (source base metal film 51) at a relatively low first crystal density per unit area.

[0242] The first source metal film 55 is formed by sputtering at a first deposition temperature, similar to the first gate metal film 35. In the first source metal film 55, the median of the planar area of ​​the plurality of first metal crystal grains MG1 is 8 μm. ２ Larger than that, specifically 10 μm ２That concludes the report. The median area of ​​the multiple first metal crystal grains MG1 is 50 μm. ２ Below, 45μm ２ Below, 40 μm ２ Below, 35μm ２ Below, 30μm ２ Below, 25μm ２ Below, 20μm ２ The following, or 15 μm ２ The following is also acceptable.

[0243] In this embodiment, the first source metal film 55 has a thickness approximately equal to the thickness of the first gate metal film 35. The thickness of the first source metal film 55 may be greater or less than the thickness of the first gate metal film 35. The thickness of the first source metal film 55 is less than the thickness of the second gate metal film 36.

[0244] The thickness of the first source metal film 55 is greater than the thickness (total thickness) of the source base metal film 51. In this embodiment, the thickness of the first source metal film 55 is greater than the thickness of the interlayer film 20 (depth of the source opening 25 and depth of the gate opening 27). The thickness of the first source metal film 55 may be less than the thickness of the interlayer film 20.

[0245] The ratio of the thickness of the first source metal film 55 to the thickness of the source body metal film 52 (first thickness ratio) may be 0.7 or more and less than 1. The first thickness ratio may have a value that falls within at least one of the following ranges: 0.7 or more and 0.75 or less, 0.75 or more and 0.8 or less, 0.8 or more and 0.85 or less, 0.85 or more and 0.95 or less, and 0.95 or more and less than 1.

[0246] The second source metal film 56 is laminated in a film-like manner on the first source metal film 55. The second source metal film 56 is located above the opening ends (insulating surfaces of the interlayer film 20) of the multiple source openings 25.

[0247] The second source metal film 56 has a portion that faces the insulating surface of the interlayer film 20 via the first source metal film 55, and a portion that faces the plurality of source openings 25 via the first source metal film 55. The second source metal film 56 covers the plurality of electrode recesses of the first source metal film 55 in a film-like manner, forming a source metal surface 50s having the plurality of electrode recesses ER.

[0248] The second source metal film 56 contains a plurality of second metal crystal grains MG2 (aluminum-based metal crystal grains) made of the same type of aluminum-based metal as the first source metal film 55 (second gate metal film 36).

[0249] In other words, multiple second metal crystal grains MG2 are stacked on top of multiple first metal crystal grains MG1 (first source metal film 55) at a second crystal density higher than the first crystal density per unit area. Of course, the second source metal film 56 may be made of an aluminum-based metal different from the first source metal film 55 (second gate metal film 36).

[0250] The second source metal film 56, together with the first source metal film 55, forms a metal crystal boundary MB resulting from the density difference between the first crystal density of a plurality of first metal crystal grains MG1 and the second crystal density of a plurality of second metal crystal grains MG2.

[0251] In other words, the source metal film 50 has a boundary MB between the first source metal film 55 and the second source metal film 56 due to the density difference between the first and second crystal densities. The boundary MB extends horizontally above the multiple source openings 25 along the insulating surface of the interlayer film 20 and the source metal surface 50s.

[0252] The second source metal film 56 is formed by sputtering at a second deposition temperature lower than the first deposition temperature, similar to the second gate metal film 36. The median of the planar area of ​​multiple second metal crystal grains MG2 is less than the median of the planar area of ​​multiple first metal crystal grains MG1. The median of the planar area of ​​multiple second metal crystal grains MG2 is 0 μm. ２ Larger than 10 μm ２ It is less than.

[0253] The median area of ​​multiple second metal crystal grains MG2 is 9 μm. ２Below, 8 μm ２ Below, 7 μm ２ Below, 6 μm ２ Below, 5 μm ２ Below, 4μm ２ Below, 3μm ２ Below, 2μm ２ The following, or 1 μm ２ Preferably the following (10 μm at 300°C) ２ It is less than 5 μm at 200°C. ２ (Less than) The median planar area of ​​multiple second metal crystal grains MG2 is 0.5 μm ２ More than 1μm ２ More than 2 μm ２ or greater than 3 μm ２ That's fine too.

[0254] The second source metal film 56 has a thickness less than that of the first source metal film 55 (first gate metal film 35) and forms the surface layer of the source metal surface 50s. The thickness of the second source metal film 56 is approximately equal to the thickness of the second gate metal film 36. The thickness of the second source metal film 56 may be greater or less than the thickness of the second gate metal film 36.

[0255] In this embodiment, the thickness of the second source metal film 56 is less than the thickness of the interlayer film 20 (depth of the source opening 25 and depth of the gate opening 27). The thickness of the second source metal film 56 may be greater than the thickness of the interlayer film 20. In this embodiment, the thickness of the second source metal film 56 is greater than the thickness (total thickness) of the source base metal film 51. The thickness of the second source metal film 56 may be less than the thickness of the source base metal film 51.

[0256] The ratio of the thickness of the second source metal film 56 to the thickness of the source body metal film 52 (second thickness ratio) may be greater than 0 and 0.3 or less. The second thickness ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.25 or less, and 0.25 or more and 0.3 or less.

[0257] The thickness of the second source metal film 56 is preferably greater than 0 nm and 1000 nm or less. The thickness of the second source metal film 56 may have a value that falls within at least one of the following ranges: greater than 0 nm and 100 nm or less, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, and 900 nm to 1000 nm.

[0258] Thus, the source metal film 50 has a laminated structure that includes a first source metal film 55 having a relatively low first crystal density per unit area, and a second source metal film 56 having a second crystal density higher than the first crystal density per unit area.

[0259] The first source metal film 55 is embedded in multiple source openings 25 (uneven regions 26) and covers the insulating surface of the interlayer film 20. This enhances the embedding ability of the source metal film 50 into the multiple source openings 25.

[0260] On the other hand, the second source metal film 56 is positioned above the opening ends of the multiple source openings 25 (the insulating surfaces of the interlayer film 20), forming the source metal surface 50s. This improves the surface condition of the source metal film 50 and reduces the influence of residual oxide ROx on the electrical properties (e.g., resistance) of the source metal film 50.

[0261] Unlike the gate metal surface 30s, the source metal surface 50s has multiple electrode recesses ER resulting from multiple source openings 25 (uneven regions 26). These multiple electrode recesses ER, as well as multiple second grain boundaries, function as delamination initiation points for residual oxide ROx.

[0262] In other words, the source metal surface 50s has a larger surface area than the gate metal surface 30s, while having a greater number of delamination points for residual oxide ROx per unit area than the gate metal surface 30s. As a result, residual oxide ROx is appropriately removed from the source metal surface 50s, which has a relatively large surface area.

[0263] In particular, for multiple electrode recesses ER with spacing of 3 μm or less, the median flat area is 10 μm. ２ By applying multiple second metal crystal grains MG2 of less than , the delamination initiation site per unit area of ​​residual oxide ROx is appropriately increased.

[0264] For example, the median area of ​​multiple second metal crystal grains MG2 is 10 μm. ２ If less than 10%, the maximum width of the second metal crystal grain MG2, which is 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, or 90% or more, may be greater than the spacing of the electrode recesses ER (spacing of the source openings 25).

[0265] In this embodiment, the source body metal film 52 had a laminated structure including a first source metal film 55 and a second source metal film 56. However, the source body metal film 52 may also have a single-layer structure consisting of the second source metal film 56. This configuration also improves the surface condition of the source metal surface 50s.

[0266] The semiconductor device 1A includes an upper insulating film 60 that selectively covers the interlayer film 20. The upper insulating film 60 selectively covers the gate metal film 30, the gate wiring metal film 40, and the source metal film 50 on the interlayer film 20. The upper insulating film 60 protects the covered object from external forces and moisture (humidity).

[0267] The upper insulating film 60 has one or more (one in this embodiment) gate upper openings 61 that cover the peripheral edge of the gate metal film 30 in a film-like manner and expose the inner part of the gate metal film 30. The gate upper openings 61 may also be called "gate pad openings," "first pad openings," etc. In this embodiment, the upper insulating film 60 covers the entire area of ​​the gate wiring metal film 40.

[0268] The upper insulating film 60 has one or more (one in this embodiment) source upper openings 62 that cover the peripheral edge of the source metal film 50 in a film-like manner and expose the inner part of the source metal film 50. The source upper openings 62 may also be called "source pad openings," "second pad openings," etc. In this embodiment, the source upper openings 62 expose the first electrode portion 50a, the second electrode portion 50b, and the third electrode portion 50c together.

[0269] If the upper insulating film 60 has a plurality of source upper openings 62, the plurality of source upper openings 62 may include at least two of the following: a source upper opening 62 that exposes the first electrode portion 50a, a source upper opening 62 that exposes the second electrode portion 50b, and a source upper opening 62 that exposes the third electrode portion 50c.

[0270] The upper insulating film 60 coats the interlayer film 20 in a film-like manner in the outer region 9b of the inactive region 9. The upper insulating film 60 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 63 between itself and the periphery of the chip 2.

[0271] The dicing street 63 exposes the interlayer film 20. If the interlayer film 20 is formed with a gap inward from the periphery of the first main surface 3, the dicing street 63 may expose the first main surface 3. In this case, the upper insulating film 60 may have a portion that directly covers the periphery of the first main surface 3.

[0272] The dicing street 63 extends in a band-like manner along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 63 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the inner part of the chip 2.

[0273] The upper insulating film 60 has a thickness less than the thickness of the chip 2. In this embodiment, the thickness of the upper insulating film 60 is greater than the thickness of the interlayer film 20. The thickness of the upper insulating film 60 may be less than the thickness of the interlayer film 20.

[0274] In this embodiment, the thickness of the upper insulating film 60 is greater than the thickness of the gate metal film 30 (gate wiring metal film 40). The thickness of the upper insulating film 60 may be less than the thickness of the gate metal film 30 (gate wiring metal film 40). In this embodiment, the thickness of the upper insulating film 60 is greater than the thickness of the source metal film 50. The thickness of the upper insulating film 60 may be less than the thickness of the source metal film 50.

[0275] In this embodiment, the thickness of the upper insulating film 60 is greater than the combined thickness of the gate metal film 30 and the source metal film 50. The thickness of the upper insulating film 60 may also be less than the combined thickness of the gate metal film 30 and the source metal film 50.

[0276] The thickness of the upper insulating film 60 may be greater than 0 μm and 50 μm or less. The thickness of the upper insulating film 60 may have a value that falls within at least one of the following ranges: greater than 0 μm and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or more and 50 μm or less.

[0277] In this embodiment, the upper insulating film 60 has a laminated structure including an insulating inorganic film 64 and an insulating organic film 65, which are laminated in this order from the chip 2 side (interlayer film 20 side). The inorganic film 64 may be referred to as the "first insulating film," "inorganic insulating film," etc., and the organic film 65 may be referred to as the "second insulating film," "organic insulating film," "resin film," etc.

[0278] The upper insulating film 60 only needs to contain at least one of the inorganic film 64 and the organic film 65, and does not necessarily need to contain both the inorganic film 64 and the organic film 65 simultaneously. The inorganic film 64 may have a single-layer structure or a multilayer structure containing at least one of the silicon oxide film, silicon nitride film, and silicon oxynitride film.

[0279] The inorganic film 64 may have a single-layer or multilayer structure comprising at least one of the following: NSG film, PSG film, BSG film, BPSG film, and TEOS film. Preferably, the inorganic film 64 contains an insulating material different from the interlayer film 20. Preferably, the inorganic film 64 contains a silicon nitride film.

[0280] The inorganic film 64 selectively covers the gate metal film 30, the gate wiring metal film 40, and the source metal film 50 on the interlayer film 20. The inorganic film 64 covers the periphery of the gate metal film 30 in a film-like manner, and demarcates one or more (one in this embodiment) gate upper openings 61 that expose the inner portion of the gate metal film 30. In this embodiment, the inorganic film 64 covers the entire area of ​​the gate wiring metal film 40.

[0281] The inorganic film 64 covers the peripheral edge of the source metal film 50 in a film-like manner and demarcates one or more (one in this embodiment) source upper openings 62 that expose the inner portion of the source metal film 50. The inorganic film 64 covers the interlayer film 20 in a film-like manner in the outer region 9b. The inorganic film 64 is formed with a gap inward from the peripheral edge of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 63 between itself and the peripheral edge of the chip 2.

[0282] If the interlayer film 20 is formed with a gap inward from the periphery of the first main surface 3, the inorganic film 64 may have a portion that directly covers the periphery of the first main surface 3. The inorganic film 64 may have a thickness less than the thickness of the interlayer film 20. The thickness of the inorganic film 64 may be less than the thickness of the gate metal film 30 (gate wiring metal film 40) and the source metal film 50.

[0283] The thickness of the inorganic film 64 may be greater than 0 μm and less than or equal to 2 μm. The thickness of the inorganic film 64 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, between 0.75 μm and 1 μm, between 1 μm and 1.25 μm, between 1.25 μm and 1.5 μm, between 1.5 μm and 1.75 μm, and between 1.75 μm and 2 μm.

[0284] The organic film 65 may consist of a resin film other than a thermosetting resin. The organic film 65 may consist of a light-transmitting resin or a transparent resin. The organic film 65 may contain a negative-type or positive-type photosensitive resin. The organic film 65 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0285] The organic film 65 coats the inorganic film 64 in a film-like manner. The organic film 65 has portions that cover the interlayer film 20 via the inorganic film 64, portions that cover the gate metal film 30 via the inorganic film 64, portions that cover the gate wiring metal film 40 via the inorganic film 64, and portions that cover the source metal film 50. In this embodiment, the organic film 65 covers the entire area of ​​the gate wiring metal film 40 via the inorganic film 64.

[0286] The organic film 65 covers the peripheral edge of the gate metal film 30 via the inorganic film 64, and demarcates one or more (one in this embodiment) gate upper openings 61 that expose the inner portion of the gate metal film 30. The organic film 65 may expose the end of the inorganic film 64 at the wall surface of the gate upper opening 61. The organic film 65 may cover the end of the inorganic film 64 at the wall surface of the gate upper opening 61.

[0287] The organic film 65 covers the peripheral edge of the source metal film 50 via the inorganic film 64, and defines one or more (one in this embodiment) source upper openings 62 that expose the inner portion of the source metal film 50. The organic film 65 may expose the end of the inorganic film 64 at the wall surface of the source upper opening 62. In this case, the exposed width of the end of the inorganic film 64 may be greater than the thickness of the inorganic film 64. The organic film 65 may cover the end of the inorganic film 64 at the wall surface of the source upper opening 62.

[0288] The organic film 65 coats the interlayer film 20 in a film-like manner via the inorganic film 64 in the outer region 9b. The organic film 65 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 63 between itself and the periphery of the chip 2.

[0289] The outer wall portion of the organic film 65 may be located on the inward side of the first main surface 3 in the dicing street 63 compared to the outer wall portion of the inorganic film 64, and the outer wall portion of the inorganic film 64 may be exposed. The exposed width of the outer wall portion of the inorganic film 64 may be greater than or equal to the thickness of the inorganic film 64. Of course, the outer wall portion of the organic film 65 may be located on the peripheral side of the first main surface 3 compared to the outer wall portion of the inorganic film 64, and may cover the outer wall portion of the inorganic film 64.

[0290] If the interlayer film 20 is formed with a gap inward from the periphery of the first main surface 3, the organic film 65 may have a portion that directly covers the periphery of the first main surface 3. The organic film 65 has a thickness less than the thickness of the chip 2. The thickness of the organic film 65 is greater than the thickness of the inorganic film 64. In this embodiment, the thickness of the organic film 65 is greater than the thickness of the interlayer film 20. The thickness of the organic film 65 may be less than the thickness of the interlayer film 20.

[0291] In this embodiment, the thickness of the organic film 65 is greater than the thickness of the gate metal film 30 (gate wiring metal film 40). The thickness of the organic film 65 may also be less than the thickness of the gate metal film 30 (gate wiring metal film 40). In this embodiment, the thickness of the organic film 65 is greater than the thickness of the source metal film 50. The thickness of the organic film 65 may also be less than the thickness of the source metal film 50.

[0292] In this embodiment, the thickness of the organic film 65 is greater than the combined thickness of the gate metal film 30 and the source metal film 50. The thickness of the organic film 65 may also be less than the combined thickness of the gate metal film 30 and the source metal film 50.

[0293] The thickness of the organic film 65 may be greater than 0 μm and 50 μm or less. The thickness of the organic film 65 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less.

[0294] The inorganic film 64 may cover the peripheral edge of the gate metal film 30 while also having a removal portion that exposes part or all of the corner (electrode side wall) of the gate metal film 30. In this case, the organic film 65 may have a portion within the removal portion of the inorganic film 64 that directly covers the corner (electrode side wall) of the gate metal film 30.

[0295] The inorganic film 64 does not necessarily need to cover the entire gate wiring metal film 40, and may have a removal portion that exposes part or all of the gate wiring metal film 40. In this case, the organic film 65 may have a portion that directly covers the gate wiring metal film 40 within the removal portion of the inorganic film 64.

[0296] The inorganic film 64 may have a removal portion that covers the peripheral edge of the source metal film 50 while exposing part or all of the corners (electrode sidewalls) of the source metal film 50. In this case, the organic film 65 may have a portion that directly covers the corners (electrode sidewalls) of the source metal film 50. The inorganic film 64 may simultaneously have two or three of the removal portions for the gate metal film 30, the gate wiring metal film 40, and the source metal film 50.

[0297] The semiconductor device 1A includes a gate upper metal film 70 disposed on the gate metal surface 30s of the gate metal film 30. The gate upper metal film 70 may also be called a "gate upper electrode". The gate upper metal film 70 is a plating film (gate plating film) laminated within the gate upper opening 61, starting from the gate metal surface 30s.

[0298] In other words, the gate upper metal film 70 covers the second gate metal film 36 (a plurality of second metal crystal grains MG2) which has a relatively high second crystal density. The gate upper metal film 70 has a portion that is in contact with the wall surface of the gate upper opening 61. In this embodiment, the gate upper metal film 70 is in contact with both the inorganic film 64 and the organic film 65 at the wall surface of the gate upper opening 61.

[0299] The gate upper metal film 70 may cover the end of the inorganic film 64 at a distance from the wall surface of the organic film 65, and may be in contact only with the inorganic film 64 at the wall surface of the gate upper opening 61. If the organic film 65 covers the end of the inorganic film 64, the gate upper metal film 70 may be in contact only with the organic film 65 at the wall surface of the gate upper opening 61.

[0300] The gate upper metal film 70 has a gate upper metal surface 70s that is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the gate upper opening 61) toward the gate metal film 30. The gate upper metal surface 70s extends flat along the gate metal surface 30s.

[0301] In this embodiment, the gate upper metal film 70 has a laminated structure including a first nickel film 71, a first palladium film 72, and a first gold film 73, which are stacked in this order from the gate metal film 30 side. The first nickel film 71 is a plating film (first Ni plating film) containing pure nickel or a nickel alloy with a purity of 99% or more.

[0302] The first nickel film 71 is directly laminated in a film-like manner on the gate metal surface 30s within the gate upper opening 61. In other words, the first nickel film 71 directly coats the second gate metal film 36 (a plurality of second metal crystal grains MG2) which has a relatively high second crystal density.

[0303] The first nickel film 71 has a portion that contacts the wall surface of the gate upper opening 61. The first nickel film 71 is in contact with either or both of the inorganic film 64 and the organic film 65 at the wall surface of the gate upper opening 61.

[0304] The first nickel film 71 may cover the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65, and may be in contact only with the inorganic film 64 at the wall surface of the gate upper opening 61. If the organic film 65 covers the edge of the inorganic film 64, the first nickel film 71 may be in contact only with the organic film 65 at the wall surface of the gate upper opening 61. The first nickel film 71 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the gate upper opening 61) toward the gate metal film 30.

[0305] The first nickel film 71 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the first nickel film 71 is greater than the thickness of the interlayer film 20. The thickness of the first nickel film 71 may also be less than the thickness of the interlayer film 20.

[0306] In this embodiment, the thickness of the first nickel film 71 is greater than the thickness of the first gate metal film 35. In this embodiment, the thickness of the first nickel film 71 is greater than the thickness of the second gate metal film 36. In this embodiment, the thickness of the first nickel film 71 is greater than the thickness of the gate metal film 30 (the total thickness of the first gate metal film 35 and the second gate metal film 36).

[0307] The thickness of the first nickel film 71 may be less than the thickness of the gate metal film 30. The thickness of the first nickel film 71 may be less than the thickness of the first gate metal film 35. The thickness of the first nickel film 71 may be less than the thickness of the second gate metal film 36.

[0308] The thickness of the first nickel film 71 may be greater than 0 μm and 50 μm or less. The thickness of the first nickel film 71 may have a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or more and 50 μm or less.

[0309] The first palladium film 72 is a plating film (first Pd plating film) containing pure palladium or a palladium alloy with a purity of 99% or more. The first palladium film 72 is laminated in a film-like manner on the first nickel film 71. The first palladium film 72 has a portion that is in contact with the wall surface of the gate upper opening 61.

[0310] The first palladium film 72 is in contact with the organic film 65 at the wall surface of the gate upper opening 61. If the first nickel film 71 is formed at a distance from the wall surface of the organic film 65, the first palladium film 72 may have a portion that covers the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65. The first palladium film 72 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the gate upper opening 61) toward the gate metal film 30.

[0311] The first palladium film 72 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the first palladium film 72 is less than the thickness of the interlayer film 20. The thickness of the first palladium film 72 may be greater than the thickness of the interlayer film 20. The thickness of the first palladium film 72 may be less than the thickness of the first nickel film 71.

[0312] In this embodiment, the thickness of the first palladium film 72 is smaller than the thickness of the gate metal film 30 (the total thickness of the first gate metal film 35 and the second gate metal film 36). The thickness of the first palladium film 72 may be larger than the thickness of the gate metal film 30.

[0313] In this embodiment, the thickness of the first palladium film 72 is less than the thickness of the first gate metal film 35. The thickness of the first palladium film 72 may be greater than the thickness of the first gate metal film 35. In this embodiment, the thickness of the first palladium film 72 is greater than the thickness of the second gate metal film 36. The thickness of the first palladium film 72 may be less than the thickness of the second gate metal film 36.

[0314] The thickness of the first palladium film 72 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the first palladium film 72 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0315] The first gold film 73 is a plating film (first Au plating film) containing pure gold or a gold alloy with a purity of 99% or more. The first gold film 73 is laminated in a film-like manner on the first palladium film 72. The first gold film 73 has a portion that is in contact with the wall surface of the gate upper opening 61.

[0316] The first gold film 73 is in contact with the organic film 65 at the wall surface of the gate upper opening 61. If the first nickel film 71 is formed at a distance from the wall surface of the organic film 65, the first gold film 73 may have a portion that covers the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65. The first gold film 73 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the gate upper opening 61) toward the gate metal film 30.

[0317] The first gold film 73 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the first gold film 73 is less than the thickness of the interlayer film 20. The thickness of the first gold film 73 may be greater than the thickness of the interlayer film 20. The thickness of the first gold film 73 is less than the thickness of the first nickel film 71. The thickness of the first gold film 73 may be greater than or less than the thickness of the first palladium film 72.

[0318] In this embodiment, the thickness of the first gold film 73 is less than the thickness of the gate metal film 30 (the total thickness of the first gate metal film 35 and the second gate metal film 36). The thickness of the first gold film 73 may be greater than the thickness of the gate metal film 30.

[0319] In this embodiment, the thickness of the first gold film 73 is less than the thickness of the first gate metal film 35. The thickness of the first gold film 73 may be greater than the thickness of the first gate metal film 35. In this embodiment, the thickness of the first gold film 73 is greater than the thickness of the second gate metal film 36. The thickness of the first gold film 73 may be less than the thickness of the second gate metal film 36.

[0320] The thickness of the first gold film 73 may be greater than 0 μm and 1 μm or less. The thickness of the first gold film 73 may be greater than 0 μm and 0.2 μm or less, 0.2 μm or more and 0.4 μm or less, 0.4 μm or more and 0.6 μm or less, 0.6 μm or more and 0.8 μm or less, and 0.8 μm or more and 1 μm or less.

[0321] Figure 17 is a diagram illustrating the relationship between the crystal density of the gate metal film 30 and the surface state of the gate upper metal film 70 (gate upper metal surface 70s). Figure 17 is the same as Figure 15, but with four additional image diagrams showing the surface state of the gate upper metal surface 70s, as captured by a metallurgical microscope. Specifically, the four image diagrams show the gate upper metal surface 70s when the gate upper metal film 70 is formed on top of the gate metal film 30 formed at deposition temperatures of 400°C, 350°C, 300°C, and 200°C.

[0322] Under a metallurgical microscope, light was shone onto the gate upper metal surface 70s, and the surface condition was observed based on the contrast of light and dark in the reflected light. In the four image diagrams, the black dots indicate fine pits (FP) formed on the gate upper metal surface 70s. These fine pits (FP) may also be referred to as "fine recesses."

[0323] Referring to Figure 17, the amount of fine pitted FP decreased with decreasing deposition temperature. In other words, the amount of fine pitted FP decreased with increasing crystal density per unit area of ​​the gate metal film 30 (multiple metal crystal grains MG).

[0324] In particular, the number of fine pit FPs decreased significantly above 300°C. From this, it can be understood that as the crystal density increased, the starting point for the formation of fine pit FPs decreased, and as the film formation properties of the gate upper metal film 70 improved, the flatness (smoothness) of the gate upper metal surface 70s improved.

[0325] Referring again to Figure 16, in the case of the gate metal surface 30s according to the reference example, residual oxide ROx remains on the gate metal surface 30s. The affinity of the gate upper metal film 70 (first nickel film 71 in this embodiment) to the gate metal surface 30s differs between the region on the residual oxide ROx and the region outside the residual oxide ROx.

[0326] Therefore, the gate upper metal film 70 includes a first coating portion CP1 that covers the gate metal surface 30s outside the residual oxide ROx, and a second coating portion CP2 that covers the residual oxide ROx. The first coating portion CP1 has a relatively large thickness, while the second coating portion CP2 has a smaller thickness than the first coating portion CP1.

[0327] In the case of the gate metal surface 30s according to the reference example, the residual oxide ROx functions as a film formation inhibiting part (plating inhibiting part in this embodiment) of the gate upper metal film 70, resulting in the thickness of the second coating part CP2 being lower than the thickness of the first coating part CP1. As a result, the second coating part CP2 is recessed toward the residual oxide ROx, forming fine pit FP on the gate metal surface 30s. In other words, the residual oxide ROx becomes the starting point for the formation of fine pit FP on the gate upper metal surface 70s.

[0328] On the other hand, referring again to Figure 13, the gate metal surface 30s in the first embodiment is formed by a second gate metal film 36 having a relatively high second crystal density, thereby suppressing the remaining residual oxide ROx. As a result, the formation of fine pit FPs caused by residual oxide ROx is suppressed, and the flatness (film formation) of the gate upper metal film 70 on the gate metal surface 30s is improved.

[0329] The semiconductor device 1A includes a source upper metal film 75 disposed on the source metal surface 50s of the source metal film 50. The source upper metal film 75 may also be called a "source upper electrode". The source upper metal film 75 is a plating film (source plating film) laminated within the source upper opening 62, starting from the source metal surface 50s.

[0330] In other words, the source upper metal film 75 covers the second source metal film 56 (a plurality of second metal crystal grains MG2) which has a relatively high second crystal density. The source upper metal film 75 has a portion that is in contact with the wall surface of the source upper opening 62. In this embodiment, the source upper metal film 75 is in contact with both the inorganic film 64 and the organic film 65 at the wall surface of the source upper opening 62.

[0331] The source upper metal film 75 may cover the end of the inorganic film 64 at a distance from the wall surface of the organic film 65, and may be in contact only with the inorganic film 64 at the wall surface of the source upper opening 62. If the organic film 65 covers the end of the inorganic film 64, the source upper metal film 75 may be in contact only with the organic film 65 at the wall surface of the source upper opening 62.

[0332] The source upper metal film 75 has a source upper metal surface 75s that is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the source upper opening 62) toward the source metal film 50. The source upper metal surface 75s extends along the source metal surface 50s and has multiple recesses (multiple irregularities) caused by multiple electrode recesses ER (multiple irregularities) of the source metal surface 50s.

[0333] In this embodiment, the source upper metal film 75 has a laminated structure that includes a second nickel film 76, a second palladium film 77, and a second gold film 78, which are laminated in this order from the source metal film 50 side, similar to the first nickel film 71, first palladium film 72, and first gold film 73 of the gate upper metal film 70.

[0334] The second nickel film 76 is a plating film (first Ni plating film) containing pure nickel or a nickel alloy with a purity of 99% or more. The second nickel film 76 is formed from the same type of nickel material as the first nickel film 71.

[0335] The second nickel film 76 is directly laminated in a film-like manner on the source metal surface 50s within the source upper opening 62. In other words, the second nickel film 76 directly coats the second source metal film 56 (multiple second metal crystal grains MG2) which has a relatively high second crystal density.

[0336] The second nickel film 76 has a portion in contact with the wall surface of the source upper opening 62. The second nickel film 76 is in contact with one or both of the inorganic film 64 and the organic film 65 on the wall surface of the source upper opening 62.

[0337] The second nickel film 76 may cover the end of the inorganic film 64 with a space from the wall surface of the organic film 65, and be in contact with only the inorganic film 64 on the wall surface of the source upper opening 62. When the organic film 65 covers the end of the inorganic film 64, the second nickel film 76 may be in contact with only the organic film 65 on the wall surface of the source upper opening 62. The second nickel film 76 is formed with a space from the height position of the insulating surface of the upper insulating film 60 (the opening end of the source upper opening 62) toward the source metal film 50 side.

[0338] The second nickel film 76 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the second nickel film 76 is greater than the thickness of the interlayer film 20. The thickness of the second nickel film 76 may be less than the thickness of the interlayer film 20.

[0339] In this embodiment, the thickness of the second nickel film 76 is greater than the thickness of the first source metal film 55 (first gate metal film 35). In this embodiment, the thickness of the second nickel film 76 is greater than the thickness of the second source metal film 56 (second gate metal film 36). In this embodiment, the thickness of the second nickel film 76 is greater than the thickness of the source metal film 50 (gate metal film 30) (the total thickness of the thickness of the first source metal film 55 and the thickness of the second source metal film 56).

[0340] The thickness of the second nickel film 76 may be smaller than the thickness of the source metal film 50. The thickness of the second nickel film 76 may be smaller than the thickness of the first source metal film 55. The thickness of the second nickel film 76 may be smaller than the thickness of the second source metal film 56. In this embodiment, the thickness of the second nickel film 76 is substantially equal to the thickness of the first nickel film 71. The thickness of the second nickel film 76 may be larger or smaller than the thickness of the first nickel film 71.

[0341] The thickness of the second nickel film 76 may be greater than 0 μm and 50 μm or less. The thickness of the second nickel film 76 may be a value falling within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, and 40 μm or more and 50 μm or less.

[0342] The second palladium film 77 is a plated film (first Pd plated film) containing pure palladium having a purity of 99% or more or a palladium alloy. The second palladium film 77 is formed of the same type of palladium material as the first palladium film 72. The second palladium film 77 is laminated in a film form on the second nickel film 76. The second palladium film 77 has a portion in contact with the wall surface of the source upper opening 62.

[0343] The second palladium film 77 is in contact with the organic film 65 on the wall surface of the source upper opening 62. When the second nickel film 76 is formed spaced apart from the wall surface of the organic film 65, the second palladium film 77 may have a portion that is spaced apart from the wall surface of the organic film 65 and covers an end portion of the inorganic film 64. The second palladium film 77 is formed spaced apart toward the source metal film 50 from the height position of the insulating surface of the upper insulating film 60 (the opening end of the source upper opening 62).

[0344] The thickness of the first palladium film 72 is less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the second palladium film 77 is less than the thickness of the interlayer film 20. The thickness of the second palladium film 77 may be greater than the thickness of the interlayer film 20.

[0345] The thickness of the second palladium film 77 is smaller than the thickness of the second nickel film 76 (first nickel film 71). In this embodiment, the thickness of the second palladium film 77 is substantially equal to the thickness of the first palladium film 72. The thickness of the second palladium film 77 may be greater than or smaller than the thickness of the first palladium film 72.

[0346] In this embodiment, the thickness of the second palladium film 77 is smaller than the thickness of the source metal film 50 (gate metal film 30) (the total thickness of the first source metal film 55 and the second source metal film 56). The thickness of the second palladium film 77 may be larger than the thickness of the source metal film 50.

[0347] In this embodiment, the thickness of the second palladium film 77 is smaller than the thickness of the first source metal film 55 (first gate metal film 35). The thickness of the second palladium film 77 may be larger than the thickness of the first source metal film 55. In this embodiment, the thickness of the second palladium film 77 is larger than the thickness of the second source metal film 56 (second gate metal film 36). The thickness of the second palladium film 77 may be smaller than the thickness of the second source metal film 56.

[0348] The thickness of the second palladium film 77 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the second palladium film 77 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0349] The second gold film 78 is a plating film (first Au plating film) containing pure gold or a gold alloy with a purity of 99% or more. The second gold film 78 is formed from the same type of gold material as the first gold film 73. The second gold film 78 is laminated in a film-like manner on the second palladium film 77. The second gold film 78 has a portion that is in contact with the wall surface of the source upper opening 62.

[0350] The second gold film 78 is in contact with the organic film 65 at the wall surface of the source upper opening 62. If the second nickel film 76 is formed at a distance from the wall surface of the organic film 65, the second gold film 78 may have a portion that covers the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65. The second gold film 78 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the source upper opening 62) toward the source metal film 50.

[0351] The thickness of the second gold film 78 is less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the second gold film 78 is less than the thickness of the interlayer film 20. The thickness of the second gold film 78 may be greater than the thickness of the interlayer film 20.

[0352] The thickness of the second gold film 78 is less than the thickness of the second nickel film 76 (first nickel film 71). The thickness of the second gold film 78 may be greater than or less than the thickness of the second palladium film 77 (first palladium film 72). In this configuration, the thickness of the second gold film 78 is approximately equal to the thickness of the first gold film 73. The thickness of the second gold film 78 may be greater than or less than the thickness of the first gold film 73.

[0353] In this embodiment, the thickness of the second gold film 78 is less than the thickness of the source metal film 50 (gate metal film 30) (the total thickness of the first source metal film 55 and the second source metal film 56). The thickness of the second gold film 78 may be greater than the thickness of the source metal film 50.

[0354] In this embodiment, the thickness of the second gold film 78 is less than the thickness of the first source metal film 55 (first gate metal film 35). The thickness of the second gold film 78 may be greater than the thickness of the first source metal film 55. In this embodiment, the thickness of the second gold film 78 is greater than the thickness of the second source metal film 56 (second gate metal film 36). The thickness of the second gold film 78 may be less than the thickness of the second source metal film 56.

[0355] The thickness of the second gold film 78 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the second gold film 78 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0356] Referring again to Figures 5, 6, and 11, the source metal film 50, like the gate metal film 30, has a source metal surface 50s formed by a second source metal film 56 having a relatively high second crystal density. As a result, multiple depressions caused by multiple second crystal grain boundaries function as delamination initiation points for residual oxide ROx, thereby properly removing residual oxide ROx and suppressing the remaining residual oxide ROx on the source metal surface 50s.

[0357] As a result, the surface condition of the source metal surface 50s is improved, and at the same time, the influence of residual oxide ROx on the electrical properties (e.g., resistance) of the source metal film 50 is reduced. In addition, the flatness (film formation) of the source upper metal film 75 on the source metal surface 50s is improved, and the formation of fine pit FPs caused by residual oxide ROx is suppressed.

[0358] Unlike the gate metal surface 30s, the source metal surface 50s has multiple electrode recesses ER resulting from multiple source openings 25 (uneven regions 26). These multiple electrode recesses ER, like multiple second grain boundaries, function as delamination initiation points for residual oxide ROx. As a result, the formation of fine pits FP in the source upper metal film 75, which has a larger planar area than the gate upper metal film 70, is appropriately suppressed.

[0359] The semiconductor device 1A includes a drain metal film 80 as a drain pad electrode covering the second main surface 4. The drain metal film 80 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," etc. The drain metal film 80 may have a single-layer structure or a multilayer structure containing at least one of an aluminum-based metal film, a titanium-based metal film, a nickel-based metal film, a palladium-based metal film, a gold-based metal film, and a silver-based metal film.

[0360] The drain metal film 80 covers the entire area of ​​the second main surface 4 and is mechanically and electrically connected to the first semiconductor layer 6. The drain metal film 80 forms ohmic contact with the first semiconductor layer 6. The drain metal film 80 may be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The drain metal film 80 may partially cover the second main surface 4 so that the peripheral portion of the second main surface 4 is exposed.

[0361] The breakdown voltage that can be applied between the source metal film 50 (source upper metal film 75) and the drain metal film 80 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less.

[0362] The breakdown voltage may have a value that falls within at least one of the following ranges: 500V to 750V, 750V to 1000V, 1000V to 1250V, 1250V to 1500V, 1500V to 1750V, 1750V to 2000V, 2000V to 2250V, 2250V to 2500V, and 2500V to 3000V.

[0363] As described above, the semiconductor device 1A may include a coating (20) and metal films (30, 50). The metal films (30, 50) may be placed on the coating (20) and may include metal surfaces (30s, 50s) formed by a plurality of metal crystal grains (MG). The median flat area per unit area of ​​the plurality of metal crystal grains (MG) is 10 μm. ２ It is acceptable to be less than [a certain value].

[0364] This configuration provides a semiconductor device 1A having metal films (30, 50) with excellent surface condition. For example, with this semiconductor device 1A, the residue of residual oxides (ROx) on the metal surfaces (30s, 50s) can be suppressed. This reduces the electrical effects caused by residual oxides (ROx) and simultaneously suppresses the deterioration of the reliability of the metal films (30, 50) caused by residual oxides (ROx).

[0365] The semiconductor device 1A may include an upper insulating film (60). The upper insulating film (60) is placed on the metal films (30, 50) and may have upper openings (61, 62) that expose the metal films (30, 50). With this configuration, the metal films (30, 50) are protected by the upper insulating film (60).

[0366] The semiconductor device 1A may include upper metal films (70, 75). The upper metal films (70, 75) may cover the metal films (30, 50) within the upper openings (61, 62). This configuration suppresses poor film formation of the upper metal films (70, 75) caused by residual oxides (ROx) and improves the flatness of the upper metal films (70, 75) relative to the metal films (30, 50).

[0367] The coating (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the metal film (30) may be placed on the flat region (28) at a distance from the uneven region (26).

[0368] The chip (2) may contain SiC. This configuration provides a semiconductor device 1A as a novel SiC semiconductor device. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of suppressing residual oxides (ROx) is effective in improving electrical properties and reliability.

[0369] From an alternative perspective, the semiconductor device 1A may include a coating (20) and metal films (30, 50). The metal films (30, 50) may cover the coating (20) and have metal surfaces (30s, 50s) extending along the coating (20). In such a configuration, the metal films (30, 50) may have a first metal film (35, 55) and a second metal film (36, 56).

[0370] The first metal films (35, 55) are formed on the coating body (20) side and may have a first crystal density per unit area. The second metal films (36, 56) are formed on the metal surface (30s, 50s) side and may have a second crystal density higher than the first crystal density per unit area.

[0371] According to this configuration, a semiconductor device 1A having metal films (30, 50) with an excellent surface state is provided. For example, according to this semiconductor device 1A, the residual oxide (ROx) remaining on the metal surfaces (30s, 50s) can be suppressed by the second metal films (36, 56).

[0372] Thereby, the electrical influence caused by the residual oxide (ROx) is reduced, and at the same time, the decrease in reliability of the metal films (30, 50) caused by the residual oxide (ROx) is suppressed. Further, if a conventional semiconductor device has a metal film corresponding to the first metal film (35, 55), the reliability of the metal film can be improved only by adding the second metal film (36, 56).

[0373] The second metal films (36, 56) may have a thickness smaller than the thickness of the first metal films (35, 55). According to this configuration, since the relatively thin second metal films (36, 56) are formed on the relatively thick first metal films (35, 55), manufacturing is easy.

[0374] The metal films (30, 50) may have a metal crystal boundary portion (MB) that extends along the metal surfaces (30s, 50s) between the first metal films (35, 55) and the second metal films (36, 56), and is formed due to the density difference between the first crystal density and the second crystal density.

[0375] The first metal films (35, 55) may have a first value with respect to the median of the area of a plurality of crystal grains per unit area. The second metal films (36, 56) may have a second value smaller than the first value with respect to the median. The first value may be 10 µm ２ or more and 50 µm ２ or less. The second value is larger than 0 µm ２ and smaller than 10 µm ２ .

[0376] The coating (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the metal films (30, 50) may be placed on the flat region (28) of the coating (20).

[0377] The coating (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the metal films (30, 50) may be placed on the uneven region (26) of the coating (20).

[0378] In this case, the first metal film (55) may backfill the uneven region (26). The second metal film (56) may cover the first metal film (55) in a film-like manner above the uneven region (26). With this configuration, the unevenness caused by the uneven region (26) is mitigated by the first metal film (55), which has relatively good embedding properties, and the flatness on the uneven region (26) is improved. On the other hand, the remaining residual oxide (ROx) is suppressed by the second metal film (56).

[0379] The metal film (30, 50) may be a gate metal film (30). This configuration provides a semiconductor device 1A having a gate metal film (30) with excellent surface condition. For example, this configuration can suppress the residue of residual oxide (ROx) on the gate metal surface (30s). This reduces the electrical effects caused by residual oxide (ROx) and simultaneously suppresses the deterioration of the reliability of the gate metal film (30) caused by residual oxide (ROx).

[0380] The metal film (30, 50) may also be a source metal film (50). This configuration provides a semiconductor device 1A having a source metal film (50) with excellent surface condition. For example, this configuration can suppress the residue of residual oxides (ROx) on the source metal surface (50s). This reduces electrical effects caused by residual oxides (ROx) and simultaneously suppresses a decrease in the reliability of the source metal film (50) caused by residual oxides (ROx).

[0381] The semiconductor device 1A may include an upper insulating film (60). The upper insulating film (60) may partially cover the metal films (30, 50) and have upper openings (61, 62) that selectively expose the metal films (30, 50). With this configuration, the metal films (30, 50) can be protected by the upper insulating film (60), and at the same time, a potential application portion to the metal films (30, 50) can be ensured through the upper openings (61, 62).

[0382] The upper insulating film (60) may have a single-layer structure or a multilayer structure including either or both of an insulating inorganic film (64) and an insulating organic film (65). The upper insulating film (60) may also have a multilayer structure including an inorganic film (64) and an organic film (65) stacked in this order from the coating body (20) side.

[0383] The semiconductor device 1A may include upper metal films (70, 75) that cover the metal films (30, 50). The upper metal films (70, 75) may cover the metal films (30, 50) within the upper openings (61, 62). This configuration suppresses poor film formation of the upper metal films (70, 75) caused by residual oxides (ROx) and improves the flatness of the upper metal films (70, 75) relative to the metal films (30, 50).

[0384] The semiconductor device 1A may include a chip (2) and an insulating interlayer film (20) as a coating (20). The interlayer film (20) may cover the chip (2). In this case, the metal films (30, 50) may cover the interlayer film (20).

[0385] The chip (2) may contain SiC. This configuration provides a semiconductor device 1A as a novel SiC semiconductor device. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of suppressing residual oxides (ROx) is effective in improving electrical properties and reliability.

[0386] The semiconductor device 1A may include an active region (8), an inactive region (9), and a transistor structure (T). The active region (8) may be provided on the chip (2). The inactive region (9) may be provided on the chip (2) outside the active region (8). The transistor structure (T) may be formed in the active region (8). The interlayer film (20) may cover the chip (2) with the active region (8) and the inactive region (9).

[0387] The metal film (30) may cover the interlayer film (20) in the inactive region (9) and be electrically connected to the gate of the transistor structure (T). This configuration provides a semiconductor device 1A having a gate metal film (30) as a metal film (30) with excellent surface condition.

[0388] This configuration suppresses the residue of residual oxides (ROx) on the gate metal surface (30s). As a result, electrical effects caused by residual oxides (ROx) are reduced, and at the same time, the deterioration of the reliability of the gate metal film (30) caused by residual oxides (ROx) is suppressed.

[0389] The metal film (50) may cover the interlayer film (20) in the active region (8) and be electrically connected to the source of the transistor structure (T). This configuration provides a semiconductor device 1A having a source metal film (50) as a metal film (50) with excellent surface condition.

[0390] This configuration suppresses the residue of residual oxides (ROx) on the source metal surface (50s). As a result, electrical effects caused by residual oxides (ROx) are reduced, and at the same time, the deterioration of the reliability of the source metal film (50) caused by residual oxides (ROx) is suppressed.

[0391] Figure 18 is a schematic diagram showing a wafer structure 81 (semiconductor wafer structure) used in the manufacture of semiconductor device 1A. The wafer structure 81 includes a wafer 82. The wafer 82 is the substrate for the chip 2 and is made of the same material as the chip 2.

[0392] The wafer 82 is formed in a flat disc shape. Of course, the wafer 82 may also be formed in a flat rectangular parallelepiped shape. The wafer 82 has a first wafer main surface 83 on one side, a second wafer main surface 84 on the other side, and a wafer side surface 85 connecting the first wafer main surface 83 and the second wafer main surface 84. The first wafer main surface 83 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 84 corresponds to the second main surface 4 of the chip 2.

[0393] The wafer structure 81 has markings 86 on the wafer side surface 85 that indicate the crystal orientation of the SiC single crystal. The markings 86 may include either an orientation flat or an orientation notch, or both (Figure 18 illustrates an orientation flat).

[0394] An orientation flat consists of a notch that is cut out in a straight line when viewed from above. An orientation notch consists of a notch that is recessed in a concave shape (for example, tapered shape) toward the center of the first wafer main surface 83 when viewed from above.

[0395] The marker 86 may include either or both a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction. The marker 86 may also include either or both an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.

[0396] The wafer structure 81 includes a plurality of device regions 87 set on the wafer 82 (first wafer main surface 83). The plurality of device regions 87 are regions corresponding to the semiconductor device 1A and are each set in a rectangular shape in plan view. In this configuration, the plurality of device regions 87 are set in a matrix along the first direction X and the second direction Y in plan view. The plurality of device regions 87 are each set with a gap inward from the wafer side surface 85 in plan view.

[0397] Multiple device regions 87 are demarcated by multiple cutting lines 88 that extend in a grid pattern along a first direction X and a second direction Y. The multiple cutting lines 88 correspond to the first to fourth sides 5A to 5D of the chip 2. The multiple cutting lines 88 are defined by multiple alignment marks, etc., formed on the wafer 82 (for example, the first wafer main surface 83).

[0398] Although specific illustrations are omitted, the wafer structure 81 includes an active region 8, an inactive region 9, a body region 10, a plurality of gate structures 11, a plurality of source regions 16, a plurality of contact regions 17, a well region 18, an interlayer film 20, gate wiring 23, uneven regions 26 (a plurality of source openings 25), a flat region 28, and a plurality of gate openings 27 in each device region 87.

[0399] These configurations are obtained by replacing "chip 2" with "wafer 82" in the above description, replacing "first main surface 3" with "first wafer main surface 83", replacing "second main surface 4" with "first wafer main surface 83", and replacing "first to fourth side surfaces 5A to 5D" with "planned cutting lines 88 (first to fourth planned cutting lines 88 corresponding to the first to fourth side surfaces 5A to 5D)".

[0400] Figures 19A to 19L are cross-sectional views showing examples of manufacturing methods for the semiconductor device 1A shown in Figure 1. Figure 20 is an enlarged cross-sectional view showing the process of forming the first base metal film 95. Figure 21 is an enlarged cross-sectional view showing the process of forming the second base metal film 96. Figure 22 is an enlarged cross-sectional view showing the process of forming the oxide film 99. Figure 23 is an enlarged cross-sectional view showing the process of removing the oxide film 99. Figure 23 is an enlarged cross-sectional view showing the process of forming the gate upper metal film 70 (source upper metal film 75).

[0401] The manufacturing process of the pad region 9a of the wafer structure 81 shown in Figure 12 will be described below. In addition, specific descriptions of various components of the semiconductor device 1A (including numerical values ​​such as thickness and size) will be omitted as appropriate, and the above-mentioned explanation will apply.

[0402] First, a wafer structure 81 is prepared, referring to Figure 19A. Next, the process of forming the base metal film 90 is carried out, referring to Figures 19B to 19D. The base metal film 90 is the base for the gate metal film 30, the gate wiring metal film 40, and the source metal film 50, and has a base surface 90s that has regions corresponding to the gate metal surface 30s and the source metal surface 50s.

[0403] Referring to Figure 19B, the process of forming the base metal film 90 includes the process of forming the base underlay metal film 91. The base underlay metal film 91 is the base for the gate underlay metal film 31 and the source underlay metal film 51. In this embodiment, the process of forming the base underlay metal film 91 includes the process of forming a first base underlay metal film 92 and the process of forming a second base underlay metal film 93.

[0404] The first base underlay metal film 92 is the base for the first gate underlay metal film 33 and the first source underlay metal film 53, and consists of a titanium film as an example of a titanium-based metal film. The first base underlay metal film 92 is formed in a film-like manner on the insulating surface of the interlayer film 20 by sputtering. The first base underlay metal film 92 covers the entire area of ​​the interlayer film 20 in each device region 87.

[0405] In other words, the first base underlay metal film 92 covers the uneven regions 26 and flat regions 28 of the interlayer film 20 in a film-like manner. Specifically, the first base underlay metal film 92 is formed in a film-like manner following the first wafer main surface 83, the insulating surface of the interlayer film 20, the walls of the multiple source openings 25, and the walls of the multiple gate openings 27.

[0406] The second base underlay metal film 93 is the base for the second gate underlay metal film 34 and the second source underlay metal film 54, and consists of a titanium alloy film (in this embodiment, a titanium nitride film) as an example of a titanium-based metal film. The second base underlay metal film 93 is formed in a film-like manner on the first base underlay metal film 92 by sputtering. The second base underlay metal film 93 covers the entire interlayer film 20 via the first base underlay metal film 92 in each device region 87.

[0407] In other words, the second base underlay metal film 93 covers the uneven regions 26 and flat regions 28 of the interlayer film 20 in a film-like manner via the first base underlay metal film 92. Specifically, the second base underlay metal film 93 is formed in a film-like manner via the first base underlay metal film 92, following the shape of the first wafer main surface 83, the insulating surface of the interlayer film 20, the walls of the multiple source openings 25, and the walls of the multiple gate openings 27.

[0408] Referring to Figures 19C and 19D, the process of forming the base metal film 90 includes the process of forming the base body metal film 94. In this embodiment, the process of forming the base body metal film 94 includes the process of forming the first base metal film 95 and the process of forming the second base metal film 96 (see also Figures 20 and 21).

[0409] The first base metal film 95 is the base for the first gate metal film 35 and the first source metal film 55, and is made of an aluminum-based metal. The second base metal film 96 is the base for the second gate metal film 36 and the second source metal film 56, and is made of an aluminum-based metal. The metal type of the second base metal film 96 is the same as the metal type of the first base metal film 95.

[0410] Referring to Figure 19C, the first base metal film 95 is formed on the base underlay metal film 91 by sputtering at the aforementioned first deposition temperature (higher than 300°C and 500°C or lower) (see also Figure 20). The first deposition temperature may be a value that falls within at least one of the following ranges: higher than 300°C and 350°C or lower, 350°C or higher and 400°C or lower, 400°C or higher and 450°C or lower, and 450°C or higher and 500°C or lower. The first deposition temperature is preferably 350°C or higher.

[0411] As a result, multiple first metal crystal grains MG1 are deposited on the base metal film 91 with a relatively high first crystal density, forming a first base metal film 95. The first median of the planar area of ​​the multiple first metal crystal grains MG1 is 8 μm ２ Larger than that, specifically 10 μm ２ That concludes the report. The first median is 50 μm. ２ Below, 45μm ２ Below, 40 μm ２ Below, 35μm ２ Below, 30μm２ Below, 25μm ２ Below, 20μm ２ The following, or 15 μm ２ The following is also acceptable.

[0412] The first base metal film 95 is formed to cover the entire interlayer film 20 in each device region 87 via the base underlay metal film 91. In other words, the first base metal film 95 covers the uneven regions 26 and flat regions 28 of the interlayer film 20 in a film-like manner via the base underlay metal film 91.

[0413] Specifically, the first base metal film 95 backfills the multiple source openings 25 and multiple gate openings 27 via the base underlay metal film 91, and covers the base underlay metal film 91 in a film-like manner on the insulating surface of the interlayer film 20. Multiple electrode recesses are formed on the electrode surface of the first source metal film 55.

[0414] Referring to Figure 19D, the second base metal film 96 is formed on the first base metal film 95 by sputtering at the aforementioned second deposition temperature (0°C to 300°C) (see also Figure 21). The second deposition temperature may have a value that falls within at least one of the following ranges: 0°C to 50°C, 50°C to 100°C, 100°C to 150°C, 150°C to 200°C, 200°C to 250°C, and 250°C to 300°C.

[0415] The second precipitation temperature is preferably less than 300°C. The second precipitation temperature is preferably 250°C or lower. The second precipitation temperature is preferably 200°C or lower. The second precipitation temperature may be 50°C or higher, 75°C or higher, 100°C or higher, 125°C or higher, 150°C or higher, or 175°C or higher.

[0416] As a result, multiple second metal crystal grains MG2 are deposited on the first base metal film 95 (multiple first metal crystal grains MG1) at a second crystal density lower than the first crystal density, forming a second base metal film 96. The second median of the planar area of ​​the multiple second metal crystal grains MG2 is less than the first median of the planar area of ​​the multiple first metal crystal grains MG1. The second median is 0 μm. ２ Larger than 10 μm ２ It is less than.

[0417] The second median is 9 μm. ２ Below, 8 μm ２ Below, 7 μm ２ Below, 6 μm ２ Below, 5 μm ２ Below, 4μm ２ Below, 3μm ２ Below, 2μm ２ The following, or 1 μm ２ Preferably the following (10 μm at 300°C) ２ It is less than 5 μm at 200°C. ２ (It is less than ). The second median is 0.5 μm ２ More than 1μm ２ More than 2 μm ２ or greater than 3 μm ２ That's fine too.

[0418] The second base metal film 96 is formed to cover the entire interlayer film 20 via the first base metal film 95 in each device region 87. In other words, the second base metal film 96 covers the uneven regions 26 and flat regions 28 of the interlayer film 20 in a film-like manner via the first base metal film 95.

[0419] Specifically, the second base metal film 96 faces the insulating surface of the interlayer film 20 via the first base metal film 95, and faces a plurality of source openings 25 and a plurality of gate openings 27 via the first base metal film 95. A plurality of electrode recesses ER caused by the plurality of source openings 25 are formed on the base surface 90s of the second base metal film 96. As a result, a base metal film 90 having a laminated structure including a base underlay metal film 91 and a base body metal film 94 is formed.

[0420] Next, referring to Figure 19E, a first resist mask 97 having a predetermined pattern is formed on the base metal film 90. The first resist mask 97 is formed by applying a photoresist to the base metal film 90, and then exposing and developing the photoresist in a predetermined pattern. The first resist mask 97 covers the areas on the base metal film 90 where the gate metal film 30, gate wiring metal film 40, and source metal film 50 are to be formed, while leaving the other areas exposed.

[0421] Next, unwanted portions of the base metal film 90 are removed by etching via the first resist mask 97. This process includes etching of the second base metal film 96, etching of the first base metal film 95, etching of the second base underlay metal film 93, and etching of the first base underlay metal film 92.

[0422] In this step, the first base metal film 95 and the second base metal film 96 are removed simultaneously, and then the second base underlay metal film 93 and the first base underlay metal film 92 are removed in sequence. These etching methods may be either dry etching or wet etching, or both. This forms the gate metal film 30, the gate wiring metal film 40, and the source metal film 50. The first resist mask 97 is then removed.

[0423] Next, referring to Figures 19F to 19J, the process of forming the upper insulating film 60 is carried out. Referring to Figure 19F, in this process, first, the inorganic film 64 of the upper insulating film 60 is formed on the interlayer film 20 so as to cover the gate metal film 30, the gate wiring metal film 40, and the source metal film 50. The inorganic film 64 may be formed by the CVD (Chemical Vapor Deposition) method.

[0424] Next, referring to Figure 19G, a second resist mask 98 having a predetermined pattern is formed on the interlayer film 20 so as to cover the gate metal film 30, the gate wiring metal film 40, and the source metal film 50.

[0425] The second resist mask 98 is formed by coating a photoresist onto the interlayer film 20, and then exposing and developing the photoresist in a predetermined pattern. The second resist mask 98 exposes the areas on the inorganic film 64 where the gate upper opening 61, source upper opening 62, and dicing street 63 are to be formed, while covering the areas other than those areas.

[0426] Next, unwanted portions of the inorganic film 64 are removed by etching via the second resist mask 98. The etching method may be either dry etching or wet etching, or both. This forms the gate upper opening 61, the source upper opening 62, and the dicing street 63 in the inorganic film 64.

[0427] Next, referring to Figure 19H, the removal of the second resist mask 98 is performed. In this step, the second resist mask 98 is removed by an oxygen plasma ashing method.

[0428] Referring to Figure 22, this step includes the step of forming an oxide film 99. Specifically, this step includes the step of bringing oxygen, which is generated by oxygen plasma, into contact with the gate metal surface 30s of the second gate metal film 36. As a result, an oxide film 99 (aluminum oxide film) is formed on the gate metal surface 30s exposed from the gate upper opening 61. The oxide film 99 covers a plurality of second metal crystal grains MG2 of the second gate metal film 36.

[0429] Similarly, this step includes bringing oxygen, generated by oxygen plasma, into contact with the source metal surface 50s of the second source metal film 56. This forms an oxide film 99 on the source metal surface 50s exposed from the source upper opening 62. The oxide film 99 coats a plurality of second metal crystal grains MG2 of the second source metal film 56.

[0430] Of course, the oxide film 99 may not be a result of the removal process of the second resist mask 98, but may be a naturally occurring oxide film formed when the gate metal surface 30s and the source metal surface 50s are exposed to the atmosphere (oxygen atmosphere) at any point during the process. Also, the oxide film 99 may be any other unwanted oxide film formed at any point during the process.

[0431] Next, referring to Figure 19I, the photoresist 100, which will serve as the base for the organic film 65, is applied onto the interlayer film 20. The photoresist 100 coats the gate metal film 30, gate wiring metal film 40, source metal film 50, and inorganic film 64 together in a film-like manner on the interlayer film 20.

[0432] Next, referring to Figure 19J, the photoresist 100 is exposed to a pattern corresponding to the gate upper opening 61, source upper opening 62, and dicing street 63, and then developed. As a result, the photoresist 100 hardens in the exposure pattern, forming an organic film 65 having the gate upper opening 61, source upper opening 62, and dicing street 63.

[0433] Next, referring to Figure 19K, the oxide film 99 is removed. The oxide film 99 is removed by an etching method (wet etching method) using a chemical solution (for example, a chemical solution containing hydrofluoric acid). In this step, multiple second grain boundaries of multiple second metal crystal grains MG2 function as peeling points for the oxide film 99 relative to the chemical solution (see also Figure 23).

[0434] In the second gate metal film 36, the second crystal density per unit area (density of the second crystal grain boundary) is relatively high, so the oxide film 99 is appropriately removed. As a result, the residual oxide ROx remaining on the gate metal surface 30s is appropriately suppressed.

[0435] Similarly, in the second source metal film 56, the second crystal density per unit area (density of the second crystal grain boundary) is relatively high, so the oxide film 99 is properly removed. This effectively suppresses the remaining residual oxide ROx on the source metal surface 50s. In the second source metal film 56, multiple electrode recesses ER also function as peeling points for the oxide film 99, thus increasing the efficiency of oxide film 99 removal.

[0436] Next, referring to Figure 19L, the gate upper metal film 70 and the source upper metal film 75 are formed. The gate upper metal film 70 has a laminated structure including a first nickel film 71, a first palladium film 72, and a first gold film 73. The source upper metal film 75 has a laminated structure including a second nickel film 76, a second palladium film 77, and a second gold film 78.

[0437] This process includes a first plating step of immersing the wafer structure 81 in a nickel plating solution, a second plating step of immersing the wafer structure 81 in a palladium plating solution, and a third plating step of immersing the wafer structure 81 in a gold plating solution. The second plating step is performed after the first plating step, and the third plating step is performed after the second plating step.

[0438] As a result, a gate upper metal film 70 having a laminated structure including a first nickel film 71, a first palladium film 72, and a first gold film 73 is formed on the gate metal film 30. In addition, a source upper metal film 75 having a laminated structure including a second nickel film 76, a second palladium film 77, and a second gold film 78 is formed on the source metal film 50.

[0439] In other words, the second nickel film 76, the second palladium film 77, and the second gold film 78 of the source upper metal film 75 are formed simultaneously with the first nickel film 71, the first palladium film 72, and the first gold film 73 of the gate upper metal film 70.

[0440] On the gate metal surface 30s, the generation of residual oxide ROx (i.e., residual material of the oxide film 99) is suppressed by the second gate metal film 36 having a second crystal density. As a result, the decrease in the film-forming ability of the gate upper metal film 70 caused by residual oxide ROx is suppressed, and the generation of fine pit FP is suppressed.

[0441] Similarly, on the source metal surface 50s, the generation of residual oxide ROx (i.e., residual material of the oxide film 99) is suppressed by the second source metal film 56 having a second crystal density. This suppresses the decrease in the film-forming ability of the source upper metal film 75 caused by residual oxide ROx, and suppresses the generation of fine pit FPs.

[0442] Subsequently, the wafer structure 81 is thinned from the second wafer main surface 84 by grinding or etching as needed, and a drain metal film 80 is formed on the second wafer main surface 84. Then, the wafer structure 81 is cut along the planned cutting line 88, and multiple semiconductor devices 1A are manufactured.

[0443] Figure 25 is an enlarged cross-sectional view showing the process of forming the oxide film 99 according to the reference example. Figure 26 is an enlarged cross-sectional view showing the process of removing the oxide film 99 according to the reference example. Figure 27 is an enlarged cross-sectional view showing the process of forming the gate upper metal film 70 and the source upper metal film 75 according to the reference example.

[0444] In the example, the process of forming the base metal film 94 consists only of the process of forming the first base metal film 95, and the process of forming the second base metal film 96 is omitted. In other words, the gate upper metal film 70 is formed from the first gate metal film 35, and the source upper metal film 75 is formed from the first source metal film 55.

[0445] Referring to Figure 25, in the oxide film formation step (ashing step for the second resist mask 98), an oxide film 99 is formed on the gate metal surface 30s and an oxide film 99 is formed on the source metal surface 50s (see also Figures 19H and 22).

[0446] Referring to Figure 26, in the oxide film 99 removal step, the oxide film 99 is removed by an etching method using a chemical solution (see also Figure 23). In this step, multiple first grain boundaries of multiple first metal crystal grains MG1 function as peeling points for the oxide film 99 relative to the chemical solution.

[0447] In the first gate metal film 35, the first crystal density per unit area (density of the first crystal grain boundary) is relatively low (i.e., lower than the second crystal density), which reduces the removal rate of the oxide film 99. As a result, residual oxide ROx remains on the gate metal surface 30s. This tendency becomes more pronounced as the first crystal density (density of the first crystal grain boundary) decreases with increasing first deposition temperature.

[0448] Similarly, on the source metal surface 50s, the first crystal density per unit area (density of the first crystal grain boundary) is relatively low (i.e., lower than the second crystal density), resulting in a reduced removal rate of the oxide film 99. As a result, residual oxide ROx remains on the gate metal surface 30s. This tendency becomes more pronounced as the first crystal density (density of the first crystal grain boundary) decreases with increasing first deposition temperature.

[0449] However, on the source metal surface 50s, multiple electrode recesses ER function as peeling points for the oxide film 99, resulting in a higher removal rate of the oxide film 99 on the source metal surface 50s than on the gate metal surface 30s. Consequently, the residual oxide ROx per unit area on the source metal surface 50s is lower than on the gate metal surface 30s.

[0450] Referring to Figure 27, in the gate upper metal film formation process, residual oxide ROx functions as a film formation inhibiting part (in this embodiment, a plating inhibiting part) of the gate upper metal film 70. As a result, the film formation ability of the gate upper metal film 70 with respect to residual oxide ROx decreases, and fine pits FP with relatively small film thicknesses are formed on the gate metal surface 30s.

[0451] Similarly, in the process of forming the source upper metal film 75, the residual oxide ROx functions as a film formation inhibiting part (in this embodiment, a plating inhibiting part) of the source upper metal film 75. As a result, the film formation ability of the source upper metal film 75 with respect to the residual oxide ROx decreases, and fine pits FP with relatively small film thicknesses are formed on the source metal surface 50s. The number of fine pits FP per unit area on the source metal surface 50s is less than the number of fine pits FP per unit area on the gate metal surface 30s.

[0452] On the other hand, the manufacturing method of semiconductor device 1A involves a sputtering method at 300°C or lower, where the median flat area per unit area of ​​multiple metal crystal grains MG is 10 μm. ２ The process may include a step of forming a metal film (30, 50) having metal surfaces (30s, 50s) that are less than 50 on the film-forming body (20).

[0453] This manufacturing method provides a semiconductor device 1A having a metal film (30, 50) with excellent surface condition. For example, this manufacturing method can suppress the residue of residual oxides (ROx) on the metal surfaces (30s, 50s) of the metal film (30, 50). This reduces the electrical effects caused by residual oxides (ROx) and simultaneously suppresses the deterioration of the reliability of the metal film (30, 50) caused by residual oxides (ROx).

[0454] This manufacturing method may include a step of removing the oxide film (99) from the metal surfaces (30s, 50s) of the metal films (30, 50) using a chemical solution after the metal film (30, 50) formation step. According to this manufacturing method, the grain boundaries of multiple metal crystal grains MG formed at a relatively high density function as peeling points for the oxide film (99). As a result, the removal rate of the oxide film (99) is improved, and the remaining residual oxide (ROx) is suppressed.

[0455] This manufacturing method may include a step of forming an upper metal film (70, 75) on the metal surface (30s, 50s) of the metal film (30, 50) after the step of removing the oxide film (99). According to this manufacturing method, defects in the formation of the upper metal film (70, 75) caused by residual oxides (ROx) are suppressed, and the flatness of the upper metal film (70, 75) with respect to the metal surface (30s, 50s) is improved.

[0456] The film-forming body (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the metal film (30, 50) may be formed on the flat region (28). According to this manufacturing method, the removal rate of the oxide film (99) is improved on the metal surface (30s, 50s) of the metal film (30, 50) formed on the flat region (28).

[0457] The film-forming body (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). The metal film (30, 50) may be formed on the uneven region (26).

[0458] In this case, the metal surfaces (30s, 50s) of the metal films (30, 50) are located above the uneven region (26) and may have irregularities (ER) caused by the uneven region (26). According to this manufacturing method, the irregularities (ER) of the metal films (30, 50) function as peeling points for the oxide film (99), resulting in an improved removal rate of the oxide film (99).

[0459] The process of forming the metal film (30, 50) may include a process of forming a base metal film (90) and a process of removing unnecessary parts of the base metal film (90). The process of forming the base metal film (90) involves a sputtering method at 300°C or lower, wherein the median planar area per unit area of ​​multiple metal crystal grains MG is 10 μm. ２ The process may include a step of forming a base metal film (90) having a metal surface less than 20 on the film to be deposited (20).

[0460] The step of removing unwanted portions of the base metal film (90) may include the steps of forming a resist mask (91) having a predetermined pattern on the base metal film (90), and removing unwanted portions of the base metal film (90) by an etching method through the resist mask (91) to form metal films (30, 50).

[0461] From an alternative perspective, the method for manufacturing the semiconductor device 1A may include the steps of: forming a first base metal film (95) having a first crystal density per unit area on a film-forming body by sputtering at a first deposition temperature; forming a second base metal film (96) having a second crystal density higher than the first crystal density per unit area on the first base metal film (95) by sputtering at a second deposition temperature below the first deposition temperature; and removing unnecessary portions of the first base metal film (95) and the second base metal film (96) to form a metal film (30, 50) having a laminated structure including a first metal film (35, 55) made up of a part of the first base metal film (95) and a second metal film (36, 56) made up of a part of the second base metal film (96).

[0462] This manufacturing method provides a semiconductor device 1A having a second metal film (36, 56) with excellent surface condition. For example, this manufacturing method allows the residual oxide (ROx) to be suppressed by the second metal film (36, 56).

[0463] This reduces the electrical effects caused by residual oxides (ROx) and suppresses the decrease in the reliability of the second metal film (36, 56) caused by residual oxides (ROx). In this manufacturing method, the first deposition temperature may be higher than 300°C, and the second deposition temperature may be 300°C or lower.

[0464] This manufacturing method may include a step of removing the oxide film (99) from the metal surface (30s, 50s) of the second metal film (36, 56) after the metal film (30, 50) formation step. According to this manufacturing method, the grain boundaries of multiple metal crystal grains MG formed at a relatively high density on the metal surface (30s, 50s) function as peeling points for the oxide film (99), resulting in an increased removal rate of the oxide film (99).

[0465] This manufacturing method may include a step of forming an upper metal film (70, 75) on the metal surface (30s, 50s) of the second metal film (36, 56) after the step of removing the oxide film (99). According to this manufacturing method, poor film formation of the upper metal film (70, 75) caused by residual oxides (ROx) is suppressed, and the flatness of the upper metal film (70, 75) relative to the metal film (30, 50) is improved.

[0466] The film-forming body (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the first metal film (35, 55) and the second metal film (36, 56) may be formed on the flat region (28). According to this manufacturing method, the removal rate of the oxide film (99) is improved on the metal surface (30s, 50s) of the metal film (30, 50) formed on the flat region (28).

[0467] The film-forming body (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the first metal film (35, 55) and the second metal film (36, 56) may be formed on the uneven region (26). According to this manufacturing method, the removal rate of the oxide film (99) is improved on the metal surface (30s, 50s) of the metal film (30, 50) formed on the uneven region (26).

[0468] In this case, the first metal film (55) may be formed to fill the uneven region (26) and cover the film-forming body (20). The second metal film (56) may be formed above the uneven region (26) and cover the first metal film (55). According to this manufacturing method, the unevenness caused by the uneven region (26) is mitigated by the first metal film (55), which has relatively good embedding properties, and the flatness on the uneven region (26) is improved. On the other hand, the remaining residual oxide (ROx) is suppressed by the second metal film (56).

[0469] In this case, the metal surfaces (30s, 50s) of the metal films (30, 50) are located above the uneven region (26) and may have irregularities (ER) caused by the uneven region (26). According to this manufacturing method, the irregularities (ER) of the metal films (30, 50) function as peeling points for the oxide film (99), resulting in an improved removal rate of the oxide film (99).

[0470] The film to be deposited (20) may have an uneven region (26) containing a plurality of openings (25) and a flat region (28) outside the uneven region (26). In this case, the step of removing the first base metal film (95) and the second base metal film (96) may include the step of forming a flat metal film (30) having a laminated structure including the first metal film (35) and the second metal film (36) on the flat region (28), and forming an uneven metal film (50) having a laminated structure including the first metal film (55) and the second metal film (56) on the uneven region (26).

[0471] Figure 28 is an enlarged plan view showing the pad area 9a of the semiconductor device 1B according to the second embodiment. Figure 29 is a cross-sectional view along the line XXIX-XXIX shown in Figure 28. The semiconductor device 1B has an embodiment in which the layout of the interlayer film 20 of the semiconductor device 1A has been changed.

[0472] Specifically, in this embodiment, the interlayer film 20 includes a second uneven region 101 having a plurality of gate openings 27 on its insulating surface. The second uneven region 101 (the plurality of gate openings 27) is formed in the portion of the interlayer film 20 that covers the pad region 9a. Hereinafter, the plurality of gate openings 27 in the pad region 9a will be referred to as the "second gate opening 102".

[0473] Multiple second gate openings 102 penetrate the interlayer film 20 at intervals from multiple source openings 25 toward the pad region 9a, exposing the pad portions 23a of the gate wiring 23. Each of the multiple second gate openings 102 has a bottom wall partitioned by the pad portion 23a and a side wall partitioned by the interlayer film 20.

[0474] In this embodiment, the multiple second gate openings 102 each extend in a strip-like manner in the first direction X, following the direction of extension of the multiple gate structures 11 (multiple source openings 25), and are formed with gaps in the second direction Y. The multiple second gate openings 102 may be arranged with gaps in the first direction X and each extend in a strip-like manner in the second direction Y. In other words, the multiple second gate openings 102 may extend in a direction different from the multiple source openings 25.

[0475] The multiple second gate openings 102 may be arranged in a dot-like pattern (matrix or staggered pattern) with spacing in the first direction X and the second direction Y. In this case, the multiple second gate openings 102 may be formed in a polygonal shape (quadrilateral or hexagonal) or circular shape in plan view.

[0476] The multiple second gate openings 102 may be formed with a density (occupied area per unit area) approximately equal to the density (occupied area per unit area) of the multiple source openings 25. The density of the multiple second gate openings 102 may be less than the density of the multiple source openings 25.

[0477] The density of the multiple second gate openings 102 may be greater than the density of the multiple source openings 25. For example, in this case, one or more second gate openings 102 may be formed along the periphery of the pad portion 23a.

[0478] Multiple second gate openings 102 may have an opening width approximately equal to the opening width of the source opening 25. The opening width of the second gate openings 102 may be greater than or less than the opening width of the source opening 25. The opening width of the second gate openings 102 may be greater than 0 μm and 3 μm or less. The opening width may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0479] The aperture width may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0480] The spacing between the multiple second gate openings 102 may be greater than or less than the opening width of the second gate opening 102. The spacing between the second gates may be approximately equal to the spacing between the source openings 25. The spacing between the second gates may be greater than or less than the spacing between the source openings 25.

[0481] The spacing of the second gate openings 102 may be greater than 0 μm and 3 μm or less. The spacing of the second gate openings 102 may be 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 0.8 μm or less, 0.6 μm or less, or 0.4 μm or less.

[0482] The spacing of the second gate opening 102 may be greater than 0 μm and fall within at least one of the following ranges: 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0483] The gate metal film 30 has a laminated structure including a gate base metal film 31 and a gate body metal film 32, similar to the first embodiment. The gate base metal film 31 has a laminated structure including a first gate base metal film 33 and a second gate base metal film 34. Of course, the gate base metal film 31 may also have a single-layer structure consisting of the first gate base metal film 33 or the second gate base metal film 34.

[0484] The first gate base metal film 33 covers the insulating surface of the interlayer film 20 in a film-like manner and penetrates the multiple second gate openings 102 from above the interlayer film 20. Specifically, the first gate base metal film 33 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner, a portion that covers the wall surfaces of the multiple second gate openings 102 in a film-like manner, and a portion that covers the pad portions 23a of the gate wiring 23 in a film-like manner. The first gate base metal film 33 is mechanically and electrically connected to the pad portions 23a within the multiple second gate openings 102.

[0485] The second gate base metal film 34 covers the first gate base metal film 33 in a film-like manner and penetrates the multiple second gate openings 102 from above the interlayer film 20. Specifically, the second gate base metal film 34 has a portion that covers the insulating surface of the interlayer film 20 in a film-like manner via the first gate base metal film 33, a portion that covers the wall surfaces of the multiple second gate openings 102 in a film-like manner via the first gate base metal film 33, and a portion that covers the pad portion 23a in a film-like manner via the first gate base metal film 33. The second gate base metal film 34 is electrically connected to the pad portion 23a via the first gate base metal film 33.

[0486] The gate body metal film 32 is laminated in a film-like manner on the interlayer film 20 (gate base metal film 31) and forms the main body of the gate metal film 30. The gate body metal film 32 penetrates into the multiple second gate openings 102 from above the interlayer film 20. Specifically, the gate body metal film 32 has a portion that covers the interlayer film 20 in a film-like manner via the gate base metal film 31, and a portion that is embedded in the multiple second gate openings 102 via the gate body metal film 32.

[0487] The gate body metal film 32 has a laminated structure including a first gate metal film 35 and a second gate metal film 36, which are laminated in this order from the gate base metal film 31 (interlayer film 20) side. The first gate metal film 35 is laminated in a film-like manner on the gate base metal film 31.

[0488] The first gate metal film 35 covers the gate base metal film 31 in a film-like manner and penetrates into the multiple second gate openings 102 from above the interlayer film 20. The first gate metal film 35 has a portion that covers the interlayer film 20 in a film-like manner via the gate base metal film 31, and a portion that is embedded in the multiple second gate openings 102 via the gate base metal film 31.

[0489] In this configuration, the first gate metal film 35 backfills the multiple second gate openings 102 and is electrically connected to the pad portion 23a via the gate base metal film 31 within the multiple second gate openings 102.

[0490] The first gate metal film 35 has multiple electrode recesses that are recessed above the multiple second gate openings 102 and toward the bottom walls of the multiple second gate openings 102. In other words, the first gate metal film 35 has multiple irregularities caused by the multiple second gate openings 102 (second uneven region 101).

[0491] The second gate metal film 36 is laminated in a film-like manner on the first gate metal film 35. The second gate metal film 36 is located above the opening ends of the multiple second gate openings 102 (the insulating surfaces of the interlayer film 20). In other words, the second gate metal film 36 has a portion that faces the insulating surface of the interlayer film 20 via the first gate metal film 35, and a portion that faces the multiple second gate openings 102 via the first gate metal film 35.

[0492] The second gate metal film 36 covers the multiple electrode recesses of the first gate metal film 35 in a film-like manner, forming a gate metal surface 30s having multiple electrode recesses ER resulting from multiple second gate openings 102 (second uneven regions 101).

[0493] Thus, the gate metal film 30 according to the second embodiment has a laminated structure including a first gate metal film 35 having a relatively low first crystal density per unit area, and a second gate metal film 36 having a second crystal density higher than the first crystal density.

[0494] The first gate metal film 35 is embedded in a plurality of second gate openings 102 and covers the insulating surface of the interlayer film 20. The second gate metal film 36 is located above the opening ends (insulating surface of the interlayer film 20) of the plurality of second gate openings 102 and forms the gate metal surface 30s.

[0495] As a result, the embedding ability of the gate metal film 30 into the multiple second gate openings 102 (second uneven regions 101) is enhanced by the first gate metal film 35, and the surface condition of the gate metal surface 30s is improved by the second gate metal film 36.

[0496] In this embodiment, the gate body metal film 32 had a laminated structure including a first gate metal film 35 and a second gate metal film 36. However, the gate body metal film 32 may also have a single-layer structure consisting of the second gate metal film 36. This configuration also improves the surface condition of the gate metal surface 30s.

[0497] The semiconductor device 1B, like the first embodiment, includes a gate upper metal film 70. The gate upper metal film 70 has a laminated structure including a first nickel film 71, a first palladium film 72, and a first gold film 73.

[0498] The first nickel film 71 is laminated in a film-like manner on the gate metal surface 30s following the shape of a plurality of electrode recesses ER. The first palladium film 72 is laminated in a film-like manner on top of the first nickel film 71. The first gold film 73 is laminated in a film-like manner on top of the first palladium film 72.

[0499] The gate upper metal film 70 is formed on the gate metal surface 30s, where the residual oxide ROx is suppressed by a plurality of second metal crystal grains MG2 (second crystal density) and a plurality of electrode recesses ER. This reduces the electrical influence caused by the residual oxide ROx, while simultaneously improving the flatness (film formation) of the gate upper metal film 70 relative to the gate metal film 30 (second gate metal film 36).

[0500] In particular, for multiple electrode recesses ER with spacing of 3 μm or less, the median flat area is 10 μm. ２ By applying multiple second metal crystal grains MG2 of less than , the delamination initiation site per unit area of ​​residual oxide ROx is appropriately increased.

[0501] For example, the median area of ​​multiple second metal crystal grains MG2 is 10 μm. ２ If less than 10%, the maximum width of the second metal crystal grain MG2, which is 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, or 90% or more, may be greater than the spacing of the electrode recesses ER (spacing of the second gate openings 102).

[0502] Figure 30 is a cross-sectional view showing a semiconductor device 1C according to the third embodiment. Figure 31 is an enlarged cross-sectional view of a key part shown in Figure 30. Referring to Figures 30 and 31, in this embodiment, the semiconductor device 1C has a planar gate type transistor structure T instead of a trench gate type transistor structure T.

[0503] The semiconductor device 1C, like the semiconductor device 1A, includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and an inactive region 9. In this embodiment, the semiconductor device 1C includes a plurality of p-type body regions 10 formed on the surface layer of the first main surface 3.

[0504] Multiple body regions 10 are formed in the active region 8, spaced apart from the periphery of the first main surface 3, but not in the inactive region 9. In this configuration, each of the multiple body regions 10 extends in a strip-like manner in the first direction X and is formed with spacing in the second direction Y. In other words, the multiple body regions 10 extend in a stripe-like manner in the first direction X.

[0505] Multiple body regions 10 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7. Multiple body regions 10 are formed at intervals from an intermediate depth position of the second semiconductor layer 7 toward the first main surface 3.

[0506] The semiconductor device 1C includes a plurality of planar gate structures 103 instead of the gate structure 11. The gate structures 103 may also be referred to as "planar structures," "planar gate structures," etc. The plurality of gate structures 103 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but are not formed in the inactive region 9.

[0507] In this configuration, the multiple gate structures 103 each extend in a strip-like manner in the first direction X and are formed with gaps in the second direction Y. In other words, the multiple gate structures 103 extend in a stripe-like manner in the first direction X. The multiple gate structures 103 straddle the periphery of multiple adjacent body regions 10 in the second direction Y.

[0508] The multiple gate structures 103 have a laminated structure including a planar insulating film 104 and a planar electrode 105 stacked in this order from the first main surface 3 side. The planar insulating film 104 may be referred to as a "gate insulating film," and the planar electrode 105 may be referred to as a "gate electrode."

[0509] The planar insulating film 104 may have a single-layer structure or a multilayer structure including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The planar insulating film 104 may also include at least one of the oxide film of the chip 2 (second semiconductor layer 7) and an oxide film other than the oxide film of the chip 2.

[0510] The planar insulating film 104 coats the first main surface 3 in a film-like manner and covers the peripheral edges of a plurality of adjacent body regions 10. The thickness of the planar insulating film 104 may be greater than 0 nm and 250 nm or less. The thickness of the planar insulating film 104 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0511] The planar electrode 105 includes either a metallic conductor or a non-metallic conductor (a conductor other than a metallic material), or both. In this embodiment, the planar electrode 105 includes conductive polysilicon. The embedded electrode 15 may include either a p-type conductive polysilicon or an n-type conductive polysilicon, or both. The planar electrode 105 is positioned on a planar insulating film 104 and faces the periphery of a plurality of adjacent body regions 10 across the planar insulating film 104.

[0512] The semiconductor device 1C includes a plurality of n-type source regions 16 formed on the surface of a plurality of body regions 10. In this configuration, the plurality of source regions 16 are formed in a one-to-many correspondence with respect to one body region 10. In this configuration, the plurality of source regions 16 extend in a strip-like manner in a first direction X and are formed with gaps in a second direction Y on the surface of the corresponding body region 10.

[0513] Multiple source regions 16 are formed in the inner part of the corresponding body region 10, spaced apart from the periphery of the body region 10, and face the periphery of the planar electrode 105 via the planar insulating film 104 in the thickness direction Z. The multiple source regions 16, together with the second semiconductor layer 7, define channels that extend along the first main surface 3 in the surface layer of the body region 10 directly below the periphery of the corresponding planar electrode 105.

[0514] The semiconductor device 1C includes a plurality of p-type contact regions 17 formed on the surface of a plurality of body regions 10. In this configuration, each of the contact regions 17 is formed in a one-to-one correspondence with a single body region 10. In this configuration, each of the contact regions 17 is interposed in the region between a plurality of adjacent source regions 16 in the second direction Y on the surface of the corresponding body region 10, and extends in a strip shape in the first direction X.

[0515] Of course, the multiple contact regions 17 may be formed in a one-to-many correspondence with respect to a single body region 10. In this case, the multiple contact regions 17 may be formed on the surface of the corresponding body region 10, spaced apart in the first direction X. In this embodiment, the multiple contact regions 17 have a depth greater than the depth of the multiple source regions 16.

[0516] The semiconductor device 1C, as in the first embodiment, includes a well region 18 (pad well region 18a and outer well region 18b), an interlayer film 20 (first interlayer film 21 and second interlayer film 22), gate wiring 23 (pad portion 23a and line portion 23b), uneven region 26 (multiple source openings 25), multiple gate openings 27, a flat region 28, a gate metal film 30, a gate wiring metal film 40, a source metal film 50, an upper insulating film 60 (inorganic film 64 and organic film 65), a gate upper metal film 70, a source upper metal film 75, and a drain metal film 80.

[0517] In this configuration, the first interlayer film 21 is connected to the planar insulating film 104 in the active region 8, the second interlayer film 22 covers the planar electrode 105 in the active region 8, and the gate wiring metal film 40 is connected to the planar electrode 105 in the active region 8. In this configuration, multiple source openings 25 are formed in the regions between the multiple planar electrodes 105, respectively, exposing the corresponding multiple source regions 16 and contact regions 17.

[0518] Further explanations are the same as those for the first embodiment and are therefore omitted. As described above, even with a semiconductor device 1C having a planar gate structure 103, the same effects as those described in the first embodiment are achieved.

[0519] Figure 32 is a plan view showing a semiconductor device 1D according to the fourth embodiment. Figure 33 is a cross-sectional view along the line XXXIII-XXXIII shown in Figure 32. Figure 34 is a plan view showing the layout of the first main metal film 115 shown in Figure 33. Figure 35 is an enlarged cross-sectional view showing the main part of the first main metal film 115 shown in Figure 33.

[0520] Semiconductor device 1D is a semiconductor rectifier, an example of an electronic component having a diode structure D as an example of a device structure (functional device). In this embodiment, the diode structure D has a Schottky junction type vertical structure.

[0521] Referring to Figures 32 to 35, semiconductor device 1D includes a chip 2, a first semiconductor layer 6, a second semiconductor layer 7, an active region 8, and an inactive region 9, similar to semiconductor device 1A. Chip 2 may also be referred to as "coating body," "coating target," or "film deposition target."

[0522] In this configuration, the active region 8 is located in the center of the first main surface 3. The active region 8 is set to a polygonal shape (a quadrilateral in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view. The inactive region 9 is located at the periphery of the first main surface 3 in this configuration and is set to a polygonal ring (a quadrilateral ring in this configuration) surrounding the active region 8.

[0523] The semiconductor device 1D includes an n-type diode region 110 formed in the surface layer of the first main surface 3 in the active region 8. The diode region 110 may also be called an "impurity region," etc. In this embodiment, the diode region 110 is formed using a part of the second semiconductor layer 7 and has the n-type impurity concentration of the second semiconductor layer 7. Of course, the n-type impurity concentration of the diode region 110 may be higher or lower than the n-type impurity concentration of the second semiconductor layer 7.

[0524] The semiconductor device 1D includes a p-type guard region 111 formed in the surface layer of the first main surface 3 in an inactive region 9. The guard region 111 may also be referred to as an "impurity region," etc. In this embodiment, the guard region 111 has a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0525] The guard region 111 is formed at a distance from the periphery of the first main surface 3 and extends in a band-like shape along the active region 8. The guard region 111 has a portion extending in a first direction X and a portion extending in a second direction Y in a plan view, and partitions the active region 8 from multiple directions. In this embodiment, the guard region 111 is formed as a polygonal ring (quadrilateral ring) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the diode region 110 (active region 8).

[0526] The guard region 111 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the guard region 111 demarcates the diode region 110 (active region 8). The outer edge of the guard region 111 extends substantially parallel to the inner edge of the guard region 111.

[0527] The semiconductor device 1D includes an insulating interlayer film 112 that selectively covers the first main surface 3. The interlayer film 112 may have a single-layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer film 112 may have a single-layer structure or a multilayer structure that includes at least one of an NSG film, a PSG film, a BSG film, a BPSG film, and a TEOS film.

[0528] The interlayer film 112 covers the peripheral edge of the first main surface 3. Specifically, the interlayer film 112 covers the outer edge of the guard region 111 and has contact openings 113 that expose the diode region 110 and the inner edges of the guard region 111. In this embodiment, the contact openings 113 are formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the peripheral edge of the first main surface 3 in a plan view.

[0529] The interlaminar film 112 may have a thickness greater than 0 μm and 5 μm or less. The thickness of the interlaminar film 112 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 2 μm or less, 2 μm or more and 3 μm or less, 3 μm or more and 4 μm or less, and 4 μm or more and 5 μm or less.

[0530] The semiconductor device 1D includes a metallic first main metal film 115 disposed on the first main surface 3 of a chip 2, which is an example of a coating body. The first main metal film 115 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad," "anode electrode," etc.

[0531] The first main metal film 115 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The first main metal film 115 is positioned on the first main surface 3 within the contact opening 113 and is mechanically and electrically connected to the first main surface 3.

[0532] The first main metal film 115 is electrically connected to the inner edges of the diode region 110 and the guard region 111. The first main metal film 115 forms a Schottky junction with the diode region 110. This forms a Schottky barrier diode as a diode structure D, which includes the diode region 110 as the cathode and the first main metal film 115 as the anode.

[0533] The first main metal film 115 extends in a film-like manner along the first main surface 3 and is drawn out onto the insulating surface of the interlayer film 112 through the wall surface of the contact opening 113. The first main metal film 115 has a metal surface 115s that extends flat along the first main surface 3. The metal surface 115s has a portion that extends along the insulating surface of the interlayer film 112.

[0534] The first main metal film 115, like the gate metal film 30 of the first embodiment, has a laminated structure including an underlay metal film 116 and a main metal film 117 that are stacked in this order from the chip 2 side. The underlay metal film 116 is formed as a barrier electrode and has a single-layer structure consisting of a single metal film or a laminated structure including multiple metal films.

[0535] In this embodiment, the base metal film 116 has a laminated structure including a first base metal film 118 and a second base metal film 119. Of course, the base metal film 116 may also have a single-layer structure consisting of the first base metal film 118 or the second base metal film 119.

[0536] The first base metal film 118 covers the first main surface 3 in a film-like manner. Specifically, the first base metal film 118 has a portion that covers the first main surface 3 in a film-like manner, a portion that covers the wall surface of the contact opening 113 in a film-like manner, and a portion that covers the insulating surface of the interlayer film 112 in a film-like manner.

[0537] In this embodiment, the first underlay metal film 118 consists of a titanium film, which is an example of a titanium-based metal film, and forms a Schottky junction with the diode region 110. The first underlay metal film 118 has a thickness less than the thickness of the interlayer film 112.

[0538] The thickness of the first underlay metal film 118 may be greater than 0 nm and 200 nm or less. The thickness of the first underlay metal film 118 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, and 150 nm to 200 nm.

[0539] The second base metal film 119 covers the first base metal film 118 in a film-like manner. Specifically, the second base metal film 119 has a portion that covers the first main surface 3 in a film-like manner via the first base metal film 118, a portion that covers the wall surface of the contact opening 113 in a film-like manner via the first base metal film 118, and a portion that covers the insulating surface of the interlayer film 112 in a film-like manner via the first base metal film 118.

[0540] In this embodiment, the second base metal film 119 consists of a titanium alloy film (in this embodiment, a titanium nitride film) as an example of a titanium-based metal film. The second base metal film 119 has a thickness less than the thickness of the interlayer film 112. The thickness of the second base metal film 119 is greater than the thickness of the first base metal film 118.

[0541] The thickness of the second base metal film 119 may be greater than 0 nm and 300 nm or less. The thickness of the second base metal film 119 may have a value that falls within at least one of the following ranges: greater than 0 nm and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or more and 200 nm or more and 250 nm or more and 300 nm or less.

[0542] The main metal film 117 forms the main body of the first main metal film 115. The main metal film 117 is made of a different metal from the first base metal film 118 and the second base metal film 119. The main metal film 117 contains an active metal that has reducing properties. In this embodiment, the main metal film 117 is made of an aluminum-based metal (pure aluminum or an aluminum alloy with a purity of 99% or more). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0543] The main metal film 117 has a thickness greater than the thickness of the underlayment metal film 116 (the total thickness of the first underlayment metal film 118 and the second underlayment metal film 119). In this embodiment, the thickness of the main metal film 117 is greater than the thickness of the interlayer film 112. The thickness of the main metal film 117 may be less than the thickness of the interlayer film 112.

[0544] The thickness of the main metal film 117 may be greater than 0 μm and 5 μm or less. The thickness of the main metal film 117 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0545] The main metal film 117 is laminated in a film-like manner on the base metal film 116 (chip 2) and forms the main body of the first main metal film 115. The main metal film 117 contains a plurality of metal crystal grains MG (aluminum-based metal crystal grains) made of aluminum-based metal.

[0546] In this embodiment, the main metal film 117 is formed with different crystal densities in the thickness direction Z. Specifically, the main metal film 117 has a laminated structure including a first metal film 120 and a second metal film 121 that are laminated in this order from the base metal film 116 (chip 2) side.

[0547] The first metal film 120 is laminated in a film-like manner on the base metal film 116. In this configuration, the first metal film 120 backfills the contact opening 113 via the base metal film 116. The first metal film 120 has a portion that covers the first main surface 3 in a film-like manner via the base metal film 116, a portion that covers the wall surface of the contact opening 113 in a film-like manner via the base metal film 116, and a portion that covers the interlayer film 112 in a film-like manner via the gate base metal film 31.

[0548] The first metal film 120 contains a plurality of first metal crystal grains MG1 (aluminum-based metal crystal grains) made of an aluminum-based metal. The plurality of first metal crystal grains MG1 have relatively large planar area and cross-sectional area in median (or average) values ​​per unit area.

[0549] In the first metal film 120, the median of the planar area of ​​the multiple first metal crystal grains MG1 is 8 μm. ２ Larger than that, specifically 10 μm ２ That concludes the report. The median area of ​​the multiple first metal crystal grains MG1 is 50 μm. ２ Below, 45μm ２ Below, 40 μm ２ Below, 35μm ２ Below, 30μm ２ Below, 25μm ２ Below, 20μm ２ The following, or 15 μm ２ The following is also acceptable.

[0550] The first metal film 120 is formed by sputtering at a first deposition temperature. The first deposition temperature is preferably higher than 300°C and 500°C or lower. The first deposition temperature may have a value that falls within at least one of the following ranges: higher than 300°C and 350°C or lower, 350°C or higher and 400°C or lower, 400°C or higher and 450°C or lower, and 450°C or higher and 500°C or lower.

[0551] The first metal film 120 has a thickness greater than the thickness of the underlying metal film 116. In this embodiment, the thickness of the first metal film 120 is greater than the thickness of the interlayer film 112 (the depth of the contact opening 113). The thickness of the first metal film 120 may be less than the thickness of the interlayer film 112.

[0552] The ratio of the thickness of the first metal film 120 to the thickness of the main metal film 117 (first thickness ratio) may be 0.7 or more and less than 1. The first thickness ratio may have a value that falls within at least one of the following ranges: 0.7 or more and 0.75 or less, 0.75 or more and 0.8 or less, 0.8 or more and 0.85 or less, 0.85 or more and 0.95 or less, and 0.95 or more and less than 1.

[0553] The second metal film 121 is laminated in a film-like manner on the first metal film 120. The second metal film 121 is located above the opening end of the contact opening 113 (the insulating surface of the interlayer film 112). In other words, the second metal film 121 has a portion that faces the insulating surface of the interlayer film 112 via the first metal film 120, and a portion that faces the contact opening 113 via the first metal film 120.

[0554] The second metal film 121 contains a plurality of second metal crystal grains MG2 (aluminum-based metal crystal grains) made of the same type of aluminum-based metal as the first metal film 120. The plurality of second metal crystal grains MG2 have a planar area and cross-sectional area that are smaller than the planar area and cross-sectional area of ​​the plurality of first metal crystal grains MG1 in terms of median (or average) values ​​per unit area, and are laminated on the plurality of first metal crystal grains MG1 (first metal film 120) at a second crystal density that is higher than the first crystal density per unit area.

[0555] The second metal film 121, together with the first metal film 120, forms a metal crystal boundary MB resulting from the density difference between the first crystal density of a plurality of first metal crystal grains MG1 and the second crystal density of a plurality of second metal crystal grains MG2. In other words, the first main metal film 115 has a boundary MB between the first metal film 120 and the second metal film 121 resulting from the density difference between the first and second crystal densities. The boundary MB extends along the first main surface 3 and the interlayer film 112.

[0556] In the second metal film 121, the median of the planar areas of the multiple second metal crystal grains MG2 is less than the median of the planar areas of the multiple first metal crystal grains MG1. The median of the planar areas of the multiple second metal crystal grains MG2 is 0 μm. ２ Larger than 10 μm ２ It is less than.

[0557] The median area of ​​multiple second metal crystal grains MG2 is 9 μm. ２ Below, 8 μm ２ Below, 7 μm ２ Below, 6 μm ２ Below, 5 μm ２ Below, 4μm ２ Below, 3μm ２ Below, 2μm ２ The following, or 1 μm ２ Preferably the following (10 μm at 300°C) ２ It is less than 5 μm at 200°C. ２ (Less than) The median planar area of ​​multiple second metal crystal grains MG2 is 0.5 μm ２ More than 1μm ２ More than 2 μm ２ or greater than 3 μm ２ That's fine too.

[0558] The second metal film 121 is formed by a sputtering method at a second deposition temperature lower than the first deposition temperature. The second deposition temperature may be between 0°C and 300°C. The second deposition temperature may have a value that falls within at least one of the following ranges: 0°C to 50°C, 50°C to 100°C, 100°C to 150°C, 150°C to 200°C, 200°C to 250°C, and 250°C to 300°C.

[0559] The second precipitation temperature is preferably less than 300°C. The second precipitation temperature is preferably 250°C or lower. The second precipitation temperature is preferably 200°C or lower. The second precipitation temperature may be 50°C or higher, 75°C or higher, 100°C or higher, 125°C or higher, 150°C or higher, or 175°C or higher.

[0560] The second metal film 121 has a thickness less than that of the first metal film 120 and forms the surface layer of the metal surface 115s. In this embodiment, the thickness of the second metal film 121 is less than the thickness of the interlayer film 112 (the depth of the contact opening 113). The thickness of the second metal film 121 may be greater than the thickness of the interlayer film 112.

[0561] In this embodiment, the thickness of the second metal film 121 is greater than the thickness (total thickness) of the underlying metal film 116. In this embodiment, the thickness of the second metal film 121 may also be less than the thickness (total thickness) of the underlying metal film 116.

[0562] The ratio of the thickness of the second metal film 121 to the thickness of the main metal film 117 (second thickness ratio) may be greater than 0 and 0.3 or less. The second thickness ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.01 or less, 0.01 or more and 0.05 or less, 0.05 or more and 0.1 or less, 0.1 or more and 0.15 or less, 0.15 or more and 0.25 or less, and 0.25 or more and 0.3 or less.

[0563] The thickness of the second metal film 121 is preferably greater than 0 nm and 1000 nm or less. The thickness of the second metal film 121 may have a value that falls within at least one of the following ranges: greater than 0 nm and 100 nm or less, 100 nm to 200 nm, 200 nm to 300 nm, 300 nm to 400 nm, 400 nm to 500 nm, 500 nm to 600 nm, 600 nm to 700 nm, 700 nm to 800 nm, 800 nm to 900 nm, and 900 nm to 1000 nm.

[0564] In this embodiment, the main metal film 117 had a laminated structure including a first metal film 120 and a second metal film 121. However, the main metal film 117 may also have a single-layer structure consisting of the second metal film 121. This configuration also improves the surface condition of the metal surface 115s.

[0565] The semiconductor device 1D includes an upper insulating film 60 that selectively covers the interlayer film 112, similar to the first embodiment. The upper insulating film 60 has one or more (one in this embodiment) upper openings 122 that cover the peripheral edge of the first main metal film 115 in a film-like manner on the interlayer film 112 and expose the inner portion of the first main metal film 115. The upper openings 122 may also be referred to as "pad openings," "anode pad openings," etc.

[0566] In this configuration, the upper opening 122 is divided into a polygonal shape (a quadrilateral shape in this configuration) having four sides parallel to the periphery of the first main surface 3 in a plan view. The upper insulating film 60 coats the interlayer film 112 in a film-like manner on the inactive region 9 side. The upper insulating film 60 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that defines the dicing street 63 between itself and the periphery of the chip 2.

[0567] The dicing street 63 exposes the interlayer film 112. If the interlayer film 112 is formed with a gap inward from the periphery of the first main surface 3, the dicing street 63 may expose the first main surface 3. In this case, the upper insulating film 60 may have a portion that directly covers the periphery of the first main surface 3.

[0568] The dicing street 63 extends in a band-like manner along the periphery of the chip 2 in a plan view. In this embodiment, the dicing street 63 is formed as an ended or endless polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.

[0569] The upper insulating film 60 has a thickness less than the thickness of the chip 2. In this embodiment, the thickness of the upper insulating film 60 is greater than the thickness of the interlayer film 112. The thickness of the upper insulating film 60 may be less than the thickness of the interlayer film 112. In this embodiment, the thickness of the upper insulating film 60 is greater than the thickness of the first main metal film 115. The thickness of the upper insulating film 60 may be less than the thickness of the first main metal film 115.

[0570] The upper insulating film 60 has a laminated structure including an insulating inorganic film 64 and an insulating organic film 65, stacked in this order from the chip 2 side (interlayer film 112 side), similar to the semiconductor device 1A. The upper insulating film 60 only needs to contain at least one of the inorganic film 64 and the organic film 65, and does not necessarily need to contain both the inorganic film 64 and the organic film 65 simultaneously.

[0571] The inorganic film 64 covers the peripheral edge of the first main metal film 115 in a film-like manner on the interlayer film 112, and demarcates one or more (one in this embodiment) upper openings 122 that expose the inner part of the first main metal film 115.

[0572] The inorganic film 64 coats the interlayer film 112 in a film-like manner in the inactive region 9. The inorganic film 64 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 63 between itself and the periphery of the chip 2.

[0573] If the interlayer film 112 is formed with a gap inward from the periphery of the first main surface 3, the inorganic film 64 may have a portion that directly covers the periphery of the first main surface 3. The inorganic film 64 may have a thickness less than the thickness of the interlayer film 112. The thickness of the inorganic film 64 may be less than the thickness of the first main metal film 115.

[0574] The organic film 65 coats the inorganic film 64 in a film-like manner. The organic film 65 has a portion that coats the interlayer film 112 via the inorganic film 64, and a portion that coats the first main metal film 115 via the inorganic film 64.

[0575] The organic film 65 covers the periphery of the first main metal film 115 via the inorganic film 64, and demarcates one or more (one in this embodiment) upper openings 122 that expose the inner portion of the first main metal film 115. The organic film 65 may expose the end of the inorganic film 64 at the wall surface of the upper opening 122. In this case, the exposed width of the end of the inorganic film 64 may be greater than the thickness of the inorganic film 64. The organic film 65 may cover the end of the inorganic film 64 at the wall surface of the upper opening 122.

[0576] The organic film 65 coats the interlayer film 112 in a film-like manner via the inorganic film 64 in the inactive region 9. The organic film 65 is formed with a gap inward from the periphery of the chip 2 (first to fourth side surfaces 5A to 5D) and has an outer wall portion that demarcates the dicing street 63 between itself and the periphery of the chip 2.

[0577] The outer wall portion of the organic film 65 may be located on the inward side of the first main surface 3 in the dicing street 63 compared to the outer wall portion of the inorganic film 64, and the outer wall portion of the inorganic film 64 may be exposed. The exposed width of the outer wall portion of the inorganic film 64 may be greater than or equal to the thickness of the inorganic film 64. Of course, the outer wall portion of the organic film 65 may be located on the peripheral side of the first main surface 3 compared to the outer wall portion of the inorganic film 64, and may cover the outer wall portion of the inorganic film 64.

[0578] If the interlayer film 112 is formed with a gap inward from the periphery of the first main surface 3, the organic film 65 may have a portion that directly covers the first main surface 3. In this embodiment, the thickness of the organic film 65 is greater than the thickness of the interlayer film 112. The thickness of the organic film 65 may be less than the thickness of the interlayer film 112. In this embodiment, the thickness of the organic film 65 is greater than the thickness of the first main metal film 115. The thickness of the organic film 65 may be less than the thickness of the first main metal film 115.

[0579] The inorganic film 64 may have a removal portion that covers the peripheral edge of the first main metal film 115 while exposing part or all of the corner (electrode side wall) of the first main metal film 115. In this case, the organic film 65 may have a portion that directly covers the corner (electrode side wall) of the first main metal film 115 within the removal portion of the inorganic film 64.

[0580] The semiconductor device 1D includes an upper metal film 125 disposed on the metal surface 115s of the first main metal film 115. The upper metal film 125 is a plating film laminated within the upper opening 122, starting from the metal surface 115s. In other words, the upper metal film 125 covers a second metal film 121 (a plurality of second metal crystal grains MG2) having a relatively high second crystal density.

[0581] The upper metal film 125 has a portion that contacts the wall surface of the upper opening 122. In this configuration, the upper metal film 125 is in contact with both the inorganic film 64 and the organic film 65 at the wall surface of the upper opening 122.

[0582] The upper metal film 125 may cover the end of the inorganic film 64 at a distance from the wall surface of the organic film 65, and may be in contact only with the inorganic film 64 at the wall surface of the upper opening 122. If the organic film 65 covers the end of the inorganic film 64, the upper metal film 125 may be in contact only with the organic film 65 at the wall surface of the upper opening 122.

[0583] The upper metal film 125 has an upper metal surface 125s that is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the upper opening 122) toward the first main metal film 115. The upper metal surface 125s extends along the metal surface 115s.

[0584] The upper metal film 125 has a laminated structure including a nickel film 126, a palladium film 127, and a gold film 128, which are stacked in this order from the first main metal film 115 side. The nickel film 126 is a plating film (Ni plating film) containing pure nickel or a nickel alloy with a purity of 99% or more.

[0585] The nickel film 126 is directly laminated in a film-like manner on the upper metal surface 125s within the upper opening 122. In other words, the nickel film 126 directly coats the second metal film 121 (multiple second metal crystal grains MG2) which has a relatively high second crystal density.

[0586] The nickel film 126 has a portion that contacts the wall surface of the upper opening 122. The nickel film 126 is in contact with either or both of the inorganic film 64 and the organic film 65 at the wall surface of the upper opening 122.

[0587] The nickel film 126 may cover the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65, and may be in contact only with the inorganic film 64 at the wall surface of the upper opening 122. If the organic film 65 covers the edge of the inorganic film 64, the nickel film 126 may be in contact only with the organic film 65 at the wall surface of the gate upper opening 61. The nickel film 126 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the upper opening 122) toward the first main metal film 115.

[0588] The nickel film 126 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the nickel film 126 is greater than the thickness of the first main metal film 115. The thickness of the nickel film 126 may also be less than the thickness of the first main metal film 115.

[0589] The nickel film 126 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the nickel film 126 is greater than the thickness of the interlayer film 20. The thickness of the nickel film 126 may be less than the thickness of the interlayer film 20.

[0590] In this embodiment, the thickness of the nickel film 126 is greater than the thickness of the first metal film 120. In this embodiment, the thickness of the nickel film 126 is greater than the thickness of the second metal film 121. In this embodiment, the thickness of the nickel film 126 is greater than the thickness of the first main metal film 115 (the total thickness of the first metal film 120 and the second metal film 121).

[0591] The thickness of the nickel film 126 may be less than the thickness of the first main metal film 115. The thickness of the first nickel film 71 may be less than the thickness of the first metal film 120. The thickness of the first nickel film 71 may be less than the thickness of the second metal film 121.

[0592] The thickness of the nickel film 126 may be greater than 0 μm and 50 μm or less. The thickness of the nickel film 126 may have a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or more and 50 μm or less.

[0593] The palladium film 127 is a plating film (Pd plating film) containing pure palladium or a palladium alloy with a purity of 99% or more. The palladium film 127 is laminated in a film-like manner on the nickel film 126. The palladium film 127 has a portion that is in contact with the wall surface of the upper opening 122.

[0594] The palladium film 127 is in contact with the organic film 65 at the wall surface of the upper opening 122. If the nickel film 126 is formed at a distance from the wall surface of the organic film 65, the palladium film 127 may have a portion that covers the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65. The palladium film 127 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the upper opening 122) toward the first main metal film 115.

[0595] The palladium film 127 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the palladium film 127 is less than the thickness of the interlayer film 20. The thickness of the palladium film 127 may be greater than the thickness of the interlayer film 20. The thickness of the palladium film 127 may be less than the thickness of the nickel film 126.

[0596] In this embodiment, the thickness of the palladium film 127 is smaller than the thickness of the first main metal film 115 (the total thickness of the first metal film 120 and the second metal film 121). The thickness of the palladium film 127 may be larger than the thickness of the first main metal film 115.

[0597] In this embodiment, the thickness of the palladium film 127 is smaller than the thickness of the first metal film 120. The thickness of the palladium film 127 may be larger than the thickness of the first metal film 120. In this embodiment, the thickness of the palladium film 127 is smaller than the thickness of the second metal film 121. The thickness of the palladium film 127 may be larger than the thickness of the second metal film 121.

[0598] The thickness of the palladium film 127 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the palladium film 127 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0599] The gold film 128 is a plating film (first Au plating film) containing pure gold or a gold alloy with a purity of 99% or more. The gold film 128 is laminated in a film-like manner on the palladium film 127. The gold film 128 has a portion that is in contact with the wall surface of the upper opening 122.

[0600] If the nickel film 126 is formed at a distance from the wall surface of the organic film 65, the gold film 128 may have a portion that covers the edge of the inorganic film 64 at a distance from the wall surface of the organic film 65. The gold film 128 is in contact with the organic film 65 at the wall surface of the upper opening 122. The gold film 128 is formed at a distance from the height of the insulating surface of the upper insulating film 60 (the opening end of the upper opening 122) toward the first main metal film 115.

[0601] The gold film 128 has a thickness less than the thickness of the upper insulating film 60. In this embodiment, the thickness of the gold film 128 is less than the thickness of the interlayer film 20. The thickness of the gold film 128 may be greater than the thickness of the interlayer film 20. The thickness of the gold film 128 is less than the thickness of the nickel film 126. The thickness of the gold film 128 may be greater than or less than the thickness of the palladium film 127.

[0602] In this embodiment, the thickness of the gold film 128 is smaller than the thickness of the first main metal film 115 (the total thickness of the first metal film 120 and the second metal film 121). The thickness of the gold film 128 may be larger than the thickness of the first main metal film 115.

[0603] In this embodiment, the thickness of the gold film 128 is smaller than the thickness of the first metal film 120. The thickness of the gold film 128 may be larger than the thickness of the first metal film 120. In this embodiment, the thickness of the gold film 128 is smaller than the thickness of the second metal film 121. The thickness of the gold film 128 may be larger than the thickness of the second metal film 121.

[0604] The thickness of the gold film 128 may be greater than 0 μm and less than or equal to 1 μm. The thickness of the gold film 128 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.2 μm, between 0.2 μm and 0.4 μm, between 0.4 μm and 0.6 μm, between 0.6 μm and 0.8 μm, and between 0.8 μm and 1 μm.

[0605] The semiconductor device 1D includes a second main metal film 130 that covers the second main surface 4. The second main metal film 130 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad," "cathode electrode," etc. The second main metal film 130 may have a single-layer structure or a multilayer structure that includes at least one of an aluminum-based metal film, a titanium-based metal film, a nickel-based metal film, a palladium-based metal film, a gold-based metal film, and a silver-based metal film.

[0606] The second main metal film 130 covers the entire area of ​​the second main surface 4 and is mechanically and electrically connected to the first semiconductor layer 6. The second main metal film 130 forms ohmic contact with the first semiconductor layer 6. The second main metal film 130 may extend along the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. The second main metal film 130 may partially cover the second main surface 4, exposing the peripheral portion of the second main surface 4.

[0607] The breakdown voltage that can be applied between the first main metal film 115 and the second main metal film 130 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0608] The semiconductor device 1D is manufactured by applying the manufacturing method shown in Figures 19A to 19L to the wafer structure 81, similar to the case of semiconductor device 1A. In the case of semiconductor device 1D, the wafer structure 81 includes an active region 8, an inactive region 9, a diode region 110, a guard region 111, an interlayer film 112, and a contact opening 113 in each device region 87.

[0609] In the manufacturing method of semiconductor device 1D, the base metal film 90 serves as the base for the first main metal film 115. That is, the base underlay metal film 91 serves as the base for the underlay metal film 116. Specifically, the first base underlay metal film 92 serves as the base for the first underlay metal film 118, and the second base underlay metal film 93 serves as the base for the second underlay metal film 119. Similarly, the base main body metal film 94 serves as the base for the main body metal film 117. Specifically, the first base metal film 95 serves as the base for the first metal film 120, and the second base metal film 96 serves as the base for the second metal film 121.

[0610] As described above, the semiconductor device 1D may include a coating (2) and a metal film (115). The metal film (115) may be placed on the coating (2) and may include a metal surface (115s) formed by a plurality of metal crystal grains (MG). The median flat area per unit area of ​​the plurality of metal crystal grains (MG) is 10 μm. ２ It is acceptable to be less than [a certain value].

[0611] This configuration provides a semiconductor device 1D having a metal film (115) with excellent surface condition. For example, with this semiconductor device 1D, the residue of residual oxides (ROx) on the metal surface (115s) can be suppressed. This reduces the electrical effects caused by residual oxides (ROx) and simultaneously suppresses the deterioration of the reliability of the metal film (115) caused by residual oxides (ROx).

[0612] The semiconductor device 1D may include an upper insulating film (60). The upper insulating film (60) is placed on a metal film (115) and may have an upper opening (122) that exposes the metal film (115).

[0613] The semiconductor device 1D may include an upper metal film (125). The upper metal film (125) may cover the metal film (115) within the upper opening (122). This configuration suppresses poor film formation of the upper metal film (125) caused by residual oxides (ROx) and improves the flatness of the upper metal film (125) relative to the metal film (115).

[0614] The coating (2) may be a chip (2). The chip (2) may contain SiC. This configuration provides a semiconductor device 1D as a novel SiC semiconductor device. With a SiC semiconductor device, the electrical properties are appropriately improved by the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of suppressing residual oxides (ROx) is effective in improving electrical properties and reliability.

[0615] The semiconductor device 1D may include an n-type (first conductivity type) diode region (110) formed on the chip (2). In this case, the metal film (115) may be electrically connected to the diode region (110).

[0616] The metal film (115) may form a Schottky junction with the diode region (110) and together with the diode region (110) constitute a diode structure (D). This configuration suppresses the deterioration of the reliability of the diode structure (D) caused by residual oxides (ROx). The semiconductor device 1D may include an interlayer film (112) that covers the chip (2). In this case, the metal film (115) may have a portion that covers the interlayer film (112).

[0617] From an alternative perspective, the semiconductor device 1D may include a coating (2) and a metal film (115). The metal film (115) may cover the coating (2) and have a metal surface (115s) extending along the coating (2). In such a configuration, the metal film (115) may have a first metal film (120) and a second metal film (121).

[0618] The first metal film (120) is formed on the coating body (2) side and may have a first crystal density per unit area. The second metal film (121) is formed on the metal surface (115s) side and may have a second crystal density higher than the first crystal density per unit area.

[0619] This configuration provides a semiconductor device 1D having a metal film (115) with excellent surface condition. For example, with this semiconductor device 1D, the remaining residual oxide (ROx) on the metal surface (115s) can be suppressed by the second metal film (121).

[0620] This reduces the electrical effects caused by residual oxides (ROx) and suppresses the deterioration of the reliability of the metal film (115) caused by residual oxides (ROx). Furthermore, if the current semiconductor device has a metal film corresponding to the first metal film (120), the reliability of that metal film is improved simply by adding the second metal film (121).

[0621] The second metal film (121) may have a thickness less than that of the first metal film (120). This configuration makes manufacturing easier because a relatively thin second metal film (121) is formed on top of a relatively thick first metal film (120).

[0622] The metal film (115) extends along the metal surface (115s) between the first metal film (120) and the second metal film (121), and may have a crystal boundary (MB) formed due to the density difference between the first and second crystal densities.

[0623] The first metal film (120) may have a first value with respect to the median area of ​​multiple crystal grains per unit area. The second metal film (121) may have a second value smaller than the first value with respect to the median. The first value is 10 μm ２ 50 μm or more ２ The following is also acceptable. The second value is 0 μm ２ Larger than 10 μm ２ It is acceptable to be less than [a certain value].

[0624] The coating (2) may be a chip (2). The chip (2) may contain SiC. This configuration provides a semiconductor device 1D as a novel SiC semiconductor device. With a SiC semiconductor device, the electrical properties are appropriately improved by the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effect of suppressing residual oxides (ROx) is effective in improving electrical properties and reliability.

[0625] The semiconductor device 1D may include an n-type (first conductivity type) diode region (110) formed on the chip (2). In this case, the metal film (115) may be electrically connected to the diode region (110).

[0626] The metal film (115) may form a Schottky junction with the diode region (110) and together with the diode region (110) constitute a diode structure (D). This configuration suppresses the deterioration of the reliability of the diode structure (D) caused by residual oxides (ROx).

[0627] The semiconductor device 1D may include an interlayer film (112) that covers the chip (2). In this case, the metal film (115) may have a portion that covers the interlayer film (112). The interlayer film (112) may have an opening (113) that exposes the chip (2). In this case, the metal film (115) may be electrically connected to the chip (2) within the opening (113).

[0628] The first metal film (120) may coat the chip (2) in a film-like manner within the opening (113) and backfill the opening (113). The second metal film (121) may coat the first metal film (120) in a film-like manner above the opening end of the opening (113). With this configuration, the first metal film (120), which has relatively good embedding properties, mitigates the irregularities caused by the opening (113), improving the flatness on the opening (113). On the other hand, the remaining residual oxide (ROx) is suppressed by the second metal film (121).

[0629] The semiconductor device 1D may include an upper insulating film (60). The upper insulating film (60) may partially cover the metal film (115) and have an upper opening (122) that selectively exposes the metal film (115). With this configuration, the metal film (115) can be protected by the upper insulating film (60), and at the same time, a potential application portion to the metal film (115) can be ensured through the upper opening (122).

[0630] The upper insulating film (60) may have a single-layer structure or a multilayer structure including either or both of an insulating inorganic film (64) and an insulating organic film (65). The upper insulating film (60) may also have a multilayer structure including an inorganic film (64) and an organic film (65) stacked in this order from the coating (2) side.

[0631] The semiconductor device 1D may include an upper metal film (125) that covers the metal film (115). The upper metal film (125) may cover the metal film (115) within the upper opening (122). This configuration suppresses poor film formation of the upper metal film (125) caused by residual oxides (ROx) and improves the flatness of the upper metal film (125) relative to the metal film (115).

[0632] The semiconductor device 1D may include an n-type (first conductivity type) diode region (110) formed on the chip (2). In this case, the metal film (115) may be electrically connected to the diode region (110).

[0633] The metal film (115) may form a Schottky junction with the diode region (110) and together with the diode region (110) constitute a diode structure (D). This configuration suppresses the deterioration of the reliability of the diode structure (D) caused by residual oxides (ROx).

[0634] Each of the above-described embodiments (including variations) can be implemented in other forms. For example, in each of the above-described embodiments, examples were shown in which the trench-type transistor structure T and diode structure D are formed on separate chips 2. However, the trench-type transistor structure T and diode structure D may be formed on a single chip 2.

[0635] In this case, the chip 2 may have an active region 8 for a trench-type transistor structure T and an active region 8 for a diode structure D. Of course, the trench-type transistor structure T and the diode structure D may be formed in a single active region 8. In these cases, the diode structure D may be formed as a freewheeling diode for the trench-type transistor structure T.

[0636] In the embodiments described above, examples were shown in which the planar transistor structure T and the diode structure D were formed on separate chips 2. However, the planar transistor structure T and the diode structure D may also be formed on a single chip 2.

[0637] In this case, the chip 2 may have an active region 8 for a planar transistor structure T and an active region 8 for a diode structure D. Of course, the planar transistor structure T and the diode structure D may be formed in a single active region 8. In these cases, the diode structure D may be formed as a freewheeling diode for the planar transistor structure T.

[0638] The aforementioned semiconductor device 1D had a diode structure D including a diode region 110 (first main surface 3) and a first main metal film 115 that forms a Schottky junction. However, in another form, the semiconductor device 1D may have a plurality of trench structures (11) corresponding to the plurality of gate structures 11 described above. In this case, the plurality of trench structures (11) are formed on the first main surface 3 in the active region 8, similar to the case of semiconductor device 1A.

[0639] In this case, the first main metal film 115 is mechanically and electrically connected to the diode region 110 (first main surface 3) and the plurality of trench structures (11) within the contact opening 113. Specifically, the first main metal film 115 forms a Schottky junction with the diode region 110 (first main surface 3) in the region between the plurality of trench structures (11), and is mechanically and electrically connected to the embedded electrodes 15 of the plurality of trench structures (11).

[0640] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of the n-type semiconductor region is inverted to p-type, and the conductivity type of the p-type semiconductor region is inverted to n-type. In this case, the specific configuration can be obtained by replacing n-type with p-type and simultaneously replacing p-type with n-type, as shown in the above description and attached drawings.

[0641] In the embodiments described above, an n-type first semiconductor layer 6 was shown. However, the conductivity type of the first semiconductor layer 6 may be p-type. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure. In this case, as described above, the "source" of the MISFET structure is replaced by the "emitter" of the IGBT structure, and the "drain" of the MISFET structure is replaced by the "collector" of the IGBT structure.

[0642] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent the corresponding components of the aforementioned forms, but this is not intended to limit the scope of each item (Clause) to the aforementioned forms. The term "electronic component" in the following items may be replaced with "semiconductor device," "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier," etc., as needed.

[0643] [A1] Includes a coating body (2, 20) and a metal surface (30s, 50s, 115s) disposed on the coating body (2, 20) and formed by a plurality of metal crystal grains (MG, MG2), wherein the median flat area per unit area of ​​the plurality of metal crystal grains (MG, MG2) is 10 μm ２ Electronic components (1A, 1B, 1C, 1D) containing metal films (30, 50, 115) with a thickness of less than 1.5 mm.

[0644] [A2] The electronic component (1A, 1B, 1C, 1D) according to A1, further comprising an upper insulating film (60) disposed on the metal film (30, 50, 115) and having upper openings (61, 62, 122) that expose the metal film (30, 50, 115).

[0645] [A3] The electronic component (1A, 1B, 1C, 1D) according to A2, further comprising upper metal films (70, 75, 125) that cover the metal films (30, 50, 115) within the upper openings (61, 62, 122).

[0646] [A4] The coating (2, 20) has an uneven region (26) including a plurality of openings (25) and a flat region (28) outside the uneven region (26), and the metal film (30, 50, 115) is placed on the flat region (28) at a distance from the uneven region (26), the electronic component (1A, 1B, 1C, 1D) according to any one of A1 to A3.

[0647] [A5] Electronic components (1A, 1B, 1C, 1D) comprising a coating body (2, 20), a metal film (30, 50, 115) covering the coating body (2, 20) and having metal surfaces (30s, 50s, 115s) extending along the coating body (2, 20), wherein the metal film (30, 50, 115) has a first metal crystal density per unit area and is formed on the coating body (2, 20) side, and a second metal film (36, 56, 121) having a second metal crystal density higher than the first metal crystal density per unit area and is formed on the metal surface (30s, 50s, 115s) side.

[0648] [A6] The second metal film (36, 56, 121) is thinner than the first metal film (35, 55, 1), and is an electronic component (1A, 1B, 1C, 1D) as described in A5.

[0649] [A7] The electronic component (1A, 1B, 1C, 1D) according to A5 or A6, wherein the metal film (30, 50, 115) is formed due to a density difference between the first metal crystal density and the second metal crystal density between the first metal film (35, 55, 120) and the second metal film (36, 56, 121), and has a metal crystal boundary (MB) extending along the metal surface (30s, 50s, 115s).

[0650] [A8] The electronic component (1A, 1B, 1C, 1D) according to any one of A5 to A7, wherein the first metal film (35, 55, 120) comprises a plurality of first metal crystal grains (MG1) and has a first value with respect to the median of the planar area of ​​the plurality of first metal crystal grains (MG1) per unit area, and the second metal film (36, 56, 121) comprises a plurality of second metal crystal grains (MG2) and has a second value smaller than the first value with respect to the median of the planar area of ​​the plurality of second metal crystal grains (MG2) per unit area.

[0651] [A9] The coating (2, 20) has an uneven region (26) including a plurality of openings and a flat region (28) outside the uneven region (26), and the metal film (30, 50, 115) is disposed on the flat region (28) of the coating (2, 20), the electronic component (1A, 1B, 1C, 1D) according to any one of A5 to A8.

[0652] [A10] An electronic component (1A, 1B, 1C, 1D) according to any one of A5 to A9, further comprising an upper insulating film (60) having upper openings (61, 62, 122) that partially cover the metal films (30, 50, 115) and selectively expose the metal films (30, 50, 115).

[0653] [A11] The electronic component (1A, 1B, 1C, 1D) according to A10, wherein the upper insulating film (60) has a single-layer structure or a multi-layer structure including either or both of an insulating inorganic film (64) and an insulating organic film (65).

[0654] [A12] An electronic component (1A, 1B, 1C, 1D) according to any one of A5 to A11, further comprising an upper metal film (70, 75, 125) covering the metal film (30, 50, 115).

[0655] [A13] An electronic component (1A, 1B, 1C, 1D) according to any one of A5 to A12, further comprising a chip (2) and an insulating interlayer film (20) as the coating body (2, 20) that covers the chip (2), wherein the metal film (30, 50, 115) covers the interlayer film (20).

[0656] [A14] The chip (2) is an electronic component (1A, 1B, 1C, 1D) as described in A13, which includes SiC.

[0657] [A15] An electronic component (1A, 1B, 1C, 1D) according to A13 or A14, further comprising: an active region (8) provided on the chip (2); inactive regions (9, 9a) provided outside the active region (8) on the chip (2); and a transistor structure (T) formed on the active region (8), wherein the interlayer film (20) covers the chip (2) with the active region (8) and the inactive regions (9, 9a), and the metal film (30, 50, 115) covers the interlayer film (20) with the inactive regions (9, 9a) and is electrically connected to the gate of the transistor structure (T).

[0658] [A16] The median area per unit area of ​​multiple metal crystal grains (MG, MG2) obtained by sputtering at 300°C or below is 10 μm. ２ A method for manufacturing electronic components (1A, 1B, 1C, 1D), comprising the step of forming a metal film (30, 50, 115) having a metal surface (30s, 50s, 115s) that is less than 100 on a film-forming body (20, 82, 112).

[0659] [A17] A method for manufacturing electronic components (1A, 1B, 1C, 1D) according to A16, further comprising: a step of removing an oxide film (99) from the metal surface (30s, 50s, 115s) with a chemical solution after the step of forming the metal film (30, 50, 115); and a step of forming an upper metal film (70, 75, 125) on the metal surface (30s, 50s, 115s) after the step of removing the oxide film (99).

[0660] [A18] A method for manufacturing electronic components (1A, 1B, 1C, 1D), comprising the steps of: forming a first base metal film (95) having a first metal crystal density per unit area on a workpiece (20, 82, 112) by sputtering at a first temperature; forming a second base metal film (96) having a second metal crystal density higher than the first metal crystal density per unit area on the first base metal film (95) by sputtering at a second temperature lower than the first temperature; and removing unnecessary portions of the first base metal film (95) and the second base metal film (96) to form a metal film (30, 50, 115) having a laminated structure including a first metal film (35, 55, 120) made up of a part of the first base metal film (95) and a second metal film (36, 56, 121) made up of a part of the second base metal film (96).

[0661] [A19] A method for manufacturing electronic components (1A, 1B, 1C, 1D) according to A18, wherein the first temperature is higher than 300°C and the second temperature is 300°C or lower.

[0662] [A20] A method for manufacturing electronic components (1A, 1B, 1C, 1D) according to A18 or A19, further comprising: a step of removing an oxide film (99) from the metal surface (30s, 50s, 115s) of the second metal film (36, 56, 121) after the step of forming the metal film (30, 50, 115); and a step of forming an upper metal film (70, 75, 125) on the metal surface (30s, 50s, 115s) of the second metal film (36, 56, 121) after the step of removing the oxide film (99).

[0663] Although specific forms have been described in detail above, these are merely examples to illustrate the technical content. The various technical ideas extracted from this specification can be combined as appropriate, without being limited by the order of explanation, the order of the examples of forms, or the order of the modifications within the specification.

[0664] 1A...Semiconductor device (electronic component), 1B...Semiconductor device (electronic component), 1C...Semiconductor device (electronic component), 1D...Semiconductor device (electronic component), 2...Chip (coating), 8...Active region, 9...Inactive region, 9a...Pad region (inactive region), 20...Interlayer film (coating, film-deposited body), 25...Source opening (opening), 26...Rough region, 28...Flat region, 30...Gate metal film (metal film), 30s...Gate metal surface (metal surface), 35...First gate metal film (first metal film), 36...Second gate metal film (second metal film), 50...Source metal film (metal film), 50s...Source metal surface (metal surface), 55...First source metal film (first metal film), 56...Second source metal film (second metal film), 60... Upper insulating film, 61... Gate upper opening (upper opening), 62... Source upper opening (upper opening), 64... Inorganic film, 65... Organic film, 70... Gate upper metal film (upper metal film), 75... Source upper metal film (upper metal film), 82... Wafer (film-deposited material), 95... First base metal film, 96... Second base metal film, 99... Oxide film, 112... Interlayer film (coating, film-deposited material), 115... First main metal film (metal film), 115s... Metal surface, 120... First metal film, 121... Second metal film, 122... Upper opening, 125... Upper metal film, MB... Boundary, MG... Metal crystal grain, MG1... First metal crystal grain, MG2... Second metal crystal grain, T... Transistor structure

Claims

1. A coating body and a metal surface disposed on the coating body and formed by a plurality of metal crystal grains, wherein the median flat area per unit area of ​​the plurality of metal crystal grains is 10 μm ２ Electronic components containing a metal film that is less than [amount missing].

2. The electronic component according to claim 1, further comprising an upper insulating film disposed on the metal film and having an upper opening that exposes the metal film.

3. The electronic component according to claim 2, further comprising an upper metal film that covers the metal film within the upper opening.

4. The electronic component according to any one of claims 1 to 3, wherein the coating body has an uneven region including a plurality of openings and a flat region outside the uneven region, and the metal film is disposed on the flat region at a distance from the uneven region.

5. An electronic component comprising: a coating body; a metal film covering the coating body and having a metal surface extending along the coating body, wherein the metal film comprises: a first metal film having a first metal crystal density per unit area and formed on the coating body side; and a second metal film having a second metal crystal density higher than the first metal crystal density per unit area and formed on the metal surface side.

6. The electronic component according to claim 5, wherein the second metal film is thinner than the first metal film.

7. The electronic component according to claim 5 or 6, wherein the metal film is formed between the first metal film and the second metal film due to a density difference between the first metal crystal density and the second metal crystal density, and has a boundary portion of metal crystals extending along the metal surface.

8. The electronic component according to any one of claims 5 to 7, wherein the first metal film comprises a plurality of first metal crystal grains and has a first value with respect to the median of the planar area of ​​the plurality of first metal crystal grains per unit area, and the second metal film comprises a plurality of second metal crystal grains and has a second value smaller than the first value with respect to the median of the planar area of ​​the plurality of second metal crystal grains per unit area.

9. The electronic component according to any one of claims 5 to 8, wherein the coating has an uneven region including a plurality of openings and a flat region outside the uneven region, and the metal film is disposed on the flat region of the coating.

10. The electronic component according to any one of claims 5 to 9, further comprising an upper insulating film having an upper opening that partially covers the metal film and selectively exposes the metal film.

11. The electronic component according to claim 10, wherein the upper insulating film has a single-layer structure or a multilayer structure comprising either an insulating inorganic film or an insulating organic film or both.

12. The electronic component according to any one of claims 5 to 11, further comprising an upper metal film covering the metal film.

13. The electronic component according to any one of claims 5 to 12, further comprising a chip and an insulating interlayer film as the coating body covering the chip, wherein the metal film covers the interlayer film.

14. The electronic component according to claim 13, wherein the chip includes SiC.

15. The electronic component according to claim 13 or 14, further comprising: an active region provided on the chip; an inactive region provided outside the active region on the chip; and a transistor structure formed in the active region, wherein the interlayer film covers the chip in the active region and the inactive region; and the metal film covers the interlayer film in the inactive region and is electrically connected to the gate of the transistor structure.

16. The median area per unit area of ​​multiple metal crystal grains obtained by sputtering at temperatures below 300°C is 10 μm. ２ A method for manufacturing an electronic component, comprising the step of forming a metal film having a metal surface less than 1 / 2 on a film-forming body.

17. A method for manufacturing an electronic component according to claim 16, further comprising: a step of removing an oxide film from the metal surface with a chemical solution after the metal film formation step; and a step of forming an upper metal film on the metal surface after the oxide film removal step.

18. A method for manufacturing an electronic component, comprising: a step of forming a first base metal film having a first metal crystal density per unit area on a film-forming material by sputtering at a first temperature; a step of forming a second base metal film having a second metal crystal density higher than the first metal crystal density per unit area on the first base metal film by sputtering at a second temperature below the first temperature; and a step of removing unnecessary portions of the first base metal film and the second base metal film to form a metal film having a laminated structure including a first metal film made of a part of the first base metal film and a second metal film made of a part of the second base metal film.

19. The method for manufacturing an electronic component according to claim 18, wherein the first temperature is higher than 300°C and the second temperature is 300°C or lower.

20. A method for manufacturing an electronic component according to claim 18 or 19, further comprising: a step of removing an oxide film from the metal surface of the second metal film after the metal film formation step; and a step of forming an upper metal film on the metal surface of the second metal film after the oxide film removal step.

Images