Semiconductor device
Patent Information
- Application Number
- PCT/JP2026/006915
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-28
- Filing Date
- 2026-02-25
- Publication Date
- 2026-09-03
Smart Images
Figure JP2026006915_03092026_PF_FP_ABST
Abstract
Description
Semiconductor device
[0001] The present disclosure relates to a semiconductor device.
[0002] Group III-V semiconductors, particularly arsenic-based GaAs or AlGaAs, or nitride-based GaN or AlGaN, can easily form heterostructures such as AlGaAs / GaAs and AlGaN / GaN. In the case of group III nitride semiconductors, in addition to the band gap difference, due to fixed charges caused by spontaneous polarization resulting from the difference in ion radius or piezoelectric polarization generated from the lattice constant difference between AlGaN and GaN, a high-mobility, high-concentration electron channel (two-dimensional electron gas: 2DEG (Dimensional Electron Gas)) can be generated on the GaAs side of AlGaAs / GaAs and on the GaN layer side at the AlGaN / GaN interface. By controlling this two-dimensional electron gas as a channel, it becomes possible to form a high electron mobility transistor (HEMT: High Electron Mobility Transistor). Utilizing the high-speed operation enabled by this high mobility, its application as high-frequency devices such as amplifiers and switching elements is expanding.
[0003] In such a semiconductor device, electrons may be trapped near or inside the channel layer. When trapped electrons (electron traps) are generated, operation delay, an increase in on-resistance and the like occur, so neutralization of electron traps is required.
[0004] Patent Document 1 discloses a device having a hole injection structure that injects holes for neutralizing electron traps.
[0005] U.S. Patent No. 10741682 Specification
[0006] However, in the device of Patent Document 1, since the drain voltage supplied to the drain electrode is applied to the p-type layer for electron traps, the electric field intensity from the drain electrode with respect to the gate electrode increases, which causes problems such as an increase in leakage current and insufficient withstand voltage.
[0007] Therefore, this disclosure provides a semiconductor device capable of neutralizing electron traps and suppressing electric field strength.
[0008] A semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided on the substrate, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer, a p-type third nitride semiconductor layer provided on the second nitride semiconductor layer, a gate electrode provided on the third nitride semiconductor layer, a source electrode and a drain electrode provided on the gate electrode, a p-type fourth nitride semiconductor layer provided on the second nitride semiconductor layer and between the gate electrode and the drain electrode, and an injection electrode provided on the fourth nitride semiconductor layer and supplied with an injection voltage lower than the drain voltage supplied to the drain electrode.
[0009] According to one aspect of this disclosure, a semiconductor device capable of neutralizing electron traps and suppressing electric field strength can be realized.
[0010] Figure 1 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. Figure 2A is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. Figure 2B is a plan view showing the configuration of a semiconductor device according to Embodiment 2. Figure 3 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 1 of Embodiment 2. Figure 4 is a cross-sectional view showing the configuration of a semiconductor device according to Modification 2 of Embodiment 2. Figure 5A is the first diagram showing the configuration of a resistive voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 5B is the second diagram showing the configuration of a resistive voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 6 is a diagram showing the simulation results of the voltage and current of the resistive voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 7A is a cross-sectional view showing a first example of the configuration of a resistive element according to Embodiment 2 and each of its modifications. Figure 7B is a cross-sectional view showing a second example of the configuration of a resistive element according to Embodiment 2 and each of its modifications. Figure 7C is a cross-sectional view showing a third example of the configuration of a resistive element according to Embodiment 2 and each of its modifications. Figure 7D is a cross-sectional view showing a fourth example of the configuration of a resistive element according to Embodiment 2 and each of its modifications. Figure 7E is a cross-sectional view showing a fifth example of the configuration of a resistive element according to Embodiment 2 and each of its modifications. Figure 8A is the first diagram showing the configuration of the capacitive voltage divider circuit according to Embodiment 2 and each modified example. Figure 8B is the second diagram showing the configuration of the capacitive voltage divider circuit according to Embodiment 2 and each modified example. Figure 9 is a diagram showing the simulation results of the voltage and current of the capacitive voltage divider circuit according to Embodiment 2 and each modified example. Figure 10A is the first diagram showing the configuration of the capacitive-resistive voltage divider circuit according to Embodiment 2 and each modified example. Figure 10B is the second diagram showing the configuration of the capacitive-resistive voltage divider circuit according to Embodiment 2 and each modified example. Figure 11 is a diagram showing the simulation results of the voltage and current of the capacitive-resistive voltage divider circuit according to Embodiment 2 and each modified example. Figure 12A is the first plan view for explaining the manufacturing method of the resistive element according to Embodiment 2 and each modified example. Figure 12B is a cross-sectional view of the resistive element in the process of manufacturing according to Embodiment 2 and each modified example, cut along the XIIb-XIIb cutting line in Figure 12A. Figure 13A is the second plan view for explaining the manufacturing method of the resistive element according to Embodiment 2 and each modified example.Figure 13B is a cross-sectional view of a resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XIIIb-XIIIb cutting line in Figure 13A. Figure 14 is a cross-sectional view of a resistive element in the manufacturing stage, showing the state after ion implantation in the manufacturing stage shown in Figure 13B. Figure 15A is a third plan view for explaining the manufacturing method of a resistive element according to Embodiment 2 and each of its modifications. Figure 15B is a cross-sectional view of a resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XVb-XVb cutting line in Figure 15A. Figure 16A is a fourth plan view for explaining the manufacturing method of a resistive element according to Embodiment 2 and each of its modifications. Figure 16B is a cross-sectional view of a resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XVIb-XVIb cutting line in Figure 16A. Figure 17A is a fifth plan view for explaining the manufacturing method of a resistive element according to Embodiment 2 and each of its modifications. Figure 17B is a cross-sectional view of a resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XVIIb-XVIIb cutting line in Figure 17A. Figure 18A is a sixth plan view for illustrating the manufacturing method of a resistive element according to Embodiment 2 and each of its modifications. Figure 18B is a cross-sectional view of a resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XVIIIb-XVIIIb cutting line in Figure 18A. Figure 19A is a plan view showing a first example of a grounding method for a voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 19B is a cross-sectional view showing a first example of a grounding method for a voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 20A is a plan view showing a second example of a grounding method for a voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 20B is a cross-sectional view showing a second example of a grounding method for a voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 21 is a plan view showing a third example of a grounding method for a voltage divider circuit according to Embodiment 2 and each of its modifications.
[0011] The embodiments of this disclosure will be described below with reference to the drawings. The embodiments described below are all preferred examples of the disclosure. Therefore, the numerical values, shapes, materials, components, arrangement and connection configurations of components, as well as the steps (processes) and their order, shown in the following embodiments are examples and are not intended to limit the disclosure. Accordingly, any components in the following embodiments that are not described in the independent claims representing the highest-level concepts of this disclosure will be described as optional components.
[0012] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, the scale and other aspects may not necessarily be consistent across all figures. In each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.
[0013] Furthermore, in this specification, the terms "upper" and "lower" in the configuration of semiconductor devices do not refer to the upper (vertically upward) and lower (vertically downward) directions in absolute spatial perception, but rather are terms defined by the relative positional relationship based on the stacking order in a stacked structure. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.
[0014] Furthermore, in this specification and drawings, the X, Y, and Z axes represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the stacking direction of each layer of the semiconductor device is defined as the Z axis, and the two axes parallel to the main surface of the semiconductor device are defined as the X and Y axes. Also, in this specification, "plan view" means viewing the semiconductor device from the Z axis direction. Also, in this specification, "cross-sectional view" means viewing the semiconductor device, which has been cut by a plane defined by the X and Z axes, from the Y axis direction.
[0015] Furthermore, in this specification, terms indicating relationships between identical elements, terms indicating the shape of elements such as rectangles, and numerical values and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent (or about 10%).
[0016] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not indicate the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.
[0017] (Embodiment 1) [1. Configuration of the semiconductor device] First, the configuration of the semiconductor device according to this embodiment will be described with reference to Figure 1. Figure 1 is a cross-sectional view showing the configuration of the semiconductor device 100 according to this embodiment.
[0018] As shown in Figure 1, the semiconductor device 100 includes a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 106, a fourth nitride semiconductor layer 107, a first insulating layer 201, a second insulating layer 202, a third insulating layer 203, a fourth insulating layer 204, a drain electrode 301, a source electrode 302, a gate electrode 303, an injection electrode 304, diffusion-preventing metal layers 311 and 312, a drain wiring layer 401, a source wiring layer 402, and gate wiring (not shown). The third nitride semiconductor layer 106 and the gate electrode 303 form the gate portion, and the fourth nitride semiconductor layer 107 and the injection electrode 304 form the hole injection portion.
[0019] The semiconductor device 100 has an active region and an inactive region (see the inactive region 108 shown in Figure 2B, described later) in a plan view. The active region is the region sandwiched between the drain electrode 301 and the source electrode 302 in a plan view, and in the active region, a two-dimensional electron gas layer 105 is formed on the first nitride semiconductor layer 103 side of the heterointerface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.
[0020] The substrate 101 is, for example, a substrate made of Si. The substrate 101 is not limited to a substrate made of Si, but may also be a substrate made of sapphire, SiC, GaN, AlN, etc.
[0021] The buffer layer 102 is formed on the substrate 101. The buffer layer 102 is a nitride semiconductor layer consisting of multiple stacked structures of AlN and AlGaN, for example, with a thickness of 2 μm. The buffer layer 102 may also be composed of a single or multiple layers of Group III nitride semiconductors such as GaN, AlGaN, AlN, InGaN, AlInGaN, or SiC. The thickness is the length in the Z-axis direction.
[0022] The first nitride semiconductor layer 103 is formed on the substrate 101. In this embodiment, the first nitride semiconductor layer 103 is formed on the buffer layer 102. The first nitride semiconductor layer 103 is composed of, for example, an undoped (i-type) GaN with a thickness of 300 nm. Undoped (i-type) means that impurities are not intentionally doped during epitaxial growth. In addition to GaN, the first nitride semiconductor layer 103 may be composed of a group III nitride semiconductor such as AlGaN, InGaN, or AlInGaN. Furthermore, the first nitride semiconductor layer 103 may contain not only undoped (i-type) impurities but also n-type impurities such as Si or p-type impurities such as Mg and C. The first nitride semiconductor layer 103 is also called a channel layer (channel GaN layer).
[0023] The second nitride semiconductor layer 104 is formed on the first nitride semiconductor layer 103. The second nitride semiconductor layer 104 is a barrier layer composed of, for example, undoped (i-type) AlGaN with a thickness of 15 nm and an Al composition ratio of 25%. The second nitride semiconductor layer 104 is not limited to AlGaN, but may also be composed of a group III nitride semiconductor such as AlN, InGaN, or AlInGaN. Furthermore, the second nitride semiconductor layer 104 may contain not only undoped (i-type) impurities, but also n-type impurities such as Si or p-type impurities such as Mg and C.
[0024] In this embodiment, the band gap of the second nitride semiconductor layer 104 is larger than the band gap of the first nitride semiconductor layer 103. Furthermore, the second nitride semiconductor layer 104, which is made of undoped (i-type) AlGaN, and the first nitride semiconductor layer 103, which is also made of undoped (i-type) GaN, have a heterostructure. In other words, the interface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 is a heterojunction, and a heterobarrier is formed at the interface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.
[0025] As a result, a two-dimensional electron gas layer 105 is formed near the boundary between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, for example, on the first nitride semiconductor layer 103 side of the heterointerface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 (in other words, on the second nitride semiconductor layer 104 side (Z-axis positive side) within the first nitride semiconductor layer 103).
[0026] Furthermore, a semiconductor layer with a thickness of approximately 1 to 2 nm, for example made of AlN, may be provided as a spacer layer between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.
[0027] The drain electrode 301 and source electrode 302 are provided on the second nitride semiconductor layer 104, which is exposed at an opening provided at a distance in the first insulating layer 201. The drain electrode 301 and source electrode 302 are each provided in contact with the second nitride semiconductor layer 104 and are electrically connected to the first nitride semiconductor layer 103. The drain electrode 301 and source electrode 302 are multilayer electrode films, for example, consisting of a laminated structure in which a Ti film and an Al film are stacked in order. Furthermore, the drain electrode 301 and source electrode 302 are electrically ohmic connected to the two-dimensional electron gas layer 105.
[0028] Here, by utilizing recesses created by removing a portion of the second nitride semiconductor layer 104 and / or the first nitride semiconductor layer 103 in the formation of the drain electrode 301 and source electrode 302, the ohmic connection resistance between the drain electrode 301 and source electrode 302 and the two-dimensional electron gas layer 105 can be reduced, thereby more effectively reducing the resistance during ON operation.
[0029] The third nitride semiconductor layer 106 is provided on the second nitride semiconductor layer 104 at a position between the drain electrode 301 and the source electrode 302, spaced apart from the drain electrode 301 and the source electrode 302. The third nitride semiconductor layer 106 is composed of, for example, Mg-doped p-type GaN. Here, for example, the Mg dopant concentration is 4.0E19(E １９ atoms / cm ３ However, 1.0E17 atoms / cm ３ More than 8.0E19atoms / cm ３ The following conditions are acceptable. Note that the p-type dopant is not limited to Mg. For example, Zn, C, etc. may be used as the p-type dopant.
[0030] The fourth nitride semiconductor layer 107 is provided at a position between the drain electrode 301 and the gate electrode 303. The material and thickness of the fourth nitride semiconductor layer 107 may be the same as those of the third nitride semiconductor layer 106. The thickness of the fourth nitride semiconductor layer 107 and the third nitride semiconductor layer 106 may be, for example, 100 nm.
[0031] Furthermore, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 are not limited to GaN, but may be composed of group III nitride semiconductors such as AlN, AlGaN, InGaN, AlInGaN, and InN. Also, the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107 may be not only single layers of p-type layers, but also stacked structures of multiple concentrations of p-type layers, or stacked structures including i-type or n-type layers.
[0032] The first insulating layer 201 is disposed on the second nitride semiconductor layer 104 and on a portion of the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107. The first insulating layer 201 is composed of, for example, SiN (e.g., P-Sin) with a thickness of 50 nm. However, the first insulating layer 201 is not limited to SiN and may be composed of SiO2, Al2O3, C (diamond), AlN, or SiC. Furthermore, the first insulating layer 201 may contain n-type impurities such as Si, O, or Se. In other words, the first insulating layer 201 may contain a dopant exhibiting a conductivity type opposite to that of the dopants contained in the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107.
[0033] The second insulating layer 202 is placed on the first insulating layer 201 and on a portion of the drain electrode 301 and the source electrode 302. The second insulating layer 202 is made of, for example, SiN (e.g., P-Sin) with a thickness of 50 nm. However, the second insulating layer 202 is not limited to SiN and may be made using SiO2, Al2O3, C (diamond), AlN, or SiC.
[0034] The third insulating layer 203 is placed on the second insulating layer 202, the gate electrode 303, and the injection electrode 304. The third insulating layer 203 is made of, for example, SiN (e.g., P-Sin) with a thickness of 100 nm. However, the third insulating layer 203 is not limited to SiN and may be made of SiO2, Al2O3, C (diamond), AlN, or SiC.
[0035] The fourth insulating layer 204 is placed on top of the third insulating layer 203. The fourth insulating layer 204 is also called an interlayer insulating film and is made of, for example, SiN (e.g., P-Sin) with a thickness of 800 nm. Note that the fourth insulating layer 204 is not limited to SiN and may be made using SiO2, Al2O3, C (diamond), AlN, or SiC.
[0036] The gate electrode 303 is provided in contact with the upper surface of the third nitride semiconductor layer 106. The gate electrode 303 is provided on the third nitride semiconductor layer 106 and the second insulating layer 202, and is provided in contact with the upper surface of the third nitride semiconductor layer 106 that is exposed by opening the first insulating layer 201 and the second insulating layer 202. Here, the gate electrode 303 is a multilayer electrode film consisting of a laminated structure in which a TiN film, an Al film, and a TiN film are stacked in order. The thickness of the TiN film is, for example, 20 nm, and the thickness of the Al film is, for example, 200 nm, but the thicknesses are not limited to these.
[0037] The configuration of the gate electrode 303 is not limited to this. Metals such as Ti, TiN, TaN, W, Ni, Pd, Au, and Al may be used as electrode materials. Furthermore, the structure may be a single layer of metal or a laminated structure of multiple metals.
[0038] The injection electrode 304 is an electrode provided on the fourth nitride semiconductor layer 107, and in this embodiment, it is a Schottky electrode provided in contact with the upper surface of the fourth nitride semiconductor layer 107. A Schottky diode is formed by the injection electrode 304 and the fourth nitride semiconductor layer 107. The injection electrode 304 is provided on the fourth nitride semiconductor layer 107 and the second insulating layer 202, and is provided in contact with the upper surface of the fourth nitride semiconductor layer 107 that is exposed by opening the first insulating layer 201 and the second insulating layer 202. The injection electrode 304 has a configuration similar to that of the gate electrode 303, for example. The injection electrode 304 is also made of the same electrode material as the gate electrode 303, for example.
[0039] The drain wiring layer 401 is a metal layer provided on the drain electrode 301 to supply the drain voltage Vd. The drain wiring layer 401 is a multilayer wiring film consisting of a laminated structure in which a TiN film, an Al film, and a TiN film are sequentially stacked, but is not limited to this. Metals such as Ti, TiN, TaN, W, Ni, Pd, Au, and Al may be used as the wiring material. Furthermore, the structure may be a single layer of metal or a laminated structure of multiple metals.
[0040] The diffusion barrier metal layer 311 is disposed between the drain electrode 301 and the drain wiring layer 401, and suppresses diffusion of metal atoms between the drain electrode 301 and the drain wiring layer 401. The diffusion barrier metal layer 311 is configured using a high melting point metal material such as TiN, Pt, Mo, Nb, W, but is not limited thereto. The thickness of the diffusion barrier metal layer 311 is, for example, 50 nm, but is not limited thereto.
[0041] The source wiring layer 402 is provided on the source electrode 302 and connected to GND. The configuration and material of the source wiring layer 402 may be the same as those of the drain wiring layer 401.
[0042] The diffusion barrier metal layer 312 is disposed between the source electrode 302 and the source wiring layer 402, and suppresses diffusion of metal atoms between the source electrode 302 and the source wiring layer 402. The diffusion barrier metal layer 312 is configured using a high melting point metal material such as TiN, Pt, Mo, Nb, W, but is not limited thereto. The thickness of the diffusion barrier metal layer 312 is, for example, 50 nm, but is not limited thereto.
[0043] Here, when the implantation voltage supplied to the implantation electrode 304 is Vh, the implantation voltage Vh is lower than the drain voltage Vd supplied to the drain electrode 301. Since holes can be supplied to the vicinity of or inside the channel layer by supplying the implantation voltage Vh to the fourth nitride semiconductor layer 107, electrons trapped in the vicinity of or inside the channel layer (electron traps) can be neutralized. This can suppress an increase in on-resistance. Further, since the implantation voltage Vh is lower than the drain voltage Vd, the electric field intensity applied to the gate electrode 303 is reduced compared to the case where the implantation voltage Vh is equal to the drain voltage Vd, thereby suppressing the occurrence of gate leakage current and dielectric breakdown. Note that the implantation voltage Vh may be supplied by performing boosting and high-voltage control on a voltage from outside the semiconductor device 100 inside the semiconductor device 100, or may be supplied by stepping down the drain voltage Vd.
[0044] When the threshold voltage of a transistor including a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 106, a drain electrode 301, a source electrode 302, and a gate electrode 303 is defined as Vth, an implantation voltage Vh satisfies the following Formula 1.
[0045] Vth < Vh < Vd ···Formula 1
[0046] Furthermore, when a distance between the drain electrode 301 and the gate electrode 303 is defined as Lgd, and a distance between the gate electrode 303 and an implantation electrode 304 is defined as Lgp, the following Formula 2 is satisfied.
[0047] Vh / Lgp < Vd / Lgd ···Formula 2
[0048] It is only required to satisfy at least one of Formula 1 and Formula 2. Further, the distance Lgd may be determined in accordance with the drain voltage Vd.
[0049] From the viewpoint of effectively neutralizing electron traps generated in the vicinity of the gate electrode 303, the fourth nitride semiconductor layer 107 is preferably disposed at a position close to the gate electrode 303 in the X-axis direction, which is a direction of the shortest distance connecting the drain electrode 301 and the gate electrode 303 and is an example of a first direction. For example, the distance Lgp may be 1 / 2 or less of the distance Lgd, may be 1 / 3 or less thereof, or may be 1 / 4 or less thereof.
[0050] The fourth nitride semiconductor layer 107 is not limited to being provided as one layer, and a plurality of the fourth nitride semiconductor layers 107 may be provided.
[0051] (Embodiment 2) [2. Configuration of Semiconductor Device] Hereinafter, a semiconductor device according to the present embodiment will be described with reference to FIGS. 2A and 2B. In the following description, differences from Embodiment 1 will be mainly described, and descriptions of contents that are the same as or similar to those in Embodiment 1 will be omitted or simplified.
[0052] Figure 2A is a cross-sectional view showing the configuration of the semiconductor device 100A according to this embodiment. Figure 2B is a plan view showing the configuration of the semiconductor device 100A according to this embodiment. Figure 2B shows a plan view of the semiconductor device 100A shown in Figure 2A when cut along the IIb-IIb cutting line. In this embodiment, an example in which multiple fourth nitride semiconductor layers 107 are provided will be described.
[0053] As shown in Figures 2A and 2B, the semiconductor device 100A comprises a plurality of fourth nitride semiconductor layers 107 and a voltage divider circuit 500 for supplying injection voltage to each row of fourth nitride semiconductor layers 107. Specifically, the semiconductor device 100A comprises a plurality of fourth nitride semiconductor layers 107a, a plurality of fourth nitride semiconductor layers 107b, and a plurality of fourth nitride semiconductor layers 107c that contact the drain electrode 301, with each row being different from the others. In other words, in the semiconductor device 100A, a plurality of fourth nitride semiconductor layers 107 are provided discretely in the X-axis direction and the Y-axis direction, respectively. It can also be said that the plurality of fourth nitride semiconductor layers 107 are arranged in a two-dimensional manner. The Y-axis direction is a direction orthogonal to the first direction in a plan view and is an example of the second direction. Furthermore, the fourth nitride semiconductor layer 107a may be an example of the first fourth nitride semiconductor layer, and the fourth nitride semiconductor layer 107b may be an example of the second fourth nitride semiconductor layer. Also, the fourth nitride semiconductor layer 107c may be an example of the second fourth nitride semiconductor layer, and the fourth nitride semiconductor layers 107a and 107b may be examples of the first fourth nitride semiconductor layer. Note that the fourth nitride semiconductor layer 107 is not formed in the inert region 108.
[0054] In a plan view, the region where the fourth nitride semiconductor layer 107 is provided may have a higher on-resistance than the region where the fourth nitride semiconductor layer 107 is not provided. As shown in Figure 2B, by arranging the fourth nitride semiconductor layer 107 with a gap in the Y-axis direction, the on-resistance can be effectively reduced. This makes it less likely for the current flowing between the drain and source to be obstructed when the transistor is turned on.
[0055] The injection electrode 304a extends in the Y-axis direction and supplies an injection voltage Vh1 to each of the fourth nitride semiconductor layers 107a arranged in the Y-axis direction. The injection electrode 304b extends in the Y-axis direction and supplies an injection voltage Vh2 to each of the fourth nitride semiconductor layers 107b arranged in the Y-axis direction. The injection voltages Vh1 and Vh2 are voltages supplied from the voltage divider circuit 500 and are, for example, different voltages. In this way, by arranging the fourth nitride semiconductor layers 107 discretely in the X-axis direction, it becomes possible to supply different voltages to the fourth nitride semiconductor layers 107 at different positions in the X-axis direction.
[0056] The voltage divider circuit 500 is a circuit for stepping down the drain voltage Vd and supplying it to each injection electrode 304. Details of the voltage divider circuit 500 will be described later with reference to Figures 5A to 11.
[0057] An injection voltage Vh1 is supplied to the fourth nitride semiconductor layer 107a via the voltage divider circuit 500, an injection voltage Vh2 is supplied to the fourth nitride semiconductor layer 107b via the voltage divider circuit 500, and a drain voltage Vd is supplied to the fourth nitride semiconductor layer 107c via the drain electrode 301. Here, each voltage satisfies the relationship shown in Equation 3 below.
[0058] Vh2>Vh1>Vd...Formula 3
[0059] Thus, the injection voltage supplied to each fourth nitride semiconductor layer 107 may decrease as it approaches the gate electrode 303 from the drain electrode 301. Note that the injection voltage supplied to the fourth nitride semiconductor layer 107 closer to the gate electrode 303 (an example of a second fourth nitride semiconductor layer) among the two fourth nitride semiconductor layers 107 arranged in the X-axis direction should be lower than the voltage supplied to the fourth nitride semiconductor layer 107 closer to the drain electrode 301 (an example of a first fourth nitride semiconductor layer).
[0060] The multiple fourth nitride semiconductor layers 107 may be discretely arranged in at least one of the X-axis and Y-axis directions. Alternatively, the multiple fourth nitride semiconductor layers 107 may be arranged one-dimensionally in either the X-axis or Y-axis direction. Furthermore, if the multiple fourth nitride semiconductor layers 107 are discretely arranged in the X-axis direction, each fourth nitride semiconductor layer 107 may be provided to extend in the Y-axis direction.
[0061] (Various Modifications of Embodiment 2) The semiconductor device according to this modification will be described below with reference to Figures 3 and 4. In the following description, the differences from Embodiment 2 will be the main focus, and the same or similar content as in Embodiment 2 will be omitted or simplified. Figures 3 and 4 are cross-sectional views showing the configuration of the semiconductor device according to each example of this modification.
[0062] As shown in Figure 3, in the semiconductor device 100B, a first insulating layer 201 and a second insulating layer 202 are arranged between the fourth nitride semiconductor layer 107 and the injection electrode 304. In other words, the fourth nitride semiconductor layer 107 and the injection electrode 304 are not in direct contact. The semiconductor device 100B has a coupled structure in which voltage is applied to the fourth nitride semiconductor layer 107 via the insulating layer.
[0063] Figure 3 illustrates an example where the length of the injection electrode 304 in the X-axis direction is the same as the length of the fourth nitride semiconductor layer 107 in the X-axis direction; however, the shape or size of the injection electrode 304 is not limited to this. Other examples of other shapes or sizes of the injection electrode 304 will be described with reference to Figure 4.
[0064] As shown in Figure 4, the semiconductor device 100C includes an injection electrode 304 formed to cover the fourth nitride semiconductor layer 107. The injection electrode 304 has an extended portion that extends in the X-axis direction and protruding portions that project from both ends of the extended portion toward the negative Z-axis, but its shape is not limited thereto.
[0065] Thus, by having a structure in which the injection electrode 304 and the fourth nitride semiconductor layer 107 perform a coupled voltage application via an insulating layer, it becomes possible to form the injection electrode 304 without being affected by the size of the fourth nitride semiconductor layer 107 (for example, the length in the X-axis direction in the example of Figure 4). This improves the degree of freedom in the shape and size of the injection electrode 304.
[0066] (Configuration of the voltage divider circuit) Next, the configuration of the voltage divider circuit 500 will be explained with reference to Figures 5A to 11. Figure 5A is the first figure showing the configuration of a resistive voltage divider circuit (an example of the voltage divider circuit 500) according to Embodiment 2 and each of its modified examples. Figure 5A shows a resistive voltage divider circuit that generates one output voltage Vd2.
[0067] As shown in Figure 5A, the voltage divider circuit 500 may have a configuration in which two resistive elements are connected in series. The two resistive elements include a resistive element with resistance value R1 and a resistive element with resistance value R2. This makes it possible to divide the drain voltage Vd at all times. The voltage between the two resistive elements (i.e., the output voltage Vd2 output from the voltage divider circuit 500) is calculated by the following equation 4, where Vd1 is the drain voltage.
[0068] Vd2=Vd1×R2 / (R1+R2)...Formula 4
[0069] Figure 5B is the second figure showing the configuration of the resistor voltage divider circuit according to Embodiment 2 and its various modifications. In Figure 5B, in addition to the voltage divider circuit 500 shown in Figure 5A, a power supply and the like are shown. Here, the resistance values R1 and R2 are assumed to be 10 kΩ, and the power supply voltage Vdd is assumed to be 650 V. Also, the transistor is assumed to switch on and off every 10 μsec (that is, the gate electrode 303 is supplied with a gate voltage that switches on and off every 10 μsec). Note that the values shown in Figure 5B are examples and are not limited thereto.
[0070] As shown in Figure 5B, the drain voltage Vd1 is supplied to the voltage divider circuit 500 via a 1kΩ resistor. The drain voltage Vd1 is the same voltage as the drain voltage Vd supplied to the drain electrode 301. In the example in Figure 5B, the output voltage Vd2 is divided by the resistor when the transistor is off, and becomes half the voltage of the drain voltage Vd1. When the transistor is turned on, a drain current I flows through the transistor. The drain current I is calculated by the following equation 5.
[0071] I=Vdd / R3...Formula 5
[0072] Furthermore, from the viewpoint of suppressing an increase in the transistor's drain leakage current, the resistive element should have a high resistance of a predetermined value or higher. The predetermined value may be, for example, 1 kΩ or more, 5 kΩ, 20 kΩ, or 100 kΩ. For example, by having a resistance value of 1 kΩ or more for the resistive element, an increase in the overall leakage current of the transistor circuit can be effectively suppressed. Thus, the resistive element may be made of a high-resistance metal of, for example, 1 kΩ or more.
[0073] Figure 6 shows the simulation results of the voltage and current of the resistive voltage divider circuit according to Embodiment 2 and its various modifications. Figure 6 shows the simulation results of the drain voltage Vd1, the output voltage (output voltage Vd2 shown in Figure 5B), and the drain current I.
[0074] As shown in Figure 6, it can be seen that the output voltage Vd2 is output from the voltage divider circuit 500 during the period when the transistor is off (for example, during periods of approximately 12-20 μs and 32-40 μs).
[0075] Here, the configuration of the resistive element will be explained with reference to Figures 7A to 7E. Figures 7A to 7E are cross-sectional views showing examples of the configuration of the resistive element according to Embodiment 2 and each of its modified forms.
[0076] As shown in Figure 7A, the resistive element may be configured to include a semiconductor resistor (semiconductor resistive region). The semiconductor resistor has electrodes 501 and 502 and an insulating layer 503 on a second nitride semiconductor layer 104. Electrodes 501 and 502 are located at both ends of the insulating layer 503. The voltage divider resistor is formed by the first nitride semiconductor layer 103, the second nitride semiconductor layer 104, the two-dimensional electron gas layer 105, electrodes 501 and 502, and the insulating layer 503. Electrodes 501 and 502 are an example of a pair of electrodes.
[0077] As shown in Figure 7B, the resistance between electrodes 501 and 502 may be further increased by ion implantation in the second nitride semiconductor layer 104 in addition to the configuration of Figure 7A. In ion implantation, impurities such as B, F, C, and Fe are implanted. For example, the first region of the second nitride semiconductor layer 104 directly beneath the insulating layer 503 and the second region of the second nitride semiconductor layer 104 directly beneath electrodes 501 and 502 have different types and concentrations of impurities. In the first region, for example, the concentration of at least one of B, F, C, and Fe may be higher than in the second region. Electrode 502 is electrically connected to, for example, the drain electrode 301.
[0078] As shown in Figure 7C, the second nitride semiconductor layer 104 (for example, AlGaN which functions as a barrier layer) may be thinned by etching or the like. This increases the resistance of the two-dimensional electron gas layer 105, thereby increasing the resistance between electrodes 501 and 502. In the example in Figure 7C, the thickness of the portion of the second nitride semiconductor layer 104 directly beneath the insulating layer 503 is thinner than the thickness of the portion of the second nitride semiconductor layer 104 directly beneath electrodes 501 and 502. The portion of the second nitride semiconductor layer 104 directly beneath the insulating layer 503 is the portion of the second nitride semiconductor layer 104 that has a surface in contact with the lower surface (Z-axis negative side) of the insulating layer 503. Also, the portion of the second nitride semiconductor layer 104 directly beneath electrodes 501 and 502 is the portion of the second nitride semiconductor layer 104 that has a surface in contact with the lower surface (Z-axis negative side) of electrodes 501 and 502.
[0079] In Figure 7C, the magnitude of the resistance of the two-dimensional electron gas layer 105 is indicated by the way the dashed lines are displayed, with shorter dashed lines indicating higher resistance. It can also be said that the resistance of the two-dimensional electron gas layer 105 directly beneath the insulating layer 503 is higher than the resistance of the two-dimensional electron gas layer 105 directly beneath electrodes 501 and 502.
[0080] As shown in Figure 7D, the resistance between electrodes 501 and 502 may be increased by the inverse piezoelectric effect by placing a fifth nitride semiconductor layer 504 on top of the second nitride semiconductor layer 104. The fifth nitride semiconductor layer 504 is a nitride semiconductor layer having a lattice power of about the same magnitude as the channel layer.
[0081] As shown in Figure 7E, the resistance between electrodes 501 and 502 may be further increased by ion implantation into the second nitride semiconductor layer 104 in the configuration shown in Figure 7D. Ion implantation may be performed through the fifth nitride semiconductor layer 504 or before the fifth nitride semiconductor layer 504 is formed. Ion implantation may be performed, for example, for the purpose of device isolation.
[0082] Next, examples in which the resistive element includes a capacitive element will be explained with reference to Figures 8A to 11. Figure 8A is the first figure showing the configuration of a capacitive voltage divider circuit (an example of a voltage divider circuit 500) according to Embodiment 2 and each of its modifications. Figure 8A shows a resistive voltage divider circuit that generates a single output voltage Vd2.
[0083] As shown in Figure 8A, the voltage divider circuit 500 may have a configuration in which two capacitive elements are connected in series. The two capacitive elements include a capacitive element with capacitance value C1 and a capacitive element with capacitance value C2. The voltage between the two capacitive elements (i.e., the output voltage Vd2 output from the voltage divider circuit 500) is calculated by the following equation 6.
[0084] Vd2=Vd1×C1 / (C1+C2)...Formula 6
[0085] Figure 8B is the second figure showing the configuration of the resistive voltage divider circuit according to Embodiment 2 and its various modifications. In Figure 8B, in addition to the voltage divider circuit 500 shown in Figure 8A, a power supply and the like are shown. Here, the capacitance values C1 and C2 are assumed to be 10 pF, and the power supply voltage Vdd is assumed to be 650 V. Note that the values shown in Figure 8B are illustrative and not limited thereto.
[0086] As shown in Figure 8B, the drain voltage Vd1 is supplied to the voltage divider circuit via a 1kΩ resistor. In the example in Figure 8B, the output voltage Vd2 is half the drain voltage Vd1.
[0087] Figure 9 shows the simulation results of the voltage and current of the capacitive voltage divider circuit according to Embodiment 2 and each of its modifications. Figure 9 shows the simulation results of the drain voltage Vd1, the output voltage (output voltage Vd2 shown in Figure 8B), and the drain current I.
[0088] As shown in Figure 9, it can be seen that, in accordance with the on / off operation of the transistor, a voltage approximately half of the drain voltage Vd1 is output as the output voltage Vd2 from the voltage divider circuit 500 at predetermined time intervals.
[0089] As shown in Figure 9, it can be seen that the output voltage Vd2 is output from the voltage divider circuit 500 during the period when the transistor is off (for example, the periods of 10-20 μs and 30-40 μs).
[0090] Next, an example in which the voltage divider circuit 500 includes both resistive and capacitive elements will be described with reference to Figures 10A to 11. Figures 10A and 10B are diagrams showing the configuration of a capacitive-resistive voltage divider circuit (an example of a voltage divider circuit 500) according to Embodiment 2 and its various modifications. Figure 10A shows a voltage divider circuit 500 that generates voltages applied to two fourth nitride semiconductor layers 107.
[0091] As shown in Figures 10A and 10B, the voltage divider circuit 500 may have a configuration in which one capacitive element and two resistive elements are connected in series. The capacitance value of the capacitive element is C. The voltage between the capacitive element and the resistive element (i.e., the first output voltage Vd2 output from the voltage divider circuit 500) and the voltage between the two resistive elements (i.e., the second output voltage Vd3 output from the voltage divider circuit 500) are calculated by the following equations 7 to 10, where Vd1 is the drain voltage. Equations 7 and 8 are for calculating the voltage output at the moment the transistor is turned on, and equations 9 and 10 are for calculating the voltage output at the moment the transistor is turned off.
[0092] Vd2==-Vd1...Formula 7 Vd3=-Vd1×R1 / (R1+R2)...Formula 8 Vd2=Vd1...Formula 9 Vd3=Vd1×R1 / (R1+R2)...Formula 10
[0093] As shown in equations 7 and 8, a negative voltage is output from the voltage divider circuit only at the moment it is turned on, and as shown in equations 9 and 10, a positive voltage is output from the voltage divider circuit only at the moment it is turned off.
[0094] Figure 11 shows the simulation results of the voltage and current of the resistive voltage divider circuit according to Embodiment 2 and each modified example. Figure 6 shows the simulation results of the drain voltage Vd1, the divided voltage output voltages (the first output voltage Vd2 and the second output voltage Vd3 shown in Figure 10B), and the drain current I.
[0095] As shown in Figure 11, it can be seen that negative voltages, the first output voltage Vd2 and the second output voltage Vd3, are output at the moment the transistor is turned on (for example, 0 μs and 20 μs), and positive voltages, the first output voltage Vd2 and the second output voltage Vd3, are output at the moment the transistor is turned off (for example, 10 μs).
[0096] (Method for Manufacturing a Voltage Divider Circuit) Next, the method for manufacturing the voltage divider circuit 500 shown in Figure 7D will be explained with reference to Figures 12A to 17B. Figure 12A is a first plan view for explaining the method for manufacturing a resistor element according to Embodiment 2 and each of its modified examples. Figure 12B is a cross-sectional view of a resistor element in the process of being manufactured according to Embodiment 2 and each of its modified examples, cut along the XIIb-XIIb cutting line in Figure 12A.
[0097] Figures 12A and 12B show the state in which epitaxial growth layers are stacked on the substrate 101. The epitaxial growth layer includes a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, and a p-type GaN layer 607. The p-type GaN layer 607 is a layer for forming the third nitride semiconductor layer 106 and the fourth nitride semiconductor layer 107, and is formed over the entire plane.
[0098] Figure 13A is a second plan view illustrating the manufacturing method of the resistive element according to Embodiment 2 and its various modifications. Figure 13B is a cross-sectional view of the resistive element during manufacturing according to Embodiment 2 and its various modifications, cut along the XIIIb-XIIIb cutting line in Figure 13A. Note that in Figure 13A, only the third nitride semiconductor layer 106, the fourth nitride semiconductor layer 107, and the GaN layers 507a and 507b are shown.
[0099] As shown in Figures 13A and 13B, the p-type GaN layer 607 is patterned by dry etching. Patterning forms a third nitride semiconductor layer 106 that constitutes the gate portion, a fourth nitride semiconductor layer 107 that constitutes the hole injection portion, and GaN layers 507a and 507b that constitute the voltage divider resistor portion. The GaN layers 507a and 507b constitute a fifth nitride semiconductor layer 504.
[0100] The third nitride semiconductor layer 106 is formed in an elongated shape in the Y-axis direction, and the fourth nitride semiconductor layer 107 is formed discretely in the Y-axis direction. The spacing between the multiple fourth nitride semiconductor layers 107 is not particularly limited; they may be arranged at equal intervals or at different intervals. Also, the planar shapes of the multiple fourth nitride semiconductor layers 107 may be the same or different. In the example shown in Figure 2B, an example is shown in which the multiple fourth nitride semiconductor layers 107 have a rectangular shape. The GaN layers 507a and 507b have a shape in which portions that are convex towards the positive X-axis side and portions that are convex towards the negative X-axis side are alternately connected.
[0101] Figure 14 is a cross-sectional view of a resistive element during the manufacturing stage, showing the state after ion implantation, as shown in Figure 13B.
[0102] As shown in Figure 14, ion implantation is performed only in the desired area (dashed box A). For example, device isolation is achieved by increasing the resistance of a portion of the two-dimensional electron gas layer 105 through ion implantation of F-based ions.
[0103] Figure 15A is a third plan view illustrating the manufacturing method of the resistive element according to Embodiment 2 and its various modifications. Figure 15B is a cross-sectional view of the resistive element in the process of manufacturing according to Embodiment 2 and its various modifications, cut along the XVb-XVb cutting line in Figure 15A. Figure 15A is a view obtained by adding a drain electrode 301, a source electrode 302, electrodes 501 and 502 to Figure 13A.
[0104] As shown in Figures 15A and 15B, a P-SiN film containing P-SiN, an example of the material constituting the first insulating layer 201, is formed. After opening the P-SiN film in the source and drain regions, a metal that will become the source electrode 302 and drain electrode 301 is deposited, etched, and patterned. This forms the first insulating layer 201, the source electrode 302, and the drain electrode 301. Subsequently, heat treatment is performed to alloy the materials and form an ohmic connection between the source electrode 302 and drain electrode 301 and the two-dimensional electron gas layer 105. In addition, a second insulating layer 202 is formed to cover each layer.
[0105] Figure 16A is a fourth plan view illustrating the manufacturing method of the resistive element according to Embodiment 2 and its various modifications. Figure 16B is a cross-sectional view of the resistive element in the process of manufacturing according to Embodiment 2 and its various modifications, cut along the XVIb-XVIb line in Figure 16A. Figure 16A is a view of Figure 15A with the gate electrode 303 and metal layer 310 added.
[0106] As shown in Figures 16A and 16B, the source electrode 302 and drain electrode 301 are protected by forming a P-SiN film containing P-SiN, which is an example of the material constituting the second insulating layer 202. Then, the gate electrode opening and the hole injection region opening are formed, the gate metal is deposited, and the pattern is etched. This forms the gate electrode 303 and the metal layer 310. The metal layer 310 connects the voltage divider resistor and the hole injection region. Subsequently, P-SiN or P-SiO, which is an example of the material constituting the third insulating layer 203, is formed. ２ A protective film containing the protective film is formed.
[0107] Figure 17A is a fifth plan view illustrating the manufacturing method of the resistive element according to Embodiment 2 and each of its modifications. Figure 17B is a cross-sectional view of the resistive element during manufacturing according to Embodiment 2 and each of its modifications, cut along the XVIIb-XVIIb cutting line in Figure 17A. Figure 17A is a view of Figure 16A with the addition of a diffusion-preventing metal layer 320.
[0108] As shown in Figures 17A and 17B, next, the protective films (for example, the second insulating layer 202 and the third insulating layer 203) of the source electrode portion, drain electrode portion, gate wiring connection portion, and resistor wiring connection portion are opened. For example, the portion of the protective film above the source electrode 302, the portion above the drain electrode 301, the portion above the region of the gate electrode 303 to which the gate wiring is connected (for example, the region on the Y-axis negative side of the gate electrode 303), and the portions above electrodes 501 and 502 are opened. Next, a diffusion-preventing metal layer 320 is deposited in the opened portions and patterned by dry etching. After that, P-SiO ２Alternatively, an insulating layer 210 containing TEOS (Tetra Ethoxy Silane) or the like is formed, and a fourth insulating layer 204 is formed by opening the wiring contact portion.
[0109] Figure 18A is a sixth plan view illustrating the manufacturing method of the resistive element according to Embodiment 2 and each of its modifications. Figure 18B is a cross-sectional view of the resistive element in the process of manufacturing according to Embodiment 2 and each of its modifications, cut along the XVIIIb-XVIIIb cutting line in Figure 18A. Figure 18A is a view of Figure 17A with a wiring layer 330 added.
[0110] As shown in Figures 18A and 18B, a metal layer of about 4.0 μm thick is formed using Al containing Si and Cu, and patterned by dry etching. This forms the wiring layer 330. The wiring layer 330 on the source electrode 302 is formed to cover the gate electrode 303. The wiring layer 330 on the drain electrode 301 is connected to one end of the voltage divider resistor. The other end of the voltage divider resistor is connected to the pad and finally to GND.
[0111] Next, the grounding method for the voltage divider circuit 500 will be explained with reference to Figures 19A to 21. In the following explanation, an example will be described in which a GND layer (not shown) is formed on the back surface (Z-axis negative side) of the substrate 101 of the semiconductor device 100, and the device is grounded to this GND layer. However, for example, a GND layer may be formed on the mounting substrate on which the semiconductor device 100 is mounted, and the device may be grounded to this GND layer.
[0112] The voltage divider circuit 500 may be grounded via a scribe line or via openings (through holes penetrating in the Z-axis direction) that penetrate each layer on the substrate 101. By grounding using the scribe line and the openings within the chip, voltage division can be achieved at the chip level. For example, the voltage divider circuit 500 does not have to be grounded via a wire. An example of grounding via a scribe line is illustrated using Figures 19A and 19B, and an example of grounding via an opening is illustrated using Figures 20A and 20B. Grounding may also be done via a wire, and an example of grounding via a wire is illustrated using Figure 21.
[0113] Figure 19A is a plan view showing a first example of a grounding method for the voltage divider circuit 500 according to Embodiment 2 and its various modifications. Figure 19B is a cross-sectional view showing a first example of a grounding method for the voltage divider circuit 500 according to Embodiment 2 and its various modifications.
[0114] As shown in Figures 19A and 19B, the voltage divider circuit 500 may be grounded to the GND layer via a wiring layer 330a formed across the scribe line SL on the substrate 101. In other words, the wiring layer 330a may be provided along the side of each layer. Thus, the voltage divider circuit 500 may be grounded to the substrate 101. Note that in Figures 19A and 19B, only the portion of the wiring layer 330a that connects the voltage divider circuit 500 to the surface (Z-axis positive side) of the substrate 101 is shown.
[0115] Figure 20A is a plan view showing a second example of a grounding method for the voltage divider circuit 500 according to Embodiment 2 and its various modifications. Figure 20B is a cross-sectional view showing a second example of a grounding method for the voltage divider circuit 500 according to Embodiment 2 and its various modifications.
[0116] As shown in Figures 20A and 20B, the voltage divider circuit 500 may be formed to fill the opening h on the substrate 101. The wiring layer 330b may be in contact with, for example, the surface of the substrate 101.
[0117] The wiring layer on the front surface of the substrate 101 and the GND layer on the back surface may be electrically connected, for example, through through holes (for example, so-called vias) formed in the substrate 101, or they may be connected by other means. For example, the wiring layers 330a and 330b may be formed to penetrate the vias.
[0118] Figure 21 is a plan view showing a third example of a grounding method for the voltage divider circuit 500 according to Embodiment 2 and each of its modifications.
[0119] As shown in Figure 21, the wiring layer 330c formed on the electrode 501 of the voltage divider circuit has a protruding portion 330c1 on the Y-positive side, which is a protruding portion on the X-minus side. The protruding portion 330c1 may function as a wire connection portion connected by a wire or the like to an individual GND terminal provided outside the semiconductor device 100. In this way, the voltage divider circuit may be connected to GND by a separate path so that current does not flow from the voltage divider circuit to the transistor. An individual GND terminal means, for example, a GND terminal that is electrically isolated from the source electrode. Note that no opening h is formed on the substrate 101.
[0120] (Other Embodiments) Although semiconductor devices, etc., according to one or more embodiments have been described above based on Embodiment 1, Embodiment 2, and Modifications 1 and 2 of Embodiment 2, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications that a person skilled in the art could conceive of may be applied to these embodiments, and forms constructed by combining components from different embodiments may also be included in this disclosure.
[0121] For example, the GND of the voltage divider circuit 500 according to the second embodiment described above may be connected to, for example, the source electrode 302.
[0122] Furthermore, for example, the voltage divider circuit 500 according to the second embodiment described above is not limited to being formed on the substrate 101, but may be manufactured separately from the substrate 101, and the voltage divider circuit 500 and the semiconductor device 100 may be connected by wires or the like.
[0123] Furthermore, for example, the resistance value of the resistive element and the capacitance value of the capacitive element in the voltage divider circuit 500 according to the second embodiment may be appropriately determined so that the voltage supplied to the fourth nitride semiconductor layer 107, which is located closer to the gate electrode 303, becomes smaller.
[0124] Furthermore, the order of each step in the semiconductor device manufacturing method described in the above embodiments may be changed. Also, each step in the semiconductor device manufacturing method described in the above embodiments may be carried out as a single step or as separate steps. "Carried out as a single step" means that each step is carried out using a single device, that each step is carried out consecutively, or that each step is carried out in the same location. "Separate steps" means that each step is carried out using a different device, that each step is carried out at a different time (for example, on a different day), or that each step is carried out in a different location.
[0125] (Note) Based on the above description of embodiments, the following technologies are disclosed.
[0126] (Technical 1) A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer; a p-type third nitride semiconductor layer provided on the second nitride semiconductor layer; a gate electrode provided on the third nitride semiconductor layer; a source electrode and a drain electrode provided on the gate electrode; a p-type fourth nitride semiconductor layer provided on the second nitride semiconductor layer and between the gate electrode and the drain electrode; and an injection electrode provided on the fourth nitride semiconductor layer and supplied with an injection voltage lower than the drain voltage supplied to the drain electrode.
[0127] This allows for the neutralization of electron traps through hole injection from the fourth nitride semiconductor layer, thereby strengthening collapse prevention. Furthermore, since a voltage lower than the drain voltage is supplied to the fourth nitride semiconductor layer, the increase in electric field strength to the gate electrode can be suppressed compared to the case where the drain voltage is supplied to the fourth nitride semiconductor layer. Therefore, the semiconductor device can achieve both electron trap neutralization and electric field strength suppression.
[0128] (Technology 2) The semiconductor device according to Technology 1, wherein at least one of the following equations 1 and 2 holds true, where Vth is the threshold voltage of the gate electrode, Vd is the drain voltage, Vh is the injection voltage, Lgd is the distance between the gate electrode and the drain electrode, and Lgp is the distance between the gate electrode and the fourth nitride semiconductor layer.
[0129] Vth<Vh<Vd...Formula 1 Vh / Lgp<Vd / Lgd...Formula 2
[0130] This allows for an effective reduction in the electric field strength applied to the gate by applying a fourth nitride semiconductor layer and voltage between the gate and drain.
[0131] (Technical 3) The semiconductor device according to Technical 1 or 2, wherein the fourth nitride semiconductor layer is provided discretely in a plurality in the first direction in which the gate electrode and the drain electrode are aligned.
[0132] This allows for the effective neutralization of the gate-drain electron trap using multiple fourth nitride semiconductor layers.
[0133] (Technical 4) The semiconductor device according to Technical 3, wherein the plurality of fourth nitride semiconductor layers arranged in the first direction include a first fourth nitride semiconductor layer and a second fourth nitride semiconductor layer that is closer to the gate electrode than the first fourth nitride semiconductor layer, and the injection voltage supplied to the second fourth nitride semiconductor layer is lower than the injection voltage supplied to the first fourth nitride semiconductor layer.
[0134] As a result, the fourth nitride semiconductor layer, positioned closer to the gate electrode, can effectively inject holes under low electric field loads on the gate. This effectively suppresses leakage current and dielectric breakdown.
[0135] (Technical 5) The semiconductor device according to any one of Technical 1 to 4, wherein the fourth nitride semiconductor layer is provided discretely in a second direction orthogonal to the first direction in which the gate electrode and the drain electrode are aligned.
[0136] This helps to suppress interference with the transistor's on-operation.
[0137] (Technical 6) The semiconductor device according to any one of Technical 1 to 5, wherein the injection electrode is a Schottky electrode provided in contact with the fourth nitride semiconductor layer.
[0138] This makes it possible to suppress the flow of current between the fourth nitride semiconductor layer and the injection electrode due to the diode characteristics when the potential is in the reverse direction. In other words, it is possible to suppress the flow of leakage current from the injection electrode to the gate electrode.
[0139] (Technical 7) The semiconductor device according to any one of Technical 1 to 6, further comprising an insulating layer between the fourth nitride semiconductor layer and the injection electrode.
[0140] This makes it possible to suppress the flow of current between the fourth nitride semiconductor layer and the injection electrode. In other words, it is possible to suppress the leakage current flowing from the injection electrode to the gate electrode. Furthermore, since the formation of an electrode opening is unnecessary, the injection electrode can be formed even if the fourth nitride semiconductor layer is fine.
[0141] (Technical 8) A semiconductor device according to any one of Technical 1 to 7, comprising a voltage divider circuit for supplying the injection voltage to the injection electrode by dividing the drain voltage.
[0142] This eliminates the need for a separate power supply for the injection voltage, thus simplifying the semiconductor device.
[0143] (Technical 9) The voltage divider circuit is a semiconductor device according to Technical 8, comprising a resistive element for dividing the drain voltage.
[0144] This allows the drain voltage to be easily divided using resistive elements. For example, the desired voltage division ratio can be achieved simply by adjusting the ratio of the resistance values of the resistive elements.
[0145] (Technical 10) The resistive element is a semiconductor device as described in Technical 9, which is made of a high-resistance metal.
[0146] This allows resistors to be placed on top of transistors, improving layout flexibility.
[0147] (Technical 11) The resistive element is a semiconductor device according to Technical 9, comprising a semiconductor resistor.
[0148] This reduces the cost of creating the metal resistance layer.
[0149] (Technical 12) The semiconductor device is as described in Technical 11, wherein the semiconductor resistor is formed by ion implantation.
[0150] This reduces the area required for semiconductor resistors, making it easier to increase their resistance.
[0151] (Technical 13) The voltage divider circuit is a semiconductor device according to Technical 11 or 12, comprising an insulating layer formed on the second nitride semiconductor layer and a pair of electrodes formed on both ends of the insulating layer, wherein the thickness of the portion of the second nitride semiconductor layer directly below the insulating layer is thinner than the thickness of the portion of the second nitride semiconductor layer directly below the pair of electrodes.
[0152] This reduces the area required for semiconductor resistors, making it easier to increase their resistance.
[0153] (Technical 14) The resistive element is a semiconductor device according to any one of Technical 11 to 13, comprising a fifth nitride semiconductor layer on the second nitride semiconductor layer.
[0154] This reduces the area required for semiconductor resistors, making it easier to increase their resistance.
[0155] (Technical 15) The voltage divider circuit is a semiconductor device according to any one of Technical 8 to 14, comprising a capacitive element for dividing the drain voltage.
[0156] As a result, GND is connected to the source electrode, so GND current = source current. Since no current flows between the drain and source of the voltage divider circuit, power consumption can be reduced.
[0157] (Technical 16) The voltage divider circuit is grounded by a GND layer provided on the substrate, and is a semiconductor device according to any one of Technical 8 to 15.
[0158] This prevents the current from the voltage divider circuit from flowing directly into the source electrode. Furthermore, it allows for a reduction in the GND current by, for example, the parasitic resistance of the substrate.
[0159] This disclosure is useful for semiconductor devices using nitride semiconductors.
[0160] 100, 100A, 100B, 100C Semiconductor device 101 Substrate 102 Buffer layer 103 First nitride semiconductor layer 104 Second nitride semiconductor layer 105 Two-dimensional electron gas layer 106 Third nitride semiconductor layer 107, 107a, 107b, 107c Fourth nitride semiconductor layer 108 Inert region 201 First insulating layer 202 Second insulating layer 203 Third insulating layer 204 Fourth insulating layer 210 Insulating layer 301 Drain electrode 302 Source electrode 303 Gate electrode 304, 304a, 304b Injection electrode 310 Metal layer 311, 312, 320 Diffusion-preventing metal layer 330, 330a, 330b, 330c Wiring layer 330c1 Protrusion 401 Drain wiring layer 402 Source wiring layer 500 Voltage divider circuit 501, 502 Electrodes 503 Insulating layer 504 Fifth nitride semiconductor layer 507a, 507b GaN layer 607 p-type GaN layer A Dashed line frame h Aperture Lgd, Lgp Distance SL Scribe line
Claims
1. A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer; a p-type third nitride semiconductor layer provided on the second nitride semiconductor layer; a gate electrode provided on the third nitride semiconductor layer; a source electrode and a drain electrode provided on the gate electrode; a p-type fourth nitride semiconductor layer provided on the second nitride semiconductor layer and between the gate electrode and the drain electrode; and an injection electrode provided on the fourth nitride semiconductor layer and supplied with an injection voltage lower than the drain voltage supplied to the drain electrode.
2. Let Vth be the threshold voltage of the gate electrode, Vd be the drain voltage, Vh be the injection voltage, Lgd be the distance between the gate electrode and the drain electrode, and Lgp be the distance between the gate electrode and the fourth nitride semiconductor layer. Then at least one of the following equations 1 and 2 holds: Vth < Vh < Vd ... Equation 1 Vh / Lgp < Vd / Lgd ... Equation 2 The semiconductor device according to claim 1.
3. The semiconductor device according to claim 1 or 2, wherein the fourth nitride semiconductor layer is provided discretely in a first direction in which the gate electrode and the drain electrode are aligned.
4. The semiconductor device according to claim 3, wherein the plurality of fourth nitride semiconductor layers arranged in the first direction comprises a first fourth nitride semiconductor layer and a second fourth nitride semiconductor layer closer to the gate electrode than the first fourth nitride semiconductor layer, and the injection voltage supplied to the second fourth nitride semiconductor layer is lower than the injection voltage supplied to the first fourth nitride semiconductor layer.
5. The semiconductor device according to claim 1 or 2, wherein the fourth nitride semiconductor layer is provided discretely in a second direction orthogonal to the first direction in which the gate electrode and the drain electrode are aligned.
6. The semiconductor device according to claim 1 or 2, wherein the injection electrode is a Schottky electrode provided in contact with the fourth nitride semiconductor layer.
7. The semiconductor device according to claim 1 or 2, further comprising an insulating layer between the fourth nitride semiconductor layer and the injection electrode.
8. The semiconductor device according to claim 1 or 2, further comprising a voltage divider circuit for supplying the injection voltage to the injection electrode by dividing the drain voltage.
9. The semiconductor device according to claim 8, wherein the voltage divider circuit comprises a resistive element for dividing the drain voltage.
10. The semiconductor device according to claim 9, wherein the resistive element is made of a high-resistance metal.
11. The semiconductor device according to claim 9, wherein the resistive element is configured to include a semiconductor resistor.
12. The semiconductor device according to claim 11, wherein the semiconductor resistor is formed by ion implantation.
13. The semiconductor device according to claim 11, wherein the voltage divider circuit comprises an insulating layer formed on the second nitride semiconductor layer and a pair of electrodes formed at both ends of the insulating layer, and the thickness of the portion of the second nitride semiconductor layer directly beneath the insulating layer is thinner than the thickness of the portion of the second nitride semiconductor layer directly beneath the pair of electrodes.
14. The semiconductor device according to claim 11, wherein the resistive element comprises a fifth nitride semiconductor layer on the second nitride semiconductor layer.
15. The semiconductor device according to claim 8, wherein the voltage divider circuit comprises a capacitive element for dividing the drain voltage.
16. The semiconductor device according to claim 8, wherein the voltage divider circuit is grounded by a GND layer provided on the substrate.