Semiconductor device

Abstract

The semiconductor device includes: a semiconductor layer having a main surface; an insulating interlayer film covering the main surface; an opening penetrating the interlayer film and exposing the semiconductor layer; a metal via electrode connected to the semiconductor layer in the opening; and a metal main electrode disposed on the interlayer film and forming a connection boundary portion with the via electrode.

Description

Semiconductor equipment

[0001] This application claims priority under Japanese Patent Application No. 2025-031029, filed with the Japan Patent Office on 28 February 2025, the entire contents of which are incorporated herein by reference. This disclosure relates to semiconductor devices.

[0002] Patent document 1 (US2021 / 036116A1) discloses a field-effect transistor comprising a silicon carbide layer, a superjunction structure, and a gate electrode. The superjunction structure includes alternating p-type and n-type regions formed in the silicon carbide layer. The gate electrode is embedded in a gate trench formed in the p-type region.

[0003] U.S. Patent Application Publication No. 2021 / 036116

[0004] [Summary] This disclosure provides a novel semiconductor device.

[0005] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a body region of a second conductivity type formed on the surface of the main surface; a trench-type gate structure formed on the main surface so as to penetrate the body region and extending in a first direction along the main surface; a well region of a second conductivity type formed below the gate structure within the semiconductor layer; and a pillar region of a second conductivity type extending in a second direction along the main surface within the semiconductor layer so as to intersect the gate structure and electrically connecting the well region to the body region.

[0006] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a trench-type gate structure formed on the main surface and extending in a first direction along the main surface; a first region of the first conductivity type extending in a second direction along the main surface so as to intersect the gate structure below the gate structure within the semiconductor layer; and a second region of the second conductivity type extending in the second direction so as to intersect the gate structure below the gate structure within the semiconductor layer and forming a pn junction with the first region.

[0007] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; and a mesh region of a second conductivity type extending in a mesh-like manner in a first and second direction along the main surface at a thickness position spaced apart from the main surface within the semiconductor layer, and dividing a plurality of intermesh regions of the first conductivity type as a plurality of current paths within the semiconductor layer.

[0008] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a plurality of trenches extending in a striped pattern in a first direction on the main surface; a plurality of first striped regions of a second conductivity type, each formed below the plurality of trenches within the semiconductor layer and extending in a striped pattern in the first direction following the plurality of trenches; and a plurality of second striped regions of a second conductivity type extending in a striped pattern in a second direction intersecting the first direction within the semiconductor layer so as to be connected in a mesh-like manner to the plurality of first striped regions, and defining inter-mesh regions of the first conductivity type as current paths within the semiconductor layer.

[0009] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a trench-type gate structure formed on the main surface; a first region of a first conductivity type having an impurity concentration higher than that of the semiconductor layer, formed within the semiconductor layer along the gate structure, and having a first bottom located below the depth position of the bottom wall of the gate structure; and a second region of a second conductivity type formed within the semiconductor layer below the gate structure so as to form a pn junction with the first region, and having a second bottom located on the bottom wall side of the gate structure below the depth position of the first bottom.

[0010] This disclosure provides a semiconductor device comprising: an n-type semiconductor layer containing SiC and having a base concentration due to a pentavalent element; an n-type first pillar region extending in the thickness direction within the semiconductor layer and having the base concentration and a first additional concentration due to a pentavalent element applied to the base concentration; and a p-type second pillar region extending in the thickness direction within the semiconductor layer and having the base concentration and a second additional concentration due to a trivalent element applied to the base concentration, wherein the second pillar region comprises a p-type lower region having the base concentration and the second additional concentration, and a p-type upper region having the base concentration, the second additional concentration, and a correction concentration due to a pentavalent element applied to the base concentration to adjust the second additional concentration downward.

[0011] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a trench-type gate structure formed on the main surface; a first pillar region of a first conductivity type having a first lower region located below the depth position of the bottom wall of the gate structure within the semiconductor layer; and a second pillar region of a second conductivity type having a second lower region located below the depth position of the bottom wall within the semiconductor layer and forming a pn junction with the first lower region.

[0012] This disclosure provides a semiconductor device comprising: a semiconductor layer having a main surface; a gate structure including a trench formed on the main surface; an insulating film covering the wall surface of the trench; an embedded electrode embedded in the trench via the insulating film; and an embedded insulator covering the embedded electrode within the trench so as to expose the main surface; and a main electrode having a portion that directly covers the main surface and a portion that directly covers the embedded insulator, and electrically insulated from the embedded electrode by the embedded insulator.

[0013] This disclosure provides a semiconductor device comprising: a semiconductor layer having a main surface; an insulating interlayer film covering the main surface; an opening penetrating the interlayer film and exposing the semiconductor layer; a metallic via electrode connected to the semiconductor layer within the opening; and a metallic main electrode disposed on the interlayer film and forming a connection boundary with the via electrode.

[0014] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a trench-type gate structure formed on the main surface and extending in a first direction along the main surface; a first region of the first conductivity type extending in a second direction along the main surface so as to intersect the gate structure within the semiconductor layer; and a second region of the second conductivity type extending in a second direction so as to intersect the gate structure within the semiconductor layer and forming a pn junction with the first region.

[0015] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a body region of a second conductivity type formed on the surface of the main surface; a trench-type gate structure formed on the main surface so as to penetrate the body region and extending in a first direction along the main surface; a first region of the first conductivity type formed in the semiconductor layer below the body region and extending in a second direction along the main surface so as to intersect the gate structure; and a second region of the second conductivity type formed in the semiconductor layer below the body region and extending in the second direction so as to intersect the gate structure.

[0016] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; a trench-type gate structure extending in one direction on the main surface; a plurality of first regions of the first conductivity type formed at intervals in the one direction following the extending direction of the gate structure in the region directly beneath the gate structure within the semiconductor layer; and a plurality of second regions of the second conductivity type formed alternately with the plurality of first regions in the one direction in the region directly beneath the gate structure within the semiconductor layer.

[0017] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; an active region provided on the inner part of the main surface; an outer region provided on the peripheral edge of the main surface; a trench-type gate structure formed on the main surface in the active region; a pillar region of a second conductivity type formed deeper than the gate structure within the semiconductor layer of the active region; and a field region of a second conductivity type formed within the semiconductor layer of the outer region.

[0018] This disclosure provides a semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface; an active region provided on the inner part of the main surface; an outer region provided on the peripheral edge of the main surface; a trench-type gate structure extending in a first direction along the main surface in the active region; a pillar region of a second conductivity type extending in a second direction along the main surface so as to intersect the gate structure within the semiconductor layer of the active region and formed deeper than the gate structure; and an outer well region of a second conductivity type formed within the semiconductor layer of the outer region.

[0019] The aforementioned or any other purposes, features, and effects will be revealed in the detailed description with reference to the attached drawings.

[0020] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example of the layout of the first main surface shown in Figure 2. Figure 4 is an enlarged plan view showing the inner part of the active region shown in Figure 3. Figure 5 is an enlarged plan view showing the peripheral part of the active region shown in Figure 3. Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 4. Figure 10 is a cross-sectional view along the line XX shown in Figure 5. Figure 11 is an enlarged cross-sectional view of the gate structure shown in Figure 6. Figure 12 is an enlarged cross-sectional view of the gate structure shown in Figure 7. Figure 13 is a further enlarged cross-sectional view of the source opening shown in Figure 11. Figure 14 is a cross-sectional perspective view showing the first main part of the active region. Figure 15 is a cross-sectional perspective view showing the second main part of the active region. Figure 16 is a cross-sectional perspective view showing the third main part of the active region. Figure 17 is a cross-sectional perspective view showing the fourth main part of the active region. Figure 18 is a horizontal cross-sectional view along the line XVIII-XVIII shown in Figure 6. Figure 19 is a horizontal cross-sectional view along the line XIX-XIX shown in Figure 6. Figure 20 is a graph illustrating the impurity concentration of the first pillar region. Figure 21 is a graph illustrating the impurity concentration of the second pillar region. Figure 22 is a cross-sectional view showing the outer region. Figure 23 is an enlarged plan view showing the active region of the semiconductor device according to the second embodiment. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 23. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 23. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 23. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 23. Figure 28 is a cross-sectional perspective view of the active region shown in Figure 23. Figure 29 is an enlarged plan view showing the active region of the semiconductor device according to the third embodiment. Figure 30 is a cross-sectional view along the line XXX-XXX shown in Figure 29. Figure 31 is a cross-sectional view along the line XXXI-XXXI shown in Figure 29. Figure 32 is a cross-sectional perspective view of the active region shown in Figure 29. Figure 33 is a cross-sectional perspective view showing the active region of the semiconductor device according to the fourth embodiment. Figure 34 is a graph illustrating the impurity concentrations of the first pillar region and the second pillar region shown in Figure 33.Figure 35 is a cross-sectional view showing the active region of the semiconductor device according to the fifth embodiment together with the via electrode and source electrode according to the first example. Figure 36 is an enlarged cross-sectional view of the via electrode and source electrode shown in Figure 35. Figure 37A is an enlarged cross-sectional view of the via electrode and source electrode according to the second example. Figure 37B is an enlarged cross-sectional view of the via electrode and source electrode according to the third example. Figure 37C is an enlarged cross-sectional view of the via electrode and source electrode according to the fourth example. Figure 37D is an enlarged cross-sectional view of the via electrode and source electrode according to the fifth example. Figure 37E is an enlarged cross-sectional view of the via electrode and source electrode according to the sixth example. Figure 37F is an enlarged cross-sectional view of the via electrode and source electrode according to the seventh example. Figure 37G is an enlarged cross-sectional view of the via electrode and source electrode according to the eighth example. Figure 37H is an enlarged cross-sectional view of the via electrode and source electrode according to the ninth example. Figure 37I is an enlarged cross-sectional view of the via electrode and source electrode according to the tenth example. Figure 38 is a plan view showing the semiconductor device according to the sixth embodiment. Figure 39 is a cross-sectional view along the line XXXIX-XXXIX shown in Figure 38. Figure 40 is a plan view showing an example layout of the first main surface shown in Figure 39. Figure 41 is an enlarged plan view showing the inner part of the active region shown in Figure 40. Figure 42 is an enlarged plan view showing the peripheral part of the active region shown in Figure 40. Figure 43 is a cross-sectional view along the line XLIII-XLIII shown in Figure 41. Figure 44 is a cross-sectional view along the line XLIV-XLIV shown in Figure 41. Figure 45 is a cross-sectional view along the line XLV-XLV shown in Figure 41. Figure 46 is a cross-sectional view along the line XLVI-XLVI shown in Figure 41. Figure 47 is a cross-sectional view along the line XLVII-XLVII shown in Figure 42. Figure 48 is an enlarged cross-sectional view of the gate structure shown in Figure 43. Figure 49 is an enlarged cross-sectional view of the gate structure shown in Figure 44. Figure 50 is a cross-sectional perspective view showing the first main part of the active region shown in Figure 40. Figure 51 is a cross-sectional perspective view showing the second main part of the active region shown in Figure 40. Figure 52 is a cross-sectional perspective view showing a modified example of the gate structure. Figure 53 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices. Figure 54A is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54B is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54C is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54D is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process.Figure 54E is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54F is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54G is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54H is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54I is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54J is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54K is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54L is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54M is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54N is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54O is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54P is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54Q is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 54R is a cross-sectional view showing one step in an example of a semiconductor device manufacturing process. Figure 55A is a cross-sectional view showing one step in an example of a via electrode and source electrode manufacturing process. Figure 55B is a cross-sectional view showing one step in an example of the manufacturing process for via electrodes and source electrodes. Figure 55C is a cross-sectional view showing one step in an example of the manufacturing process for via electrodes and source electrodes. Figure 55D is a cross-sectional view showing one step in an example of the manufacturing process for via electrodes and source electrodes. Figure 55E is a cross-sectional view showing one step in an example of the manufacturing process for via electrodes and source electrodes. Figure 56 is a cross-sectional perspective view showing a first modified example applied to a semiconductor device according to the first to sixth embodiments. Figure 57 is a cross-sectional perspective view showing a second modified example applied to a semiconductor device according to the first to sixth embodiments. Figure 58 is a cross-sectional perspective view showing a third modified example applied to a semiconductor device according to the first to sixth embodiments. Figure 59 is a cross-sectional perspective view showing a fourth modified example applied to a semiconductor device according to the first to sixth embodiments.

[0021] [Detailed Explanation] The specific form is described in detail below with reference to the attached drawings. The attached drawings are all schematic diagrams and are not strictly accurate; relative positions, scales, ratios, angles, etc., do not necessarily match. Corresponding structures in the attached drawings are given the same reference numerals, and redundant explanations are omitted or simplified. For structures whose explanations are omitted or simplified, the explanation given before the omission or simplification applies.

[0022] In this specification, open language terms such as "including" and "having" are described as encompassing closed language terms such as "consisting of." In this specification, "substantially" includes not only numerical values ​​(forms) that are equal to the numerical value (form) being compared, but also numerical errors (form errors) within a range of ±10% based on the numerical value (form) being compared.

[0023] This specification uses terms such as "First," "Second," and "Third," but these are symbols attached to the names of each structure to clarify the order of explanation, and are not intended to limit the names of each structure.

[0024] In this specification, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may be referred to as the "first conductivity type" and "n-type" as the "second conductivity type."

[0025] "P-type" is a conductivity type derived from trivalent elements, while "n-type" is a conductivity type derived from pentavalent elements. Trivalent elements are at least one of boron, aluminum, gallium, and indium. Pentavalent elements are at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0026] Figure 1 is a plan view showing a semiconductor device 1A according to the first embodiment. Figure 2 is a cross-sectional view taken along the line II-II shown in Figure 1. Figure 3 is a plan view showing an example layout of the first main surface 3 shown in Figure 2. Figure 4 is an enlarged plan view showing the inner part of the active region 8 shown in Figure 3. Figure 5 is an enlarged plan view showing the peripheral part of the active region 8 shown in Figure 3.

[0027] Figure 6 is a cross-sectional view along the line VI-VI shown in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII shown in Figure 4. Figure 8 is a cross-sectional view along the line VIII-VIII shown in Figure 4. Figure 9 is a cross-sectional view along the line IX-IX shown in Figure 4. Figure 10 is a cross-sectional view along the line XX shown in Figure 5.

[0028] Figure 11 is an enlarged cross-sectional view of the gate structure 15 shown in Figure 6. Figure 12 is an enlarged cross-sectional view of the gate structure 15 shown in Figure 7. Figure 13 is a further enlarged cross-sectional view of the source opening 56 shown in Figure 11. Figures 14 to 17 are cross-sectional perspective views showing the first to fourth main parts of the active region 8. Figure 18 is a horizontal cross-sectional view along the line XVIII-XVIII shown in Figure 6. Figure 19 is a horizontal cross-sectional view along the line XIX-XIX shown in Figure 6.

[0029] Referring to Figures 1 to 19, semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure (functional device). The transistor structure Tr has a trench gate type vertical structure.

[0030] The semiconductor device 1A includes a chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). In this embodiment, the chip 2 includes a single crystal of a wide-bandgap semiconductor. In other words, the semiconductor device 1A is a "wide-bandgap semiconductor device". The chip 2 may also be referred to as a "semiconductor chip," "wide-bandgap semiconductor chip," etc.

[0031] Wide-bandgap semiconductors are semiconductors that have a bandgap greater than that of silicon (Si). Examples of wide-bandgap semiconductors include gallium nitride (GaN), silicon carbide (SiC), and diamond (C). In this configuration, chip 2 is a "SiC chip" containing a hexagonal SiC single crystal. In other words, semiconductor device 1A is a "SiC semiconductor device".

[0032] Hexagonal SiC single crystals have multiple polytypes, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, an example is shown in which chip 2 contains a 4H-SiC single crystal, but chip 2 may contain other polytypes. Of course, chip 2 may also contain cubic or polycrystalline materials. For example, chip 2 may contain a 3C (Cubic)-SiC single crystal or a 3C-SiC polycrystalline material.

[0033] The chip 2 includes a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connected to the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view viewed from the thickness direction Z of the chip 2 (hereinafter simply referred to as "plan view"). The thickness direction Z is also a normal direction (vertical direction) with respect to the first main surface 3 and the second main surface 4.

[0034] The first main surface 3 and the second main surface 4 are formed by the c-plane of a SiC single crystal. The first main surface 3 may be formed by a silicon surface ((0001) plane) of the SiC single crystal, and the second main surface 4 may be formed by a carbon surface ((000-1) plane) of the SiC single crystal.

[0035] The first side surface 5A extends in a first direction X. The second side surface 5B is connected to the first side surface 5A and extends in a second direction Y that intersects (specifically, is orthogonal to) the first direction X. The third side surface 5C is connected to the second side surface 5B and extends in the first direction X. The fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C and extends in the second direction Y.

[0036] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. The first direction X may be the a-axis direction and the second direction Y may be the m-axis direction. The first direction X may be a direction intersecting both the a-axis direction and the m-axis direction, and the second direction Y may be a direction intersecting both the a-axis direction and the m-axis direction.

[0037] Hereinafter, a direction extending along the first main surface 3 may be referred to as a "horizontal direction". The horizontal direction is a direction along the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is orthogonal to the thickness direction Z.

[0038] The chip 2 (first main surface 3 and second main surface 4) has an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the thickness direction Z (vertical line) toward the off-direction by the off-angle. The off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y). The off-direction may be the m-axis direction of the SiC single crystal.

[0039] The off-angle may be greater than 0° and not greater than 10°. The off-angle may have a value belonging to at least one of the ranges of greater than 0° and not greater than 1°, 1° or more and not greater than 2.5°, 2.5° or more and not greater than 5°, 5° or more and not greater than 7.5°, and 7.5° or more and not greater than 10°.

[0040] The off-angle is preferably not greater than 5°. The off-angle is particularly preferably 2° or more and not greater than 4.5°. The off-angle is typically set in a range of 4°±0.1°. This specification does not exclude an embodiment where the off-angle is 0° (that is, an embodiment where the first main surface 3 is a just plane with respect to the c-plane).

[0041] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in a region on the second main surface 4 side within the chip 2. The first semiconductor layer 6 may also be referred to as a "first layer (region)", a "drain layer (region)", or the like. The first semiconductor layer 6 extends in a layered manner along the second main surface 4, and forms the second main surface 4 and the first to fourth side surfaces 5A to 5D.

[0042] The first semiconductor layer 6 has 1×10 １８ cm －３ -3 or more and 1×10 ２１ cm －３ -3 or less n-type impurity concentration. The n-type impurity concentration of the first semiconductor layer 6 may be substantially constant in the thickness direction Z. The n-type impurity concentration of the first semiconductor layer 6 may be adjusted by a single type of pentavalent element. It is preferable that the first semiconductor layer 6 contains a pentavalent element other than phosphorus. In the present embodiment, the concentration of the first semiconductor layer 6 is adjusted by nitrogen as the pentavalent element.

[0043] The first semiconductor layer 6 includes a single crystal of a wide-bandgap semiconductor. In this embodiment, the first semiconductor layer 6 is a semiconductor substrate (SiC substrate) containing a hexagonal SiC single crystal. The first semiconductor layer 6 includes a 4H-SiC single crystal and has the aforementioned off-direction and off-angle. Of course, the first semiconductor layer 6 may be made of other polytypes. The first semiconductor layer 6 may be made of a 3C-SiC polycrystal.

[0044] The first semiconductor layer 6 may have a thickness greater than 0 μm and 500 μm or less. The thickness of the first semiconductor layer 6 may have a value that falls within at least one of the following ranges: greater than 0 μm and 10 μm or less, 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, 350 μm or more and 400 μm or more and 400 μm or more and 450 μm or more and 500 μm or less.

[0045] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in the region on the first main surface 3 side relative to the first semiconductor layer 6 within the chip 2. The second semiconductor layer 7 may also be referred to as the "second layer (region)," "drain layer (region)," "drift layer (region)," etc. The second semiconductor layer 7 has an n-type impurity concentration lower than that of the first semiconductor layer 6. The n-type impurity concentration of the second semiconductor layer 7 may be approximately constant in the thickness direction Z.

[0046] The second semiconductor layer 7 is stacked on top of the first semiconductor layer 6. The second semiconductor layer 7 extends in layers along the first main surface 3 (first semiconductor layer 6), forming the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0047] The second semiconductor layer 7 contains a single crystal of a wide-bandgap semiconductor. In this embodiment, the second semiconductor layer 7 is a semiconductor layer (SiC layer) containing a hexagonal SiC single crystal. In this embodiment, the second semiconductor layer 7 consists of an epitaxial layer containing a 4H-SiC single crystal (hexagonal) and has the aforementioned off-direction and off-angle. Of course, the second semiconductor layer 7 may have a polytype different from that of the first semiconductor layer 6.

[0048] The second semiconductor layer 7 has a thickness less than the thickness of the first semiconductor layer 6. The thickness of the second semiconductor layer 7 may be greater than 0 μm and 25 μm or less. The thickness of the second semiconductor layer 7 may be a value that falls within at least one of the following ranges: greater than 0 μm and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, 12.5 μm or more and 15 μm or less, 15 μm or more and 17.5 μm or less, 17.5 μm or more and 20 μm or less, 20 μm or more and 22.5 μm or less, and 22.5 μm or more and 25 μm or less.

[0049] The semiconductor device 1A includes an active region 8 set on the first main surface 3. The active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated. The active region 8 is set in the inner part of the first main surface 3, spaced apart from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). In a plan view, the active region 8 is set as a polygonal shape with four sides parallel to the periphery of the first main surface 3 (in this form, a rectangular shape with a concave recess along the center of the first side surface 5A).

[0050] The ratio of the surface area of ​​the active region 8 to the surface area of ​​the first main surface 3 (area ratio) may be 0.5 or more and less than 1. The area ratio may have a value that falls within at least one of the following ranges: 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, 0.9 or more and 0.95 or less, and 0.95 or more and less than 1.

[0051] The semiconductor device 1A includes an outer region 9 set outside the active region 8 on the first main surface 3. The outer region 9 is a region that does not include the device structure (transistor structure Tr). The outer region 9 is set at the periphery of the first main surface 3. The outer region 9 is provided in the region between the periphery of the first main surface 3 and the active region 8. In a plan view, the outer region 9 extends in a band shape along the active region 8 and is set in a polygonal ring (a quadrilateral ring in this embodiment) that surrounds the active region 8.

[0052] The semiconductor device 1A includes a p-type body region 10 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The body region 10 may also be referred to as the "impurity region," "surface region," etc. A source potential may be applied to the body region 10. The source potential may be a reference potential that serves as the basis for circuit operation. The reference potential may also be the ground potential.

[0053] The body region 10 is formed in the active region 8, spaced apart from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3, and is not formed in the outer region 9. In this configuration, the body region 10 is formed across the entire area of ​​the active region 8. The body region 10 is formed on the surface layer of the first main surface 3 and extends in layers along the first main surface 3. The body region 10 replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0054] The body region 10 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The body region 10 may also be formed with a gap from the depth position of the middle part of the second semiconductor layer 7 toward the first main surface 3.

[0055] The body region 10 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode (body diode) that includes the second semiconductor layer 7 as the cathode region and the body region 10 as the anode region.

[0056] The semiconductor device 1A includes a plurality of trench-type (trench electrode type) gate structures 15 formed in the inner portion (active region 8) of the first main surface 3. The gate structures 15 may also be referred to as "trench structures," "trench gate structures," etc. A gate potential (gate signal) is applied to the plurality of gate structures 15 as a control potential.

[0057] Multiple gate structures 15 are formed in the active region 8 at intervals from the periphery of the first main surface 3, but not in the outer region 9. In a plan view, the multiple gate structures 15 each extend in a strip-like manner in the first direction X (= m-axis direction) and are arranged at intervals in the second direction Y (= a-axis direction). In a plan view, the multiple gate structures 15 are arranged in a stripe-like manner extending in the first direction X. The extension directions of the multiple gate structures 15 intersect (specifically, are perpendicular to) the off-direction of the SiC single crystal.

[0058] The longer sides of the multiple gate structures 15 are formed by the a-plane ((11-20) plane) of the SiC single crystal, and the shorter sides of the multiple gate structures 15 are formed by the m-plane ((1-100) plane) of the SiC single crystal. Depending on the extension direction of the multiple gate structures 15, the longer sides may be formed by the m-plane and the shorter sides may be formed by the a-plane.

[0059] The bottom walls of the multiple gate structures 15 are formed by the c-planes (Si planes) of the SiC single crystal. The bottom walls of the multiple gate structures 15 may extend substantially flat along the horizontal direction. The bottom walls of the multiple gate structures 15 may be curved in an arc toward the second main surface 4.

[0060] The gate structure 15 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. The width of the gate structure 15 is preferably 1.5 μm or less.

[0061] In this configuration, the multiple gate structures 15 are arranged at intervals greater than the width of each gate structure 15. Of course, the spacing between the gate structures 15 may be less than the width of each gate structure 15.

[0062] The spacing of the gate structures 15 may be greater than 0 μm and less than or equal to 3 μm. The spacing of the gate structures 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. Preferably, the spacing of the gate structures 15 is 2 μm or less.

[0063] The multiple gate structures 15 penetrate the body region 10 and are formed at intervals from the bottom of the second semiconductor layer 7 (first semiconductor layer 6) toward the first main surface 3. The side walls of the multiple gate structures 15, together with the first main surface 3, define the obliquely inclined open ends. The open ends of the multiple gate structures 15 may be curved in an arc shape (circular arc shape).

[0064] The multiple gate structures 15 are formed substantially perpendicular to the first main surface 3. The multiple gate structures 15 may be formed in a tapered shape toward the bottom of the second semiconductor layer 7. The inclination angle (absolute value) of the side walls (long sides) of the gate structures 15 with respect to the horizontal plane may be 85° or more and 95° or less.

[0065] The inclination angle may have a value that falls within at least one of the following ranges: 85° to 87.5°, 87.5° to 90°, 90° to 92.5°, and 92.5° to 95°. Preferably, the inclination angle is 87° to 93°.

[0066] The gate structure 15 may have a depth greater than 0 μm and less than or equal to 3 μm. The depth of the gate structure 15 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm. Preferably, the depth of the gate structure 15 is 2 μm or less.

[0067] The gate structure 15 may have an aspect ratio of 1 to 3. The aspect ratio of the gate structure 15 is the ratio of the depth of the gate structure 15 to the width of the gate structure 15. The aspect ratio may have a value that falls within at least one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, and 2.5 to 3.

[0068] The multiple gate structures 15 each include a trench 16, an insulating film 17, and an embedded electrode 18. The trench 16 may be referred to as a "gate trench," the insulating film 17 as a "gate insulating film," and the embedded electrode 18 as a "gate embedded electrode." The trench 16 is formed on the first main surface 3 and demarcates the wall surfaces (side walls and bottom walls) of the gate structure 15.

[0069] The insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The insulating film 17 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The insulating film 17 may include a silicon oxide film containing oxides other than the oxide of the chip 2.

[0070] The insulating film 17 coats the walls (side walls and bottom walls) of the trench 16 in a film-like manner. The thickness of the insulating film 17 covering the bottom wall of the trench 16 may be greater than the thickness of the insulating film 17 covering the side walls of the trench 16.

[0071] The thickness of the insulating film 17 may be greater than 0 nm and 250 nm or less. The thickness of the insulating film 17 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0072] The embedded electrode 18 includes either a metal conductor or a non-metallic conductor, or both. The embedded electrode 18 may also include conductive polysilicon. In this case, the embedded electrode 18 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. It is preferable that the embedded electrode 18 is made of n-type conductive polysilicon.

[0073] The embedded electrode 18 is embedded in the trench 16 via an insulating film 17. The embedded electrode 18 has an electrode surface located on the bottom wall side of the trench 16 with respect to the height position of the first main surface 3. The electrode surface is located on the first main surface 3 side with respect to the depth position of the middle part of the trench 16. The electrode surface may also be located on the bottom wall side of the trench 16 with respect to the depth position of the middle part of the trench 16. The electrode surface may have a recess facing the bottom wall side.

[0074] The semiconductor device 1A includes a plurality of p-type well regions 20 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The well regions 20 may also be referred to as "impurity regions," "gate well regions," etc. The well regions 20 have a p-type impurity concentration higher than that of the body region 10. Source potentials are applied to the plurality of well regions 20.

[0075] Multiple well regions 20 are formed in the active region 8, spaced apart from the periphery of the first main surface 3, but not in the outer region 9. Multiple well regions 20 are formed within the second semiconductor layer 7, spaced apart from the first main surface 3 and the bottom of the second semiconductor layer 7, and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7. Multiple well regions 20 replace the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0076] The multiple well regions 20 each extend in a strip-like manner in the first direction X when viewed from above, and are arranged with gaps in the second direction Y. The multiple well regions 20 are arranged in a stripe-like manner extending in the first direction X when viewed from above. The extension directions of the multiple well regions 20 intersect (specifically orthogonal to) the off-direction of the SiC single crystal.

[0077] Multiple well regions 20 are formed in the regions below (specifically directly beneath) the multiple gate structures 15, and overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z. In other words, the multiple well regions 20 extend in a strip-like manner in the first direction X, following the extension direction of the corresponding gate structure 15 in a plan view. The multiple well regions 20 mitigate the electric field for the multiple gate structures 15 from the bottom wall side.

[0078] With respect to the first direction X, the ends of the multiple well regions 20 may be located inward or outward from the ends of the multiple gate structures 15. Of course, the multiple well regions 20 may be formed at intervals in the first direction X in a one-to-many correspondence with respect to one gate structure 15. In this case, the multiple well regions 20 may extend in a strip-like shape in the first direction X.

[0079] With respect to the second direction Y, in this embodiment, each of the multiple well regions 20 is formed to be wider than the corresponding gate structure 15. That is, each of the multiple well regions 20 has a width greater than the width of the corresponding gate structure 15 and protrudes from the side walls of the corresponding gate structure 15 to both sides in the second direction Y.

[0080] The amount of overhang of the well region 20 relative to the side wall of the gate structure 15 may be greater than 0 μm and 0.5 μm or less. The amount of overhang may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.2 μm or less, 0.2 μm or more and 0.3 μm or less, 0.3 μm or more and 0.4 μm or less, and 0.4 μm or more and 0.5 μm or less.

[0081] Each of the multiple well regions 20 has an upper end located on the bottom wall side of the corresponding gate structure 15, and a bottom located on the bottom side of the second semiconductor layer 7. The upper ends of the multiple well regions 20 are formed with a gap between the bottom of the body region 10 and the bottom wall side of the corresponding gate structure 15.

[0082] The upper ends of the multiple well regions 20 are located on the bottom wall side of the corresponding gate structure 15 with respect to the depth position of the intermediate part of the corresponding gate structure 15. The upper ends of the multiple well regions 20 are connected to the bottom wall of the corresponding gate structure 15 and face the embedded electrode 18 via the insulating film 17. The upper ends of the multiple well regions 20 are located near the corners of the bottom wall of the corresponding gate structure 15.

[0083] The upper ends of the multiple well regions 20 may have portions that run along the lower end of the side wall of the corresponding gate structure 15 via the vicinity of the corner of the bottom wall of the corresponding gate structure 15. In other words, the multiple well regions 20 may face the embedded electrode 18 via the insulating film 17 at the side wall of the corresponding gate structure 15.

[0084] The depth of the well region 20 relative to the bottom wall of the gate structure 15 is less than the depth of the gate structure 15 relative to the first main surface 3. The ratio of the depth of the well region 20 to the depth of the gate structure 15 may be greater than 0 and 0.5 or less.

[0085] The depth ratio may be greater than 0 and less than or equal to 0.1, between 0.1 and 0.2, between 0.2 and 0.3, between 0.3 and 0.4, or between 0.4 and 0.5. Of course, the depth of the well region 20 may be greater than the depth of the gate structure 15.

[0086] The depth of the well region 20 may be greater than 0 μm and less than or equal to 1 μm. The depth of the well region 20 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.1 μm, between 0.1 μm and 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, and between 0.75 μm and 1 μm.

[0087] The semiconductor device 1A includes a plurality of n-type first pillar regions 21 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The first pillar regions 21 may also be referred to as "first regions," "first impurity regions," "first column regions," etc. The plurality of first pillar regions 21 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0088] The multiple first pillar regions 21 may be considered as a part (a component) of the second semiconductor layer 7, as a high-concentration region of the second semiconductor layer 7. The n-type impurity concentration in the multiple first pillar regions 21 is lower than the p-type impurity concentration in the multiple well regions 20. The n-type impurity concentration in the multiple first pillar regions 21 may be higher or lower than the p-type impurity concentration in the body region 10.

[0089] Multiple first pillar regions 21 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 9. Of course, multiple first pillar regions 21 may also be formed in the outer region 9 within the second semiconductor layer 7. In this case, multiple first pillar regions 21 may be exposed from at least one of the first to fourth side surfaces 5A to 5D (for example, the first side surface 5A and the third side surface 5C).

[0090] The multiple first pillar regions 21 are arranged at intervals in the first direction X (= m-axis direction) in a plan view, and each extends in a strip-like manner in the second direction Y (= a-axis direction). In other words, the multiple first pillar regions 21 are arranged in a stripe-like manner extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 15. The direction of extension of the multiple first pillar regions 21 coincides with the off-direction of the SiC single crystal.

[0091] The first pillar region 21 may have a width greater than 0 μm and less than or equal to 3 μm. The width of the first pillar region 21 may be greater than or less than the width of the gate structure 15. The width of the first pillar region 21 may be greater than or less than the spacing of the gate structure 15.

[0092] The width of the first pillar region 21 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0093] Multiple first pillar regions 21 may be formed at intervals greater than 0 μm and 3 μm or less. The spacing between the first pillar regions 21 may be greater than or less than the width of the first pillar regions 21. The spacing between the first pillar regions 21 may be greater than or less than the width of the gate structure 15. The spacing between the first pillar regions 21 may be greater than or less than the spacing of the gate structure 15.

[0094] The spacing of the first pillar region 21 may have a value that is greater than 0 μm and falls within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less.

[0095] Multiple first pillar regions 21 are formed in a region below the bottom of the body region 10 and extend in a vertical columnar shape along the thickness direction Z. Multiple first pillar regions 21 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0096] In this configuration, each of the multiple first pillar regions 21 is formed by a single n-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). The axial channel is a region (channel) with relatively wide interatomic distances in the SiC single crystal and is surrounded by rows of atoms that constitute the crystal axis extending in the stacking direction. In other words, the axial channel is a region in which a region with sparse interatomic distances (atomic density) in the horizontal direction extends in the thickness direction Z.

[0097] The axial channel is preferably a region surrounded by atomic rows along the low-index crystal axis among the crystal axes. The low-index crystal axis is a crystal axis in which the absolute values ​​of "a1", "a2", "a3", and "c" are all between 0 and 2 (preferably 1) with respect to Miller indices (a1, a2, a3, c).

[0098] In this configuration, the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. In other words, the multiple first pillar regions 21 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. In other words, the multiple first pillar regions 21 are tilted by the off-angle from the vertical axis in the off-direction.

[0099] In this configuration, the extension direction (a-axis direction) of the multiple first pillar regions 21 coincides with the off-direction of the off-angle. Therefore, the multiple first pillar regions 21 extend almost perpendicularly in a cross-sectional view along the direction perpendicular to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0100] The first pillar region 21 has a depth greater than the depth of the gate structure 15. The depth of the first pillar region 21 is less than the thickness of the second semiconductor layer 7. The depth of the first pillar region 21 may be greater than 0 μm and 5 μm or less.

[0101] The depth of the first pillar region 21 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. Preferably, the depth of the first pillar region 21 is 1 μm or more.

[0102] The first pillar region 21 may have an aspect ratio of 1 or more and 10 or less. The aspect ratio of the first pillar region 21 is the ratio of the depth of the first pillar region 21 to the width of the first pillar region 21.

[0103] The aspect ratio of the first pillar region 21 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0104] Each of the multiple first pillar regions 21 has a first upper region 21U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 15, and a first lower region 21L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 15. The n-type impurity concentration in the multiple first pillar regions 21 is lower than the p-type impurity concentration in the multiple well regions 20 in both the first upper region 21U and the first lower region 21L.

[0105] The first upper region 21U is interposed in the region between the multiple gate structures 15 and extends in the second direction Y. The first upper region 21U is connected to the side walls of the multiple gate structures 15 and faces the embedded electrode 18 via the insulating film 17 of the multiple gate structures 15. The first upper region 21U has a first upper end connected to the body region 10.

[0106] In this embodiment, the first upper region 21U has a first constriction that is narrowed in the first direction X, and a first bulge that extends in the first direction X. The first constriction is formed in the thickness range between the bottom walls of the multiple gate structures 15 and the bottom of the body region 10, and is a portion in which the width in the first direction X gradually decreases toward the body region 10.

[0107] The first bulge is formed in the thickness range between the bottom of the body region 10 and the first constriction, and is a portion in which the width in the first direction X gradually increases toward the bottom of the body region 10. In this embodiment, the first bulge forms a first upper end connected to the body region 10.

[0108] The first lower region 21L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 15, and intersects with the multiple gate structures 15 in three dimensions. In other words, the multiple first pillar regions 21 (first lower region 21L) are formed in the region directly below the gate structures 15, spaced apart in the first direction X following the direction of extension of the gate structures 15.

[0109] In this configuration, the first lower region 21L intersects with and connects to multiple well regions 20 in the region directly below the multiple gate structures 15. At the first intersection Cr1 of the well region 20 and the first lower region 21L (see Figure 18), the p-type impurity concentration in the well region 20 is offset (reduced) by the amount of the n-type impurity concentration (pentavalent element concentration) in the first lower region 21L.

[0110] The first lower region 21L has a first bottom portion 21B located below the depth position of the bottom walls of the multiple gate structures 15. The first bottom portion 21B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 15, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 15.

[0111] The first bottom portion 21B is located below the bottoms of the multiple well regions 20. The first bottom portion 21B has a portion that extends in the second direction Y in the region directly below the multiple well regions 20, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 20. The first bottom portion 21B faces the bottom walls of the multiple gate structures 15 via the multiple well regions 20.

[0112] The distance between the bottom of the well region 20 and the first bottom 21B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 21B. The distance between the bottom wall of the gate structure 15 and the first bottom 21B is less than the distance between the bottom of the second semiconductor layer 7 and the first bottom 21B. Of course, the distance between the bottom of the well region 20 (the bottom wall of the gate structure 15) and the first bottom 21B may be greater than the distance between the bottom of the second semiconductor layer 7 and the first bottom 21B.

[0113] In this embodiment, the distance between the bottom wall of the gate structure 15 and the first bottom 21B is smaller than the depth of the gate structure 15. The distance between the bottom wall of the gate structure 15 and the first bottom 21B may be larger than the depth of the gate structure 15.

[0114] The first pillar region 21 does not necessarily have to include both the first constriction and the first bulge simultaneously. The first pillar region 21 may have the first constriction but not the first bulge. In this case, the first constriction may be connected to the body region 10 as the first upper end. The first pillar region 21 may not have the first constriction but have the first bulge. In this case, the first bulge may be connected to the body region 10 as the first upper end.

[0115] The first pillar region 21 does not necessarily have both a first constriction and a first bulge. In this case, the first pillar region 21 may extend perpendicularly in the thickness direction Z. Of course, the first pillar region 21 may be formed in a tapered or tapered shape in the thickness direction Z.

[0116] The semiconductor device 1A includes a plurality of p-type second pillar regions 22 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The second pillar regions 22 may also be referred to as "second regions," "second impurity regions," "second column regions," etc.

[0117] Multiple second pillar regions 22 have a p-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. The p-type impurity concentration of the multiple second pillar regions 22 is lower than the p-type impurity concentration of the multiple well regions 20. The p-type impurity concentration of the multiple second pillar regions 22 may be higher or lower than the p-type impurity concentration of the body region 10.

[0118] Multiple second pillar regions 22 are formed in the active region 8 at intervals from the periphery of the first main surface 3, and are not formed in the outer region 9. Of course, multiple second pillar regions 22 may also be formed in the outer region 9 within the second semiconductor layer 7. In this case, multiple second pillar regions 22 may be exposed from at least one of the first to fourth side surfaces 5A to 5D (for example, the first side surface 5A and the third side surface 5C).

[0119] The multiple second pillar regions 22 are arranged at intervals in the first direction X (= m-axis direction) in a plan view, and each extends in a strip-like manner in the second direction Y (= a-axis direction). In other words, the multiple second pillar regions 22 are arranged in a stripe-like manner extending in the second direction Y in a plan view, and intersect (specifically orthogonally) with the multiple gate structures 15. The direction of extension of the multiple second pillar regions 22 coincides with the off-direction of the SiC single crystal.

[0120] Multiple second pillar regions 22 are formed alternately with multiple first pillar regions 21 in the first direction X, and form pn junctions with the multiple first pillar regions 21. As a result, a bipolar diode is formed that includes multiple first pillar regions 21 as cathode regions and multiple second pillar regions 22 as anode regions.

[0121] The multiple second pillar regions 22 have a charge balance with respect to the multiple first pillar regions 21 and constitute a superjunction structure with the multiple first pillar regions 21. Charge balance means that the depletion layers extending from the multiple second pillar regions 22 are connected within the multiple first pillar regions 21.

[0122] The second pillar region 22 has a width corresponding to the spacing of the first pillar region 21. The width of the second pillar region 22 may be approximately equal to the width of the first pillar region 21. The width of the second pillar region 22 may be greater than or less than the width of the first pillar region 21. The width of the second pillar region 22 may be greater than or less than the width of the gate structure 15. The width of the second pillar region 22 may be greater than or less than the spacing of the gate structure 15.

[0123] The width of the second pillar region 22 may be greater than 0 μm and less than or equal to 3 μm. The width of the second pillar region 22 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0124] Multiple second pillar regions 22 are formed at intervals corresponding to the width of the first pillar region 21. The spacing of the second pillar regions 22 may be approximately equal to the width of the second pillar region 22. The spacing of the second pillar regions 22 may be greater than or less than the width of the second pillar region 22.

[0125] The spacing of the second pillar region 22 may be approximately equal to the spacing of the first pillar region 21. The spacing of the second pillar region 22 may be larger or smaller than the spacing of the first pillar region 21. The spacing of the second pillar region 22 may be larger or smaller than the width of the gate structure 15. The spacing of the second pillar region 22 may be larger or smaller than the spacing of the gate structure 15.

[0126] The spacing of the second pillar region 22 may be greater than 0 μm and less than or equal to 3 μm. The spacing of the second pillar region 22 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than or equal to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, and 2.5 μm to 3 μm.

[0127] Multiple second pillar regions 22 are formed in a region below the bottom of the body region 10 and extend in a vertical columnar shape along the thickness direction Z. Multiple second pillar regions 22 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3 and face the first semiconductor layer 6 via a portion of the second semiconductor layer 7.

[0128] In this configuration, each of the multiple second pillar regions 22 is formed by a single p-type impurity region extending along the axial channel of the SiC single crystal (second semiconductor layer 7). In other words, the multiple second pillar regions 22 extend along the c-axis as the axial channel and have the aforementioned off-direction and off-angle. In other words, the multiple second pillar regions 22 are inclined by the off-angle from the vertical axis in the off-direction.

[0129] In this configuration, the extension direction (a-axis direction) of the multiple second pillar regions 22 coincides with the off-direction of the off-angle. Therefore, the multiple second pillar regions 22 extend almost perpendicularly in a cross-sectional view along the direction orthogonal to the off-direction (first direction X = a-axis direction) (second direction Y = m-axis direction).

[0130] The second pillar region 22 has a depth greater than the depth of the gate structure 15. The depth of the second pillar region 22 is less than the thickness of the second semiconductor layer 7. The depth of the second pillar region 22 may be approximately equal to the depth of the first pillar region 21.

[0131] The depth of the second pillar region 22 may be greater than the depth of the first pillar region 21. The depth of the second pillar region 22 may be less than the depth of the first pillar region 21. The depth of the second pillar region 22 may be greater than 0 μm and 5 μm or less.

[0132] The depth of the second pillar region 22 may be greater than 0 μm and fall within at least one of the following ranges: 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or more and 5 μm or less. Preferably, the depth of the second pillar region 22 is 1 μm or more.

[0133] The second pillar region 22 may have an aspect ratio approximately equal to that of the first pillar region 21. The aspect ratio of the second pillar region 22 is the ratio of the depth of the second pillar region 22 to its width. The aspect ratio of the second pillar region 22 may be greater than or less than that of the first pillar region 21.

[0134] The aspect ratio of the second pillar region 22 may be between 1 and 10. The aspect ratio of the second pillar region 22 may have a value that falls within at least one of the following ranges: 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to 6, 6 to 7, 7 to 8, 8 to 9, and 9 to 10.

[0135] Each of the multiple second pillar regions 22 has a second upper region 22U located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 15, and a second lower region 22L located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 15. The p-type impurity concentration in the multiple second pillar regions 22 is lower than the p-type impurity concentration in the multiple well regions 20 in both the second upper region 22U and the second lower region 22L.

[0136] The second upper region 22U is interposed in the region between the multiple gate structures 15 and extends in the second direction Y. The second upper region 22U is connected to the side walls of the multiple gate structures 15 and faces the embedded electrode 18 via the insulating film 17 of the multiple gate structures 15. The second upper region 22U has a second upper end connected to the body region 10.

[0137] The second upper region 22U is located between the multiple gate structures 15 and forms a pn junction with the first upper region 21U of the multiple first pillar regions 21. The second upper region 22U has a charge balance with the first upper region 21U in the region between the multiple gate structures 15 and forms a superjunction structure with the first upper region 21U.

[0138] In this embodiment, the second upper region 22U has a second bulge that expands in the first direction X and a second constriction that narrows in the first direction X. The second bulge is formed along the first constriction of the first pillar region 21 in a thickness range between the bottom walls of the multiple gate structures 15 and the bottom of the body region 10, and is a portion in which the width in the first direction X gradually increases toward the body region 10.

[0139] The second constriction is formed along the first bulge of the first pillar region 21 in the region between the body region 10 and the second bulge, and is a portion in which the width in the first direction X gradually decreases toward the bottom of the body region 10. In other words, the irregularities of the second upper region 22U interlock with the irregularities of the first upper region 21U. In this embodiment, the second constriction forms a second upper end connected to the body region 10.

[0140] The second lower region 22L extends in the second direction Y in the region below the bottom walls of the multiple gate structures 15 and intersects with the multiple gate structures 15 in three dimensions. In other words, the multiple second pillar regions 22 (second lower region 22L) are formed in the region directly below the gate structures 15, spaced apart in the first direction X following the direction of extension of the gate structures 15. The multiple second pillar regions 22 are formed alternately with the multiple first pillar regions 21 in the region directly below the gate structures 15 in the first direction X.

[0141] In this configuration, the second lower region 22L intersects with and connects to the multiple well regions 20 in the region directly below the multiple gate structures 15. In other words, the multiple second pillar regions 22 are interposed between the body region 10 and the multiple well regions 20, electrically connecting the multiple well regions 20 to the body region 10. The multiple second pillar regions 22 are electrically interlocked with the body region 10 and the multiple well regions 20.

[0142] In the second intersection Cr2 of the well region 20 and the second lower region 22L (see Figure 18), the p-type impurity concentration in the well region 20 is increased by the amount of the p-type impurity concentration (trivalent element concentration) in the second lower region 22L. In other words, the p-type impurity concentration in the second intersection Cr2 is higher than the p-type impurity concentration in the first intersection Cr1.

[0143] The second lower region 22L forms a pn joint with the first lower region 21L of the multiple first pillar regions 21. Specifically, the second lower region 22L has a portion that forms a pn joint with the first lower region 21L in the region directly below the multiple gate structures 15, and a portion that forms a pn joint with the first lower region 21L outside the region directly below the multiple gate structures 15.

[0144] The second lower region 22L has a portion that forms a pn junction with the first lower region 21L in the region directly below the multiple well regions 20, and a portion that forms a pn junction with the first lower region 21L outside the region directly below the multiple well regions 20. The second lower region 22L has a charge balance with the first lower region 21L and constitutes a superjunction structure with the first lower region 21L.

[0145] The second lower region 22L has a second bottom portion 22B located below the depth position of the bottom walls of the multiple gate structures 15. The second bottom portion 22B has a portion that extends in the second direction Y in the region directly below the multiple gate structures 15, and a portion that extends in the second direction Y outside the region directly below the multiple gate structures 15.

[0146] The second bottom portion 22B is located below the bottoms of the multiple well regions 20. The second bottom portion 22B has a portion that extends in the second direction Y in the region directly below the multiple well regions 20, and a portion that extends in the second direction Y outside the region directly below the multiple well regions 20. The second bottom portion 22B faces the bottom walls of the multiple gate structures 15 via the multiple well regions 20.

[0147] The second bottom 22B may be located in the region directly beneath the multiple gate structures 15 at approximately the same depth as the first bottom 21B of the first pillar region 21. The second bottom 22B may be located below the first bottom 21B (towards the bottom of the second semiconductor layer 7) in the region directly beneath the multiple gate structures 15. The second bottom 22B may be located above the first bottom 21B (towards the bottom wall of the multiple gate structures 15 / towards the bottom of the multiple well regions 20) in the region directly beneath the multiple gate structures 15.

[0148] The distance between the bottom of the well region 20 and the second bottom 22B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 22B. The distance between the bottom wall of the gate structure 15 and the second bottom 22B is less than the distance between the bottom of the second semiconductor layer 7 and the second bottom 22B. Of course, the distance between the bottom of the well region 20 (the bottom wall of the gate structure 15) and the second bottom 22B may be greater than the distance between the bottom of the second semiconductor layer 7 and the second bottom 22B.

[0149] In this embodiment, the distance between the bottom wall of the gate structure 15 and the second bottom 22B is smaller than the depth of the gate structure 15. The distance between the bottom wall of the gate structure 15 and the second bottom 22B may be larger than the depth of the gate structure 15.

[0150] The second pillar region 22 does not necessarily have to include both the second bulge and the second constriction simultaneously. The second pillar region 22 may have the second bulge but not the second constriction. In this case, the second bulge may be connected to the body region 10 as the second upper end. The second pillar region 22 may not have the second bulge but have the second constriction. In this case, the second constriction may be connected to the body region 10 as the second upper end.

[0151] The second pillar region 22 does not necessarily have both a second bulge and a second constriction. In this case, the second pillar region 22 may extend perpendicularly in the thickness direction Z. Of course, the second pillar region 22 may be formed in a tapered or tapered shape in the thickness direction Z.

[0152] Referring to Figures 18 and 19, the semiconductor device 1A includes a p-type mesh region 25 formed within the second semiconductor layer 7 in a horizontal cross-sectional view. The mesh region 25 extends in a mesh-like manner in the first direction X (m-axis direction) and the second direction Y (a-axis direction) along the first main surface 3 at a thickness position spaced apart from the first main surface 3 within the second semiconductor layer 7.

[0153] The mesh region 25 divides the second semiconductor layer 7 into multiple n-type inter-mesh regions 26, which serve as multiple current paths. The mesh region 25 narrows the current when the device is on and improves short-circuit withstand capability. The mesh region 25 is formed in a region below the depth position of the bottom of the body region 10. The mesh region 25 is formed in a region below the bottom walls of the multiple gate structures 15 (trenches 16).

[0154] The mesh region 25 integrally includes a plurality of p-shaped well regions 20 as a plurality of first regions (first stripe regions) extending in a strip shape in the first direction X, and a plurality of p-shaped second pillar regions 22 as a plurality of second regions (second stripe regions) extending in a strip shape in the second direction Y.

[0155] Multiple well regions 20 extend in a stripe-like pattern in the first direction X at thickness positions spaced apart from the first main surface 3 within the second semiconductor layer 7. Each of the multiple well regions 20 is formed in the region below (specifically directly beneath) the multiple gate structures 15, and overlaps with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z.

[0156] Each of the multiple second pillar regions 22 has a p-type impurity concentration lower than that of the multiple well regions 20. The multiple second pillar regions 22 extend in a stripe pattern in the second direction Y within the second semiconductor layer 7 so as to be connected to the multiple well regions 20 in a mesh-like manner, and demarcate the multiple well regions 20 and the multiple inter-mesh regions 26.

[0157] Multiple second pillar regions 22 are connected to multiple well regions 20 in a cross shape. Of course, multiple second pillar regions 22 may also be connected to multiple well regions 20 in a T shape. The second pillar regions 22 may have a width greater than the width of the well regions 20. The width of the second pillar regions 22 may be less than the width of the well regions 20. The width of the second pillar regions 22 may be approximately equal to the width of the well regions 20.

[0158] The multiple second pillar regions 22 extend vertically in the thickness direction Z of the second semiconductor layer 7 in a cross-sectional view, and each has a second upper region 22U (first portion) located above the multiple well regions 20, and a second lower region 22L (second portion) located below the multiple well regions 20. The second bottom portion 22B of the second lower region 22L is located below the bottom portion of the multiple well regions 20.

[0159] Multiple second upper regions 22U are connected to the body region 10, and multiple second lower regions 22L are connected to multiple well regions 20. In other words, the multiple second lower regions 22L form a mesh region 25 with the multiple well regions 20 and demarcate multiple intermesh regions 26. Furthermore, the multiple second upper regions 22U are formed as connection parts that electrically connect the mesh region 25 to the body region 10.

[0160] The multiple intermesh regions 26 are partitioned in a row along the first direction X, following the direction of extension of the multiple well regions 20 (multiple gate structures 15) in a plan view. The multiple intermesh regions 26 are partitioned in a row along the second direction Y, following the direction of extension of the multiple second pillar regions 22 (multiple first pillar regions 21) in a plan view. In other words, the multiple intermesh regions 26 are partitioned in a matrix with spacing in the first direction X and the second direction Y in a plan view.

[0161] In this configuration, the multiple intermesh regions 26 are formed by multiple n-type first pillar regions 21 having an n-type impurity concentration higher than that of the second semiconductor layer 7, and extend in a vertically elongated columnar shape along the thickness direction Z. The multiple intermesh regions 26 form low-resistance current paths having a resistance value lower than that of the second semiconductor layer 7.

[0162] Each of the multiple mesh regions 26 comprises a first upper region 21U (first part) partitioned above the bottom walls of the multiple gate structures 15, and a first lower region 21L (second part) partitioned below the bottom walls of the multiple gate structures 15.

[0163] The first upper region 21U is partitioned by a plurality of gate structures 15 and a plurality of second pillar regions 22 (second upper region 22U). The first lower region 21L is partitioned by a mesh region 25. In other words, the first lower region 21L is partitioned by a plurality of well regions 20 and a plurality of second pillar regions 22 (second lower region 22L).

[0164] Figure 20 is a graph illustrating the n-type impurity concentration in the first pillar region 21. Figure 21 is a graph illustrating the p-type impurity concentration in the second pillar region 22. In Figures 20 and 21, the vertical axis represents the impurity concentration [cm³]. －３ The horizontal axis shows the depth [μm] with the first main surface 3 as the zero point. In Figures 20 and 21, the depth of the gate structure 15 is set to approximately 1.2 μm as an example.

[0165] Figure 20 shows the base concentration CB and the first concentration gradient G1 due to pentavalent elements. Figure 21 shows the base concentration CB, the first concentration gradient G1 due to pentavalent elements, and the second concentration gradient G2 due to trivalent elements. The base concentration CB represents the n-type impurity concentration (pentavalent element concentration) of the second semiconductor layer 7, the first concentration gradient G1 represents the n-type impurity concentration (pentavalent element concentration) of the first pillar region 21, and the second concentration gradient G2 represents the p-type impurity concentration (trivalent element concentration) of the second pillar region 22.

[0166] The base concentration CB in this form is 1 × 10⁻⁶ １６ cm －３ It is set to a certain degree and has a nearly constant concentration gradient in the thickness direction Z. In this form, the base concentration CB is attributable to a single pentavalent element (nitrogen, phosphorus, arsenic, antimony, or bismuth).

[0167] The base concentration CB is preferably attributable to a pentavalent element other than phosphorus. In this form, the base concentration CB is attributable to nitrogen as a pentavalent element. The base concentration CB may also be attributable to two or more pentavalent elements (at least two of nitrogen, phosphorus, arsenic, antimony, and bismuth).

[0168] The first concentration gradient G1 of the first pillar region 21 is formed by imparting a pentavalent element to the second semiconductor layer 7 and consists of a base concentration CB and a first added concentration C1 due to the pentavalent element. Preferably, the first added concentration C1 is due to a pentavalent element different from the pentavalent element of the base concentration CB. In other words, preferably, the first added concentration C1 is due to a pentavalent element other than nitrogen (at least one of phosphorus, arsenic, antimony, and bismuth).

[0169] The first added concentration C1 is preferably due to a single pentavalent element. The pentavalent element of the first added concentration C1 is preferably phosphorus. The first added concentration C1 may also be due to the same type of pentavalent element (nitrogen) as the pentavalent element of the base concentration CB. The first added concentration C1 may also be due to two or more pentavalent elements.

[0170] The first additional concentration C1 (first concentration gradient G1) includes a first gradually increasing portion 31, a first gradual portion 32, and a first gradually decreasing portion 33. The first gradually increasing portion 31 is a portion forming the first upper end portion (first upper region 21U) of the first pillar region 21, and is formed spaced apart from the first main surface 3. The pentavalent element concentration of the first gradually increasing portion 31 increases at a relatively steep rate toward the second main surface 4.

[0171] The first gradually increasing portion 31 may have a depth (thickness) greater than 0 μm and not more than 1 μm. The depth of the first gradually increasing portion 31 may have a value falling within at least one range selected from the group consisting of: greater than 0 μm and not more than 0.1 μm, 0.1 μm or more and not more than 0.25 μm, 0.25 μm or more and not more than 0.5 μm, 0.5 μm or more and not more than 0.75 μm, and 0.75 μm or more and not more than 1 μm. The depth of the first gradually increasing portion 31 is preferably 0.5 μm or less.

[0172] The first gradual portion 32 is formed below the first gradually increasing portion 31 via a concentration transition portion. The concentration transition portion is a portion where the slope of the concentration change rate (for example, the average value per unit depth) changes from positive to zero or negative.

[0173] The first gradual portion 32 is formed in the depth range of the middle portion of the first pillar region 21, and is a portion where the concentration change rate per unit depth is relatively gradual. The first gradual portion 32 forms one or both of the first upper region 21U and the first lower region 21L. In this embodiment, the first gradual portion 32 is formed across the first upper region 21U and the first lower region 21L.

[0174] The first gradual portion 32 maintains an n-type impurity concentration of not less than a constant value in a depth range larger than that of the first gradually increasing portion 31, and forms the main body of the first pillar region 21. The concentration change rate per unit depth of the first gradual portion 32 is smaller than the concentration change rate per unit depth of the first gradually increasing portion 31. In this embodiment, the first gradual portion 32 is 5×10 １６ cm －３ and maintains an n-type impurity concentration of not less than the above value.

[0175] The first slow portion 32 may occupy a depth range of at least 20% to 80% of the depth of the first pillar region 21. The depth range of the first slow portion 32 may be at least one of the following ranges: 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, and 70% to 80%. Preferably, the depth range of the first slow portion 32 is 50% or more.

[0176] The first tapering section 33 is the portion that forms the first bottom 21B (first lower region 21L) of the first pillar region 21. The depth range of the first tapering section 33 is smaller than the depth range of the first slow section 32. The concentration of pentavalent elements in the first tapering section 33 decreases at a relatively steep rate from the first slow section 32 toward the second main surface 4. The concentration decrease rate per unit depth in the first tapering section 33 is greater than the concentration decrease rate per unit depth in the first slow section 32.

[0177] The first tapering section 33 may have a depth (thickness) greater than 0 μm and 1 μm or less. The depth of the first tapering section 33 may be a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less. The depth of the first tapering section 33 is preferably 0.5 μm or less.

[0178] The second concentration gradient G2 in the second pillar region 22 is formed by imparting a trivalent element to the second semiconductor layer 7 and consists of a base concentration CB and a second added concentration C2 due to the trivalent element. The second added concentration C2 is higher than the base concentration CB and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type.

[0179] In this form, the second addition concentration C2 is attributable to a single trivalent element (boron, aluminum, gallium, or indium). In this form, the second addition concentration C2 is attributable to aluminum as a trivalent element. The second addition concentration C2 may be attributable to two or more trivalent elements (at least two of boron, aluminum, gallium, and indium).

[0180] Referring to Figure 21, the second added concentration C2 has a second increasing portion 34, a second slow increasing portion 35, and a second decreasing portion 36. The second increasing portion 34 is the portion that forms the second upper end (second upper region 22U) of the second pillar region 22, and is formed at a distance from the first main surface 3. The concentration of trivalent elements in the second increasing portion 34 increases at a relatively steep rate toward the second main surface 4.

[0181] The second increasing portion 34 may have a depth (thickness) greater than 0 μm and 1 μm or less. The depth of the second increasing portion 34 may be a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less. The depth of the second increasing portion 34 is preferably 0.5 μm or less.

[0182] The second slow-down section 35 is formed below the second increasing section 34 via a concentration transition section. The concentration transition section is the part where the slope of the concentration change rate (for example, the average value per unit depth) changes from positive to zero or negative.

[0183] The second slow-reaction portion 35 is formed in the depth range of the intermediate part of the second pillar region 22 and is a portion in which the rate of change of concentration per unit depth is relatively slow. The second slow-reaction portion 35 forms either or both of the second upper region 22U and the second lower region 22L. In this embodiment, the second slow-reaction portion 35 is formed spanning the second upper region 22U and the second lower region 22L.

[0184] The second slow-intensity section 35 maintains a p-type impurity concentration above a certain value in a depth range larger than that of the second increasing-intensity section 34, and forms the main body of the second pillar region 22. The concentration change rate of the second slow-intensity section 35 per unit depth is smaller than the concentration change rate of the second increasing-intensity section 34 per unit depth. In this configuration, the second slow-intensity section 35 is 5 × 10 １６ cm －３ The above p-type impurity concentrations are maintained.

[0185] The second slow portion 35 may occupy a thickness range of at least 20% to 80% of the depth of the second pillar region 22. The depth range of the second slow portion 35 may be at least one of the following ranges: 20% to 30%, 30% to 40%, 40% to 50%, 50% to 60%, 60% to 70%, and 70% to 80%. The depth range of the second slow portion 35 is preferably 50% or more.

[0186] The second tapering section 36 is the portion that forms the second bottom 22B (second lower region 22L) of the second pillar region 22. The depth range of the second tapering section 36 is smaller than the depth range of the second slow section 35. The concentration of trivalent elements in the second tapering section 36 decreases at a relatively steep rate from the second slow section 35 toward the second main surface 4. The concentration decrease rate per unit depth in the second tapering section 36 is greater than the concentration decrease rate per unit depth in the second slow section 35.

[0187] The second tapering section 36 may have a depth (thickness) greater than 0 μm and 1 μm or less. The depth of the second tapering section 36 may be a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, and 0.75 μm or more and 1 μm or less. The depth of the second tapering section 36 is preferably 0.5 μm or less.

[0188] The second added concentration C2 in the second increasing section 34 is higher than the first added concentration C1 in the first increasing section 31. With respect to the first increasing section 31 and the second increasing section 34, the concentration ratio of the second added concentration C2 to the first added concentration C1 may be greater than 1 and 10 or less. The concentration ratio may be in at least one of the following ranges: greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, and 8 or more and 10 or less.

[0189] The second added concentration C2 of the second slowing portion 35 is higher than the first added concentration C1 of the first slowing portion 32. Specifically, the second added concentration C2 on the second upper region 22U side of the second slowing portion 35 is greater than the first added concentration C1 on the first upper region 21U side of the first slowing portion 32.

[0190] With respect to the first slowing portion 32 and the second slowing portion 35, the concentration ratio of the second added concentration C2 to the first added concentration C1 may be greater than 1 and 10 or less. The concentration ratio may be in at least one of the following ranges: greater than 1 and 2 or less, 2 or more and 4 or less, 4 or more and 6 or less, 6 or more and 8 or less, and 8 or more and 10 or less.

[0191] When trivalent and pentavalent elements are introduced into the second semiconductor layer 7 (SiC), the introduction efficiency of the trivalent elements differs from that of the pentavalent elements. Specifically, while both trivalent and pentavalent elements are captured by the second semiconductor layer 7 (SiC) during ion implantation, the capture probability of trivalent elements in the second semiconductor layer 7 is higher than that of pentavalent elements in the second semiconductor layer 7.

[0192] Therefore, when forming a second pillar region 22 having a depth similar to that of the first pillar region 21, it is necessary to increase the amount of trivalent elements introduced into the second semiconductor layer 7, taking into account the capture rate of trivalent elements by the second semiconductor layer 7. As a result, the concentration of trivalent elements tends to be higher than the concentration of pentavalent elements at relatively shallow positions in the second semiconductor layer 7.

[0193] In this configuration, the second concentration gradient G2 of the second pillar region 22 has a corrected concentration C3 due to pentavalent elements in the second upper region 22U. The corrected concentration C3 is further applied to the base concentration CB and the second added concentration C2 of the second upper region 22U, offsetting a portion of the second added concentration C2 and adjusting the second added concentration C2 downward.

[0194] The corrected concentration C3 improves the accuracy of the charge balance between the first pillar region 21 and the second pillar region 22, thereby improving the electrical characteristics of the superjunction structure. In this embodiment, the corrected concentration C3 is applied to the second increasing section 34 and the second slowing section 35. In other words, the corrected concentration C3 mitigates the concentration difference between the first increasing section 31 and the second increasing section 34, and mitigates the concentration difference between the first slowing section 32 and the second slowing section 35.

[0195] The corrected density C3 is selectively applied to the thickness range of the second slowing portion 35. In this embodiment, the corrected density C3 is applied to the upper region of the second slowing portion 35, but not to the lower region of the second slowing portion 35. The corrected density C3 is not applied to the second gradual reduction portion 36. In other words, the corrected density C3 is not applied to the second lower region 22L of the second pillar region 22.

[0196] The corrected concentration C3 is lower than the second added concentration C2. The corrected concentration C3 is higher than the base concentration CB. The corrected concentration C3 is higher than the first added concentration C1. It is preferable that the corrected concentration C3 is due to a different pentavalent element than the pentavalent element in the base concentration CB. It is preferable that the corrected concentration C3 is due to a pentavalent element other than nitrogen (at least one of phosphorus, arsenic, antimony, and bismuth).

[0197] The corrected concentration C3 is preferably due to a single pentavalent element. The pentavalent element of the corrected concentration C3 is preferably phosphorus. The corrected concentration C3 may also be due to the same type of pentavalent element (nitrogen) as the pentavalent element of the base concentration CB. The corrected concentration C3 may also be due to two or more pentavalent elements.

[0198] The corrected concentration C3 is applied in multiple steps at different depth positions in the second pillar region 22, and the second concentration gradient G2 (second added concentration C2) is adjusted downward at multiple depth positions. In this configuration, the corrected concentration C3 is applied at different depth positions in the second upper region 22U. As a result, multiple concentration adjustment gradients Ga that increase or decrease the p-type impurity concentration are introduced at multiple depth positions in the second upper region 22U.

[0199] Multiple concentration adjustment gradients Ga are introduced in both the second increasing section 34 and the second slowing section 35. The multiple concentration adjustment gradients Ga may form a portion in the second upper region 22U that is more concentrated than the first concentration gradient G1 of the first pillar region 21, and a portion that is less concentrated than the first concentration gradient G1 of the first pillar region 21.

[0200] Multiple concentration adjustment gradients Ga may each have a thickness range greater than 0 μm and less than or equal to 0.5 μm. The thickness range of the concentration adjustment gradient Ga may have at least one of the following thickness ranges: greater than 0 μm and less than or equal to 0.1 μm, between 0.1 μm and 0.2 μm, between 0.2 μm and 0.3 μm, between 0.3 μm and 0.4 μm, and between 0.4 μm and 0.5 μm.

[0201] The ratio of the average value of the p-type impurity concentration in the second slow-release section 35 to the average value of the n-type impurity concentration in the first slow-release section 32 may be 0.7 or more and 1.3 or less. The p-type impurity concentration in the second slow-release section 35 is the p-type impurity concentration after correction by the correction concentration C3.

[0202] The concentration ratio may have a value that falls within at least one of the following ranges: 0.7 to 0.8, 0.8 to 0.9, 0.9 to 1, 1 to 1.1, 1.1 to 1.2, and 1.2 to 1.3.

[0203] The semiconductor device 1A includes a plurality of n-type source regions 40 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The source regions 40 may also be referred to as "impurity regions," "high-concentration regions," etc. The source regions 40 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7.

[0204] The n-type impurity concentration in the source region 40 is higher than the p-type impurity concentration in the body region 10. The n-type impurity concentration in the source region 40 is higher than the n-type impurity concentration in the first pillar region 21. The n-type impurity concentration in the source region 40 is higher than the p-type impurity concentration in the second pillar region 22.

[0205] Multiple source regions 40 are formed on the surface of the body region 10, spaced apart from the bottom of the body region 10 towards the first main surface 3, in the region between the multiple gate structures 15. The multiple source regions 40 extend in a band shape in the first direction X, following the direction of extension of the multiple gate structures 15.

[0206] The multiple source regions 40 are formed in a region that overlaps with the multiple second pillar regions 22 in the thickness direction Z via a portion of the body region 10 (i.e., a region that overlaps with the multiple first pillar regions 21). In this embodiment, the multiple source regions 40 overlap both the multiple first pillar regions 21 and the multiple second pillar regions 22 in the thickness direction Z via a portion of the body region 10.

[0207] The multiple source regions 40 have portions that overlap with the multiple first pillar regions 21 along the side walls of the multiple gate structures 15, and portions that overlap with the multiple second pillar regions 22 along the side walls of the multiple gate structures 15.

[0208] Each of the multiple source regions 40 has a portion located on the first main surface 3 side with respect to the electrode surface of the embedded electrode 18, and a portion located on the bottom wall side of the gate structure 15 with respect to the electrode surface of the embedded electrode 18. The multiple source regions 40 are connected to the multiple gate structures 15 in the second direction Y and face the embedded electrode 18 via an insulating film 17.

[0209] The multiple source regions 40 are formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3. The multiple source regions 40 may also have portions located toward the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15.

[0210] The semiconductor device 1A includes a plurality of p-type contact regions 41 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The contact regions 41 may also be referred to as "impurity regions," "high-concentration regions," etc.

[0211] The contact region 41 has a higher p-type impurity concentration than the body region 10. The contact region 41 may be considered a high-concentration area of ​​the body region 10. The p-type impurity concentration in the contact region 41 is higher than the n-type impurity concentration in the first pillar region 21. The p-type impurity concentration in the contact region 41 is higher than the p-type impurity concentration in the second pillar region 22.

[0212] Multiple contact regions 41 are formed in the region between the multiple gate structures 15, spaced apart from the bottom of the body region 10 toward the first main surface 3, on the surface of the body region 10. The multiple contact regions 41 are formed spaced apart in the first direction X, following the extending direction of the multiple gate structures 15.

[0213] With respect to a plurality of contact regions 41 formed on one side and the other side in the second direction Y for a single gate structure 15, the plurality of contact regions 41 on the other side are opposite the contact region 41 on the one side in the second direction Y when viewed from above. In other words, the plurality of contact regions 41 are arranged in a matrix with spacing in the first direction X and the second direction Y when viewed from above.

[0214] The multiple contact regions 41 are formed in the thickness direction Z in a region that overlaps with the multiple first pillar regions 21 via a part of the body region 10 (i.e., a region that overlaps with the multiple second pillar regions 22).

[0215] In this embodiment, the multiple contact regions 41 are formed at intervals in the first direction X from the multiple first pillar regions 21 in a plan view, and do not overlap with the first pillar regions 21 in the thickness direction Z. Of course, the multiple contact regions 41 may have portions that overlap with the first pillar regions 21 in the thickness direction Z.

[0216] In this configuration, the multiple contact regions 41 overlap with the multiple second pillar regions 22 in a one-to-one correspondence in the thickness direction Z, and are electrically connected to the multiple second pillar regions 22 via the body region 10. In other words, the multiple contact regions 41 are electrically connected to the multiple well regions 20 via the multiple second pillar regions 22.

[0217] In this configuration, the multiple contact regions 41 are formed at intervals in the second direction Y from the multiple gate structures 15 and are surrounded by corresponding source regions 40. In other words, the multiple contact regions 41 face the multiple gate structures 15 via a portion of the source region 40 corresponding to the second direction Y.

[0218] The multiple contact regions 41 are formed deeper than the multiple source regions 40 and have bottoms located closer to the bottom of the body region 10 than the bottoms of the multiple source regions 40. The multiple contact regions 41 may be formed shallower than the multiple source regions 40.

[0219] Multiple contact regions 41 are formed at intervals from the depth position of the intermediate part of the multiple gate structures 15 toward the first main surface 3. The multiple contact regions 41 may also have portions located toward the bottom wall side of the multiple gate structures 15 with respect to the depth position of the intermediate part of the multiple gate structures 15.

[0220] The semiconductor device 1A includes a plurality of n-type cap regions 42 formed within the second semiconductor layer 7 in the inner portion (active region 8) of the first main surface 3. The cap regions 42 may also be referred to as "impurity regions," "high-concentration regions," etc.

[0221] The cap region 42 has an n-type impurity concentration higher than that of the second semiconductor layer 7. The n-type impurity concentration of the cap region 42 is higher than that of the p-type impurity concentration of the body region 10. The n-type impurity concentration of the cap region 42 may be higher or lower than that of the p-type impurity concentration of the well region 20.

[0222] The n-type impurity concentration in the cap region 42 is higher than the n-type impurity concentration in the first pillar region 21. The n-type impurity concentration in the cap region 42 is higher than the p-type impurity concentration in the second pillar region 22. The n-type impurity concentration in the cap region 42 may be higher or lower than the n-type impurity concentration in the source region 40.

[0223] The multiple cap regions 42 are each formed in the region between the multiple gate structures 15, in the region below the body region 10. The multiple cap regions 42 are formed with a gap between them and the first main surface 3 from the depth position of the bottom wall of the multiple gate structures 15. The multiple cap regions 42 include a plurality of first cap regions 42A and a plurality of second cap regions 42B.

[0224] The multiple first cap regions 42A are formed at intervals in the first direction X, following the extending direction of the multiple gate structures 15, and are adjacent to the multiple gate structures 15 in the second direction Y. Each of the multiple first cap regions 42A is formed in a one-to-one correspondence with each of the multiple first pillar regions 21. The multiple first cap regions 42A are connected to the first upper regions 21U of the multiple first pillar regions 21, thereby increasing the n-type impurity concentration in the first upper regions 21U.

[0225] The multiple first cap regions 42A are positioned on the bottom wall side of the trench 16 with respect to the electrode surface of the embedded electrode 18 and face the embedded electrode 18 via the insulating film 17. The multiple first cap regions 42A face the multiple source regions 40 in the thickness direction Z via a part of the body region 10. As a result, the multiple first cap regions 42A, together with the multiple source regions 40, form a first channel Ch1 along the multiple gate structures 15 within the body region 10.

[0226] The multiple second cap regions 42B are interposed in the regions between the multiple gate structures 15, in the regions between the multiple first cap regions 42A that are adjacent in the first direction X. The multiple second cap regions 42B extend in a strip shape in the first direction X along the side walls of the corresponding gate structures 15.

[0227] Multiple second cap regions 42B are formed at intervals from each other in the second direction Y when viewed in cross-section along the second direction Y, and face each other in the second direction Y via a portion of the corresponding second pillar region 22 (see Figure 7).

[0228] In other words, the multiple second cap regions 42B are interposed in the region between the side wall of the corresponding gate structure 15 and the corresponding second pillar region 22 in a cross-sectional view along the second direction Y (see Figure 7). Furthermore, the multiple second cap regions 42B are interposed in the thickness direction Z between the body region 10 and the corresponding second pillar region 22 in a cross-sectional view along the second direction Y (see Figure 7).

[0229] The multiple second cap regions 42B are each formed in the portion of the second upper region 22U of the multiple second pillar regions 22 that is interposed between the multiple first cap regions 42A. In this embodiment, the multiple second cap regions 42B are drawn out in a strip shape in the first direction X along the side walls of the multiple gate structures 15 from the multiple first cap regions 42A, and replace the conductivity type of a part of the second upper region 22U of the multiple second pillar regions 22 from p type to n type.

[0230] The multiple second cap regions 42B face the multiple source regions 40 in the thickness direction Z via a portion of the body region 10. Thus, the multiple second cap regions 42B, together with the multiple source regions 40, form a second channel Ch2 within the body region 10 along the multiple gate structures 15. The multiple second cap regions 42B may also have portions facing the multiple contact regions 41 in the thickness direction Z via a portion of the body region 10.

[0231] In this way, the multiple cap regions 42 extend the current path connecting the multiple first pillar regions 21 and the multiple source regions 40 through the first channel Ch1 originating from the first cap region 42A and the second channel Ch2 originating from the second cap region 42B.

[0232] The semiconductor device 1A includes a p-type outer well region 45 formed within the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The outer well region 45 may also be referred to as the "impurity region". The outer well region 45 has a p-type impurity concentration lower than that of the well region 20. The p-type impurity concentration of the outer well region 45 may be higher or lower than that of the body region 10.

[0233] The p-type impurity concentration in the outer well region 45 may be approximately equal to that of the second pillar region 22. The p-type impurity concentration in the outer well region 45 may be higher or lower than that of the second pillar region 22. The p-type impurity concentration in the outer well region 45 is lower than that of the contact region 41. A source potential is applied to the outer well region 45.

[0234] The outer well region 45 is formed on the surface of the first main surface 3 and replaces the conductivity type of the second semiconductor layer 7 from n-type to p-type. The outer well region 45 is formed at intervals from the periphery of the first main surface 3 to the inward side of the first main surface 3 (towards the active region 8) and extends in layers along the first main surface 3. In a plan view, the outer well region 45 extends in a band shape along the active region 8.

[0235] In this embodiment, the outer well region 45 is formed as a polygonal ring (a quadrilateral ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The outer well region 45 may have an edge portion that connects a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0236] The outer well region 45 has a width greater than the width of the gate structure 15. The width of the outer well region 45 is greater than the width of the well region 20. The width of the outer well region 45 is greater than the width of the first pillar region 21. The width of the outer well region 45 is greater than the width of the second pillar region 22.

[0237] The ratio of the width of the outer well region 45 to the width of the second pillar region 22 (width of the first pillar region 21) may be greater than 1 and 100 or less. The width ratio may have at least one thickness range among those greater than 1 and 10 or less, 10 to 20, 20 to 30, 30 to 40, 40 to 50, 50 to 60, 60 to 70, 70 to 80, 80 to 90, and 90 to 100.

[0238] The outer well region 45 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer well region 45 demarcates the boundary between the active region 8 and the outer region 9.

[0239] The inner edge of the outer well region 45 may be connected to either or both of the body region 10 and the plurality of second pillar regions 22. The inner edge of the outer well region 45 may be connected to the ends of the plurality of gate structures 15. The outer edge of the outer well region 45 is formed at a distance from the periphery of the first main surface 3 and extends substantially parallel to the inner edge of the outer well region 45.

[0240] The outer well region 45 is formed with a gap from the bottom of the second semiconductor layer 7 toward the first main surface 3, and faces the first semiconductor layer 6 through a part of the second semiconductor layer 7. The outer well region 45 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0241] In this embodiment, the outer well region 45 has a depth greater than the depth of the multiple gate structures 15. In this embodiment, the depth of the outer well region 45 is approximately equal to the depth of the multiple second pillar regions 22. The depth of the outer well region 45 may be greater or less than the depth of the multiple second pillar regions 22.

[0242] The depth of the outer well region 45 may be greater than or less than the depth of the multiple first pillar regions 21. The depth of the outer well region 45 may be less than the depth of the multiple gate structures 15. The depth of the outer well region 45 may be approximately equal to the depth of the body region 10. The depth of the outer well region 45 may be greater than or less than the depth of the body region 10.

[0243] The outer well region 45 forms a pn junction with the second semiconductor layer 7. This forms a bipolar diode including the second semiconductor layer 7 as the cathode region and the outer well region 45 as the anode region. The outer well region 45 together with the body region 10 forms a bipolar diode.

[0244] When the gate structure 15 is in the off state and a drain voltage is applied, the depletion layer extends from the outer well region 45 to the second semiconductor layer 7. The depletion layer extending from the outer well region 45 extends the depletion layer extending from the body region 10 (active region 8) to the peripheral edge of the first main surface 3, thereby mitigating the electric field (electric field concentration) at the peripheral edge of the active region 8.

[0245] The semiconductor device 1A includes a p-type outer contact region 46 formed on the surface of the outer well region 45. The outer contact region 46 may also be referred to as the "impurity region," "high-concentration region," etc. The outer contact region 46 has a higher p-type impurity concentration than the p-type impurity concentration of the outer well region 45. The outer contact region 46 may also be considered as the high-concentration portion of the outer well region 45.

[0246] The p-type impurity concentration in the outer contact region 46 is higher than the p-type impurity concentration in the body region 10. The p-type impurity concentration in the outer contact region 46 may be approximately equal to the p-type impurity concentration in the well region 20. The p-type impurity concentration in the outer contact region 46 may be greater or less than the p-type impurity concentration in the well region 20.

[0247] The p-type impurity concentration in the outer contact region 46 is higher than the p-type impurity concentration in the second pillar region 22. The p-type impurity concentration in the outer contact region 46 may be approximately equal to the p-type impurity concentration in the contact region 41. The p-type impurity concentration in the outer contact region 46 may be greater or less than the p-type impurity concentration in the contact region 41.

[0248] The outer contact region 46 extends in a band shape along the outer well region 45 in a plan view. In this configuration, the outer contact region 46 is formed as a polygonal ring (a quadrilateral ring in this configuration) with four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (multiple gate structures 15).

[0249] The outer contact region 46 may have an edge portion that connects a portion extending in a strip shape in a first direction X and a portion extending in a strip shape in a second direction Y in an arc shape (preferably a quarter-circular arc shape). The semiconductor device 1A may include a plurality of outer contact regions 46. In this case, the plurality of outer contact regions 46 may be formed with spacing between them following the extending direction of the outer well region 45.

[0250] The outer contact region 46 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the outer contact region 46 may be connected to a plurality of gate structures 15. In this case, the inner edge of the outer contact region 46 may be connected to the body region 10. The inner edge of the outer contact region 46 may be formed at a distance from the plurality of gate structures 15 on the peripheral side of the first main surface 3.

[0251] The outer edge of the outer contact region 46 is formed with a gap between the periphery of the first main surface 3 and the inward side of the first main surface 3. In this configuration, the outer edge of the outer contact region 46 is formed with a gap between the outer edge of the outer well region 45 and the inward side of the first main surface 3, and extends substantially parallel to the inner edge of the outer contact region 46.

[0252] The outer contact region 46 is formed with a gap from the bottom of the outer well region 45 toward the first main surface 3, and faces the second semiconductor layer 7 via a portion of the outer well region 45. The outer contact region 46 has a depth less than the depth of the multiple gate structures 15.

[0253] The depth of the outer contact region 46 is less than the depth of the body region 10. The depth of the outer contact region 46 may be approximately equal to the depth of the contact region 41. The depth of the outer contact region 46 may be greater than or less than the depth of the contact region 41.

[0254] The semiconductor device 1A includes at least one (or more in this embodiment) p-type field regions 47 formed within the second semiconductor layer 7 at the peripheral edge (outer region 9) of the first main surface 3. The field regions 47 may also be referred to as "impurity regions," etc. The multiple field regions 47 may be formed in an electrically floating state. The multiple field regions 47 may be fixed to the source potential.

[0255] The number of field regions 47 may be between 1 and 20. The number of field regions 47 may be a value that falls within at least one of the following ranges: between 1 and 5, between 5 and 10, between 10 and 15, and between 15 and 20. Typically, the number of field regions 47 is between 1 and 8. In this embodiment, the semiconductor device 1A includes 6 field regions 47.

[0256] The multiple field regions 47 have a p-type impurity concentration lower than the p-type impurity concentration of the well region 20. The p-type impurity concentration of the multiple field regions 47 may be higher or lower than the p-type impurity concentration of the body region 10. The p-type impurity concentration of the multiple field regions 47 may be higher or lower than the n-type impurity concentration of the first pillar region 21.

[0257] The p-type impurity concentrations in the multiple field regions 47 may be approximately equal to the p-type impurity concentration in the second pillar region 22. The p-type impurity concentrations in the multiple field regions 47 may be higher or lower than the p-type impurity concentration in the second pillar region 22. The p-type impurity concentrations in the multiple field regions 47 may be lower than the p-type impurity concentration in the contact region 41.

[0258] The p-type impurity concentrations in multiple field regions 47 may be approximately equal to the p-type impurity concentrations in the outer well region 45. The p-type impurity concentrations in multiple field regions 47 may be higher or lower than the p-type impurity concentrations in the outer well region 45. The p-type impurity concentrations in multiple field regions 47 may be lower than the p-type impurity concentrations in the outer contact region 46.

[0259] Multiple field regions 47 are formed at intervals from each other on the surface of the second semiconductor layer 7 at the periphery of the first main surface 3, and the conductivity type of the second semiconductor layer 7 is changed from n-type to p-type. Multiple field regions 47 are formed at intervals from the periphery of the first main surface 3 and the active region 8, in the region between the periphery of the first main surface 3 and the active region 8.

[0260] Multiple field regions 47 are formed at intervals from the outer well region 45 towards the periphery of the first main surface 3. In a plan view, the multiple field regions 47 extend in a band shape along the outer well region 45.

[0261] In this embodiment, the multiple field regions 47 are formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surround the active region 8 (multiple gate structures 15). The multiple field regions 47 may have edge portions that connect the portions extending in a strip shape in the first direction X and the portions extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0262] The field region 47 has a width less than the width of the outer well region 45. The width of the field region 47 may be greater than or less than the width of the gate structure 15. The width of the field region 47 may be greater than or less than the width of the well region 20. The width of the field region 47 may be greater than or less than the width of the first pillar region 21. The width of the field region 47 may be greater than or less than the width of the second pillar region 22.

[0263] Multiple field regions 47 are formed at intervals from the bottom of the second semiconductor layer 7 toward the first main surface 3, and face the first semiconductor layer 6 through a portion of the second semiconductor layer 7. The multiple field regions 47 may be located on the first main surface 3 side or on the bottom side of the second semiconductor layer 7 with respect to the depth position of the middle part of the second semiconductor layer 7.

[0264] In this configuration, the multiple field regions 47 have a depth greater than the depth of the multiple gate structures 15. In this configuration, the depth of the multiple field regions 47 is approximately equal to the depth of the multiple second pillar regions 22. The depth of the multiple field regions 47 may be greater or less than the depth of the multiple second pillar regions 22.

[0265] In this configuration, the depth of the multiple field regions 47 is approximately equal to the depth of the outer well region 45. The depth of the multiple field regions 47 may be greater or less than the depth of the outer well region 45.

[0266] The depths of the multiple field regions 47 may be greater than or less than the depths of the multiple first pillar regions 21. The depths of the multiple field regions 47 may be less than the depths of the multiple gate structures 15. The depths of the multiple field regions 47 may be approximately equal to the depth of the body region 10. The depths of the multiple field regions 47 may be greater than or less than the depth of the body region 10.

[0267] Multiple field regions 47 form a pn junction with the second semiconductor layer 7. When the gate structure 15 is off and a drain voltage is applied, multiple depletion layers spread from the multiple field regions 47 to the second semiconductor layer 7. The depletion layers spreading from the multiple field regions 47 extend the depletion layer spreading from the outer well region 45 (active region 8) toward the periphery of the first main surface 3, thereby mitigating the electric field (electric field concentration) at the periphery of the first main surface 3.

[0268] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 47 are arbitrary and can take various values ​​depending on the electric field to be relaxed. The width of the multiple field regions 47 may be approximately constant or non-uniform. The width of the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3.

[0269] The depths of the multiple field regions 47 may be approximately constant or non-uniform. The depths of the multiple field regions 47 may gradually increase or decrease toward the peripheral edge of the first main surface 3. The multiple field regions 47 may each have a relatively shallow portion and a deeper portion that is deeper than the shallow portion. The shallow portion may be formed on the inner side and the deep portion may be formed on the peripheral side.

[0270] The spacing between the multiple field regions 47 may be approximately constant or non-uniform. The spacing between the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3. The p-type impurity concentration in the multiple field regions 47 may be approximately constant or non-uniform. The p-type impurity concentration in the multiple field regions 47 may gradually increase or decrease toward the periphery of the first main surface 3.

[0271] The semiconductor device 1A includes an insulating interlayer film 50 that selectively covers the first main surface 3. In this embodiment, the interlayer film 50 has a laminated structure including a first interlayer film 51 and a second interlayer film 52. The first interlayer film 51 may be referred to as the "main surface insulating film," "lower insulating film," etc., and the second interlayer film 52 may be referred to as the "upper insulating film," etc.

[0272] The first interlayer film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first interlayer film 51 may include a silicon oxide film containing the oxide of the chip 2 (second semiconductor layer 7). The first interlayer film 51 may include a silicon oxide film containing oxides other than the oxide of the chip 2. The first interlayer film 51 may include an insulator of the same type as the insulating film 17.

[0273] The first interlayer film 51 selectively coats the first main surface 3 in an active region 8 and an outer region 9. The first interlayer film 51 covers the first main surface 3 in the active region 8, exposing multiple gate structures 15. Specifically, the first interlayer film 51 is connected to multiple insulating films 17, exposing multiple embedded electrodes 18. In this configuration, the first interlayer film 51 forms a single insulating film integral with the multiple insulating films 17.

[0274] The first interlayer membrane 51 covers the outer well region 45, the outer contact region 46, and multiple field regions 47 in the outer region 9. The first interlayer membrane 51 is continuous with the first to fourth side surfaces 5A to 5D. The first interlayer membrane 51 may be formed with an inward gap from the first to fourth side surfaces 5A to 5D, exposing the peripheral edge of the first main surface 3.

[0275] The first interlayer film 51 may have a thickness approximately equal to the thickness of the insulating film 17. The thickness of the first interlayer film 51 may be greater than 0 nm and 250 nm or less. The thickness of the first interlayer film 51 may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, and 200 nm to 250 nm.

[0276] The second interlayer film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second interlayer film 52 may have a single-layer structure or a multilayer structure including at least one of an NSG film (Nondoped Silicate Glass film), a PSG film (Phosphorus Silicon Glass film), a BSG film (Boron Silicon Glass film), a BPSG film (Boron Phosphorus Silicon Glass film), and a TEOS film (Tetraethyl Orthosilicate film).

[0277] The NSG film is a silicon oxide film without impurities, the PSG film is a silicon oxide film containing phosphorus, and the BPSG film is a silicon oxide film containing both phosphorus and boron. The second interlayer film 52 preferably has a single-layer structure or a multilayer structure including at least an NSG film.

[0278] The second interlayer film 52 may have a laminated structure including an NSG film and a PSG film (or BPSG film) stacked in this order from the chip 2 side.

[0279] The second interlayer membrane 52 covers the first interlayer membrane 51 in a film-like manner in the active region 8 and the outer region 9. The second interlayer membrane 52 covers multiple gate structures 15 in the active region 8. Specifically, the second interlayer membrane 52 penetrates into multiple trenches 16 from above the first interlayer membrane 51 and covers multiple embedded electrodes 18 within the multiple trenches 16.

[0280] The second interlayer membrane 52 covers the first main surface 3 via the first interlayer membrane 51 in the outer region 9. Specifically, the second interlayer membrane 52 covers the outer well region 45, the outer contact region 46, and multiple field regions 47 via the first interlayer membrane 51.

[0281] The second interlayer membrane 52 is continuous with the first to fourth side surfaces 5A to 5D. The outer edge of the second interlayer membrane 52 is formed with a gap inward from the first to fourth side surfaces 5A to 5D, and may expose either or both of the peripheral edge of the first main surface 3 and the first interlayer membrane 51.

[0282] The second interlayer membrane 52 has a thickness greater than the thickness of the first interlayer membrane 51. The thickness of the second interlayer membrane 52 may be greater than 0 μm and 5 μm or less. The thickness of the second interlayer membrane 52 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0283] The semiconductor device 1A includes one or more (one in this embodiment) gate wiring 55 selectively routed along the periphery (outer region 9) of the first main surface 3. The gate wiring 55 is electrically connected to a plurality of gate structures 15 and provides gate potentials to the plurality of gate structures 15.

[0284] The gate wiring 55 may contain a non-metallic conductor. The gate wiring 55 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. Preferably, the gate wiring 55 contains the same conductive material as the conductive material of the embedded electrode 18.

[0285] The gate wiring 55 is located within the interlayer film 50. Specifically, the gate wiring 55 is located on the first interlayer film 51 and covered by the second interlayer film 52. The gate wiring 55 is spaced apart from the periphery of the first main surface 3 towards the active region 8. The gate wiring 55 is spaced apart from the multiple field regions 47 (the innermost field region 47).

[0286] The gate wiring 55 is positioned at a distance from the outer edge of the outer well region 45. The gate wiring 55 is positioned at a distance from the outer edge of the outer contact region 46. In a plan view, the gate wiring 55 extends in a strip shape along the active region 8.

[0287] In this embodiment, the gate wiring 55 is formed in a polygonal ring shape (a quadrilateral ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view, and surrounds the active region 8 (a plurality of gate structures 15). The gate wiring 55 may also be formed in the shape of an ended strip. The gate wiring 55 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0288] The gate wiring 55 has an inner edge on the inner side of the first main surface 3 and an outer edge on the peripheral side of the first main surface 3. The inner edge of the gate wiring 55 is mechanically and electrically connected to the ends of the multiple gate structures 15. Specifically, the inner edge of the gate wiring 55 enters into the multiple trenches 16 from above the first interlayer membrane 51 and is mechanically and electrically connected to the multiple embedded electrodes 18 within the multiple trenches 16.

[0289] In this configuration, the gate wiring 55 is formed integrally with the multiple buried electrodes 18 as the lead-out portion of the multiple buried electrodes 18. The connection portion of the gate wiring 55 to the multiple buried electrodes 18 may be considered as part of the multiple buried electrodes 18, or as part of the gate wiring 55.

[0290] The inner edge of the gate wiring 55 covers the first main surface 3 via the first interlayer film 51 in the region between the multiple gate structures 15. The inner edge of the gate wiring 55 may overlap either or both of the body region 10 and the outer well region 45 in the region between the multiple gate structures 15.

[0291] The semiconductor device 1A includes one or more (in this embodiment, more than one) source openings 56 formed in the interlayer film 50 in the active region 8. The multiple source openings 56 are each formed in the region between the multiple gate structures 15, spaced apart from the multiple gate structures 15, and penetrate the interlayer film 50. In other words, the multiple source openings 56 each expose multiple mesa regions partitioned by the multiple gate structures 15 in the chip 2 (second semiconductor layer 7).

[0292] Multiple source openings 56 are formed at intervals in the second direction Y and each extends in a strip shape in the first direction X, following the direction of extension of the multiple gate structures 15. Multiple source openings 56 expose multiple source regions 40 and multiple contact regions 41.

[0293] The multiple source openings 56 may be formed at intervals in the first direction X in the region between two adjacent gate structures 15 in the second direction Y. In this case, the multiple source openings 56 may each extend in a strip shape in the first direction X, exposing either or both of the source region 40 and the contact region 41.

[0294] Each of the multiple source apertures 56 has an aperture width less than or equal to the spacing between the multiple gate structures 15. The aperture width may be greater than 0 μm and 3 μm or less. The aperture width may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or less, 2 μm or more and 2.25 μm or less, 2.25 μm or more and 2.5 μm or less, 2.5 μm or more and 2.75 μm or less, and 2.75 μm or more and 3 μm or less.

[0295] The aperture width may be 1.5 μm or less. The aperture width may be 1.2 μm or less. The aperture width may be 1 μm or less. The aperture width may be 0.8 μm or less. The aperture width may be 0.6 μm or less. The aperture width may be 0.4 μm or less.

[0296] The semiconductor device 1A includes one or more (in this embodiment, more) source recesses 57 formed on the first main surface 3 in the active region 8 (see Figure 13). The source recesses 57 may also be called "recesses," "mesa recesses," etc. The source recesses 57 may be considered as part of the first main surface 3 (one component). The semiconductor device 1A does not necessarily need to have source recesses 57, and a configuration without source recesses 57 may be adopted.

[0297] Multiple source recesses 57 are formed in the portion of the first main surface 3 that is exposed from multiple source openings 56. Each of the multiple source recesses 57 has a planar shape that matches the planar shape of the multiple source openings 56 and is excavated toward the second main surface 4.

[0298] Multiple source recesses 57 are formed at intervals toward the first main surface 3 from the depth positions of the bottom of the multiple source regions 40 and the depth positions of the bottom of the multiple contact regions 41, exposing the multiple source regions 40 and the multiple contact regions 41. The multiple source recesses 57 are located toward the first main surface 3 than the depth positions of the electrode surfaces of the multiple embedded electrodes 18.

[0299] The semiconductor device 1A includes one or more (in this embodiment, more than one) gate openings 58 formed in the interlayer film 50 in the outer region 9. The multiple gate openings 58 penetrate the interlayer film 50 and selectively expose the gate wiring 55.

[0300] In this configuration, the multiple gate openings 58 extend in a strip-like shape following the direction of extension of the gate wiring 55. The multiple gate openings 58 may be formed at intervals in the direction of extension of the gate wiring 55. The multiple gate openings 58 may be formed in a polygonal or circular shape in plan view. The multiple gate openings 58 may be formed in a square or hexagonal shape in plan view.

[0301] The multiple gate openings 58 may have portions that extend in a strip shape in a first direction X and portions that extend in a strip shape in a second direction Y when viewed from above. The multiple gate openings 58 may have edge portions that connect the portions that extend in the first direction X and the portions that extend in the second direction Y in an arc shape (preferably a quarter arc shape) when viewed from above. The semiconductor device 1A may include one gate opening 58 that extends in a strip shape along the gate wiring 55.

[0302] The semiconductor device 1A includes one or more (one in this embodiment) outer openings 59 formed in the interlayer film 50. The outer openings 59 are formed with a gap from the gate wiring 55 toward the periphery of the first main surface 3 and with a gap from the periphery of the first main surface 3 toward the inward side of the first main surface 3. The outer openings 59 are formed with a gap from a plurality of field regions 47 (the innermost field region 47) toward the inward side of the first main surface 3.

[0303] The outer opening 59 penetrates the interlayer film 50 and exposes the outer contact region 46. In this embodiment, the outer opening 59 has a width less than the width of the outer contact region 46 and exposes the inner portion of the outer contact region 46 at a distance from its inner and outer edges. The outer opening 59 may also expose the outer well region 45.

[0304] The outer opening 59 extends in a strip shape following the direction of extension of the outer well region 45. The outer opening 59 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y. In this embodiment, the outer opening 59 is formed as an endless polygonal ring (for example, a quadrilateral ring) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8 (multiple gate structures 15).

[0305] The outer opening 59 may have an edge portion that connects the portion extending in a strip shape in the first direction X and the portion extending in a strip shape in the second direction Y in an arc shape (preferably a quarter-circular arc shape) when viewed from above. The outer opening 59 may be formed in the shape of an end-banded strip.

[0306] The semiconductor device 1A may include a plurality of outer openings 59. In this case, the plurality of outer openings 59 may be formed at intervals in the extending direction of the outer well region 45. The plurality of outer openings 59 may be formed in a polygonal or circular shape in plan view. The plurality of outer openings 59 may be formed in a square or hexagonal shape in plan view.

[0307] The semiconductor device 1A includes a source electrode 60 located in the inner portion (active region 8) of the first main surface 3. The source electrode 60 may also be referred to as the "first main electrode," "first terminal (electrode)," "first pad (electrode)," "source pad electrode," etc. The source electrode 60 is made of metal and is located on the interlayer film 50.

[0308] In this embodiment, the source electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c. The first pad portion 60a has a relatively large surface area and forms the main body of the source electrode 60. In this embodiment, the first pad portion 60a is formed in a polygonal shape (a quadrilateral shape in this embodiment) with four sides parallel to the periphery of the first main surface 3 in a plan view, and is offset towards the third side surface 5C relative to the central part of the first main surface 3.

[0309] The second pad portion 60b has a flat area less than that of the first pad portion 60a, and extends in a strip-like (square-shaped) manner from one end of the first direction X (the end on the second side surface 5B side) toward the first side surface 5A.

[0310] The third pad portion 60c has a flat area less than the flat area of ​​the first pad portion 60a, extends in a strip shape (square shape) from the other end of the first pad portion 60a in the first direction X (the end on the fourth side surface 5D side) toward the first side surface 5A, and faces the second pad portion 60b in the first direction X. The flat area of ​​the third pad portion 60c may be approximately equal to the flat area of ​​the second pad portion 60b. The flat area of ​​the third pad portion 60c may be larger or smaller than the flat area of ​​the second pad portion 60b.

[0311] Either the second pad portion 60b or the third pad portion 60c, or both, may be used as terminal portions for current monitoring. The source electrode 60 may have only one of the second pad portion 60b or the third pad portion 60c. The source electrode 60 may consist only of the first pad portion 60a and may not have both the second pad portion 60b and the third pad portion 60c.

[0312] The source electrode 60 enters a plurality of source openings 56 from above the interlayer film 50 and is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within the plurality of source openings 56. In this embodiment, the source electrode 60 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within a plurality of source recesses 57.

[0313] The source electrode 60 is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the source electrode 60 is formed with a gap between it and the active region 8 from the multiple field regions 47. The peripheral edge of the source electrode 60 is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the source electrode 60 is formed with a gap between it and the outer edge of the outer contact region 46.

[0314] The peripheral edge of the source electrode 60 is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the source electrode 60 faces the outer well region 45 in the thickness direction Z. The peripheral edge of the source electrode 60 may also face the outer contact region 46 in the thickness direction Z.

[0315] The source electrode 60 may have a single-layer structure comprising a single metal film, or a multilayer structure comprising multiple metal films. The source electrode 60 may contain a metal film comprising at least one of the following: aluminum (Al)-based metals, titanium (Ti)-based metals, nickel (Ni)-based metals, copper (Cu)-based metals, molybdenum (Mo)-based metals, palladium (Pd)-based metals, silver (Ag)-based metals, tungsten (W)-based metals, and gold (Au)-based metals.

[0316] The source electrode 60 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The source electrode 60 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0317] In this embodiment, the source electrode 60 has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 is formed as a barrier electrode for the chip 2 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0318] In this embodiment, the base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b. The first electrode 61a consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first electrode 61a consists of a titanium-based metal film (titanium film).

[0319] The first electrode 61a penetrates the interlayer film 50 through a plurality of source openings 56. The first electrode 61a has a portion that covers the interlayer film 50 in a film-like manner, a portion that covers the walls of the plurality of source openings 56 in a film-like manner, and a portion that covers the first main surface 3 (a plurality of source recesses 57) in a film-like manner. The first electrode 61a is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within the plurality of source openings 56.

[0320] The first electrode 61a is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the first electrode 61a is formed with a gap between it and the multiple field regions 47 towards the active region 8. The peripheral edge of the first electrode 61a is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the first electrode 61a is formed with a gap between it and the outer edge of the outer contact region 46.

[0321] The peripheral edge of the first electrode 61a is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the first electrode 61a faces the outer well region 45 in the thickness direction Z. The peripheral edge of the first electrode 61a may also face the outer contact region 46 in the thickness direction Z.

[0322] The first electrode 61a has a thickness less than the thickness of the interlayer film 50. The thickness of the first electrode 61a may be greater than 0 nm and 200 nm or less. The thickness of the first electrode 61a may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0323] The second electrode 61b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second electrode 61b consists of a different metal film or alloy film than the first electrode 61a. In this embodiment, the second electrode 61b consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0324] The second electrode 61b covers the first electrode 61a in a film-like manner and penetrates the multiple source openings 56 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the wall surfaces of the multiple source openings 56 in a film-like manner via the first electrode 61a, and a portion that covers the first main surface 3 (multiple source recesses 57) in a film-like manner via the first electrode 61a. The second electrode 61b is electrically connected to the multiple source regions 40 and the multiple contact regions 41 via the first electrode 61a.

[0325] The second electrode 61b is drawn out into the outer region 9 and has a peripheral portion that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral portion of the second electrode 61b is formed with a gap between it and the multiple field regions 47 towards the active region 8. The peripheral portion of the second electrode 61b is formed with a gap between it and the outer edge of the outer well region 45. The peripheral portion of the second electrode 61b is formed with a gap between it and the outer edge of the outer contact region 46.

[0326] The peripheral edge of the second electrode 61b is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the second electrode 61b faces the outer well region 45 in the thickness direction Z. The peripheral edge of the second electrode 61b may also face the outer contact region 46 in the thickness direction Z.

[0327] The second electrode 61b has a thickness less than the thickness of the interlayer film 50. In this embodiment, the thickness of the second electrode 61b is greater than the thickness of the first electrode 61a. The thickness of the second electrode 61b may be less than the thickness of the first electrode 61a.

[0328] The thickness of the second electrode 61b may be greater than 0 nm and 300 nm or less. The thickness of the second electrode 61b may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0329] The main electrode 62 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The main electrode 62 is made of a different conductor than the first electrode 61a and the second electrode 61b. In this embodiment, the main electrode 62 is made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may contain at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0330] The main electrode 62 covers the base electrode 61 in a film-like manner and penetrates the multiple source openings 56 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surfaces of the multiple source openings 56 in a film-like manner via the base electrode 61, and a portion that covers the first main surface 3 (multiple source recesses 57) in a film-like manner via the base electrode 61. The main electrode 62 is electrically connected to the multiple source regions 40 and the multiple contact regions 41 via the base electrode 61.

[0331] The main electrode 62 is drawn out into the outer region 9 and has a peripheral edge that faces the ends of the multiple gate structures 15 via the interlayer film 50. The peripheral edge of the main electrode 62 is formed with a gap between it and the active region 8 from the multiple field regions 47. The peripheral edge of the main electrode 62 is formed with a gap between it and the outer edge of the outer well region 45. The peripheral edge of the main electrode 62 is formed with a gap between it and the outer edge of the outer contact region 46.

[0332] The peripheral edge of the main electrode 62 is formed at a distance from the outer edge of the gate wiring 55 and faces the gate wiring 55 via a portion of the interlayer film 50. In this configuration, the peripheral edge of the main electrode 62 faces the outer well region 45 in the thickness direction Z. The peripheral edge of the main electrode 62 may also face the outer contact region 46 in the thickness direction Z.

[0333] The main electrode 62 has a thickness greater than the thickness of the base electrode 61 (the total thickness of the first electrode 61a and the second electrode 61b). In this embodiment, the thickness of the main electrode 62 is greater than the thickness of the interlayer film 50. The thickness of the main electrode 62 may be less than the thickness of the interlayer film 50.

[0334] The thickness of the main electrode 62 may be greater than 0 μm and 5 μm or less. The thickness of the main electrode 62 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0335] The semiconductor device 1A includes a source finger 63 arranged on the peripheral edge (outer region 9) of the first main surface 3. The source finger 63 may also be called a "source electrode," "source wiring," or "source finger electrode." The source finger 63 is made of metal. The source finger 63 transmits the source potential applied to the source electrode 60 to other regions.

[0336] The source finger 63 is drawn out from the source electrode 60 onto the interlayer film 50. The source finger 63 is routed around the periphery of the first main surface 3 and the region between the source electrode 60, extending in a band shape along the active region 8. In this embodiment, the source finger 63 is drawn out from the side of the first pad portion 60a on the third side surface 5C side onto the outer opening 59.

[0337] The source finger 63 has a portion that extends in a strip shape in a first direction X and a portion that extends in a strip shape in a second direction Y when viewed from above. In this embodiment, the source finger 63 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the active region 8. The source finger 63 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0338] The source finger 63 enters the outer opening 59 from above the interlayer film 50 and is electrically connected to the outer contact region 46 within the outer opening 59. As a result, the source potential applied to the source electrode 60 is applied to the outer well region 45 via the outer contact region 46.

[0339] The source finger 63 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the source finger 63 is spaced apart from the plurality of gate structures 15 on the peripheral side of the first main surface 3 and faces the outer well region 45 in the thickness direction Z.

[0340] The inner edge of the source finger 63 is positioned at a distance from the gate wiring 55 toward the periphery of the first main surface 3. The inner edge of the source finger 63 may also be formed at a distance from the middle of the outer well region 45 toward the periphery of the first main surface 3. The inner edge of the source finger 63 may face the outer contact region 46 in the thickness direction Z.

[0341] The outer edge of the source finger 63 is formed at intervals from multiple field regions 47 (the innermost field region 47) toward the inward side of the first main surface 3 and extends substantially parallel to the inner edge of the source finger 63. This suppresses the shielding of the electric field dispersion path by the source finger 63, and the electric field (electric field lines) is appropriately dispersed by the multiple field regions 47.

[0342] In this embodiment, the outer edge of the source finger 63 is formed at a distance from the outer edge of the outer well region 45 toward the inward side of the first main surface 3 and is located on the outer well region 45. The outer edge of the source finger 63 may also be located on the outer contact region 46. The outer edge of the source finger 63 may also be located on the second semiconductor layer 7.

[0343] The source finger 63, like the source electrode 60, has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b.

[0344] The first electrode 61a extends from above the interlayer film 50 into the outer opening 59. The first electrode 61a has a portion that covers the insulating surface of the interlayer film 50 in a film-like manner, a portion that covers the wall surface of the outer opening 59 in a film-like manner, and a portion that covers the first main surface 3 in a film-like manner. The first electrode 61a is electrically connected to the outer contact region 46 within the outer opening 59.

[0345] The second electrode 61b covers the first electrode 61a in a film-like manner and extends into the outer opening 59 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the wall surface of the outer opening 59 in a film-like manner via the first electrode 61a, and a portion that covers the first main surface 3 in a film-like manner via the first electrode 61a. The second electrode 61b is electrically connected to the outer contact region 46 via the first electrode 61a within the outer opening 59.

[0346] The main electrode 62 covers the base electrode 61 in a film-like manner and enters the outer opening 59 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surface of the outer opening 59 in a film-like manner via the base electrode 61, and a portion that covers the first main surface 3 in a film-like manner via the base electrode 61. The main electrode 62 is electrically connected to the outer contact region 46 within the outer opening 59 via the base electrode 61.

[0347] The semiconductor device 1A includes a gate electrode 64 disposed on the first main surface 3. The gate electrode 64 may also be referred to as the "second main electrode," "second terminal (electrode)," "second pad (electrode)," "gate pad electrode," etc. The gate electrode 64 is made of metal. The gate electrode 64 is disposed on the interlayer film 50 at a distance from the source electrode 60 and source finger 63.

[0348] The gate electrode 64 is positioned in the region on the first side surface 5A side relative to the first pad portion 60a, and faces the central portion of the first side surface 5A and the first pad portion 60a in the second direction Y. The gate electrode 64 is interposed in the region between the second pad portion 60b and the third pad portion 60c, and faces both the second pad portion 60b and the third pad portion 60c in the first direction X.

[0349] The gate electrode 64 is formed in a polygonal shape (a quadrilateral in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view. The gate electrode 64 has a planar area less than the planar area of ​​the source electrode 60. The planar area of ​​the gate electrode 64 is less than the planar area of ​​the first pad portion 60a. The planar area of ​​the gate electrode 64 may be larger or smaller than the planar area of ​​the second pad portion 60b (third pad portion 60c).

[0350] In this embodiment, the gate electrode 64 faces the first main surface 3 via the interlayer film 50 and does not have a direct electrical connection to the gate wiring 55. The gate electrode 64 may be electrically connected to the gate wiring 55 via one or more gate openings 58, and electrically connected to a plurality of gate structures 15 via the gate wiring 55.

[0351] In this embodiment, the gate electrode 64 faces the outer well region 45 via the interlayer film 50. The gate electrode 64 may have portions that face multiple gate structures 15 via the interlayer film 50. The gate electrode 64 may be formed at a distance from the multiple gate structures 15 and may not face multiple gate structures 15 in the thickness direction Z.

[0352] Although not shown in the illustration, the gate electrode 64, like the source electrode 60, includes a base electrode 61 and a main electrode 62 stacked in this order from the interlayer film 50 side. The base electrode 61 has a stacked structure including a first electrode 61a and a second electrode 61b.

[0353] The semiconductor device 1A includes a gate finger 65 arranged on the peripheral edge (outer region 9) of the first main surface 3. The gate finger 65 may also be called a "gate electrode," "gate wiring," or "gate finger electrode." The gate finger 65 is made of metal. The gate finger 65 transmits the gate potential applied to the gate electrode 64 to other regions.

[0354] The gate finger 65 is drawn out from the gate electrode 64 onto the interlayer film 50. The gate finger 65 is routed in a strip-like manner in the region between the source electrode 60 and the source finger 63. The gate finger 65 has a portion that extends in a strip-like manner in a first direction X and a portion that extends in a strip-like manner in a second direction Y when viewed in plan.

[0355] In this embodiment, the gate finger 65 is formed in the shape of an ended band having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 60. The gate finger 65 is positioned closer to the periphery of the first main surface 3 than the ends of the plurality of gate structures 15. The gate finger 65 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter-circular arc shape).

[0356] The gate finger 65 enters a plurality of gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 55 within the plurality of gate openings 58. As a result, the gate potential applied to the gate electrode 64 is applied to the plurality of gate structures 15 via the gate wiring 55 and the gate finger 65.

[0357] The gate finger 65 has an inner edge portion on the inner side of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3. The inner edge portion of the gate finger 65 is formed at a distance from the plurality of gate structures 15 on the peripheral side of the first main surface 3. In other words, the gate finger 65 does not face the plurality of gate structures 15 in the thickness direction Z.

[0358] The inner edge of the gate finger 65 is positioned on the gate wiring 55. The inner edge of the gate finger 65 is horizontally opposed to the peripheral edge of the source electrode 60 on the gate wiring 55. The inner edge of the gate finger 65 may be located on the peripheral side of the first main surface 3 relative to the middle portion of the gate wiring 55. The inner edge of the gate finger 65 may be located on the inward side of the first main surface 3 relative to the middle portion of the gate wiring 55.

[0359] The outer edge of the gate finger 65 extends substantially parallel to the inner edge of the gate finger 65. The outer edge of the gate finger 65 is drawn out from above the gate wiring 55 towards the peripheral edge of the first main surface 3 and does not face the gate wiring 55 in the thickness direction Z. The outer edge of the gate finger 65 is formed with a gap between multiple field regions 47 (the innermost field region 47) on the inward side of the first main surface 3.

[0360] The outer edge of the gate finger 65 is formed with a gap between it and the outer edge of the outer well region 45, on the inward side of the first main surface 3. In this configuration, the outer edge of the gate finger 65 is formed with a gap between it and the inner edge of the outer contact region 46, on the inward side of the first main surface 3, and faces the outer well region 45.

[0361] The outer edge of the gate finger 65 is horizontally opposed to the inner edge of the source finger 63. The outer edge of the gate finger 65 may be located on the outer contact region 46. The outer edge of the gate finger 65 may be located on the second semiconductor layer 7.

[0362] The gate finger 65, like the source electrode 60 (gate electrode 64), has a laminated structure including a base electrode 61 and a main electrode 62 stacked in this order from the first main surface 3 side. The base electrode 61 has a laminated structure including a first electrode 61a and a second electrode 61b.

[0363] The first electrode 61a penetrates the interlayer film 50 through a plurality of gate openings 58. The first electrode 61a has a portion that covers the insulating surface of the interlayer film 50 in a film-like manner, a portion that covers the walls of the plurality of gate openings 58 in a film-like manner, and a portion that covers the gate wiring 55 in a film-like manner. The first electrode 61a is electrically connected to the gate wiring 55 within the plurality of gate openings 58.

[0364] The second electrode 61b covers the first electrode 61a in a film-like manner and penetrates the multiple gate openings 58 from above the interlayer film 50. The second electrode 61b has a portion that covers the interlayer film 50 in a film-like manner via the first electrode 61a, a portion that covers the walls of the multiple gate openings 58 in a film-like manner via the first electrode 61a, and a portion that covers the gate wiring 55 in a film-like manner via the first electrode 61a. The second electrode 61b is electrically connected to the gate wiring 55 via the first electrode 61a within the multiple gate openings 58.

[0365] The main electrode 62 covers the base electrode 61 in a film-like manner and penetrates the multiple gate openings 58 from above the interlayer film 50. The main electrode 62 has a portion that covers the interlayer film 50 in a film-like manner via the base electrode 61, a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner via the base electrode 61, and a portion that covers the gate wiring 55 in a film-like manner via the base electrode 61. The main electrode 62 is electrically connected to the gate wiring 55 via the base electrode 61 within the multiple gate openings 58.

[0366] The semiconductor device 1A includes a drain electrode 66 that covers the second main surface 4. The drain electrode 66 may also be referred to as the "third main electrode," "third terminal (electrode)," "third pad (electrode)," "drain pad electrode," etc. The drain electrode 66 may have a single-layer structure or a multilayer structure that includes at least one of an aluminum-based metal film, a titanium-based metal film, a nickel-based metal film, a palladium-based metal film, a gold-based metal film, and a silver-based metal film.

[0367] The drain electrode 66 is mechanically and electrically connected to the first semiconductor layer 6. The drain electrode 66 forms ohmic contact with the first semiconductor layer 6. The drain electrode 66 may cover the entire area of ​​the second main surface 4 and may be connected to the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D). The drain electrode 66 may partially cover the second main surface 4 so that the periphery of the second main surface 4 is exposed.

[0368] The breakdown voltage that can be applied between the source electrode 60 and the drain electrode 66 (between the first main surface 3 and the second main surface 4) may be 500V or more and 3000V or less. The breakdown voltage may have a value that falls within at least one of the following ranges: 500V or more and 750V or less, 750V or more and 1000V or less, 1000V or more and 1250V or less, 1250V or more and 1500V or less, 1500V or more and 1750V or less, 1750V or more and 2000V or less, 2000V or more and 2250V or more and 2250V or more and 2500V or more and 3000V or less.

[0369] As described above, the semiconductor device 1A may include an n-type second semiconductor layer 7 (semiconductor layer), a p-type body region 10, a trench-type gate structure 15, a p-type well region 20, and a p-type second pillar region 22 (pillar region).

[0370] The second semiconductor layer 7 may have a first main surface 3. The body region 10 may be formed on the surface of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to penetrate the body region 10. The gate structure 15 may extend in a first direction X along the first main surface 3.

[0371] The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may electrically connect the well region 20 to the body region 10.

[0372] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the depletion layer caused by the second pillar region 22 improves the electrical breakdown voltage (e.g., breakdown voltage), and the electrical floating state of the well region 20 is suppressed by the second pillar region 22.

[0373] This improves the electrical response characteristics of the well region 20, and the electric field on the gate structure 15 is appropriately mitigated by the well region 20. In addition, the second pillar region 22 intersecting the gate structure 15 limits the formation of non-channel areas along the gate structure 15, thereby suppressing the decrease in current processing capacity caused by the reduction in channel area.

[0374] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the breakdown voltage improvement effect of the well region 20 and the second pillar region 22 is effective.

[0375] The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0376] The well region 20 may have a higher p-type impurity concentration than the body region 10. This configuration appropriately improves the electrical response characteristics of the well region 20 and the electric field relaxation effect provided by the well region 20.

[0377] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0378] The second pillar region 22 may have a bottom located below the bottom of the well region 20. With this configuration, the electric field for the gate structure 15 is mitigated by the second pillar region 22 from below the well region 20.

[0379] The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. The second pillar region 22 may have a bottom portion having a p-type impurity concentration lower than that of the well region 20. With these configurations, the depletion layer originating from the second pillar region 22 expands appropriately.

[0380] The second pillar region 22 may have a second slow-change portion 35 in the thickness range of the intermediate portion where the rate of change of p-type impurity concentration is slow. The second pillar region 22 may be composed of a single p-type impurity region. Multiple second pillar regions 22 may be formed at intervals in the first direction X. With this configuration, the electrical breakdown voltage is improved by the multiple second pillar regions 22.

[0381] The semiconductor device 1A may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the region outside the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. With this configuration, a channel can be appropriately formed in the region outside the second pillar region 22.

[0382] The semiconductor device 1A may include a p-type contact region 41. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. With this configuration, the electrical response characteristics of the second pillar region 22 are improved by the contact region 41, and the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0383] The semiconductor device 1A may include an n-type first pillar region 21. The first pillar region 21 may extend in a second direction Y within the second semiconductor layer 7 so as to intersect with the gate structure 15. The first pillar region 21 may have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor layer 7. In this case, the second pillar region 22 may form a pn junction with the first pillar region 21.

[0384] In this configuration, the electrical breakdown voltage is improved by the depletion layer caused by the pn junction between the first pillar region 21 and the second pillar region 22. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. In this configuration, the depletion layer caused by the pn junction is appropriately expanded.

[0385] Multiple first pillar regions 21 may be formed at intervals in the first direction X. Multiple second pillar regions 22 may be formed alternately with the multiple first pillar regions 21 in the first direction X. In this case, the second pillar regions 22 may form a superjunction structure with the first pillar regions 21. This configuration appropriately improves electrical withstand voltage.

[0386] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, a trench-type gate structure 15, an n-type first pillar region 21 (first region), and a p-type second pillar region 22 (second region). The second semiconductor layer 7 may have a first main surface 3. The gate structure 15 may be formed on the first main surface 3 and extend in a first direction X along the first main surface 3.

[0387] The first pillar region 21 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15 below the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may extend in a second direction Y so as to intersect the gate structure 15 below the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may form a pn junction with the first pillar region 21.

[0388] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the depletion layer caused by the pn junction between the first pillar region 21 and the second pillar region 22 extends below the gate structure 15. As a result, the electric field for the gate structure 15 is mitigated from below the gate structure 15, improving its electrical breakdown voltage.

[0389] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the electric field relaxation effect on the gate structure 15 is effective.

[0390] The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0391] The first pillar region 21 may have a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor layer 7. With this configuration, the pn junction between the first pillar region 21 and the second pillar region 22 is appropriately adjusted by the n-type impurity concentration of the first pillar region 21.

[0392] The first pillar region 21 may have a portion located above the bottom wall of the gate structure 15 and a portion located below the bottom wall of the gate structure 15. The second pillar region 22 may have a portion located above the bottom wall of the gate structure 15 and a portion located below the bottom wall of the gate structure 15. The second pillar region 22 may form a pn joint with the first pillar region 21 at both depth positions above and below the bottom wall of the gate structure 15.

[0393] With this configuration, the depletion layer caused by the pn junction extends at depths both above and below the bottom wall of the gate structure 15, thereby appropriately improving the electrical withstand voltage. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. With this configuration, the depletion layer caused by the pn junction is appropriately expanded.

[0394] Multiple first pillar regions 21 may be formed at intervals in the first direction X. Multiple second pillar regions 22 may be formed alternately with the multiple first pillar regions 21 in the first direction X. In this case, the second pillar regions 22 may form a superjunction structure with the first pillar regions 21. This configuration appropriately improves electrical withstand voltage.

[0395] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. In this case, the first pillar region 21 may intersect the well region 20 in a region below the well region 20. The second pillar region 22 may intersect the well region 20 in a region below the well region 20 and form a pn junction with the first pillar region 21.

[0396] In this configuration, the electric field on the gate structure 15 is appropriately mitigated by the well region 20 below the gate structure 15. Furthermore, the depletion layer caused by the pn junction extends below the well region 20. This ensures that the electric field on the gate structure 15 is appropriately mitigated by the pn junction below the well region 20.

[0397] The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. The second pillar region 22 may have a bottom portion having a p-type impurity concentration lower than that of the well region 20. With these configurations, the depletion layer caused by the pn junction spreads appropriately below the well region 20.

[0398] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0399] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed on the surface layer of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10. The second pillar region 22 may be interposed between the body region 10 and the well region 20, electrically connecting the well region 20 to the body region 10.

[0400] In this configuration, the electrically floating state of the well region 20 is suppressed by the second pillar region 22. As a result, the electrical response characteristics of the well region 20 are improved, and the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0401] The well region 20 may have a p-type impurity concentration higher than that of the body region 10. This configuration appropriately improves the electrical response characteristics of the well region 20. In this case, the second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. This configuration appropriately expands the depletion layer below the well region 20 due to the second pillar region 22.

[0402] The semiconductor device 1A may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the first pillar region 21 in the thickness direction Z of the second semiconductor layer 7. With this configuration, a channel can be appropriately formed in the region between the first pillar region 21 and the source region 40.

[0403] The semiconductor device 1A may include a p-type contact region 41. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. With this configuration, the electrical response characteristics of the second pillar region 22 are improved by the contact region 41, and the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0404] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7 and a p-type network region 25. The second semiconductor layer 7 may have a first main surface 3. The network region 25 may extend in a network pattern in a first direction X and a second direction Y along the first main surface 3 at a thickness position spaced apart from the first main surface 3 within the second semiconductor layer 7. The network region 25 may partition the second semiconductor layer 7 into a plurality of n-type inter-network regions 26 that serve as a plurality of current paths.

[0405] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the current flowing through the second semiconductor layer 7 when it is ON is narrowed by the mesh region 25 (multiple intermesh regions 26), improving the short-circuit withstand capability. Furthermore, with this configuration, when the gate structure 15 is OFF and a drain voltage is applied, the depletion layer caused by the p-type mesh region 25 improves the electrical breakdown voltage.

[0406] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the short-circuit withstand capability improvement effect and the electrical breakdown voltage improvement effect of the mesh region 25 are effective.

[0407] The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0408] Multiple intermesh regions 26 may be partitioned in a row along the first direction X. Multiple intermesh regions 26 may be partitioned in a row along the second direction Y. Multiple intermesh regions 26 may be partitioned in a matrix along the first direction X and the second direction Y.

[0409] The mesh region 25 may include a plurality of p-type well regions 20 as a plurality of first fringe regions, and a plurality of p-type second pillar regions 22 as a plurality of second fringe regions.

[0410] The multiple well regions 20 may extend in a striped pattern in the first direction X at thickness positions spaced apart from the first main surface 3 within the second semiconductor layer 7. The multiple second pillar regions 22 may extend in a striped pattern in the second direction Y within the second semiconductor layer 7 so as to be connected to the multiple well regions 20 in a mesh-like manner, and may demarcate the multiple well regions 20 and the multiple inter-mesh regions 26.

[0411] The multiple second pillar regions 22 may have a p-type impurity concentration lower than that of the multiple well regions 20. The multiple second pillar regions 22 may have a bottom located below the bottom of the multiple well regions 20. With these configurations, the depletion layer caused by the network region 25 (multiple second pillar regions 22) spreads appropriately below the well regions 20.

[0412] The multiple second pillar regions 22 may extend vertically in the thickness direction Z of the second semiconductor layer 7 in a cross-sectional view. In this case, the multiple second pillar regions 22 may have portions located above the multiple well regions 20 and portions located below the multiple well regions 20. With this configuration, the depletion layer caused by the network region 25 (multiple second pillar regions 22) spreads appropriately at both depth positions above and below the multiple well regions 20.

[0413] The multiple intermesh regions 26 may have an n-type impurity concentration higher than that of the second semiconductor layer 7. In other words, the resistance values ​​of the multiple intermesh regions 26 may be lower than that of the second semiconductor layer 7. This configuration reduces energy loss due to the resistance values ​​of the multiple intermesh regions 26.

[0414] The semiconductor device 1A may include a plurality of n-type first pillar regions 21 as a plurality of third fringe regions. The plurality of first pillar regions 21 may be formed alternately with a plurality of second pillar regions 22 in a first direction X within the second semiconductor layer 7 and may extend in a fringe shape in a second direction Y within the second semiconductor layer 7 so as to intersect with a plurality of well regions 20.

[0415] Multiple first pillar regions 21 may form multiple intermesh regions 26. With this configuration, multiple intermesh regions 26 can be appropriately formed by multiple first pillar regions 21.

[0416] Multiple first pillar regions 21 may form pn junctions with multiple second pillar regions 22. With this configuration, the electrical breakdown voltage is improved by the depletion layer resulting from the pn junctions between the first pillar regions 21 and the second pillar regions 22.

[0417] The multiple first pillar regions 21 may have an n-type impurity concentration higher than that of the second semiconductor layer 7. In other words, the resistance values ​​of the multiple first pillar regions 21 may be lower than that of the second semiconductor layer 7. This configuration reduces energy loss due to the resistance values ​​of the multiple first pillar regions 21. Furthermore, the pn junction is appropriately adjusted by the n-type impurity concentration of the first pillar regions 21.

[0418] The first pillar region 21 may have a charge balance with respect to the second pillar region 22. With this configuration, the depletion layer caused by the pn junction is appropriately expanded. Multiple first pillar regions 21 may form a superjunction structure with multiple second pillar regions 22. With this configuration, the electrical withstand voltage is appropriately improved.

[0419] The semiconductor device 1A may include a trench 16 formed on the first main surface 3. In this case, the mesh region 25 may be formed in the second semiconductor layer 7 in a region below the trench 16. With this configuration, the short-circuit withstand capability improvement effect and the electrical withstand voltage improvement effect of the mesh region 25 can be obtained in the region below the trench 16.

[0420] The semiconductor device 1A may include a p-type body region 10 (surface region). The body region 10 may be formed on the surface of the first main surface 3. The mesh region 25 may be formed in the second semiconductor layer 7 in a region below the body region 10. With this configuration, the short-circuit withstand capability improvement effect and the electrical withstand voltage improvement effect of the mesh region 25 can be obtained in the region below the body region 10.

[0421] The semiconductor device 1A may include an n-type source region 40 (impurity region). The source region 40 may be located on the surface of the body region 10 and face the intermesh region 26 in the thickness direction Z of the second semiconductor layer 7. With this configuration, channels can be appropriately formed in the area overlapping the intermesh region 26.

[0422] The semiconductor device 1A may include a p-type contact region 41 (high-concentration region). The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be located on the surface of the body region 10 and face the mesh region 25 in the thickness direction Z of the second semiconductor layer 7. With this configuration, the electrical response characteristics of the body region 10 are improved, and channel formation locations are appropriately secured in the areas overlapping with the intermesh region 26.

[0423] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, a plurality of trenches 16, a plurality of p-type well regions 20 (first fringe regions), and a plurality of p-type second pillar regions 22 (second fringe regions). The second semiconductor layer 7 may have a first main surface 3. The plurality of trenches 16 may extend in a fringe pattern in a first direction X on the first main surface 3.

[0424] Multiple well regions 20 are each formed below multiple trenches 16 within the second semiconductor layer 7 and may extend in a striped pattern in a first direction X following the multiple trenches 16. Multiple second pillar regions 22 may extend in a striped pattern in a second direction Y intersecting the first direction X within the second semiconductor layer 7 so as to be connected to the multiple well regions 20 in a mesh-like manner. Multiple second pillar regions 22 may partition n-type intermesh regions 26 as current paths within the second semiconductor layer 7.

[0425] This configuration provides a novel semiconductor device 1A. For example, with this configuration, even if a relatively high voltage (drain voltage) is applied to the second semiconductor layer 7 when it is turned on, the current flowing through the second semiconductor layer 7 is narrowed by the intermesh region 26 in the region below the multiple trenches 16, thereby improving the short-circuit withstand capability. Furthermore, with this configuration, the electrical breakdown voltage when it is turned off is improved by the depletion layer resulting from the multiple well regions 20 and the multiple second pillar regions 22 in the region below the multiple trenches 16.

[0426] The semiconductor device 1A may include an n-type first pillar region 21. The first pillar region 21 may extend in a second direction Y within the second semiconductor layer 7 so as to intersect with a plurality of well regions 20.

[0427] In this case, the multiple second pillar regions 22 may be formed alternately with the first pillar regions 21 in the first direction X within the second semiconductor layer 7, and together with the multiple well regions 20, they may define an intermesh region 26 that includes at least a part of the first pillar regions 21. With this configuration, the intermesh region 26 can be properly formed by the first pillar regions 21.

[0428] The semiconductor device 1A may include a p-type body region 10 (surface region). The body region 10 may be formed on the surface of the first main surface 3. The multiple trenches 16 may penetrate the body region 10. With this configuration, in the region below the body region 10, the short-circuit withstand capability improvement effect and the electrical withstand voltage improvement effect can be obtained by the multiple well regions 20 and the multiple second pillar regions 22.

[0429] The semiconductor device 1A may include an n-type source region 40 (impurity region). The source region 40 may be located on the surface of the body region 10 and face the intermesh region 26 in the thickness direction Z of the second semiconductor layer 7. With this configuration, channels can be appropriately formed in the area overlapping the intermesh region 26.

[0430] The semiconductor device 1A may include a p-type contact region 41 (high-concentration region). The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. With this configuration, the electrical response characteristics of the body region 10 are improved, and channel formation locations are appropriately secured in the areas overlapping the intermesh region 26.

[0431] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, an n-type first pillar region 21, and a p-type second pillar region 22. The second semiconductor layer 7 may contain SiC. The second semiconductor layer 7 may have a base concentration CB due to a pentavalent element.

[0432] The first pillar region 21 has a base concentration CB and a first additional concentration C1 due to a pentavalent element added to the base concentration CB, and may extend in the thickness direction Z within the second semiconductor layer 7. The second pillar region 22 has a base concentration CB and a second additional concentration C2 due to a trivalent element added to the base concentration CB, and may extend in the thickness direction Z within the second semiconductor layer 7.

[0433] The second pillar region 22 may include a p-type second lower region 22L and a p-type second upper region 22U. The second lower region 22L may have a base concentration CB and a second additional concentration C2. The second upper region 22U may have a base concentration CB, a second additional concentration C2, and a correction concentration C3 due to a pentavalent element added to the base concentration CB to adjust the second additional concentration C2 downward.

[0434] This configuration provides a novel semiconductor device 1A. When trivalent and pentavalent elements are introduced into the second semiconductor layer 7 (SiC), the introduction efficiency of the trivalent elements differs from that of the pentavalent elements. Specifically, because trivalent elements are captured by the second semiconductor layer 7 at a shallower position than pentavalent elements, the concentration of trivalent elements at shallower positions in the second semiconductor layer 7 tends to be higher than that of pentavalent elements.

[0435] In this regard, according to semiconductor device 1A, a pentavalent element correction concentration C3 that lowers the second added concentration C2 of trivalent elements is introduced in the second upper region 22U of the second pillar region 22. As a result, the trivalent element concentration (p-type impurity concentration) in the second pillar region 22 is appropriately adjusted with respect to the pentavalent element concentration (n-type impurity concentration) in the first pillar region 21. Therefore, the electrical characteristics of semiconductor device 1A are appropriately improved.

[0436] The first pillar region 21 may extend along the axial channel of SiC. The second pillar region 22 may extend along the axial channel. With this configuration, the concentration of trivalent elements in the second pillar region 22 is appropriately adjusted with respect to the efficiency of introducing trivalent and pentavalent elements along the axial channel of SiC.

[0437] The second pillar region 22 may form a pn junction with the first pillar region 21. With this configuration, the pn junction is properly formed. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. With this configuration, the depletion layer caused by the pn junction is properly expanded. The second pillar region 22 may form a superjunction structure with the first pillar region 21. With this configuration, the electrical withstand voltage is appropriately improved.

[0438] The first pillar region 21 may have a first slow-change portion 32 in an intermediate thickness range where the rate of change in concentration is slow. The second pillar region 22 may have a second slow-change portion 35 in an intermediate thickness range where the rate of change in concentration is slow.

[0439] The first slow portion 32 may occupy a thickness range of 20% or more of the first pillar region 21. The second slow portion 35 may occupy a thickness range of 20% or more of the second pillar region 22. The second slow portion 35 may have a concentration ratio of 0.7 to 1.3 with respect to the concentration of the first slow portion 32. In this case, it is preferable that the second pillar region 22 has a charge balance with respect to the first pillar region 21.

[0440] The first additional concentration C1 may be caused by a pentavalent element of a different type from the pentavalent element of the base concentration CB. The base concentration CB may be caused by nitrogen as a pentavalent element. In this case, the first additional concentration C1 may be caused by a pentavalent element other than nitrogen.

[0441] The corrected concentration C3 may be caused by a pentavalent element of a different type from the pentavalent element of the base concentration CB. The base concentration CB may be caused by nitrogen as a pentavalent element. The corrected concentration C3 may be caused by a pentavalent element other than nitrogen. The second additional concentration C2 may be caused by one or both of boron and aluminum as trivalent elements.

[0442] The first pillar region 21 may extend in a strip shape in plan view. The second pillar region 22 may extend in a strip shape along the first pillar region 21 in plan view. The first pillar region 21 may extend along the a-axis direction of SiC in plan view. The second pillar region 22 may extend along the a-axis direction in plan view.

[0443] The semiconductor device 1A may include a gate structure 15. The gate structure 15 may be formed on the second semiconductor layer 7. In this case, the first pillar region 21 may have a portion extending in the thickness direction Z along the gate structure 15. The second pillar region 22 may have a portion extending in the thickness direction Z along the gate structure 15.

[0444] According to this configuration, in the portion along the gate structure 15, the trivalent element concentration of the second pillar region 22 with respect to the pentavalent element concentration of the first pillar region 21 is appropriately adjusted. Accordingly, the electric field applied to the gate structure 15 is appropriately relaxed by the first pillar region 21 and the second pillar region 22.

[0445] The first pillar region 21 may intersect the gate structure 15. The second pillar region 22 may intersect the gate structure 15. According to this configuration, the first pillar region 21 secures a formation position for a channel portion along the gate structure 15, and the second pillar region 22 limits a formation position for a non-channel portion along the gate structure 15. Accordingly, a decrease in current processing capacity caused by a reduction in channel area is suppressed, and electrical withstand voltage is improved.

[0446] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed in the second semiconductor layer 7 below the gate structure 15. According to this configuration, the electric field applied to the gate structure 15 is relaxed by the well region 20 below the gate structure 15. The second pillar region 22 may be electrically connected to the well region 20. According to this configuration, the well region 20 and the second pillar region 22 are appropriately electrically interlocked.

[0447] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed in a surface layer portion of the second semiconductor layer 7. In this case, the second pillar region 22 may be electrically connected to the body region 10.

[0448] The semiconductor device 1A may include an n-type source region 40. The source region 40 may face the first pillar region 21 in the thickness direction Z at a surface layer portion of the body region 10. According to this configuration, a channel can be appropriately formed in a region between the first pillar region 21 and the source region 40.

[0449] The semiconductor device 1A may include a p-type contact region 41. The contact region 41 may have a p-type impurity concentration higher than that of the body region 10. The contact region 41 may face the second pillar region 22 in the thickness direction Z at a surface layer portion of the body region 10. According to this configuration, the electrical response characteristics of the body region 10 are improved by the contact region 41, and a channel formation site is appropriately secured in a region outside the second pillar region 22.

[0450] From another perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, a trench-type gate structure 15, an n-type first pillar region 21, and a p-type second pillar region 22. The second semiconductor layer 7 may have a first main surface 3. The gate structure 15 may be formed on the first main surface 3 and extend in a first direction X along the first main surface 3.

[0451] The first pillar region 21 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may extend in a second direction Y so as to intersect the gate structure 15 within the second semiconductor layer 7 and form a pn junction with the first pillar region 21.

[0452] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the depletion layer caused by the pn junction between the first pillar region 21 and the second pillar region 22 improves the electrical breakdown voltage. In addition, the first pillar region 21 ensures the formation of a channel portion along the gate structure 15, and the second pillar region 22 limits the formation of a non-channel portion along the gate structure 15. This suppresses the decrease in current processing capability caused by the reduction in channel area.

[0453] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC. In particular, since SiC semiconductor devices are used in relatively high voltage environments, the breakdown voltage improvement effect of the first pillar region 21 and the second pillar region 22 is effective.

[0454] The first pillar region 21 may have a portion that intersects the gate structure 15 below it. The second pillar region 22 may have a portion that intersects the gate structure 15 below it and forms a pn junction with the first pillar region 21 below it. With this configuration, the electric field on the gate structure 15 is mitigated by the pn junction below the gate structure 15.

[0455] The semiconductor device 1A may include a p-type well region 20 formed below the gate structure 15 within the second semiconductor layer 7. With this configuration, the electric field on the gate structure 15 is mitigated by the well region 20 below the gate structure 15.

[0456] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0457] The second pillar region 22 may have a bottom located below the bottom of the well region 20. With this configuration, the electric field for the gate structure 15 is mitigated by the second pillar region 22 from below the well region 20.

[0458] The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. The second pillar region 22 may have a bottom portion having a p-type impurity concentration lower than that of the well region 20. With these configurations, the depletion layer originating from the second pillar region 22 expands appropriately.

[0459] The first pillar region 21 may have a portion that intersects the well region 20 below it. The second pillar region 22 may have a portion that intersects the well region 20 below it and forms a pn joint with the first pillar region 21 below it.

[0460] In this configuration, the depletion layer caused by the pn junction between the first pillar region 21 and the second pillar region 22 extends below the well region 20. As a result, the electric field for the gate structure 15 is relaxed from below the well region 20.

[0461] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed on the surface layer of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10.

[0462] The first pillar region 21 may be formed below the body region 10. The second pillar region 22 may also be formed below the body region 10. With this configuration, a pressure-resistant effect can be obtained below the body region 10 due to the pn joint between the first pillar region 21 and the second pillar region 22.

[0463] The well region 20 may have a p-type impurity concentration higher than that of the body region 10. This configuration appropriately improves the electrical response characteristics of the well region 20. In this case, the second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. This configuration appropriately expands the depletion layer caused by the second pillar region 22.

[0464] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, a p-type body region 10, a trench-type gate structure 15, an n-type first pillar region 21, and a p-type second pillar region 22. The second semiconductor layer 7 may have a first main surface 3. The body region 10 may be formed on the surface layer of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 so as to penetrate the body region 10 and extend in a first direction X along the first main surface 3.

[0465] The first pillar region 21 may be formed below the body region 10 within the second semiconductor layer 7 and may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15. The second pillar region 22 may be formed below the body region 10 within the second semiconductor layer 7 and may extend in a second direction Y so as to intersect the gate structure 15.

[0466] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the depletion layer caused by the first pillar region 21 and the second pillar region 22 extends below the body region 10. As a result, a pressure resistance improvement effect is obtained below the body region 10 due to the first pillar region 21 and the second pillar region 22.

[0467] Furthermore, the first pillar region 21 ensures the formation of channel portions along the gate structure 15, while the second pillar region 22 restricts the formation of non-channel portions along the gate structure 15. This suppresses the reduction in current processing capacity caused by the reduction in channel area.

[0468] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC.

[0469] In particular, since SiC semiconductor devices are used in relatively high voltage environments, the voltage-breaking effect of the first pillar region 21 and the second pillar region 22 is effective. The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC.

[0470] The semiconductor device 1A may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the first pillar region 21 in the thickness direction Z. With this configuration, a channel can be appropriately formed in the region between the first pillar region 21 and the source region 40.

[0471] The semiconductor device 1A may include a p-type contact region 41. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z. With this configuration, the electrical response characteristics of the second pillar region 22 are improved by the contact region 41, and the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0472] The semiconductor device 1A may include an n-type cap region 42. The cap region 42 may be formed along the gate structure 15 within the second semiconductor layer 7 so as to be interposed between the body region 10 and a portion of the second pillar region 22 in a cross-sectional view. With this configuration, a current path is formed via the cap region 42 near the second pillar region 22, reducing on-resistance.

[0473] The cap region 42 may be connected to the first pillar region 21. With this configuration, a current path is formed through the first pillar region 21 and the cap region 42, and the on-resistance is appropriately reduced.

[0474] The cap region 42 has an n-type impurity concentration higher than the p-type impurity concentration of the second pillar region 22, and may replace part of the second pillar region 22 by changing its conductivity type from p-type to n-type. According to this configuration, the cap region is appropriately interposed between the body region and a part of the second pillar region in a cross-sectional view. The cap region 42 may be formed spaced apart from the bottom wall of the gate structure 15 toward the first main surface 3 side.

[0475] The cap region 42 may face the source region 40 with the body region 10 interposed therebetween. According to this configuration, a channel can be appropriately formed in a region between the source region 40 and the cap region 42.

[0476] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 in the second semiconductor layer 7. According to this configuration, an electric field applied to the gate structure 15 is relaxed by the well region 20 below the gate structure 15.

[0477] The second pillar region 22 may electrically connect the well region 20 to the body region 10. According to this configuration, an electrically floating state of the well region 20 is suppressed by the second pillar region 22, and the electrical response characteristics of the well region 20 are improved.

[0478] From another perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, a trench-type gate structure 15, a plurality of n-type first pillar regions 21, and a plurality of p-type second pillar regions 22. The second semiconductor layer 7 may have the first main surface 3. The gate structure 15 may extend in one direction on the first main surface 3.

[0479] The plurality of first pillar regions 21 may be formed in a region directly below the gate structure 15 in the second semiconductor layer 7, spaced apart from each other in one direction along the extending direction of the gate structure 15. The plurality of second pillar regions 22 may be alternately formed with the plurality of first pillar regions 21 in one direction in the region directly below the gate structure 15 in the second semiconductor layer 7, and form pn junctions with the plurality of first pillar regions 21.

[0480] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the electrical breakdown voltage is improved by the pn junctions between a plurality of first pillar regions 21 and a plurality of second pillar regions 22 in the region directly below the gate structure 15.

[0481] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC.

[0482] In particular, since SiC semiconductor devices are used in relatively high voltage environments, the voltage-breaking effect of the multiple first pillar regions 21 and the multiple second pillar regions 22 is effective. The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC. The other direction may be the m-axis direction of SiC.

[0483] Multiple first pillar regions 21 may have an n-type impurity concentration higher than that of the second semiconductor layer 7. With this configuration, the pn junction is appropriately adjusted by the n-type impurity concentration of the first pillar regions 21.

[0484] The multiple second pillar regions 22 may have a charge balance with respect to the multiple first pillar regions 21 in the region directly below the gate structure 15. With this configuration, the depletion layer caused by the pn junction is appropriately expanded in the region directly below the gate structure 15. The multiple second pillar regions 22 may form a superjunction structure with the multiple first pillar regions 21 in the region directly below the gate structure 15. With this configuration, the electrical withstand voltage is appropriately improved.

[0485] The multiple second pillar regions 22 may be shallower than the multiple first pillar regions 21. The multiple second pillar regions 22 may be deeper than the multiple first pillar regions 21. The multiple second pillar regions 22 may include portions having a p-type impurity concentration lower than the n-type impurity concentration of the multiple first pillar regions 21. The multiple second pillar regions 22 may include portions having a p-type impurity concentration higher than the n-type impurity concentration of the multiple first pillar regions 21.

[0486] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed in the second semiconductor layer 7 in the region directly below the gate structure 15. With this configuration, the electric field on the gate structure 15 is appropriately mitigated by the well region 20 below the gate structure 15.

[0487] In this case, the multiple second pillar regions 22 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the pn junction is appropriately regulated by the p-type impurity concentration of the second pillar regions 22, and the depletion layer starting from the pn junction expands appropriately.

[0488] Multiple second pillar regions 22 may be connected to the well region 20. With this configuration, the well region 20 and the second pillar regions 22 are appropriately electrically interlocked. Multiple first pillar regions 21 may also be connected to the well region 20.

[0489] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0490] The semiconductor device 1A may include a p-type body region 10. The body region 10 may be formed on the surface layer of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10. The multiple second pillar regions 22 may be electrically connected to the body region 10. With this configuration, the body region 10 and the multiple second pillar regions 22 are appropriately electrically interconnected.

[0491] The second pillar region 22 may electrically connect the well region 20 to the body region 10. With this configuration, the electrical floating state of the well region 20 is suppressed by the second pillar region 22, and the electrical response characteristics of the well region 20 are improved. As a result, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0492] The semiconductor device 1A may include an n-type source region 40. The source region 40 may be formed on the surface of the body region 10. With this configuration, a channel can be formed on the surface of the body region 10.

[0493] The semiconductor device 1A may include a p-type contact region 41. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be formed on the surface of the body region 10. With this configuration, the electrical response characteristics of the body region 10 are improved by the contact region 41.

[0494] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, an active region 8, an outer region 9, a trench-type gate structure 15, a p-type second pillar region 22, and a p-type field region 47. The second semiconductor layer 7 may have a first main surface 3. The active region 8 may be provided in the inner part of the first main surface 3. The outer region 9 may be provided at the periphery of the first main surface 3.

[0495] The gate structure 15 may be formed on the first main surface 3 in the active region 8. The second pillar region 22 may be formed deeper than the gate structure 15 within the second semiconductor layer 7 of the active region 8. The field region 47 may be formed within the second semiconductor layer 7 of the outer region 9.

[0496] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the electrical breakdown voltage of the active region 8 is improved by the depletion layer originating from the second pillar region 22, and the electrical breakdown voltage of the outer region 9 is improved by the depletion layer originating from the field region 47.

[0497] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC.

[0498] In particular, since SiC semiconductor devices are used in relatively high voltage environments, the voltage breakdown improvement effect of the active region 8 and the voltage breakdown improvement effect of the outer region 9 are effective. The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC.

[0499] The field region 47 may be formed deeper than the gate structure 15. With this configuration, the electrical breakdown voltage of the active region 8 is improved by the second pillar region 22 which is deeper than the gate structure 15, and the electrical breakdown voltage of the outer region 9 is improved by the field region 47 which is deeper than the gate structure 15.

[0500] The gate structure 15 may extend in a first direction X along the first main surface 3. In this case, the second pillar region 22 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15. This configuration relaxes the design rule restrictions of the second pillar region 22 with respect to the gate structure 15. As a result, the channel formation area is appropriately secured in an area outside the second pillar region 22, and the pressure resistance improvement effect of the second pillar region 22 is appropriately realized.

[0501] The field region 47 may have a portion extending in a first direction X and a portion extending in a second direction Y. With this configuration, the electrical withstand voltage of the outer region 9 is appropriately improved by the field region 47.

[0502] The field region 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. With this configuration, the electric field at the edge portion of the field region 47 is appropriately mitigated.

[0503] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. With this configuration, the electric field for the gate structure 15 is mitigated by the well region 20 below the gate structure 15. The second pillar region 22 may be electrically connected to the well region 20. With this configuration, the well region 20 and the second pillar region 22 are appropriately electrically linked.

[0504] The second pillar region 22 may be formed deeper than the well region 20. With this configuration, the electric field for the gate structure 15 is relaxed by the second pillar region 22 from below the well region 20. The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the depletion layer caused by the multiple second pillar regions 22 spreads appropriately.

[0505] The field region 47 may be formed deeper than the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the field region 47 which is deeper than the well region 20. Such a configuration is particularly effective when a second pillar region 22 which is deeper than the well region 20 is formed.

[0506] The field region 47 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the field region 47, which has a lower concentration than the well region 20. This configuration is particularly effective when a second pillar region 22 with a lower concentration than the well region 20 is formed.

[0507] The semiconductor device 1A may include a p-type outer well region 45. The outer well region 45 may be formed within the second semiconductor layer 7 of the outer region 9. In this case, the field region 47 may be formed with a gap between it and the outer well region 45 on the peripheral side of the first main surface 3. With this configuration, the electrical breakdown voltage of the peripheral portion of the active region 8 is improved by the depletion layer caused by the outer well region 45.

[0508] The outer well region 45 may be formed deeper than the gate structure 15. With this configuration, the electrical breakdown voltage of the peripheral edge of the active region 8 is improved by the outer well region 45 which is deeper than the gate structure 15. Such a configuration is particularly effective when a second pillar region 22 which is deeper than the gate structure 15 is formed.

[0509] The semiconductor device 1A may include an interlayer film 50. The interlayer film 50 may cover the first main surface 3 in an active region 8 and an outer region 9. In this case, the semiconductor device 1A may include a gate finger 65 as an example of a gate electrode. The gate finger 65 may contain a metal. The gate finger 65 may be positioned on the interlayer film 50 in the outer region 9 and electrically connected to the gate structure 15.

[0510] The gate finger 65 may be positioned at a distance from the field region 47 towards the active region 8. This configuration prevents the field region 47 from shielding the electric field dispersion path with the gate finger 65. As a result, the electric field (electric field lines) in the outer region 9 is appropriately dispersed by the field region 47.

[0511] The semiconductor device 1A may include gate wiring 55. The gate wiring 55 may include a non-metallic conductor. The gate wiring 55 may be located within the interlayer film 50 in the outer region 9 and electrically connected to the gate structure 15. The gate wiring 55 may be spaced apart from the field region 47 towards the active region 8.

[0512] This configuration prevents the field region 47 from being shielded by the gate wiring 55, thereby ensuring that the electric field (electric field lines) in the outer region 9 is properly dispersed by the field region 47. The gate finger 65 may also be electrically connected to the gate wiring 55 by penetrating the interlayer film 50.

[0513] The semiconductor device 1A may include a source finger 63 as an example of a source electrode. The source finger 63 may be positioned on the interlayer film 50 in the outer region 9 and electrically connected to regions other than the gate structure 15.

[0514] The source finger 63 may be positioned at a distance from the field region 47 toward the active region 8. This configuration suppresses the shielding of the electric field dispersion path by the field region 47 by the source finger 63. As a result, the electric field (electric field lines) in the outer region 9 is appropriately dispersed by the field region 47. The source finger 63 may also be positioned on the interlayer film 50 at a distance from the gate finger 65 toward the periphery of the first main surface 3 in the outer region 9.

[0515] From an alternative perspective, the semiconductor device 1A may include an n-type second semiconductor layer 7, an active region 8, an outer region 9, a trench-type gate structure 15, a p-type second pillar region 22, and a p-type outer well region 45. The second semiconductor layer 7 may have a first main surface 3. The active region 8 may be provided in the inner part of the first main surface 3.

[0516] The outer region 9 may be provided on the periphery of the first main surface 3. The gate structure 15 may be formed on the first main surface 3 in the active region 8. The second pillar region 22 may be formed deeper than the gate structure 15 within the second semiconductor layer 7 of the active region 8. The outer well region 45 may be formed within the second semiconductor layer 7 of the outer region 9.

[0517] This configuration provides a novel semiconductor device 1A. For example, with this configuration, the electrical breakdown voltage of the active region 8 is improved by the depletion layer originating from the second pillar region 22, and the electrical breakdown voltage of the outer region 9 is improved by the depletion layer originating from the outer well region 45. The outer well region 45 may be biased toward the active region 8 side relative to the periphery of the first main surface 3 in the outer region 9.

[0518] The outer well region 45 may be formed deeper than the gate structure 15. With this configuration, the electrical breakdown voltage of the active region 8 is improved by the second pillar region 22 which is deeper than the gate structure 15, and the electrical breakdown voltage of the outer region 9 is improved by the outer well region 45 which is deeper than the gate structure 15.

[0519] The gate structure 15 may extend in a first direction X along the first main surface 3. In this case, the second pillar region 22 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15. This configuration relaxes the design rule restrictions of the second pillar region 22 with respect to the gate structure 15. As a result, the channel formation area is appropriately secured in an area outside the second pillar region 22, and the pressure resistance improvement effect of the second pillar region 22 is appropriately realized.

[0520] The outer well region 45 may have a portion extending in a first direction X and a portion extending in a second direction Y. With this configuration, the electrical withstand voltage of the outer region 9 is appropriately improved by the outer well region 45.

[0521] The outer well region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape. With this configuration, the electric field at the edge portion of the outer well region 45 is appropriately mitigated.

[0522] The semiconductor device 1A may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. With this configuration, the electric field for the gate structure 15 is mitigated by the well region 20 below the gate structure 15. The second pillar region 22 may be electrically connected to the well region 20. With this configuration, the well region 20 and the second pillar region 22 are appropriately electrically linked.

[0523] The second pillar region 22 may be formed deeper than the well region 20. With this configuration, the electric field for the gate structure 15 is relaxed by the second pillar region 22 from below the well region 20. The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the depletion layer caused by the multiple second pillar regions 22 spreads appropriately.

[0524] The outer well region 45 may be formed deeper than the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the outer well region 45, which is deeper than the well region 20. Such a configuration is particularly effective when a second pillar region 22, which is deeper than the well region 20, is formed.

[0525] The outer well region 45 may have a lower p-type impurity concentration than the well region 20. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the outer well region 45, which has a lower concentration than the well region 20. This configuration is particularly effective when a second pillar region 22 with a lower concentration than the well region 20 is formed.

[0526] The semiconductor device 1A may include at least one p-type field region 47. The field region 47 may be formed within the second semiconductor layer 7 of the outer region 9, spaced apart from the outer well region 45 to the periphery of the first main surface 3. With this configuration, the electrical breakdown voltage of the outer region 9 is improved by the depletion layer caused by both the outer well region 45 and the field region 47.

[0527] Figure 23 is an enlarged plan view showing the active region 8 of the semiconductor device 1B according to the second embodiment. Figure 24 is a cross-sectional view along the line XXIV-XXIV shown in Figure 23. Figure 25 is a cross-sectional view along the line XXV-XXV shown in Figure 23. Figure 26 is a cross-sectional view along the line XXVI-XXVI shown in Figure 23. Figure 27 is a cross-sectional view along the line XXVII-XXVII shown in Figure 23. Figure 28 is a cross-sectional perspective view of the active region 8 shown in Figure 23.

[0528] Referring to Figures 23 to 28, in the semiconductor device 1B, the multiple second pillar regions 22 are formed shallower than the multiple first pillar regions 21. In other words, the second bottom portions 22B of the multiple second pillar regions 22 are located on the first main surface 3 side than the depth position of the first bottom portions 21B of the multiple first pillar regions 21.

[0529] The multiple second bottom portions 22B are located below the depth of the bottom walls of the multiple gate structures 15. Each of the multiple second bottom portions 22B has a portion located in the region directly below the multiple gate structures 15, and a portion located outside the region directly below the multiple gate structures 15.

[0530] Specifically, the multiple second bottom portions 22B are located below the bottoms of the multiple well regions 20. Each of the multiple second bottom portions 22B has a portion located directly below the multiple well regions 20 and a portion located outside the region directly below the multiple well regions 20.

[0531] The multiple second bottoms 22B are located in the region directly below the multiple gate structures 15 (well region 20), and are positioned closer to the bottom wall of the multiple gate structures 15 (towards the bottom of the well region 20) than the multiple first bottoms 21B. The depth positions of the multiple first bottoms 21B and the multiple second bottoms 22B alternately increase and decrease along the horizontal direction (first direction X).

[0532] The multiple second bottom portions 22B, together with the sides (protruding sides) of the multiple first pillar regions 21 adjacent to each other in the first direction X, demarcate a low-density region that is part of the second semiconductor layer 7. In other words, the multiple second bottom portions 22B are electrically connected to a part of the second semiconductor layer 7 (low-density region) that has a lower density than the multiple first pillar regions 21.

[0533] The second bottom portion 22B may be formed at a distance greater than 0 nm and less than or equal to 500 nm in the thickness direction Z from the depth position of the first bottom portion 21B. The distance of the second bottom portion 22B to the first bottom portion 21B may be a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, 250 nm to 300 nm, 300 nm to 350 nm, 350 nm to 400 nm, 400 nm to 450 nm, and 450 nm to 500 nm.

[0534] As described above, the semiconductor device 1B may include an n-type second semiconductor layer 7, a trench-type gate structure 15, an n-type first pillar region 21, and a p-type second pillar region 22. The second semiconductor layer 7 may have a first main surface 3. The gate structure 15 may be formed on the first main surface 3.

[0535] The first pillar region 21 may have an n-type impurity concentration higher than that of the second semiconductor layer 7. The first pillar region 21 may be formed along the gate structure 15 within the second semiconductor layer 7. The first pillar region 21 may have a first bottom portion 21B located below the depth position of the bottom wall of the gate structure 15.

[0536] The second pillar region 22 may be formed along the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may have a second bottom portion 22B located closer to the bottom wall of the gate structure 15 than the depth position of the first bottom portion 21B of the first pillar region 21. The second pillar region 22 may form a pn junction with the first pillar region 21.

[0537] This configuration provides a novel semiconductor device 1B. In this configuration, the second pillar region 22 is formed shallower than the first pillar region 21 and is electrically connected to a portion of the second semiconductor layer 7 that is less dense than the first pillar region 21 and is located on the first main surface 3 side of the first pillar region 21. As a result, the JFET resistance is reduced by the relatively deep first pillar region 21 when the device is on, and the electric field concentration on the second pillar region 22 is mitigated when the device is off.

[0538] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1B. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC.

[0539] In particular, since SiC semiconductor devices are used in relatively high voltage environments, the effects of reducing JFET resistance and improving electrical breakdown voltage are effective. The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC.

[0540] The gate structure 15 may extend in a first direction X along the first main surface 3. The first pillar region 21 may extend in a second direction Y along the first main surface 3 so as to intersect the gate structure 15 below it. The second pillar region 22 may extend in a second direction Y so as to intersect the gate structure 15 below it.

[0541] In this configuration, the pn junction between the first pillar region 21 and the second pillar region 22 is extended in the second direction Y. This improves the electrical breakdown voltage of the pn junction. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0542] The first pillar region 21 may have a portion located above the bottom wall of the gate structure 15. The second pillar region 22 may have a portion located above the bottom wall of the gate structure 15. The second pillar region 22 may form a pn joint with the first pillar region 21 at depth positions above and below the bottom wall of the gate structure 15.

[0543] In this configuration, the depletion layer caused by the pn junction extends at depths both above and below the bottom wall of the gate structure 15. This appropriately improves the electrical withstand voltage. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. In this configuration, the depletion layer caused by the pn junction is appropriately expanded.

[0544] The semiconductor device 1B may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. With this configuration, the electric field for the gate structure 15 is mitigated by the well region 20 below the gate structure 15.

[0545] In this case, the second pillar region 22 may have a portion formed below the well region 20. With this configuration, the depletion layer caused by the second pillar region 22 extends below the well region 20. As a result, the electric field for the gate structure 15 is appropriately mitigated by the second pillar region 22 below the well region 20.

[0546] The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. The second bottom portion 22B of the second pillar region 22 may also have a p-type impurity concentration lower than that of the well region 20. With these configurations, the depletion layer originating from the second pillar region 22 spreads appropriately below the well region 20.

[0547] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend along the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0548] The semiconductor device 1B may include a p-type body region 10. The body region 10 may be formed on the surface layer of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10.

[0549] The second pillar region 22 may be interposed between the body region 10 and the well region 20, electrically connecting the well region 20 to the body region 10. With this configuration, the electrical floating state of the well region 20 is suppressed by the second pillar region 22. This improves the electrical response characteristics of the well region 20.

[0550] The well region 20 may have a p-type impurity concentration higher than that of the body region 10. This configuration appropriately improves the electrical response characteristics of the well region 20 and the electric field relaxation effect provided by the well region 20. The second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. This configuration appropriately expands the depletion layer caused by the second pillar region 22.

[0551] The first pillar region 21 may be formed below the body region 10. The second pillar region 22 may also be formed below the body region 10. With this configuration, a pressure-resistant effect can be obtained below the body region 10 due to the pn joint between the first pillar region 21 and the second pillar region 22.

[0552] The semiconductor device 1B may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the first pillar region 21 in the thickness direction Z of the second semiconductor layer 7. With this configuration, a channel can be appropriately formed in the region between the first pillar region 21 and the source region 40.

[0553] The semiconductor device 1B may include a p-type contact region 41. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z of the second semiconductor layer 7. With this configuration, the electrical response characteristics of the body region 10 are improved by the contact region 41, and the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0554] Figure 29 is an enlarged plan view showing the active region 8 of the semiconductor device 1C according to the third embodiment. Figure 30 is a cross-sectional view along the line XXX-XXX shown in Figure 29. Figure 31 is a cross-sectional view along the line XXXI-XXXI shown in Figure 29. Figure 32 is a cross-sectional perspective view of the active region 8 shown in Figure 29. Referring to Figures 29 to 32, the semiconductor device 1C has a modified form of the semiconductor device 1B.

[0555] Specifically, in semiconductor device 1C, the extension directions of the multiple first pillar regions 21 and the multiple second pillar regions 22 are changed relative to the extension direction of the multiple gate structures 15 (multiple well regions 20). The multiple gate structures 15 (multiple well regions 20) extend in a strip shape in the first direction X, as in semiconductor device 1A, and are arranged with gaps in the second direction Y.

[0556] In this configuration, the first direction X is the m-axis direction of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0557] In this configuration, the multiple first pillar regions 21 are each formed in the regions between the multiple gate structures 15 and each extends in a strip-like manner in the first direction X, following the direction of extension of the multiple gate structures 15.

[0558] The multiple first pillar regions 21, as in the semiconductor device 1A, each have an upper end portion (first upper region 21U) located on the first main surface 3 side with respect to the bottom wall of the multiple gate structures 15, and a lower end portion (first lower region 21L) located on the bottom side of the second semiconductor layer 7 with respect to the bottom wall of the multiple gate structures 15.

[0559] The upper end of the first pillar region 21 is interposed in the region between the multiple gate structures 15 and extends in a strip shape in the first direction X. The upper end of the first pillar region 21 is connected to the multiple adjacent gate structures 15 in the first direction X and faces the corresponding embedded electrode 18 via the corresponding insulating film 17. The upper end of the first pillar region 21 is connected to the body region 10.

[0560] The lower end of the first pillar region 21 extends in a first direction X in a region below the bottom walls of the multiple gate structures 15, and has a first bottom portion 21B located below the bottom walls of the multiple gate structures 15. The first bottom portion 21B is located below the bottom of the well region 20.

[0561] In this configuration, the multiple second pillar regions 22 are each formed in the region directly beneath the multiple gate structures 15 and overlap with the multiple gate structures 15 in a one-to-one correspondence in the thickness direction Z. The multiple second pillar regions 22 each extend in a strip shape in the first direction X, following the extending direction of the multiple gate structures 15, and form a pn joint with the multiple first pillar regions 21 located on both sides in the second direction Y.

[0562] Of course, the second pillar regions 22 may be formed at intervals in the first direction X in a one-to-many correspondence with respect to one gate structure 15. In this case, the multiple second pillar regions 22 may extend in a strip-like manner in the first direction X.

[0563] In this configuration, the multiple second pillar regions 22 are each formed in the region directly below the multiple well regions 20 and overlap with the multiple well regions 20 in a one-to-one correspondence in the thickness direction Z. The multiple second pillar regions 22 each have an upper end located on the bottom wall side of the multiple gate structures 15 and a lower end located on the bottom side of the second semiconductor layer 7.

[0564] The upper end of the second pillar region 22 extends in a strip shape in the first direction X and is connected to the corresponding well region 20. The lower end of the second pillar region 22 extends in a strip shape in the first direction X and has a second bottom 22B located on the bottom wall side of the corresponding gate structure 15, which is located at a depth position of the first bottom 21B of the first pillar region 21. The distance of the second bottom 22B to the first bottom 21B may be greater than 0 nm and 500 nm or less, as in the case of the semiconductor device 1B.

[0565] In this configuration, the multiple second pillar regions 22 have a charge balance with respect to the multiple first pillar regions 21 in the region directly below the multiple gate structures 15 (well regions 20). In other words, the multiple second pillar regions 22 form a superjunction structure with the multiple first pillar regions 21 in the region directly below the multiple gate structures 15 (well regions 20).

[0566] The aforementioned multiple contact regions 41 are formed on the surface of the body region 10 at intervals in the first direction X, following the direction of extension of the multiple gate structures 15, similar to the case of semiconductor device 1A. In this configuration, the multiple contact regions 41 are connected to the multiple gate structures 15 in the second direction Y.

[0567] In this configuration, the multiple contact regions 41 each include a first contact region 41A formed along the first main surface 3 on the surface layer of the body region 10, and a second contact region 41B extending along the side walls of the multiple gate structures 15.

[0568] The first contact region 41A is formed at a distance from the bottom of the body region 10 toward the first main surface 3 and faces the second pillar region 22 corresponding to the thickness direction Z via a part of the body region 10. The second contact region 41B is drawn out from the first contact region 41A toward the bottom wall of the corresponding gate structure 15 and extends along the side wall of the corresponding gate structure 15.

[0569] The second contact region 41B is connected to the corresponding well region 20 on the bottom wall side of the corresponding gate structure 15. As a result, the second contact region 41B is interposed between the first contact region 41A and the corresponding well region 20, electrically connecting the corresponding well region 20 to the body region 10 and the first contact region 41A.

[0570] The width of the second contact area 41B may be smaller than the thickness of the first contact area 41A. The thickness of the first contact area 41A is the thickness in the thickness direction Z with respect to the first main surface 3. The width of the second contact area 41B is the width in the horizontal direction (second direction Y) with respect to the side wall of the gate structure 15.

[0571] The aforementioned multiple cap regions 42 are formed in the regions between the multiple gate structures 15 and below the body region 10, similar to the case of semiconductor device 1A. In this embodiment, the multiple cap regions 42 are formed in a one-to-one correspondence between the regions between the multiple gate structures 15.

[0572] The multiple cap regions 42 each extend in a strip-like manner in the first direction X, following the direction of extension of the multiple gate structures 15. The multiple cap regions 42 are connected to the upper ends (first upper regions 21U) of the multiple first pillar regions 21, increasing the n-type impurity concentration at the upper ends (first upper regions 21U).

[0573] As described above, semiconductor device 1C may include an n-type second semiconductor layer 7, a trench-type gate structure 15, an n-type first pillar region 21, and a p-type second pillar region 22, similar to semiconductor device 1B. The second semiconductor layer 7 may have a first main surface 3. The gate structure 15 may be formed on the first main surface 3.

[0574] The first pillar region 21 may have an n-type impurity concentration higher than that of the second semiconductor layer 7. The first pillar region 21 may be formed along the gate structure 15 within the second semiconductor layer 7. The first pillar region 21 may have a first bottom portion 21B located below the depth position of the bottom wall of the gate structure 15.

[0575] The second pillar region 22 may be formed along the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may have a second bottom portion 22B located closer to the bottom wall of the gate structure 15 than the depth position of the first bottom portion 21B of the first pillar region 21. The second pillar region 22 may form a pn junction with the first pillar region 21.

[0576] This configuration provides a novel semiconductor device 1C. In this configuration, the second pillar region 22 is formed shallower than the first pillar region 21 and is electrically connected to a portion of the second semiconductor layer 7 that is less dense than the first pillar region 21 and is located on the first main surface 3 side of the first pillar region 21. As a result, the JFET resistance is reduced by the relatively deep first pillar region 21 when the device is on, and the electric field concentration on the second pillar region 22 is mitigated when the device is off.

[0577] Figure 33 is a cross-sectional perspective view showing the active region 8 of the semiconductor device 1D according to the fourth embodiment. Figure 34 is a graph illustrating the n-type impurity concentration in the first pillar region 21 along the first vertical line L1 (see dashed line) shown in Figure 33, and the p-type impurity concentration in the second pillar region 22 along the second vertical line L2 (see dashed line) shown in Figure 33. In Figure 34, the vertical axis represents the impurity concentration [cm³]. －３ The horizontal axis shows the depth [μm] relative to the depth position of 1 μm from the first main surface 3.

[0578] Referring to Figure 33, the first vertical line L1 is set to extend from the lower part of the first upper region 21U of the first pillar region 21, through the first lower region 21L of the first pillar region 21, to the second semiconductor layer 7. The second vertical line L2 is set to extend from the lower part of the second upper region 22U of the second pillar region 22, through the second lower region 22L of the second pillar region 22, to the second semiconductor layer 7.

[0579] The second bottom 22B of the second pillar region 22 is located on the bottom wall side of the gate structure 15 with respect to the depth position of the first bottom 21B of the first pillar region 21. Of course, the second bottom 22B may be located at approximately the same depth as the first bottom 21B. The second bottom 22B may also be located on the bottom side of the second semiconductor layer 7 with respect to the depth position of the first bottom 21B.

[0580] Figure 34 shows the first density gradient G1 (see thick line) of the first pillar region 21 related to the first vertical line L1, and the second density gradient G2 (see thin line) of the second pillar region 22 related to the second vertical line L2. In this configuration, the base density CB is 1 × 10⁻¹⁰, as in the case of semiconductor device 1A. １６ cm －３ It is set to a certain extent. Also, the depth of the gate structure 15 is set to approximately 1.2 μm.

[0581] The first concentration gradient G1 has a first increasing section 31, a first slowing section 32, and a first decreasing section 33, similar to the case of semiconductor device 1A. The second concentration gradient G2 has a second increasing section 34, a second slowing section 35, and a second decreasing section 36, similar to the case of semiconductor device 1A.

[0582] The semiconductor device 1D has the same configuration as semiconductor device 1A, and the p-type impurity concentration of the second pillar region 22 is adjusted relative to the n-type impurity concentration of the first pillar region 21. Specifically, the second lower region 22L of the second pillar region 22 has a lower p-type impurity concentration than the n-type impurity concentration of the first lower region 21L of the first pillar region 21.

[0583] In other words, in the semiconductor device 1D, the first pillar region 21 (first lower region 21L) has a relatively high n-type impurity concentration in the region directly below the multiple gate structures 15, while the second pillar region 22 (second lower region 22L) has a lower p-type impurity concentration than the n-type impurity concentration of the first pillar region 21 (first lower region 21L).

[0584] The second pillar region 22 has a p-type impurity concentration that is lower than the n-type impurity concentration of the first decreasing portion 33 of the first pillar region 21, at least in the second decreasing portion 36. The second pillar region 22 may also have a p-type impurity concentration that is lower than the n-type impurity concentration of the first decreasing portion 32 of the first pillar region 21, in the second slow portion 35.

[0585] The low-concentration starting point SP in the second pillar region 22 may be located above the bottom walls of the multiple gate structures 15 (towards the first main surface 3) or below the bottom walls of the multiple gate structures 15 (towards the second main surface 4). The low-concentration starting point SP is the starting point where the p-type impurity concentration in the second pillar region 22 falls below the n-type impurity concentration in the first pillar region 21.

[0586] In this embodiment, the low-concentration starting point SP is set below the bottom walls of the multiple gate structures 15 (a thickness range of 1.4 μm to 1.5 μm from the first main surface 3). The low-concentration starting point SP may be set to a thickness range greater than 0 μm and 2.5 μm or less, depending on the depth of the second pillar region 22 and the p-type impurity concentration.

[0587] The low-concentration starting point SP may be greater than 0 μm and belong to at least one of the following thickness ranges: 0.25 μm or less, 0.25 μm or more and 0.5 μm or less, 0.5 μm or more and 0.75 μm or less, 0.75 μm or more and 1 μm or less, 1 μm or more and 1.25 μm or less, 1.25 μm or more and 1.5 μm or less, 1.5 μm or more and 1.75 μm or less, 1.75 μm or more and 2 μm or more and 2 μm or more and 2.25 μm or more and 2.5 μm or less. The low-concentration starting point SP is preferably 0.5 μm or more.

[0588] The second bottom portion 22B of the second pillar region 22 is the portion where the conductivity type of the second pillar region 22 is replaced from p-type (second concentration gradient G2) to n-type (basic concentration CB), and is approximately the same as the basic concentration CB (1 × 10 in this embodiment). １６ cm －３ It has a p-type impurity concentration of approximately [amount].

[0589] The concentration difference between the n-type impurity concentration in the first pillar region 21 and the p-type impurity concentration in the second pillar region 22 gradually increases towards the second bottom 22B. The second bottom 22B has the highest concentration difference relative to the n-type impurity concentration in the first pillar region 21.

[0590] If the lower limit of the p-type impurity concentration in the second bottom 22B is set to the same value as the base concentration CB, the concentration ratio of the p-type impurity concentration in the second bottom 22B to the n-type impurity concentration in the first bottom 21B may be greater than 0 and less than 1.

[0591] The concentration ratio may have a value that falls within at least one of the following ranges: greater than 0 and 0.1 or less, 0.1 or more and 0.2 or less, 0.2 or more and 0.3 or less, 0.3 or more and 0.4 or less, 0.4 or more and 0.5 or less, 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.

[0592] In this configuration, the second upper region 22U of the second pillar region 22 is not corrected by the correction concentration C3. Therefore, the second upper region 22U of the second pillar region 22 has a p-type impurity concentration higher than the n-type impurity concentration of the first upper region 21U of the first pillar region 21. Of course, the second upper region 22U of the second pillar region 22 may be adjusted downward by the correction concentration C3, as in the case of semiconductor device 1A (see Figure 21).

[0593] As described above, the semiconductor device 1D may include an n-type second semiconductor layer 7, a trench-type gate structure 15, an n-type first pillar region 21, and a p-type second pillar region 22. The second semiconductor layer 7 may have a first main surface 3. The gate structure 15 may be formed on the first main surface 3.

[0594] The first pillar region 21 may have a first lower region 21L located below the depth of the bottom wall of the gate structure 15 within the second semiconductor layer 7. The second pillar region 22 may have a second lower region 22L located below the depth of the bottom wall within the second semiconductor layer 7 and forming a pn junction with the first lower region 21L.

[0595] This configuration provides a novel semiconductor device 1D. For example, with this configuration, the depletion layer caused by the pn junction between the first lower region 21L and the second lower region 22L extends below the gate structure 15. As a result, the electric field on the gate structure 15 is mitigated by the pn junction below the gate structure 15, improving its electrical breakdown voltage.

[0596] The second semiconductor layer 7 may contain SiC. This configuration provides a novel SiC semiconductor device 1A. With a SiC semiconductor device, the electrical properties are appropriately improved due to the physical properties of SiC.

[0597] In particular, since SiC semiconductor devices are used in relatively high voltage environments, the voltage-breaking effect caused by the pn junction between the first lower region 21L and the second lower region 22L is effective. The second semiconductor layer 7 may have an off-angle of 10° or less. The off-direction of the off-angle may be the a-axis direction of SiC.

[0598] The second lower region 22L of the second pillar region 22 may have a p-type impurity concentration lower than the n-type impurity concentration of the first lower region 21L of the first pillar region 21. For example, in such a configuration, when the width of the second pillar region 22 increases due to process errors, the increase in the shielding area of ​​the current path through the first pillar region 21 due to the depletion layer caused by the second pillar region 22 is suppressed.

[0599] The first lower region 21L of the first pillar region 21 may have a portion located directly below the bottom wall of the gate structure 15. The second lower region 22L of the second pillar region 22 may have a portion located directly below the bottom wall of the gate structure 15. With this configuration, the pn junction between the first lower region 21L and the second lower region 22L is formed in the region directly below the bottom wall of the gate structure 15. As a result, the electric field for the gate structure 15 is appropriately mitigated in the region directly below the bottom wall of the gate structure 15.

[0600] The gate structure 15 may extend in a first direction X along the first main surface 3. The first pillar region 21 may extend in a second direction Y along the first main surface 3 and intersect the gate structure 15. The second pillar region 22 may extend in a second direction Y and intersect the gate structure 15.

[0601] In this configuration, the pn junction between the first lower region 21L and the second lower region 22L is extended in the second direction Y in the region below the gate structure 15. This appropriately relaxes the electric field on the gate structure 15. In this case, the second semiconductor layer 7 may contain SiC. The first direction X may be the m-axis direction of SiC. The second direction Y may be the a-axis direction of SiC.

[0602] The first pillar region 21 may have a first upper region 21U located above the depth of the bottom wall of the gate structure 15. The second pillar region 22 may have a second upper region 22U located above the depth of the bottom wall of the gate structure 15 and forming a pn joint with the first upper region 21U.

[0603] With this configuration, the depletion layer caused by the pn junction between the first upper region 21U and the second upper region 22U expands at a depth above the bottom wall of the gate structure 15, thereby appropriately improving the electrical withstand voltage. The second pillar region 22 may have a charge balance with respect to the first pillar region 21. With this configuration, the depletion layer caused by the pn junction is appropriately expanded.

[0604] Multiple first pillar regions 21 may be formed at intervals in the first direction X. Multiple second pillar regions 22 may be formed alternately with the multiple first pillar regions 21 in the first direction X. In this case, the second pillar regions 22 may form a superjunction structure with the first pillar regions 21. This configuration appropriately improves electrical withstand voltage.

[0605] The semiconductor device 1D may include a p-type well region 20. The well region 20 may be formed below the gate structure 15 within the second semiconductor layer 7. With this configuration, the electric field for the gate structure 15 is appropriately mitigated by the well region 20 below the gate structure 15.

[0606] The well region 20 may be connected to the bottom wall of the gate structure 15. The well region 20 may be wider than the gate structure 15. The well region 20 may extend in the first direction X following the gate structure 15. With these configurations, the electric field on the gate structure 15 is appropriately mitigated by the well region 20.

[0607] The first lower region 21L of the first pillar region 21 may be located below the well region 20. The second lower region 22L of the second pillar region 22 may be located below the well region 20.

[0608] With this configuration, below the well region 20, the depletion layer caused by the second pillar region 22 suppresses an increase in the shielding area of ​​the current path through the first pillar region 21. In addition, the depletion layer caused by the pn junction between the first lower region 21L and the second lower region 22L extends below the well region 20. As a result, the electric field for the gate structure 15 is appropriately mitigated by the pn junction below the well region 20.

[0609] The first lower region 21L of the second pillar region 22 may be connected to the well region 20. With this configuration, the well region 20 and the second pillar region 22 are appropriately electrically linked. The first lower region 21L of the second pillar region 22 may have a p-type impurity concentration lower than that of the well region 20. With this configuration, the depletion layer caused by the pn junction spreads appropriately below the well region 20.

[0610] The semiconductor device 1D may include a p-type body region 10. The body region 10 may be formed on the surface layer of the first main surface 3. In this case, the gate structure 15 may penetrate the body region 10. The second pillar region 22 may be interposed between the body region 10 and the well region 20, electrically connecting the well region 20 to the body region 10.

[0611] In this configuration, the electrically stray state of the well region 20 is suppressed by the second pillar region 22. This improves the electrical response characteristics of the well region 20, and the electric field on the gate structure 15 is appropriately mitigated by the well region 20. The well region 20 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. In this configuration, the electrical response characteristics of the well region 20 are appropriately improved.

[0612] The first pillar region 21 may be formed below the body region 10. The second pillar region 22 may also be formed below the body region 10. With this configuration, below the body region 10, the increase in the shielding area of ​​the current path through the first pillar region 21 due to the depletion layer caused by the second pillar region 22 is suppressed. In addition, below the body region 10, a voltage resistance improvement effect can be obtained due to the pn junction between the first pillar region 21 and the second pillar region 22.

[0613] The semiconductor device 1D may include an n-type source region 40. The source region 40 may be located on the surface of the body region 10 and face the first pillar region 21 in the thickness direction Z. With this configuration, a channel can be appropriately formed in the region between the first pillar region 21 and the source region 40.

[0614] The semiconductor device 1D may include a p-type contact region 41. The contact region 41 may have a higher p-type impurity concentration than the p-type impurity concentration of the body region 10. The contact region 41 may be located on the surface of the body region 10 and face the second pillar region 22 in the thickness direction Z. With this configuration, the electrical response characteristics of the second pillar region 22 are improved by the contact region 41, and the channel formation location is appropriately secured in a region outside the second pillar region 22.

[0615] Figure 35 is a cross-sectional view showing the active region 8 of the semiconductor device 1E according to the fifth embodiment together with the via electrode 70 and source electrode 60 according to the first example. Figure 36 is an enlarged cross-sectional view of the via electrode 70 and source electrode 60 shown in Figure 35. Referring to Figures 35 and 36, the semiconductor device 1E includes a plurality of via electrodes 70 embedded in a plurality of source openings 56. The configuration of one via electrode 70 will be described below.

[0616] The via electrode 70 is made of metal. The via electrode 70 may have a single-layer structure containing a single metal film, or a multilayer structure containing multiple metal films. The via electrode 70 may contain a metal film containing at least one of the following: aluminum-based metals, titanium-based metals, nickel-based metals, copper-based metals, molybdenum-based metals, palladium-based metals, silver-based metals, tungsten-based metals, and gold-based metals.

[0617] The via electrode 70 may contain a metal film comprising at least one of aluminum, titanium, nickel, copper, molybdenum, palladium, silver, tungsten, and gold. The via electrode 70 may also contain an alloy film (metal film) comprising at least one of aluminum alloy, titanium alloy, nickel alloy, copper alloy, molybdenum alloy, palladium alloy, silver alloy, tungsten alloy, and gold alloy.

[0618] In this embodiment, the via electrode 70 has a laminated structure including a via base electrode 71 and a via body electrode 72 stacked in this order from the wall side of the source opening 56. The via base electrode 71 is formed as a barrier electrode for the tip 2 and has a single-layer structure consisting of a single metal film or a laminated structure consisting of multiple metal films.

[0619] In this embodiment, the via base electrode 71 has a laminated structure including a first via electrode 71a and a second via electrode 71b. The first via electrode 71a consists of a metal film containing any one of the aforementioned metals, or an alloy film containing any one of the aforementioned alloys. In this embodiment, the first via electrode 71a consists of a titanium-based metal film (titanium film).

[0620] The first via electrode 71a is formed within the source opening 56 with a gap between it and the first main surface 3, leaving the insulating surface of the interlayer film 50 exposed. The first via electrode 71a has a portion that covers the wall surface of the source opening 56 in a film-like manner, and a portion that covers the first main surface 3 (source recess 57) in a film-like manner. The first via electrode 71a is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within the source opening 56.

[0621] The first via electrode 71a has a thickness less than the thickness of the interlayer film 50. The thickness of the first via electrode 71a may be greater than 0 nm and 200 nm or less. The thickness of the first via electrode 71a may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 125 nm, 125 nm to 150 nm, 150 nm to 175 nm, and 175 nm to 200 nm.

[0622] The second via electrode 71b consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The second via electrode 71b consists of a different metal film or alloy film than the first via electrode 71a. In this embodiment, the second via electrode 71b consists of a titanium-based metal film (a titanium nitride film as an example of a titanium alloy film).

[0623] The second via electrode 71b coats the first via electrode 71a in a film-like manner within the source opening 56. The second via electrode 71b is formed within the source opening 56 with a gap between it and the first main surface 3 side from the insulating surface of the interlayer film 50, exposing the insulating surface of the interlayer film 50.

[0624] The second via electrode 71b has a portion that covers the wall surface of the source opening 56 in a film-like manner via the first via electrode 71a, and a portion that covers the first main surface 3 (source recess 57) in a film-like manner via the first via electrode 71a. The second via electrode 71b is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via the first via electrode 71a.

[0625] The second via electrode 71b has a thickness less than the thickness of the interlayer film 50. In this embodiment, the thickness of the second via electrode 71b is greater than the thickness of the first via electrode 71a. The thickness of the second via electrode 71b may be less than the thickness of the first via electrode 71a.

[0626] The thickness of the second via electrode 71b may be greater than 0 nm and 300 nm or less. The thickness of the second via electrode 71b may have a value that falls within at least one of the following ranges: greater than 0 nm and 10 nm or less, 10 nm to 25 nm, 25 nm to 50 nm, 50 nm to 75 nm, 75 nm to 100 nm, 100 nm to 150 nm, 150 nm to 200 nm, 200 nm to 250 nm, and 250 nm to 300 nm.

[0627] The via body electrode 72 consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys. The via body electrode 72 is made of a different conductor than the first via electrode 71a and the second via electrode 71b. In this embodiment, the via body electrode 72 is made of a tungsten-based metal (tungsten or tungsten alloy).

[0628] The via body electrode 72 is embedded in the source opening 56 via the via base electrode 71. The via body electrode 72 is formed in the source opening 56 with a gap between it and the first main surface 3 side from the insulating surface of the interlayer film 50, exposing the insulating surface of the interlayer film 50.

[0629] The via body electrode 72 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via a via base electrode 71. In this embodiment, the via body electrode 72 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 via the via base electrode 71 on a plurality of source recesses 57.

[0630] The via electrode body 72 has a via electrode surface located on the insulating surface side of the interlayer film 50, relative to the depth position of the intermediate portion of the source opening 56. The via electrode surface is located on the insulating surface side with respect to the depth position of the intermediate portion of the source opening 56.

[0631] The via electrode surface may be formed substantially flush with the upper end of the via base electrode 71. The via electrode surface may be located on the insulating surface side of the interlayer film 50 or on the first main surface 3 side of the upper end of the via base electrode 71. The via electrode surface may have a recess toward the first main surface 3.

[0632] The semiconductor device 1E includes the aforementioned source electrode 60 disposed on the interlayer film 50. Similar to the semiconductor device 1A, the source electrode 60 includes a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c, and has a planar layout similar to that of the source electrode 60 of semiconductor device 1A. A description of the peripheral portion of the source electrode 60 is omitted.

[0633] The source electrode 60 covers the interlayer film 50 in a film-like manner and extends in a film-like manner from above the interlayer film 50 onto a plurality of source openings 56. The source electrode 60 is mechanically and electrically connected to a plurality of via electrodes 70. Specifically, the source electrode 60 is mechanically and electrically connected to the first via electrode 71a, the second via electrode 71b, and the via body electrode 72.

[0634] In this configuration, the source electrode 60 enters the multiple source openings 56 from above the interlayer film 50 and coats the multiple via electrodes 70 in a film-like manner within the multiple source openings 56. As a result, the source electrode 60 is electrically connected to the multiple source regions 40 and the multiple contact regions 41 via the multiple via electrodes 70.

[0635] The source electrode 60 forms multiple connection boundary portions BP with the via electrode surfaces of the multiple via electrodes 70. The connection boundary portions BP between the source electrode 60 and the via electrodes 70 are formed on the first main surface 3 side with respect to the insulating surface of the interlayer film 50. The connection boundary portions BP are located on the insulating surface side with respect to the depth position of the intermediate portion of the source opening 56. The connection boundary portions BP have recessed boundary portions that follow the recesses of the via electrodes 70 and extend toward the first main surface 3 side.

[0636] In this embodiment, the source electrode 60 has a single-layer structure consisting of a main electrode 62. The main electrode 62 may contain a different conductor than the via electrode 70. The main electrode 62 may contain a different conductor than either or both of the via base electrode 71 and the via main electrode 72.

[0637] The main electrode 62 may contain a conductor different from either or both of the first via electrode 71a and the second via electrode 71b. In this embodiment, the main electrode 62 contains a conductor different from the first via electrode 71a, the second via electrode 71b, and the via main electrode 72.

[0638] In this embodiment, the main electrode 62 has a single-layer structure made of an aluminum-based metal (aluminum or an aluminum alloy). The aluminum alloy may include at least one of AlSi alloy, AlCu alloy, and AlSiCu alloy.

[0639] The main electrode 62 directly covers the insulating surface of the interlayer film 50 and the multiple via electrodes 70 in a film-like manner, and is mechanically and electrically connected to the via electrode surfaces of the multiple via electrodes 70. In this embodiment, the connection boundary BP between the source electrode 60 and the via electrodes 70 is mainly formed by the boundary between a tungsten-based metal and an aluminum-based metal.

[0640] The main electrode 62 is electrically connected to multiple source regions 40 and multiple contact regions 41 via multiple via electrodes 70. The main electrode 62 has a planar layout similar to that of the main electrode 62 of semiconductor device 1A. The peripheral portion of the main electrode 62 is omitted from this description.

[0641] The main electrode 62 has a thickness greater than the thickness of the via base electrode 71 (the total thickness of the first via electrode 71a and the second via electrode 71b). The thickness of the main electrode 62 is greater than the opening width of the source opening 56 (the width of the via main electrode 72). In this embodiment, the thickness of the main electrode 62 is greater than the thickness of the interlayer film 50. The thickness of the main electrode 62 may be less than the thickness of the interlayer film 50.

[0642] The thickness of the main electrode 62 may be greater than 0 μm and 5 μm or less. The thickness of the main electrode 62 may have a value that falls within at least one of the following ranges: greater than 0 μm and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or more and 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0643] The source electrode 60 and via electrode 70 may have layouts other than those shown in Figures 35 and 36. Other examples of the source electrode 60 and via electrode 70 are shown below. Figures 37A to 37I are enlarged cross-sectional views of the source electrode 60 and via electrode 70 according to the second to tenth examples. The configuration for one via electrode 70 is described below.

[0644] Referring to Figure 37A (second example), the via electrode 70 may include a via base electrode 71 having a single-layer structure. The via base electrode 71 may be a first via electrode 71a (a titanium film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the first via electrode 71a within the source opening 56.

[0645] The via base electrode 71 may be a second via electrode 71b (a titanium nitride film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the second via electrode 71b within the source opening 56.

[0646] Referring to Figure 37B (third example), the via electrode 70 may have a single-layer structure consisting of a via body electrode 72. That is, the via body electrode 72 may be embedded as a single unit in the source opening 56 and mechanically and electrically connected to the first main surface 3 and the wall surface of the source opening 56 within the source opening 56. In this embodiment, the via body electrode 72 is electrically connected to a plurality of source regions 40 and a plurality of contact regions 41 within the source recess 57.

[0647] Referring to Figure 37C (Fourth Example), the source electrode 60 may have a laminated structure including a base electrode 61 and a main electrode 62, similar to the case of semiconductor device 1A. The base electrode 61 may have a laminated structure including a first electrode 61a and a second electrode 61b.

[0648] The first electrode 61a coats the insulating surface of the interlayer film 50 in a film-like manner and extends into the source opening 56. The first electrode 61a is connected to the first via electrode 71a within the source opening 56. In this configuration, the first electrode 61a is made of the same conductor (titanium film) as the first via electrode 71a and is formed integrally with the first via electrode 71a.

[0649] The second electrode 61b covers the first electrode 61a in a film-like manner on the interlayer film 50 and extends into the source opening 56. The second electrode 61b is connected to the second via electrode 71b within the source opening 56. In this configuration, the second electrode 61b is made of the same conductor (titanium nitride film) as the second via electrode 71b and is formed integrally with the second via electrode 71b.

[0650] The main electrode 62 covers the base electrode 61 in a film-like manner on the interlayer film 50 and is drawn out from above the base electrode 61 onto the source opening 56. The main electrode 62 is mechanically and electrically connected to the via main electrode 72 within the source opening 56, forming a connection boundary BP with the via main electrode 72.

[0651] Referring to Figure 37D (Fifth Example), the via electrode 70 may include a via base electrode 71 having a single-layer structure. The via base electrode 71 may be a first via electrode 71a (a titanium film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the first via electrode 71a within the source opening 56.

[0652] The source electrode 60 may have a laminated structure including a base electrode 61 and a main electrode 62. The base electrode 61 may have a single-layer structure consisting of a first electrode 61a. The first electrode 61a covers the insulating surface of the interlayer film 50 in a film-like manner and fits into the source opening 56.

[0653] The first electrode 61a is connected to the first via electrode 71a within the source opening 56. In this configuration, the first electrode 61a is made of the same conductor (titanium film) as the first via electrode 71a and is formed integrally with the first via electrode 71a.

[0654] The main electrode 62 covers the base electrode 61 in a film-like manner on the interlayer film 50 and is drawn out from above the base electrode 61 onto the source opening 56. The main electrode 62 is mechanically and electrically connected to the via main electrode 72 within the source opening 56, forming a connection boundary BP with the via main electrode 72.

[0655] Of course, the via base electrode 71 may be a second via electrode 71b (a titanium nitride film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the second via electrode 71b within the source opening 56.

[0656] In this case, the base electrode 61 of the source electrode 60 may have a single-layer structure consisting of a second electrode 61b. The second electrode 61b may cover the insulating surface of the interlayer film 50 in a film-like manner and may extend into the source opening 56.

[0657] The second electrode 61b may be connected to the second via electrode 71b within the source opening 56. The second electrode 61b may be made of the same conductor (titanium nitride film) as the second via electrode 71b and may be formed integrally with the second via electrode 71b.

[0658] Referring to Figure 37E (Sixth Example), the base electrode 61 of the source electrode 60 may have a laminated structure including a first electrode 61a, a second electrode 61b, and a third electrode 61c.

[0659] The first electrode 61a coats the insulating surface of the interlayer film 50 in a film-like manner and extends into the source opening 56. The first electrode 61a is connected to the first via electrode 71a within the source opening 56. In this configuration, the first electrode 61a is made of the same conductor (titanium film) as the first via electrode 71a and is formed integrally with the first via electrode 71a.

[0660] The second electrode 61b covers the first electrode 61a in a film-like manner on the interlayer film 50 and extends into the source opening 56. The second electrode 61b is connected to the second via electrode 71b within the source opening 56. In this configuration, the second electrode 61b is made of the same conductor (titanium nitride film) as the second via electrode 71b and is formed integrally with the second via electrode 71b.

[0661] The third electrode 61c consists of a metal film containing one of the aforementioned metals, or an alloy film containing one of the aforementioned alloys, with respect to the electrode material of the source electrode 60. The third electrode 61c consists of a different metal film or alloy film than the first electrode 61a. The third electrode 61c consists of a different metal film or alloy film than the second electrode 61b. In this embodiment, the third electrode 61c consists of a tungsten-based metal film (tungsten film or tungsten alloy film).

[0662] The third electrode 61c covers the second electrode 61b in a film-like manner on the interlayer film 50 and extends into the source opening 56. The third electrode 61c is connected to the via body electrode 72 within the source opening 56.

[0663] In this embodiment, the third electrode 61c is made of the same conductor (tungsten-based metal film) as the via body electrode 72 and is integrally formed with the via body electrode 72. The third electrode 61c may have a recess facing the first main surface 3 in the portion that overlaps the source opening 56.

[0664] The third electrode 61c has a thickness less than the thickness of the interlayer film 50. The thickness of the third electrode 61c may be less than the thickness of the interlayer film 50. In this embodiment, the thickness of the third electrode 61c is greater than the thickness of the first electrode 61a. The thickness of the third electrode 61c may be less than the thickness of the first electrode 61a. In this embodiment, the thickness of the third electrode 61c is greater than the thickness of the second electrode 61b. The thickness of the third electrode 61c may be less than the thickness of the second electrode 61b.

[0665] The thickness of the third electrode 61c may be greater than 0 nm and less than or equal to 1 μm. The thickness of the third electrode 61c may have a value that falls within at least one of the following ranges: greater than 0 nm and less than or equal to 0.1 μm, between 0.1 μm and 0.25 μm, between 0.25 μm and 0.5 μm, between 0.5 μm and 0.75 μm, and between 0.75 μm and 1 μm.

[0666] The main electrode 62 covers the base electrode 61 (third electrode 61c) in a film-like manner on the interlayer film 50. In other words, in this configuration, the main electrode 62 forms a connection boundary BP with the third electrode 61c in the portion that overlaps with the source opening 56. The connection boundary BP has a recess boundary portion that follows the recess of the third electrode 61c and faces the first main surface 3 side.

[0667] Referring to Figure 37F (Seventh Example), the via electrode 70 may include a via base electrode 71 having a single-layer structure. The via base electrode 71 may be a first via electrode 71a (a titanium film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the first via electrode 71a within the source opening 56.

[0668] The source electrode 60 may have a laminated structure including a base electrode 61 and a main electrode 62. The base electrode 61 may have a laminated structure consisting of a first electrode 61a and a third electrode 61c. The first electrode 61a coats the insulating surface of the interlayer film 50 in a film-like manner and fits into the source opening 56.

[0669] The first electrode 61a is connected to the first via electrode 71a within the source opening 56. In this configuration, the first electrode 61a is made of the same conductor (titanium film) as the first via electrode 71a and is formed integrally with the first via electrode 71a.

[0670] The third electrode 61c covers the first electrode 61a in a film-like manner on the interlayer film 50 and extends into the source opening 56. The third electrode 61c is connected to the via body electrode 72 within the source opening 56.

[0671] In this embodiment, the third electrode 61c is made of the same conductor (tungsten-based metal film) as the via body electrode 72 and is integrally formed with the via body electrode 72. The third electrode 61c may have a recess facing the first main surface 3 in the portion that overlaps the source opening 56.

[0672] The main electrode 62 covers the base electrode 61 (third electrode 61c) in a film-like manner on the interlayer film 50. In other words, in this configuration, the main electrode 62 forms a connection boundary BP with the third electrode 61c in the portion that overlaps with the source opening 56. The connection boundary BP has a recess boundary portion that follows the recess of the third electrode 61c and faces the first main surface 3 side.

[0673] Of course, the via base electrode 71 may be a second via electrode 71b (a titanium nitride film as a titanium-based metal film). In this case, the via body electrode 72 may be mechanically and electrically connected to the second via electrode 71b within the source opening 56.

[0674] The base electrode 61 of the source electrode 60 may have a laminated structure consisting of a second electrode 61b and a third electrode 61c. The second electrode 61b may cover the insulating surface of the interlayer film 50 in a f...

Claims

A semiconductor layer having a main surface, An insulating interlayer film covering the main surface, An opening that penetrates the interlayer film and exposes the semiconductor layer, A metal via electrode connected to the semiconductor layer within the opening, A semiconductor device comprising a metallic main electrode disposed on the interlayer film and forming a connection boundary with the via electrode. 　 The semiconductor device according to claim 1, wherein the semiconductor layer includes SiC. 　 The semiconductor device according to claim 2, wherein the semiconductor layer has an off-angle of 10° or less. 　 The semiconductor device according to claim 3, wherein the off-direction of the off-angle is the a-axis direction of the SiC. 　 The via electrode has an electrode surface located on the main surface side of the height position of the insulating surface of the interlayer film, The semiconductor device according to any one of claims 1 to 4, wherein the main electrode directly covers the electrode surface of the via electrode within the opening. 　 The semiconductor device according to any one of claims 1 to 5, wherein the via electrode contains a tungsten-based metal. 　 The semiconductor device according to any one of claims 1 to 6, wherein the via electrode includes a metal base electrode covering the wall surface of the opening, and a metal main electrode embedded in the opening via the base electrode. 　 The aforementioned base electrode contains a titanium-based metal, The semiconductor device according to claim 7, wherein the main electrode comprises a tungsten-based metal. 　 The semiconductor device according to any one of claims 1 to 8, wherein the main electrode comprises a metal material different from that of the via electrode. 　 The semiconductor device according to any one of claims 1 to 9, wherein the main electrode comprises an aluminum-based metal. 　 Multiple trench-shaped gate structures formed at intervals on the main surface, The present invention further includes a mesa portion partitioned in the semiconductor layer by a plurality of gate structures, The interlayer film covers the multiple gate structures on the main surface, The opening exposes the mesa portion at intervals from the multiple gate structures. The semiconductor device according to any one of claims 1 to 10, wherein the via electrode is connected to the mesa portion within the opening and is electrically insulated from the plurality of gate structures by the interlayer film. 　 The semiconductor layer of the first conductivity type, The semiconductor device according to claim 11, further comprising a second conductivity type well region formed in the region directly beneath the gate structure within the semiconductor layer. 　 The semiconductor layer of the first conductivity type, A first region of a first conductivity type formed along the gate structure within the semiconductor layer, The semiconductor layer further includes a second region of a second conductivity type formed along the gate structure within the semiconductor layer and forming a pn junction with the first region, The via electrode is electrically connected to the first region and the second region, The semiconductor device according to claim 11, wherein the main electrode is electrically connected to the first region and the second region via the via electrode. 　 The semiconductor device according to claim 13, wherein the second region has a charge balance with respect to the first region. 　 The first region has a portion located directly below the gate structure, The semiconductor device according to claim 13 or 14, wherein the second region has a portion located directly below the gate structure. 　 The gate structure extends in a first direction along the main surface, The first region extends in a second direction along the main surface and intersects with the gate structure in a three-dimensional manner in the region directly below the gate structure. The semiconductor device according to any one of claims 13 to 15, wherein the second region extends in the second direction and intersects the gate structure in a three-dimensional manner in the region directly below the gate structure. 　 The body further includes a second conductive type body region formed on the surface layer of the main surface, The gate structure penetrates the body region, The first region is formed below the body region, The second region is formed below the body region, The semiconductor device according to any one of claims 13 to 16, wherein the via electrode is electrically connected to the first region and the second region via the body region. 　 The surface layer of the body region further includes a source region of a first conductivity type facing the first region in the thickness direction of the semiconductor layer, The opening is formed on the source region, The semiconductor device according to claim 17, wherein the via electrode is electrically connected to the source region within the opening. 　 The body region has a higher impurity concentration than the body region and further includes a second conductivity type contact region in the surface layer of the body region that faces the second region in the thickness direction of the semiconductor layer, The opening is formed on the contact area, The semiconductor device according to claim 17 or 18, wherein the via electrode is electrically connected to the contact region within the opening. 　 The semiconductor layer further includes a second conductivity type well region formed in the region directly beneath the gate structure, The semiconductor device according to any one of claims 17 to 19, wherein the second region is interposed in the region between the body region and the well region, and electrically connects the well region to the body region.

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