Charged particle trap device

Abstract

Provided is a charged particle trap device that can reduce the circuit size of a circuit that turns a switch circuit on and off. A trap unit 14 is provided with: a quantum charge-coupled element having a plurality of DC electrodes 31; a switching unit 21; a capacitor unit 22; and a signal delay unit 23. A control unit 15 is provided with a digital-to-analog converter 35 and a drive pulse signal generation circuit 36. A drive pulse signal from the drive pulse signal generation circuit 36 ​​is input to the signal delay unit 23, in which a plurality of time constant delay circuits 47 are connected in series. The drive pulse signals from each time constant delay circuit 47 sequentially turn on a plurality of switch circuits Sw1, Sw2, etc. A DC voltage from the digital-to-analog converter 35 is switched in synchronization with the output timing of the drive pulse signal from the signal delay unit 23. Capacitors 22a connected to each of the switch circuits Sw1, Sw2, etc. are charged, and a state in which a charging voltage is applied to the DC electrodes 31 is maintained.

Description

Charged particle trapping device

[0001] This invention relates to a charged particle trapping device.

[0002] Devices that control the position of charged particles using an electrode array with multiple electrodes are known. One such device is an ion trap device using a quantum charge-coupled device (QCCD). The ion trap device independently controls the voltage applied to each electrode of a quantum charge-coupled device equipped with a multi-electrode array, trapping ions in a specific region and moving them based on the potential generated by each electrode.

[0003] In an ion trap quantum computer, quantum charge-coupled elements are placed in a vacuum chamber kept at an extremely low temperature. Non-patent document 1 proposes an electrode array device that reduces the amount of wiring between a DAC and the quantum charge-coupled elements by sequentially switching and applying the voltage generated by a single digital-to-analog converter (hereinafter referred to as DAC) to each electrode of the quantum charge-coupled elements.

[0004] The electrode array device described in Non-Patent Document 1 includes quantum charge-coupled elements and a DAC, with L being an integer of 2 or more, and the number of electrodes of each quantum charge-coupled element being M (M = 2 Ｌ－１The quantum charge-coupled element is equipped with M switch circuits corresponding to each electrode and a switch selection circuit that selectively turns on the switch circuits in sequence. The switch selection circuit consists of M capacitors, a counter, and a digital demultiplexer. The counter is an L-bit output register that increments the count value by 1 with each clock input and outputs it to the digital demultiplexer. The digital demultiplexer receives the L-bit count value from the counter as input, and each of its M outputs is connected to a single switch circuit, turning on one switch circuit according to the count value. This cyclically switches on the switch circuits in sequence with each clock input. When one switch circuit is turned on, a voltage from the DAC is applied to the corresponding electrode and the capacitor is charged at the same time. The electrode maintains an applied voltage due to the capacitor's charging voltage from the time the corresponding switch circuit is turned off until it is turned on again. The DAC output is switched in synchronization with the clock. This allows the voltage applied to each electrode to be controlled independently.

[0005] M. Malinowski, DTC Allcock, CJ Ballance, “How to Wire a 1000-Qubit Trapped-Ion Quantum Computer,” PRX Quantum 4, 040313 19 October, 2023

[0006] However, when a circuit that selectively turns on switches in sequence is configured like the switch selection circuit in Non-Patent Document 1, there is a problem with the large size of the circuit. A large circuit size leads to problems such as high power consumption and increased heat generation.

[0007] This invention has been made in view of the above circumstances, and aims to provide a charged particle trapping device that can reduce the circuit size of the circuit that turns the switch circuit on and off.

[0008] The charged particle trapping device of the present invention comprises an electrode array having a plurality of electrodes for controlling the position of charged particles; a switching unit consisting of a plurality of switch circuits provided corresponding to the plurality of electrodes and connected to the corresponding electrodes, each switch circuit turning on in response to the input of a drive pulse signal; a drive pulse signal generation circuit that periodically generates a drive pulse signal; a signal delay unit configured by connecting a plurality of delay circuits in series corresponding to each of the plurality of switch circuits, each delay circuit delaying the input drive pulse signal and inputting it to the corresponding switch circuit and to a subsequent delay circuit; a digital-to-analog converter whose DC voltage output is switched in synchronization with the output timing of the drive pulse signal from the signal delay unit; and a capacitor unit consisting of a plurality of capacitors provided corresponding to each of the plurality of electrodes, one end of which is connected to the corresponding electrode, and the digital-to-analog converter is connected to the corresponding electrode via a switch circuit, the capacitor is charged by the DC voltage from the digital-to-analog converter when the switch circuit is turned on, and a constant charging voltage is continuously applied to the corresponding electrode during the off period of the switch circuit.

[0009] According to the present invention, the drive pulse signal from the drive pulse signal generation circuit is input to a signal delay section in which multiple delay circuits are connected in series. The drive pulse signals from each delay circuit turn on multiple switch circuits in sequence, and digital-to-analog converters are connected to the electrodes and capacitors connected to each switch circuit. Furthermore, the DC voltage from the digital-to-analog converters is switched in synchronization with the output timing of the drive pulse signal from the signal delay section. As a result, the circuit size of the circuits that turn the switch circuits on and off can be reduced.

[0010] This is a block diagram showing the main components of an ion trap type quantum computer according to an embodiment. This is a plan view showing the electrode array in a quantum charge-coupled device (QCCD). This is a block diagram showing the configuration of the trap unit and the control unit. This is a circuit diagram showing the switch circuit. This is a timing chart showing the drive pulse signal and the ON timing of the switch circuit. This is a block diagram showing an example in which a buffer is provided in the signal delay section. This is a block diagram showing an example in which a SAW filter is used as the delay circuit. This is a block diagram showing an example in which a D-FF circuit is used as the delay circuit.

[0011] The ion trap type quantum computer 10 is equipped with an ion trap device 12 as a charged particle trapping device. The ion trap device 12 comprises a trap unit 14 located inside a vacuum chamber 13 and a control unit 15 located outside the vacuum chamber 13.

[0012] The trap unit 14 is, for example, made up of multiple substrates stacked and interconnected, and a quantum charge-coupled element (QCCD) 20 with multiple electrodes mounted on the surface of the substrates is provided. The quantum charge-coupled element 20 is used for manipulating and trapping suspended ions. The substrate of the trap unit 14 is provided with a switching section 21, a capacitor section 22, and a signal delay section 23 (see Figure 3). This trap unit 14 is cooled to an extremely low temperature under vacuum in a vacuum chamber 13.

[0013] The control unit 15 consists of various circuits for controlling the quantum charge-coupled element 20. This control unit 15 is located outside the vacuum chamber 13 and is in a standard environment such as room temperature. The control unit 15 and the trap unit 14 are electrically connected by various signal lines.

[0014] The quantum charge-coupled element 20 is provided with a pair of RF electrodes (RF rails) 24 and three electrode arrays 25-27, as schematically shown in Figure 2. The RF electrodes 24 and electrode arrays 25-27 generate an electric field for manipulating and trapping suspended ions. The pair of RF electrodes 24 extend in the Z direction with a constant width (length in the X direction). An RF (Radio Frequency) voltage is applied to each RF electrode 24. This confines the ions in a direction perpendicular to the Z direction. Note that the number and arrangement of electrodes in Figure 2 are simplified for illustrative purposes.

[0015] Electrode arrays 25-27 are arranged such that one RF electrode 24 is sandwiched between electrode arrays 25 and 26 in the X direction, and the other RF electrode 24 is sandwiched between electrode arrays 26 and 27. Electrode arrays 25-27 each have a row of DC electrodes 31, to which a DC voltage is applied, arranged in the direction in which the RF electrode 24 extends (Z direction). Electrode arrays 25-27 control the Z-direction position of ions trapped in the quantum charge-coupled element 20. This control of the Z-direction position of ions involves both movement of the ions in the Z direction and maintenance at a fixed position. Movement of ions in the Z direction is achieved by changing the voltage applied to the DC electrodes 31 of electrode arrays 25-27 over time.

[0016] As shown in Figure 3, in addition to the quantum charge-coupled element 20, the trap unit 14 is provided with a switching unit 21, a capacitor unit 22, and a signal delay unit 23, as described above. The control unit 15 is provided with a digital-to-analog converter (hereinafter referred to as DAC) 35 that outputs a DC voltage to be applied to the DC electrode 31, a drive pulse signal generation circuit 36, a voltage control unit 37, a clock generation unit 38, and the like. The clock generation unit 38 generates a clock with a fixed period that defines the operating timing of the trap unit 14 and the control unit 15.

[0017] The switching unit 21 consists of multiple switch circuits Sw provided in correspondence with the multiple DC electrodes 31 of the quantum charge-coupled element 20. １ , Sw ２ , Sw ３ ...composed of. Note that the switch circuit Sw １ , Sw２ , Sw ３ When there is no need to particularly distinguish between ..., they will be described as being collectively referred to as switch circuit Sw. The switch circuit Sw is connected between the corresponding DC electrode 31 and the output of the DAC 35. Accordingly, each DC electrode 31 is connected to the output of the DAC 35 via the corresponding switch circuit Sw.

[0018] The switch circuit Sw is, for example, as shown in FIG. 4, a transmission gate configured with p-type and n-type MOSFETs 41, 42, a NOT circuit 43, and the like. The switch circuit Sw is turned on while the drive pulse signal from the signal delay unit 23 is input thereto, and is turned off when the drive pulse signal is not input. If the pulse width of this drive pulse signal is defined as Ps, the length (time) of one on-period of the switch circuit Sw is Ps. The pulse width Ps of the drive pulse signal is set to be equal to or longer than the length required for completing charging of a capacitor 22a, which will be described later. In this example, the pulse width Ps is 10 nanoseconds.

[0019] Note that DC electrodes 31 to which the same DC voltage is applied at the same timing may be connected to a single common switch circuit Sw. The DC electrodes 31 connected to the single common switch circuit Sw may be DC electrodes 31 in the same electrode array or DC electrodes 31 between different electrode arrays. In the following description, for the sake of simplifying explanation, it is assumed that a DC voltage is independently applied to M DC electrodes 31, and that M switch circuits Sw are provided.

[0020] The capacitor unit 22 is composed of a plurality of capacitors 22a provided corresponding to the plurality of DC electrodes 31. Each capacitor 22a has one end connected to the corresponding DC electrode 31 and the switch circuit Sw, and the other end grounded. Therefore, each capacitor 22a is connected to the output of the DAC 35 via a single switch circuit Sw together with the corresponding DC electrode 31. Each capacitor 22a is charged during the on-period in which the connected switch circuit Sw is turned on, and the charging voltage of the capacitor 22a is applied to the corresponding DC electrode 31.

[0021] The capacitance of the capacitor 22a is determined such that it can continue to apply the same constant voltage as the output of the DAC 35 to the DC electrode 31 during the off period of the switch circuit Sw. The constant voltage allows a voltage change to an extent that does not substantially affect the control of ion positions. In other words, if the voltage duration is defined as the time period during which a voltage substantially the same as the DC voltage from the DAC 35 can be applied to the DC electrode 31, each switch circuit Sw is turned on at time intervals equal to or shorter than the voltage duration. Note that the off period in this example is 4 milliseconds, and the voltage duration is set to 4 milliseconds or more.

[0022] The signal delay unit 23 includes a plurality of time-constant delay circuits 47 connected in series １ , 47 ２ , 47 ３ , ... When there is no particular need to distinguish between the time-constant delay circuits 47 １ , 47 ２ , 47 ３ , ... they are referred to as the time-constant delay circuit 47 in the following description. The plurality of time-constant delay circuits 47 are provided corresponding to the plurality of switch circuits Sw. Each time-constant delay circuit 47 is configured as, for example, an RC circuit, which delays an input signal by a delay time Td corresponding to the time constant of the RC circuit and outputs the delayed signal. In this example, the delay time Td of each time-constant delay circuit 47 is adjusted to be the same.

[0023] Note that as the time-constant delay circuit 47, a single flux quantum (SFQ) circuit, a half flux quantum (HFQ) circuit, a parametron element or the like using a superconducting element in a cryogenic environment may be used.

[0024] The time-constant delay circuit 47 in the first stage １A drive pulse signal from the control unit 15 is input to this. Each stage of the time constant delay circuit 47 delays the input drive pulse signal by a delay time Td and inputs it to the corresponding switch circuit Sw and to the next stage of the time constant delay circuit 47. As a result, multiple switch circuits Sw are turned on sequentially at intervals of delay time Td from the moment the drive pulse signal is input to the signal delay unit 23. The delay time Td is set to be greater than the pulse width Ps of the drive pulse signal to prevent multiple switch circuits Sw from being turned on simultaneously. In this example, the delay time Td is set to 20 nanoseconds, which is twice the pulse width Ps.

[0025] The DAC 35 generates and outputs a DC voltage to be applied to the DC electrode 31. The DAC 35 receives voltage data from the voltage control unit 37, converts that voltage data into a DC voltage, and outputs it. By changing the voltage data input from the voltage control unit 37 to the DAC 35, the DC voltage output from the DAC 35 is switched. This switching of the DC voltage from the DAC 35 is performed at intervals equal to the delay time Td. In this example, the DC voltage output from the DAC 35 is switched during the period when the switch circuit Sw is off. Note that the DC voltage before and after the DC voltage switch may be the same, in which case the DC voltage output from the DAC 35 does not change.

[0026] The drive pulse signal generation circuit 36 ​​periodically outputs a drive pulse signal. The generation period of the drive pulse signal is determined so that two or more switch circuits Sw of the switching unit 21 do not turn on simultaneously, in order to independently control the voltage applied to the M DC electrodes 31. In this example, since M time constant delay circuits 47 are used corresponding to the M DC electrodes 31, the generation period is set to M times or more the delay time Td. From the viewpoint of miniaturizing the capacitor 22a and controlling the position of ions, it is preferable to shorten the generation period, and it is preferable that the generation period be M times the delay time Td. In this example as well, the generation period is set to M times the delay time Td. The generation period of the drive pulse signal is the period in which each switch circuit Sw turns on, and this generation period of the drive pulse signal is less than or equal to the voltage duration mentioned above.

[0027] Furthermore, in the ion trap device 12, the DC electrode 31 connected to the DAC 35 is sequentially selected by the switching unit 21. There is no need to provide a power line between the trap unit 14 and the control unit 15 to supply DC voltage to each DC electrode 31. Also, by inputting to the signal delay unit 23, the DC electrode 31 connected to the DAC 35 is sequentially selected by the switching unit 21. For this reason, the signal line between the trap unit 14 and the control unit 15 to control the on / off state of each switch circuit Sw of the switching unit 21 only needs to be a signal line for sending a drive pulse signal to the signal delay unit 23. Thus, the ion trap device 12 has a configuration that reduces the amount of wiring between the trap unit 14 and the control unit 15. Note that the control unit 15 does not need to have its constituent circuits integrated, for example, on a single board, but may be provided on separate boards.

[0028] As described above, the circuit that selectively selects and sequentially turns on multiple switch circuits Sw is configured as a signal delay unit 23 with multiple time constant delay circuits 47 connected in series, resulting in a simple circuit configuration and small circuit size. Therefore, because the signal delay unit 23 has a small circuit size, power consumption is low and heat generation is low. Furthermore, because the signal delay unit 23 has a small circuit size, accurate operation can be easily obtained even at extremely low temperatures, and the effects of heat generation and other factors can be kept to a minimum.

[0029] Next, the operation of the above configuration will be explained with reference to Figure 5. When a DC voltage is applied to each DC electrode 31, first a drive pulse signal with pulse width Ps is sent from the drive pulse signal generation circuit 36 ​​to the signal delay unit 23. After the first drive pulse signal is sent, before the delay time Td has elapsed from the time of transmission, the voltage control unit 37 switches the switch circuit Sw １ The DAC 35 outputs a DC voltage V1, which is the voltage to be applied to the first DC electrode 31 connected to the DAC.

[0030] The first drive pulse signal from the drive pulse signal generation circuit 36 ​​is transmitted to the first stage time constant delay circuit 47 of the signal delay unit 23. １The input is then passed to the time constant delay circuit 47. １ A drive pulse signal is output from here. Time constant delay circuit 47 １ The drive pulse signal output from the switch circuit Sw １ This is input to the switch circuit Sw. １ It turns on.

[0031] Switch circuit Sw １ When this is turned on, this switch circuit Sw １ Through this, the first DC electrode 31 and the first capacitor 22a connected to it are connected to the DAC 35. Since the DAC 35 outputs a voltage V1, the voltage V1 is applied to the first capacitor 22a, and the first capacitor 22a is charged to the voltage V1. The charging voltage of the first capacitor 22a is applied to the first DC electrode 31, so the voltage V1 is applied to the first DC electrode 31, and an electric field corresponding to the voltage V1 is generated by the first DC electrode 31.

[0032] Switch circuit Sw １ When time Ps has elapsed since the circuit was turned on, the time constant delay circuit 47 １ The drive pulse signal from the switch circuit SW １ Because input is no longer received, the switch circuit Sw １ It turns off. Switch circuit Sw １ When the switch is turned off, the first DC electrode 31 is electrically disconnected from the DAC 35, but the voltage V1 continues to be applied to the first DC electrode 31 by the charged capacitor 22a.

[0033] Switch circuit Sw １ After the switch is turned off, the voltage control unit 37 switches the switch circuit SW ２ The DC voltage V2 to be applied to the second DC electrode 31 connected to the DAC 35 is output from the DAC 35. Meanwhile, the first stage time constant delay circuit 47 １ The drive pulse signal from the second stage time constant delay circuit 47 ２ Since it is also input, once the delay time Td has elapsed from the time of input, the second stage time constant delay circuit 47２ A drive pulse signal is output from this. This is the second stage time constant delay circuit 47 ２ The drive pulse signal from the switch circuit SW ２ When the switch is turned on, the second capacitor 22a connected to the second DC electrode 31 is charged by the voltage V2 from the DAC 35. Since the charging voltage of the second capacitor 22a is applied to the second DC electrode 31, the voltage V2 is applied to the second DC electrode 31, and an electric field corresponding to the voltage V2 is generated by the second DC electrode 31.

[0034] Switch circuit Sw ２ After time Ps has elapsed since the switch was turned on, the switch circuit Sw ２ This turns off. As a result, the second DC electrode 31 is electrically disconnected from the DAC 35, but the charged second capacitor 22a continues to apply voltage V2 to the second DC electrode 31.

[0035] Switch circuit Sw ２ After the switch is turned off, the voltage control unit 37 switches the switch circuit SW ３ The DC voltage V3 to be applied to the third DC electrode 31 connected to the DAC 35 is output. Also, the second stage time constant delay circuit 47 ２ The drive pulse signal from there is sent to the third stage time constant delay circuit 47 ３ Since it is also input, once the delay time Td has elapsed from the time of input, the third stage time constant delay circuit 47 ３ A drive pulse signal is output from there. Then, the third stage time constant delay circuit 47 ３ The drive pulse signal from the switch circuit SW ３ When the switch is turned on, the third capacitor 22a connected to the third DC electrode 31 is charged to voltage V3 by the DAC 35, and voltage V3 is applied to the third DC electrode 31. ３ The capacitor turns off after a time Ps has elapsed since it was turned on, and the voltage V3 is continuously applied to the third DC electrode 31 by the third charged capacitor 22a.

[0036] Similarly, for the fourth and subsequent DC electrodes 31, the DC voltage output from the DAC 35 is sequentially switched, and the time constant delay circuit 47 from the fourth stage onward is operated. ４ , 47 ５ ...drive pulse signals are output sequentially at intervals of delay time Td. This allows the switch circuit Sw ４ , Sw ５ ...the capacitors are turned on in order, sequentially charging the capacitors 22a connected to the fourth and subsequent DC electrodes 31, and a continuous voltage V4, V5... is applied to the fourth and subsequent DC electrodes 31. In this way, the corresponding DC voltage is applied to each of the M DC electrodes 31.

[0037] The drive pulse signal generation circuit 36 ​​outputs the second drive pulse signal when one generation cycle has elapsed since outputting the first drive pulse signal. In this example, as described above, the generation cycle is set to M times the delay time Td, so the M-th stage time constant delay circuit 47 Ｍ Simultaneously with the output of the drive pulse signal from the first unit, a second drive pulse signal is sent from the drive pulse signal generation circuit 36 ​​to the signal delay unit 23.

[0038] When the second drive pulse signal is input to the signal delay unit 23, the time constant delay circuit 47 is activated in the same manner as when the first drive pulse signal was input. １ , 47 ２ ...Drive pulse signals are output sequentially at intervals of delay time Td, and these drive pulse signals activate the switch circuit Sw １ , Sw ２ ...these are turned on in order. The DAC 35 also switches and outputs the DC voltages V1, V2, etc., which should be applied to each DC electrode 31 a second time, in the same manner as described above. As a result, each capacitor 22a is charged with the second DC voltage when the switch circuit Sw to which it is connected is turned on, and the second voltages V1, V2, etc. are continuously applied to each DC electrode 31.

[0039] After one generation cycle has elapsed since the output of the second drive pulse signal, the third drive pulse signal is sent from the drive pulse signal generation circuit 36 ​​to the signal delay unit 23. In the same manner as when the second drive pulse signal is input, the switch circuit Sw is switched at intervals of delay time Td. １ , Sw ２ ...these are turned on in order. The DAC 35 also sequentially switches and outputs the DC voltages V1, V2, etc., that should be applied to each DC electrode 31 for the third time. As a result, each capacitor 22a continuously applies the third voltage V1, V2, etc. to each DC electrode 31.

[0040] Subsequently, the drive pulse signal generation circuit 36 ​​sequentially outputs drive pulse signals, which are sequentially delayed by the time constant delay circuits 47 of the signal delay unit 23. These delayed drive pulse signals are then used to sequentially turn on multiple switch circuits Sw. In addition, the DAC 35 sequentially switches and outputs DC voltages V1, V2, etc., to be applied to each DC electrode 31, synchronized with the output timing of the drive pulse signals from the signal delay unit 23. This charges the capacitors 22a connected to each DC electrode 31 with the DC voltage to be applied to that DC electrode 31. The charging voltage of the capacitor 22a is then maintained on the DC electrode 31 until the capacitor 22a is charged again by the DC voltage from the DAC 35.

[0041] As described above, the DC voltage applied to each DC electrode 31 is changed over time to control the Z-direction position of the ions trapped in the quantum charge-coupled element 20. Because the switch circuit Sw is turned on sequentially by the signal delay unit 23, which has a small circuit size, it operates accurately even at extremely low temperatures, and the effects of heat generation from the signal delay unit 23 are kept to a minimum.

[0042] If the drive pulse signal is attenuated in the time constant delay circuit 47, a buffer (amplifier) ​​48 may be provided between the preceding time constant delay circuit 47 and the next time constant delay circuit 47, as shown in Figure 6, to amplify the drive pulse signal and maintain it at a predetermined level or higher.

[0043] In the example above, a time constant delay circuit 47 is used as the delay circuit, but the delay circuit is not limited to this. Figure 7 shows a delay circuit using a SAW filter (surface acoustic wave filter) 51, where a signal delay section 23 is constructed by multiple SAW filters 51 connected in series. In this case, the drive pulse signal from the drive pulse signal generation circuit 36 ​​is input to the first stage SAW filter 51 via the modulator 52. Inside the SAW filter 51, a delay occurs when the input modulated wave propagates as a surface acoustic wave from the input side to the output side, so this delay can be used as a delay circuit.

[0044] In the modulator 52, the drive pulse signal is modulated into a modulated wave with a frequency within the passband of the SAW filter 51. The modulated wave output from each stage of the SAW filter 51 is input to the next stage of the SAW filter 51 and also to the switch circuit Sw via the demodulator 53. The demodulator 53 is used to demodulate the modulated wave back into a drive pulse signal that turns on the switch circuit Sw. In this example, the demodulator 53 is composed of an envelope detection circuit 53a and an LPF (low-pass filter) 53b. The envelope detection circuit 53a performs envelope detection on the modulated wave, and then the LPF 53b removes the ripple to demodulate it into a drive pulse signal. The envelope detection circuit 53a can be made of, for example, a diode. The modulator 52 can be provided in either the trap unit 14 or the control unit 15, but from the viewpoint of reducing the circuit size and heat generation on the trap unit 14 side, it is preferable to provide it in the control unit 15. In this example, it is sufficient that the switch circuit Sw is turned on by the drive pulse signal output by the demodulator 53 until the charging voltage of the capacitor 22a reaches the output voltage of the DAC 35; the drive pulse signal output by the drive pulse signal generation circuit 36 ​​and the drive pulse signal output by the demodulator 53 do not need to be the same.

[0045] Figure 8 shows an example in which a D-type flip-flop (hereinafter referred to as D-FF) circuit 55 is used as a delay circuit. The signal delay section 23 in this example is composed of multiple D-FF circuits 55 connected in series. The drive pulse signal from the drive pulse signal generation circuit 36 ​​is input to the first-stage D-FF circuit 55, and the drive pulse signals output from each stage of the D-FF circuit 55 are input to the switch circuit Sw and also to the next-stage D-FF circuit 55. That is, the output of the drive pulse signal generation circuit 36 ​​is connected to the input terminal (D) of the first-stage D-FF circuit 55, and the output terminal (Q) of each stage of the D-FF circuit 55 is connected to the corresponding switch circuit Sw and also to the input terminal (D) of the next-stage D-FF circuit 55.

[0046] Each D-FF circuit 55 receives a clock signal from the clock generation unit 38. The generation period of the clock input to each D-FF circuit 55 is set to be the same as the delay time Td. As a result, the drive pulse signal propagates through each stage of the D-FF circuit 55 and is output with a delay of the delay time Td.

[0047] The above describes an ion trap device 12 of an ion trap type quantum computer 10 in which the trap unit 14 is placed under an extremely low-temperature vacuum. However, the charged particle trap device of the present invention is not limited to this. The charged particle trap device of the present invention can also be used when operated in environments with temperatures higher than extremely low temperatures or at room temperature. For example, the trap unit may be placed in a room temperature environment like the control unit, or the trap unit and control unit may be placed in a low-temperature environment. Furthermore, the trap unit can be placed under extremely low temperatures and the control unit can be placed under low temperatures for use. Moreover, the charged particles whose position is controlled by the charged particle trap device are not limited to ions, but may be charged particles such as semiconductor quantum dots (bits).

[0048] 10 Quantum computer 12 Ion trap device 14 Trap unit 15 Control unit 20 Quantum charge-coupled element 21 Switching section 22 Capacitor section 22a Capacitor 23 Signal delay section 31 DC electrode 36 Drive pulse signal generation circuit 38 Clock generation section 47 Time constant delay circuit 51 SAW filter 52 Modulator 53 Demodulator 53a Envelope detection circuit 53b LPF 55 D-type flip-flop circuit

Claims

1. A charged particle trapping device comprising: an electrode array having a plurality of electrodes for controlling the position of charged particles; a switching unit comprising a plurality of switch circuits provided corresponding to the plurality of electrodes and connected to the corresponding electrodes, each of which switches turn on in response to the input of a drive pulse signal; a drive pulse signal generation circuit that periodically generates a drive pulse signal; a signal delay unit configured by connecting a plurality of delay circuits in series, each of which delays the input drive pulse signal to the corresponding switch circuit and inputs it to a subsequent delay circuit; a digital-to-analog converter whose DC voltage output is switched in synchronization with the output timing of the drive pulse signal from the signal delay unit; and a capacitor unit comprising a plurality of capacitors provided corresponding to each of the plurality of electrodes, one end of which is connected to the corresponding electrode, and which, together with the corresponding electrode, is connected to the digital-to-analog converter via the switch circuit, and which is charged by the DC voltage from the digital-to-analog converter when the switch circuit is turned on, and which continuously applies a constant charging voltage to the corresponding electrode during the off period of the switch circuit.

2. The charged particle trapping device according to claim 1, comprising a trap unit and a control unit separated from the trap unit, wherein the trap unit is provided with at least the electrode array, the signal delay unit, the plurality of capacitors, and the plurality of switch circuits, and the control unit is provided with at least the digital-to-analog converter and the drive pulse signal generation circuit.

3. The charged particle trapping device according to claim 1 or 2, characterized in that the delay circuit is a time constant delay circuit.

4. The charged particle trapping device according to claim 3, characterized in that the signal delay unit is provided with a buffer between the preceding time constant delay circuit and the subsequent time constant delay circuit for amplifying the pulse signal input to the subsequent time constant delay circuit.

5. The charged particle trapping device according to claim 3, characterized in that the time constant delay circuit is an SFQ circuit, an HFQ circuit, or a parametron element.

6. The charged particle trapping device according to claim 1 or 2, comprising a modulator that modulates the drive pulse signal from the drive pulse signal generation circuit into a modulated signal of a predetermined frequency and outputs it to the signal delay unit, and a demodulator connected between the delay circuit and the delay circuit, wherein the delay circuit is a surface acoustic wave filter having a passband that includes the frequency of the modulated signal.

7. The charged particle trapping device according to claim 1 or 2, comprising a clock generation unit that outputs a clock, wherein the signal delay unit has a plurality of D-type flip-flops connected in series as the plurality of delay circuits, and each of the D-type flip-flops is input to a clock from the clock generation unit.

8. The charged particle trapping device according to claim 7, characterized in that the DC voltage output by the digital-to-analog converter is switched in synchronization with the clock from the clock generation unit.

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