Foldable electronic device including plurality of electronic elements

Abstract

Disclosed is a foldable electronic device comprising: a first housing portion (110); a second housing portion (120); a hinge housing portion (150) at least partially disposed between the first housing portion and the second housing portion; a hinge assembly (140); a flexible display (160); a processor (110_ap); a first aggregator circuit (110_ag) configured to convert a first control signal, which is input from the processor through a first number of ports, into a second control signal, which may be output through a second number of ports less than the first number; a second aggregator circuit (120_ag) configured to receive the second control signal through the second number of ports and convert the second control signal into a third control signal, which may be output through a third number of ports greater than the second number; and a flexible printed circuit board (FPCB) (100_fb) connected to the first aggregator circuit and the second aggregator circuit.

Description

Foldable electronic device including multiple electronic elements

[0001] Various embodiments of this document relate to a foldable electronic device comprising a plurality of electronic elements.

[0002] Portable electronic devices, such as smartphones, can support calling and content search functions based on various types of applications. In the process of providing these various functions, portable electronic devices can output a screen corresponding to each function. Users may desire to use a larger screen when utilizing the aforementioned various functions. In conventional portable electronic devices, if the display device is expanded to display the screen, the overall size increases, which may reduce portability. Accordingly, foldable electronic devices are provided to increase the screen size while maintaining portability. Such foldable electronic devices include multiple housings, and the multiple housings may have folded and unfolded states. Various electronic elements may be placed in each of the multiple housings of the foldable electronic device. The electronic elements placed in the multiple housings may be connected via electrical wiring.

[0003] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0004] The aspects of the present disclosure are intended to provide at least the advantages described below. Accordingly, an aspect of the present disclosure provides a foldable electronic device comprising a plurality of electronic components.

[0005] Additional aspects will be presented in part in the following description, and in part may become apparent from the description or be learned (or understood, clarified) by practicing the presented embodiments.

[0006] A foldable electronic device according to various embodiments of the present invention is provided. The foldable electronic device may include a housing comprising a first housing portion (110), a second housing portion (120), and a hinge housing portion (150) disposed at least partially between the first housing portion and the second housing portion; a hinge assembly (140) rotatably connected to the first housing portion and the second housing portion and at least partially accommodated in the hinge housing portion; and a flexible display (160) accommodated in the first housing portion and the second housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing. The foldable electronic device may include a processor (110_ap) housed in the first housing portion, a first aggregator circuit (110_ag) housed in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports less than the first number, a second aggregator circuit (120_ag) housed in the second housing portion and configured to receive the second control signal through the second number of ports and convert the second control signal into a third control signal that can be output through a third number of ports greater than the second number, and a flexible printed circuit board (FPCB) (100_fb) connected to the first aggregator circuit and the second aggregator circuit. A portion of the FPCB may be at least partially coupled to the hinge assembly or at least partially housed in the hinge housing portion and configured to transmit the second control signal.

[0007] A foldable electronic device (or electronic device) according to various embodiments of the present invention is provided. The foldable electronic device may include a housing comprising a first housing portion (110), a second housing portion (120), a third housing portion (130), a first hinge housing portion (151) disposed at least partially between the first housing portion and the second housing portion, and a second hinge housing portion (152) disposed at least partially between the second housing portion and the third housing portion; a first hinge assembly (140) rotatably connected to the first housing portion and the second housing portion and at least partially received in the first hinge housing portion; a second hinge assembly (140-2) rotatably connected to the second housing portion and the third housing portion and at least partially received in the second hinge housing portion; and a flexible display (160) occupied in the first housing portion, the second housing portion, and the third housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing. The foldable electronic device may include a processor (110_ap) housed in the first housing portion, a first aggregator circuit (110_ag) housed in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports less than the first number, a second aggregator circuit (130_ag) housed in the third housing portion and configured to receive the second control signal through a third number of ports and convert the second control signal into a third control signal that can be output through a fourth number of ports greater than the third number, and a connection structure connected to the first aggregator circuit and the second aggregator circuit.The above connection structure may include a first flexible printed circuit board (FPCB) portion (100_fb1) that is at least partially coupled to the first hinge assembly or at least partially received in the first hinge housing portion, and a second FPCB portion (100_fb2) that is at least partially coupled to the second hinge assembly or at least partially received in the second hinge housing portion and configured to transmit the second control signal.

[0008] Other aspects, advantages, and key features of this disclosure may become apparent to those skilled in the art from the following detailed description disclosing various embodiments of this disclosure together with the accompanying drawings.

[0009] The above and other aspects, features, and advantages of specific embodiments of this description may become more apparent from the following description in conjunction with the accompanying drawings.

[0010] FIG. 1 is a front perspective view of a foldable electronic device according to one embodiment.

[0011] FIG. 2 is a plan view of the rear direction of a foldable electronic device according to one embodiment.

[0012] FIG. 3 is a partially exploded perspective view of the foldable electronic device of FIG. 1 and FIG. 2 including a hinge device according to one embodiment.

[0013] FIG. 4 is a drawing showing an example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0014] FIG. 5 is a diagram showing an example of a structure comprising a processor and aggregator circuits, a flexible substrate and a plurality of electronic elements among the configurations of a foldable electronic device according to one embodiment.

[0015] FIG. 6 is a diagram showing another example of a structure comprising a processor and aggregator circuits, a flexible substrate and a plurality of electronic elements among the configurations of a foldable electronic device according to one embodiment.

[0016] FIG. 7 is a drawing showing another example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0017] FIG. 8 is a drawing showing a first example of the arrangement of internal components of a foldable electronic device according to one embodiment. FIG. 9 is a drawing showing at least a portion of a cross-section cut along the A0-A0' cutting line of FIG. 8.

[0018] FIG. 10 is a drawing showing a second example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0019] FIG. 11 is a drawing showing a third example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0020] FIG. 12 is a drawing showing a fourth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0021] FIG. 13 is a drawing showing a fifth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0022] FIG. 14 is a drawing showing at least a portion of a cross-section cut along the A1-A1' cutting line of FIG. 13.

[0023] FIG. 15 is a drawing showing a sixth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0024] FIG. 16 is a diagram showing a seventh example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0025] FIG. 17 is a diagram showing an example of a bus connection between electronic elements of a foldable electronic device according to one embodiment.

[0026] FIG. 18 is a drawing showing the eighth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0027] FIG. 19 is a diagram showing an example of the connection relationship between a processor and an aggregator circuit part and the aggregator circuits of a foldable electronic device according to one embodiment.

[0028] FIG. 20 is a drawing showing an example of a printed circuit board of an interposer structure to which aggregator circuits according to one embodiment are applied.

[0029] FIG. 21 is a drawing showing an example of a rollable electronic device structure to which aggregator circuits according to one embodiment are applied.

[0030] FIG. 22 is a drawing showing an example of a structure improved by applying an aggregator circuit according to one embodiment.

[0031] FIG. 23 is a block diagram of an exemplary electronic device (2300) capable of performing the operations described in this document.

[0032] The same reference number may be used to represent the same element throughout the drawing.

[0033] With reference to the accompanying drawings, the following description may be provided to facilitate a comprehensive understanding of various embodiments of the present invention as defined by the claims and their equivalents. While this description includes various specific details to aid such understanding, they should be considered merely illustrative. Accordingly, those skilled in the art will recognize that various changes and modifications to the various embodiments described herein are possible without departing from the scope and spirit of the present invention. Furthermore, for clarity and brevity, descriptions of well-known functions and configurations may be omitted.

[0034] The terms and words used in the following description and claims are not limited to their bibliographic meanings but are used by the inventor merely to facilitate a clear and consistent understanding of the invention. Accordingly, it will be apparent to those skilled in the art that the following description of various embodiments of the invention is provided for illustrative purposes only and is not intended to limit the scope of the invention as defined by the appended claims and their equivalents.

[0035] The singular forms "a," "an," and "the" should be understood to include the plural form unless the context clearly indicates otherwise. Therefore, for example, a reference to "component surface" may include one or more references to such surfaces.

[0036] Various embodiments of the present document described below can provide a structure that reduces the number of wires electrically connecting electronic elements disposed in multiple housings and enables efficient operation. For example, one embodiment of the present document can reduce (or decrease) the number of wires for signal transmission and reception between a first electronic element disposed in a first housing and a plurality of electronic elements disposed in a second housing, thereby simplifying the wiring structure disposed between the first electronic element and the plurality of electronic elements. Based on this, one embodiment of the present document can support efficient signal transmission between electronic elements while maintaining physically more robust characteristics against stress generated during the folding or unfolding operation of a foldable electronic device. Furthermore, through the embodiments described herein, material cost reduction can be achieved in the manufacturing of foldable electronic devices or in the manufacturing of flexible substrates.

[0037] Other intended purposes according to the embodiments described herein will be mentioned as necessary during the process of explaining each embodiment. For example, various purposes and effects through a foldable electronic device including a plurality of electronic elements according to various embodiments may be mentioned according to the embodiments of the detailed description.

[0038] It should be understood that the blocks of each flowchart and combinations of flowcharts can be executed by one or more computer programs containing instructions. One or more computer programs as a whole may be stored in a single memory device, or one or more computer programs may be divided into multiple parts and stored in multiple memory devices.

[0039] All functions or operations described herein may be processed by a single processor or a combination of processors. A single processor or a combination of processors is a circuit that performs processing and may include an application processor (AP, e.g., a central processing unit (CPU)), a communication processor (CP, e.g., a modem), a graphics processing unit (GPU), a neural processing unit (NPU) (e.g., an artificial intelligence (AI) chip), a wireless fidelity (Wi-Fi) chip, a Bluetooth® chip, a global positioning system (GPS) chip, a near-field communication (NFC) chip, a connectivity chip, a sensor controller, a touch controller, a fingerprint sensor controller, a display driver integrated circuit (IC), an audio codec chip, a universal serial bus (USB) controller, a camera controller, an image processing IC, a microprocessor unit (MPU), a system-on-chip (SoC), an IC, or a similar circuit.

[0040] FIG. 1 is a front perspective view of a foldable electronic device according to one embodiment. FIG. 2 is a rear plan view of a foldable electronic device according to one embodiment.

[0041] Referring to FIGS. 1 and 2, a foldable electronic device (100) (or foldable electronic device, portable electronic device, portable communication device, foldable electronic device having communication function, or electronic device) may be foldably coupled to each other with respect to a folding axis (F) through at least one hinge device (140, 140-1) (e.g., hinge module or hinge structure) and may include a first housing (110) (e.g., first housing structure) including a first side member (113) (e.g., side bezel) and a second housing (120) (e.g., second housing structure) including a second side member (123) (e.g., side bezel). For example, the first housing (110) and the second housing (120) may be configured as a foldable housing (e.g., housing structure). For example, the foldable electronic device (100) may include a first display (160) (e.g., a flexible display, a foldable display, or a main display) positioned to be supported by a first housing (110) and a second housing (120). For example, the first housing (110) may include a first surface (111) and a second surface (112) facing in the opposite direction (e.g., the -z axis direction) of the first surface (111). For example, the second housing (120) may include a third surface (121) and a fourth surface (122) facing in the opposite direction (e.g., the -z axis direction) of the third surface (121). For example, the first housing (110) may include a first rear cover (114) coupled with a first side member (113). For example, the second housing (120) may include a second rear cover (124) combined with a second side member (123). For example, when the foldable electronic device (100) is in a fully unfolded first state (e.g., unfolded state or unfolded state, flat state), the first surface (111) and the third surface (121) may be operated so that they face substantially the same direction (e.g., z-axis direction).For example, when the foldable electronic device (100) is in a completely folded second state (e.g., folded state or folded state), the first surface (111) and the third surface (121) may be operated to face each other or face in opposite directions. For example, the foldable electronic device (100) may be operated to maintain a third state (e.g., intermediate state) between the first state and the second state.

[0042] According to one embodiment, the foldable electronic device (100) may include a first receiver (101) disposed on a first surface (111) of a first housing (110), at least one first sensor module (104) (e.g., an ambient light sensor) and / or at least one first camera module (105) (e.g., a UDC, under display camera). For example, the foldable electronic device (100) may include at least one key (106) disposed on a first side member (113). For example, the foldable electronic device (100) may include at least one second camera module (108) and / or a flash (109) disposed on a second surface (112) of the first housing (110) (e.g., a first rear cover (114)). For example, the foldable electronic device (100) may include a second display (131) disposed on a fourth side (122) of a second housing (120), at least one third camera module (125) (e.g., UDC, under display camera), at least one second sensor module (126) and / or a second receiver (127). For example, the second display (131) may be disposed so as to be visually visible from the outside through at least a portion of the second rear cover (124). For example, the foldable electronic device (100) may include a speaker (102) disposed on a second side member (123), a microphone (103) disposed on a first side member (113), and / or a connector port (107). At least some of the aforementioned components may be repositioned to the first housing (110) and / or the second housing (120).

[0043] According to one embodiment, the first display (160) (e.g., flexible display) may include a first region (160a) (e.g., first planar portion) corresponding to at least a portion of the first surface (111), a second region (160b) (e.g., second planar portion) corresponding to at least a portion of the third surface (121), and a third region (160c) (e.g., flexible portion, flexible part) connecting the first region (160a) and the second region (160b), wherein the foldable electronic device (100) is deformed in a second state (e.g., folded state) and / or a third state. For example, the third region (160c) may be positioned so as to overlap at least partially with at least one hinge device (140, 140-1) when the first display (160) is viewed from above (e.g., in the z-axis direction). For example, the first display (160) may be positioned so as not to be seen from the outside in the second state, with the first surface (111) and the third surface (121) facing each other (e.g., inward-fold type). For example, the first display (160) may be positioned so as to be visually seen from the outside in the second state, with the first surface (111) and the third surface (121) facing in opposite directions (e.g., outward-fold type).

[0044] FIG. 3 is a partially exploded perspective view of a foldable electronic device of FIG. 1 and FIG. 2 including a hinge device according to various embodiments of the present disclosure.

[0045] Referring to FIG. 3, the foldable electronic device (100) may include at least one hinge device (140, 140-1) (e.g., hinge module or hinge structure) connecting a first housing (110) and a second housing (120) below a first display (160) (e.g., in the -z axis direction). For example, the at least one hinge device (140, 140-1) may include a first hinge device (140) and a second hinge device (140-1) spaced apart from the first hinge device (140) along a direction parallel to the folding axis (F) (e.g., in the ± y axis direction). For example, at least one hinge device (140, 140-1) may be supported by a first support member (1131) extending from a first side member (113) into a first space (1101) of a first housing (110) and a second support member (1231) extending from a second side member (123) into a second space (1201) of a second housing (120). For example, at least one hinge device (140, 140-1) may be positioned between the first housing (110) and the second housing (120) so as not to be visually visible from the outside through a hinge housing (150) (e.g., a hinge cover).

[0046] According to one embodiment, the first hinge device (140) may include a first rotation member (141) (e.g., a first arm or a first rotator) disposed on a first support member (1131) of a first housing (110), a second rotation member (142) (e.g., a second arm or a second rotator) disposed on a second support member (1231) of a second housing (120), and a gear assembly (143) connected to the first rotation member (141) and the second rotation member (142) so that the first housing (110) and the second housing (120) rotate symmetrically with respect to each other. For example, the gear assembly (143) may include a plurality of gears (e.g., spur gears and / or worm gears) that are geared to each other. For example, the gear assembly (143) may include a cam coupling structure for providing a free stop at various folding angles, which presses the first housing (110) and the second housing (120) with respect to each other in a direction intended to transition from a first state (e.g., unfolded state) to a second state (e.g., folded state) or from a second state to a first state. For example, the second hinge device (140-1) may have substantially the same configuration as the first hinge device (140).

[0047] According to one embodiment, the foldable electronic device (100) may include a first hinge plate (161) connected to a first support member (1131) and / or a first rotation member (141). The foldable electronic device (100) may include a second hinge plate (162) connected to a second support member (1231) and / or a second rotation member (142). For example, at least one hinge device (140, 140-1), a first rotation member (141), a second rotation member (142), a first hinge plate (161), and a second hinge plate (162) may form substantially the same plane as the first support member (1131) and the second support member (1231) when the foldable electronic device (100) is in a first state. For example, the second hinge device (140-1) may be substantially symmetric to or have substantially the same configuration as the first hinge device (140).

[0048] FIG. 4 is a drawing showing an example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0049] In order to show the connection relationships between a plurality of electronic elements (or electric components, components, elements, electric elements) according to an embodiment of the present invention, other configurations of the foldable electronic device (100) are not shown or are expressed in a simplified manner, but the foldable electronic device (100) of the present invention is not limited thereto. For example, the foldable electronic device (100) shown in FIG. 4 may include at least some of the configurations of the foldable electronic device (100) described above in FIG. 1 to FIG. 3. Accordingly, only some configurations of the foldable electronic device described in FIG. 4 and other drawings are shown and described below, but the present invention is not limited thereto, and structures for various structures and functions that may be included in the foldable electronic device (100) may be further arranged.

[0050] Referring to FIGS. 1 to 4, a foldable electronic device (100) according to one embodiment may include a first housing (110) (or first housing portion) on which a second camera module (108) is disposed, a second housing (120) (or second housing portion), a hinge housing (150) (or hinge housing portion), a first hinge device (140) (or hinge assembly), a first printed circuit board (110_p) (printed circuit board, PCB), a second printed circuit board (120_p), and a flexible substrate (100_fb) (or circuit board, flexible printed circuit board, flexible printed circuit board, FPCB). At least a portion of the hinge housing (150) may be disposed between the first housing (110) and the second housing (120). The first hinge device (140) is received in at least a portion of the hinge housing (150), and the first housing (110) and the second housing (120) may be rotatably connected. Additionally or substantially, the foldable electronic device (100) may include a flexible display (e.g., the first display (160) of FIG. 3 or a flexible display) as previously illustrated in FIG. 1 to 3. The flexible display is received in the first housing (110) and the second housing (120) and may be configured to be folded or unfolded according to the folding or unfolding state or flat state of the housings (e.g., the first housing (110) and the second housing (120)). The flexible display (or first display (160)) may include a first display area (160a) accommodated in a first housing (110), a second display area (160b) accommodated in a second housing (120), and a third display area (160c) disposed between the first display area (160a) and the second display area (160b).

[0051] The first housing (110) may include a configuration identical or similar to the first housing (110) described above in FIGS. 1 to 3. For example, at least a portion of the first housing (110) may be made of a metal material. Alternatively, at least a portion of the first housing (110) may be made of a non-metal material (or injection molded material). The first housing (110) may include, for example, an inner bottom having a rectangular (or polygonal, or a polygonal shape including at least a curved surface) shape and side portions formed at the edges of the bottom and formed higher than the bottom. The inner bottom may include a front portion on which a portion of the first display (e.g., the first display (160) of FIG. 1) is placed and a rear portion on which the first printed circuit board (110_p) is placed. As an example, the foldable electronic device (100) may further include a structure (e.g., boss, adhesive member, adhesive) for fixing a first printed circuit board (110_p) to the bottom (e.g., rear bottom) of the first housing (110). A second camera module (e.g., the second camera module (108) of FIG. 2) may be disposed on one side of the first housing (110), but the foldable electronic device (100) of the present invention is not limited thereto. For example, the second camera module (108) may be disposed in the second housing (120). A battery may be disposed in the first housing (110).

[0052] According to one embodiment, a processor (110_ap) (or processing circuitry, a chip on which the processing circuitry is placed, or at least one processor), a first aggregator circuit (110_ag) (or a first aggregator, a first aggregator circuit chip, a first circuit, a first signal control circuit), and a first signal wiring (110_sg) may be placed on the first printed circuit board (110_p). Meanwhile, in the embodiment of the present invention, only the placement of the processor (110_ap), the first aggregator circuit (110_ag), and the first signal wiring (110_sg) on ​​the first printed circuit board (110_p) has been illustrated, but the present invention is not limited thereto, and a wider variety of electronic elements may be placed therein.

[0053] The above processor (110_ap) can perform at least one of processing, transmitting, sending, receiving, or deleting various signals related to the execution of various user functions or system operation of, for example, a foldable electronic device (100). Such a processor (110_ap) may include, for example, at least one of an application processor, a communication processor, or an artificial intelligence processor. As an example, the above processor (110_ap) may include a processor including a communication interface capable of transmitting and receiving an IO (input / output) signal (or control signal) with the first aggregator circuit (110_ag). Alternatively, the above processor (110_ap) may include a processor including a communication interface capable of transmitting and receiving a signal (I / O signal or control signal) of a first specified speed (e.g., MHz) or lower with the first aggregator circuit (110_ag). For example, at least part of the processor (110_ap) may be configured to transmit and receive a specified signal (e.g., IO signal (input / output signal) (or control signal)) with a first aggregator circuit (110_ag) based on at least one communication method among I2C (inter-integrated circuit), which corresponds to a bidirectional 2-wire serial bus providing a communication link between ICs (integrated chips), I3C (improved inter-integrated circuit) which is compatible with I2C and performs 2-wire communication, I2S (integrated inter-chip sound, or inter IC sound), SPI (serial peripheral interface), IRQ (interrupt request), GPIO (general-purpose input / output), SWI (single wire interface), and 1-wire.Additionally or generally, the processor (110_ap) and the first aggregator circuit (110_ag) may include a communication interface capable of transmitting and receiving a signal of a second specified speed (e.g., greater than MHz to less than or equal to GHz) in response to at least one increase in the allowable size of the aggregator circuit, the allowable power consumption of the aggregator circuit, or the increase in the bandwidth of the serial interface of the aggregator circuit.

[0054] Additionally or generally, the processor (110_ap) may generate a control signal related to driving at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) disposed on the second printed circuit board (120_p) and transmit it to at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6), or receive a signal from the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6). According to one embodiment, the processor (110_ap) may include a housing (e.g., an epoxy structure) disposed on the first printed circuit board (110_p).

[0055] According to one embodiment, the processor (110_ap) may be configured to disable, at least temporarily, the part of the second aggregator circuit (120_ag)9 (or the second aggregator, the second aggregator circuit chip, the second circuit, the second signal conditioning circuit) connected to the touch control module that processes touch input for the foldable display (e.g., the first display (160)) when the housings (110, 120) are fully folded. For example, the processor (110_ap) may be controlled to disable an internal block that processes touch-related I / O (input / output) (e.g., input / output converters related to the touch function in the second aggregator circuit (120_ag)) under conditions that disable the touch function of the foldable display (or the first display (160) of FIG. 3) (e.g., when the housings (110, 120) are fully folded). In this regard, the second aggregator circuit (120_ag) (or the third aggregator circuit (130_ag) described below) may support automatic mode and manual mode setting options. According to one embodiment, in automatic mode, internal blocks of the second aggregator circuit (120_ag) (e.g., at least some of the internal converters or conversion circuits and transmission / reception circuits of the aggregator circuit described in FIG. 5 and FIG. 6) may be automatically enabled by an internal scheduler. For example, an I2C block included in the second aggregator circuit (120_ag) may be automatically enabled when I2C data is input, and automatically disabled when there is no I2C data input (or when it is not received for a set period of time).According to one embodiment, in manual mode, at least some of the internal blocks of the second aggregator circuit (120_ag) (e.g., at least some of the internal converters or conversion circuits and transmission / reception circuits of the aggregator circuit described in FIG. 5 and 6) may be enabled or disabled in response to the control of the processor (110_ap). In this regard, the processor (110_ap) controls the automatic or manual setting of the aggregator circuit (e.g., the second aggregator circuit (120_ag)), and in manual setting, may transmit to the aggregator circuit a signal to wake up or disable a block necessary for signal transmission among the internal blocks included in the aggregator circuit.

[0056] The first aggregator circuit (110_ag) may be housed in the first housing (110) (or housed in the first housing (110) while placed on the first printed circuit board (110_p). The first aggregator circuit (110_ag) may include N first ports (e.g., physical ports, or terminals that transmit or receive signals within the circuit) and M (a natural number smaller than N) second ports (e.g., physical ports, or terminals that transmit or receive signals within the circuit). For example, the first ports may include ports to which wiring placed between the first aggregator circuit (110_ag) and the processor (110_ap) is connected. The second ports may include ports to which wiring is connected, which is positioned between the first aggregator circuit (110_ag) and the flexible substrate (100_fb) (or a connector on the first printed circuit board (110_p) to which the connector of the flexible substrate (100_fb) is connected). According to one embodiment, the first aggregator circuit (110_ag) may be configured to convert a first control signal input from the processor (110_ap) through a first number of ports into a second control signal that can be output through a second number of ports that is less than the first number.

[0057] According to one embodiment, the first aggregator circuit (110_ag) may be configured to transmit and receive multi-IO signals (or control signals) with the processor (110_ap). In this regard, the first aggregator circuit (110_ag) may include input ports that can be connected to at least one of the communication ports of the aforementioned processor (110_ap), such as I2C, I3C, I2S, SPI, IRQ, or GPIO. When the first aggregator circuit (110_ag) receives multi-IO signals from the ports transmitting the multi-IO signals, it may perform serialization on at least some of the received multi-IO signals and transmit them to a second aggregator circuit (120_ag) placed on a second printed circuit board (120_p) through a number of wires smaller than the number of multi-IO signals. In this regard, the first aggregator circuit (110_ag) comprises a buffer capable of storing N signals transmitted by the processor (110_ap), converters (or microcontrollers) for converting the received signals, and M signals (M) of the N signals. <N 자연수)의 신호들로 직렬화할 수 병렬-직렬 변환기 및 수신된 신호들을 병렬화할 수 있는 직렬-병렬 변환기를 포함할 수 있다. 일 예로서, 상기 제1 애그리게이터 회로(110_ag)는 프로세서(110_ap)의 복수의 제어 신호들 또는 다중 IO 신호들 중 적어도 일부를 2개의 직렬 신호로 변환하여 제2 애그리게이터 회로(120_ag)에 전달하도록 구성되고, 제2 애그리게이터 회로(120_ag)로부터 수신된 직렬 신호를 다중 IO 신호들로 변환하여 프로세서(110_ap)에 전달할 수 있다. 상기 제1 애그리게이터 회로(110_ag)는 제1 인쇄회로기판(110_p)의 일 지점에 배치될 수 있다.

[0058] According to one embodiment, the first aggregator circuit (110_ag) may include a serial interface capable of transmitting a number of signals to the second aggregator circuit (120_ag) that is less than the number of multi-input / output signals (Multi IO) input from the processor (110_ap). The serial interface of the first aggregator circuit (110_ag) may be designed to output one IO or two to three IO signals (differential interface 1 lane or 2 lane, I3C+I3C, SPI+I3C…) depending on the bandwidth (BW) selected by design or setting. As an example, in the embodiment described below in FIG. 4 or FIG. 8, the first aggregator circuit (110_ag) may be configured to output a total of eight signals, each consisting of differential data (differential DATA) and clock (CLK) for transmission (TX) and reception (RX). As an example, in the embodiment described below in FIG. 7, the first aggregator circuit (110_ag) (e.g., processor-embedded aggregator circuit) may be configured to output a total of four signals as I3C SDR (single data rate) (DATA, CLK) + I3C HDR (DATA, CLK), or may be configured to output a total of six signals as SPI (DI, DO, BCLK, LRCLK) + I3C HDR (high dynamic range) (DATA, CLK). The second aggregator circuit (120_ag) or the third aggregator circuit (130_ag) (or the third aggregator, the third aggregator circuit chip, the third circuit, the third signal conditioning circuit) may include an input portion composed of signal lines that receive at least a portion of the signals output through the serial interface of the first aggregator circuit (110_ag).

[0059] The second housing (120) may include a configuration identical or similar to the second housing (120) described above in FIGS. 1 to 3. For example, at least a portion of the second housing (120) may be made of a metal material. Alternatively, at least a portion of the second housing (120) may be made of a non-metal material (or injection molded material). The second housing (120) may include, for example, an inner bottom having a rectangular (or polygonal, or a polygonal shape including at least a curved surface) shape and side portions formed at the edges of the bottom and formed higher than the bottom. The inner bottom may include a front portion where another portion of the first display (e.g., the first display (160) of FIG. 1) is placed, and a rear portion where the second printed circuit board (120_p) is placed. As an example, the foldable electronic device (100) may further include a structure (e.g., boss, adhesive member, adhesive) for fixing the second printed circuit board (120_p) to the bottom (e.g., rear bottom) of the second housing (120). A battery may be placed in the second housing (120). The second housing (120) may be formed, for example, identically or similarly to the first housing (110) and connected to the first housing (110) through a first hinge device (140) so as to be positioned at a certain angle with the first housing (110) according to a folding or unfolding operation.

[0060] The second aggregator circuit (120_ag) may be housed in the second housing (120) (or housed in the second housing (120) while placed on the second printed circuit board (120_p)). The second aggregator circuit (120_ag) may include K third ports and L (a natural number greater than K) fourth ports. For example, the third ports may include ports to which wiring is connected that is placed between the first aggregator circuit (110_ag) and the second aggregator circuit (120_ag) (or a connector on the second printed circuit board (120_p) to which the connector of the flexible substrate (100_fb) is connected). The fourth ports of the second aggregator circuit (120_ag) may be connected to at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) disposed on the second printed circuit board (120_p). The K third ports may include the same number as the M second ports of the first aggregator circuit (110_ag). Alternatively, the number of the K third ports may be different from the number of the M second ports of the first aggregator circuit (110_ag). The L fourth ports may include the same number as the N first ports of the first aggregator circuit (110_ag). Alternatively, the number of L fourth ports may differ from the N first ports of the first aggregator circuit (110_ag).

[0061] According to one embodiment, the processor (110_ap) transmits a first number of first control signals to a first aggregator circuit (110_ag), and the first aggregator circuit (110_ag) can convert the first number of first control signals (e.g., N or L) into a second number of second control signals (e.g., M or K) and transmit them to a second aggregator circuit (120_ag). As an example, the first aggregator circuit (110_ag) may include a first port (e.g., N ports) for receiving the first number of first control signals and a second port (e.g., M ports) for transmitting the second number of second control signals to the second aggregator circuit (120_ag).

[0062] The second aggregator circuit (120_ag) may be configured to receive a second control signal through a second number of ports (e.g., K or M) and to convert the second control signal into a third control signal that can be output through a third number of ports (e.g., L or N) that is greater than the second number. As an example, the second aggregator circuit (120_ag) may include a third port (e.g., K ports) for receiving a second number of second control signals and a fourth port (e.g., L ports) for outputting a third number of third control signals.

[0063] According to one embodiment, the first control signal may include a first control signal portion corresponding to a first serial communication having a first speed, and a second control signal portion corresponding to a second serial communication having a second speed different from the first speed. The third control signal may include a third control signal portion corresponding to the first serial communication, and a fourth control signal portion corresponding to the second serial communication. The first aggregator circuit (110_ag) or the second aggregator circuit (120_ag) may be configured to transmit the second control signal through the flexible substrate (100_fb) at a third speed faster than the first speed and the second speed.

[0064] According to one embodiment, a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be disposed on the second printed circuit board (120_p). Alternatively, at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be disposed on the second printed circuit board (120_p). Alternatively, at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be accommodated within the second housing (120). The plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be electrically connected to a second aggregator circuit (120_ag) and configured to receive a third control signal transmitted by the second aggregator circuit (120_ag). At least one of the plurality of electronic elements may be connected to a processor (110_ap) through a second flexible substrate different from the flexible substrate (100_fb). The other second flexible substrate may be at least partially coupled to the first hinge device (140) or at least partially received in the hinge housing (150), and may be configured to deliver a payload associated with at least one electronic element (e.g., a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6)) transmitted by the processor (110_ap) to at least one electronic element. According to one embodiment, the processor (110_ap) may transmit a control signal through the flexible substrate (100_fb) and transmit a payload through the other second flexible substrate.For example, among the signals related to driving a flexible display (e.g., the first display (160) of FIG. 3), the SPI control signal is aggregated and transmitted through the flexible substrate (100_fb), and among the signals related to driving a flexible display, the MIPI (mobile industry processor interface) signal and the power signal may be transmitted through another second flexible substrate. Alternatively, one flexible substrate may include a wiring portion in which the SPI control signal among the signals related to driving a display is aggregated and transmitted, and a wiring portion in which the MIPI signal and the power signal are transmitted.

[0065] According to one embodiment, at least one of the first aggregator circuit (110_ag) and the second aggregator circuit (120_ag) (or the second aggregator, the second aggregator circuit chip) is formed as a structure (e.g., an epoxy structure) in which internal circuits and wirings are arranged, and can be placed on each printed circuit board (e.g., the first printed circuit board (110_p) or the second printed circuit board (120_p)).

[0066] According to one embodiment, the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may include at least one of a sensor module, a PMIC (power managements IC), an audio module, a display control circuit, or a touch control module. Alternatively, the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may include at least one of a digitizer, a display (or display driving circuit), a touch panel (or touch control circuit), a camera, a sub PMIC, a speaker amplifier (speaker AMP), a SIM card (subscriber identity module (SIM) card or SIM socket), sensors, or an audio module. Referring to the illustrated drawing, the second printed circuit board (120_p) may include at least one of a first electronic element (120_pe1) (or first peripheral electronic element) that transmits and receives a control signal (or IO signal) in an I2C manner, a second electronic element (120_pe2) (or second peripheral electronic element) that receives a control signal (or IO signal) in a GPIO manner, a third electronic element (120_pe3) (or third peripheral electronic element) that transmits and receives a control signal (or IO signal) in an I2S manner, a fourth electronic element (120_pe4) (or fourth peripheral electronic element) that transmits and receives a control signal (or IO signal) in an SPI manner, a fifth electronic element (120_pe5) (or fifth peripheral electronic element) that transmits a control signal (or IO signal) in an IRQ manner, and a sixth electronic element (120_pe6) (or sixth peripheral electronic element) that transmits and receives a control signal (or IO signal) in a 13C manner.The plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be configured to receive a designated signal from or transmit to the second aggregator circuit (120_ag) based on any one of the various IO communication methods described above. In this regard, the second printed circuit board (120_p) may include a second signal wiring (120_sg) connecting the second aggregator circuit (120_ag) and the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6). At least a portion of the second signal wiring (120_sg) may be placed on at least one of the plurality of layers of the second printed circuit board (120_p). Meanwhile, the types of each electronic element (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may be changed according to the arrangement of the first to sixth electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) described in FIG. 4. When the placement position of the first internal sixth electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) described in FIG. 4 is changed, the number of signal lines and the types of signal lines included in the second signal wiring (120_sg) connecting each electronic element (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) and the second aggregator circuit (120_ag) may also be changed.

[0067] The flexible substrate (100_fb) may be positioned to connect the first aggregator circuit (110_ag) and the second aggregator circuit (120_ag). A portion of the flexible substrate (100_fb) may be at least partially coupled to the first hinge device (140) or at least partially received in the hinge housing (150) and configured to transmit (or deliver, propagate, output) the second control signal. According to one embodiment, a portion of the flexible substrate (100_fb) (e.g., a portion on the left side in the illustrated drawing) may be positioned to overlap with the first housing (110) (or the first printed circuit board (110_p)) when viewed from the rear to the front of the first display (160) (or with respect to the rear to the front of the first housing (110)). Another part of the flexible substrate (100_fb) (e.g., a part on the right side based on the illustrated drawing) may be positioned to overlap with the second housing (120) (or the second printed circuit board (120_p)) when viewed from the rear to the front of the first display (160) (or with respect to the rear to the front of the second housing (120)). A central part positioned between a part of the flexible substrate (100_fb) and another part of the flexible substrate (100_fb) may be positioned to overlap with a part of the first housing (110) and the second housing (120), or at least a part of the hinge housing (150). For example, the central part of the flexible substrate (100_fb) may be positioned in a curved shape inside the hinge housing (150). The flexible substrate (100_fb) may include flexible substrate wiring (100_se) that transmits a serial signal serialized by a first aggregator circuit (110_ag) to a second aggregator circuit (120_ag) (or transmits a signal serialized by the second aggregator circuit (120_ag) to the first aggregator circuit (110_ag).The flexible substrate wiring (100_se) may include wirings through which serialized signals are transmitted and received. As an example, other wirings may be disposed on the flexible substrate (100_fb) in addition to the flexible substrate wiring (100_se).

[0068] FIG. 5 is a diagram showing an example of a structure comprising a processor and aggregator circuits, a flexible substrate and a plurality of electronic elements among the configurations of a foldable electronic device according to one embodiment.

[0069] Referring to FIGS. 1 to 5, a foldable electronic device (100) according to a given example may include a processor (110_ap), a first aggregator circuit (110_ag), a flexible substrate (100_fb), a second aggregator circuit (120_ag), and a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6). Additionally, the foldable electronic device (100) may include a first signal wiring (110_sg) connecting a processor (110_ap) and a first aggregator circuit (110_ag), and a second signal wiring (120_sg) connecting a second aggregator circuit (120_ag) and a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6).

[0070] The processor (110_ap) may include a configuration substantially identical or similar to the processor (110_ap) described above in FIG. 4. The processor (110_ap) may include interfaces or input / output control ports (110_ap1, 110_ap2, 110_ap3, 110_ap4, 110_ap5, 110_ap6) for various input / output controls. The above input / output control ports (110_ap1, 110_ap2, 110_ap3, 110_ap4, 110_ap5, 110_ap6) may include a first input / output control port (110_ap1) corresponding to I2C, a second input / output control port (110_ap2) corresponding to I3C, a third input / output control port (110_ap3) corresponding to SPI, a fourth input / output control port (110_ap4) corresponding to I2S, a fifth input / output control port (110_ap5) corresponding to GPIO, and a sixth input / output control port (110_ap6) supporting other input / output interfaces. The first signal wiring (110_sg) may include signal lines connected to the plurality of input / output control ports (110_ap1, 110_ap2, 110_ap3, 110_ap4, 110_ap5, 110_ap6). The first signal wiring (110_sg) described in FIG. 5 may include a configuration identical or similar to the first signal wiring (110_sg) described in FIG. 4. Additionally, the arrangement of the signal lines included in the first signal wiring (110_sg) may vary depending on the type of input / output control port.For example, the first signal wiring (110_sg) comprises a certain number of signal lines for signal transmission and reception of each of the plurality of input / output control ports (110_ap1, 110_ap2, 110_ap3, 110_ap4, 110_ap5, 110_ap6) (e.g., 12 pins in 6 groups of I2C (e.g., pins for operating a sensor, PMIC, camera, sub-touchscreen (e.g., a touchscreen placed on the second display (131) of FIG. 2)), 4 pins in 1 group of I2S (e.g., pins for an audio AMP), 9 pins in 2 groups of SPI (e.g., pins for a main touchscreen placed on the first display (160) of FIG. 1, display info), 2 pins in 1 group of I3C (e.g., pins for sensors), and 23 pins in 23 groups of GPIO (e.g., for signals such as enable, reset, interrupt). It may include 50 lines including pins, or a number of lines according to the input / output functions supported by the processor (110_ap).

[0071] The first aggregator circuit (110_ag) may include a configuration identical or similar to the first aggregator circuit (110_ag) described above in FIG. 4. The first aggregator circuit (110_ag) may include a plurality of first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_ap5, 110_ap6) each connected to multiple IO ports (or a plurality of input / output control ports (110_ap1, 110_ap2, 110_ap3, 110_ap4, 110_ap5, 110_ap6)) of the processor (110_ap). Each of the first input / output converters can convert each of the multiple IO block data into a serial interface IO type and transmit it to a signal converter, or convert a signal of the serial interface IO type received from the signal converter into a multiple IO block data type. For example, the plurality of first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6) include a first input / output converter (110_c1) connected to a first input / output control port (110_ap1) of a processor (110_ap), a second input / output converter (110_c2) connected to a second input / output control port (110_ap2) of a processor (110_ap), a third input / output converter (110_c3) connected to a third input / output control port (110_ap3) of a processor (110_ap), a fourth input / output converter (110_c4) connected to a fourth input / output control port (110_ap4) of a processor (110_ap), and a fifth input / output converter connected to a fifth input / output control port (110_ap5) of a processor (110_ap). It may include a sixth input / output converter (110_c6) connected to the sixth input / output control port (110_ap6) of the converter (110_c5) and the processor (110_ap).The first to sixth input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6) may be connected to a first signal converter (110_PS) (serialize / de-serialize block). The first signal converter (110_PS) may include a parallel-to-serial converter and a serial-to-parallel converter. The first signal converter (110_PS) may use a scheduler to schedule data transmitted (delivery, propagation or output) by the input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6) and deliver it to another aggregator circuit (e.g., a second aggregator circuit (120_ag)).

[0072] According to one embodiment, the parallel-to-serial converter of the first signal converter (110_PS) can receive N signals (e.g., control signals) from a plurality of first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6), convert them into M signals (a natural number smaller than N), and then transmit them to the second aggregator circuit (120_ag) through the flexible substrate wiring (100_se) of the flexible substrate (100_fb). The serial-to-parallel converter of the first signal converter (110_PS) can divide K signals received from the second aggregator circuit (120_ag) (or the second signal converter (120_PS) of the second aggregator circuit (120_ag)) into L signals and transmit the divided signals to a plurality of first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6). Alternatively, the serial-to-parallel converter of the first signal converter (110_PS) may divide M signals received from the second aggregator circuit (120_ag) into N signals and transmit the divided signals to each of the plurality of first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, 110_c6).

[0073] According to one embodiment, the first aggregator circuit (110_ag) can aggregate / de-aggregate signals among the signals output from the processor (110_ap) that have a transmission speed below a set reference (e.g., signals transmitted through the 50 lines described above). According to one embodiment, the first aggregator circuit (110_ag) may include an internal SerDes circuit in relation to the serialization or parallelization of signals. Device info and data type information of an electronic element connected to the processor (110_ap) can be transmitted by adding relevant information to the header of the serial packet data. In this process (operation), the processor (110_ap) may use a predefined standard protocol. The serialized signal can be selected according to the total bandwidth, and the processor (110_ap) and aggregator circuit can transmit and receive the serialized signal in a manner such as I2C, I3C, and LVDS (low-voltage differential signaling).

[0074] According to one embodiment, the foldable electronic device (100) may have a plurality of serial interfaces configured for a bandwidth of a certain size or larger, or for specific interface performance. In this case, a plurality of aggregator circuits may be disposed on a single printed circuit board. Correspondingly, the foldable electronic device (100) may include a plurality of flexible substrates connecting the plurality of aggregator circuits disposed on the printed circuit boards. For example, FIG. 4 illustrates that one aggregator circuit (e.g., 110_ag) is disposed on a first printed circuit board (110_p) and one aggregator circuit (e.g., 120_ag) is disposed on a second printed circuit board (120_p), but the foldable electronic device (100) may include a plurality of aggregator circuits disposed on the first printed circuit board (110_p), a plurality of aggregator circuits disposed on the second printed circuit board (120_p), and a plurality of flexible substrates connecting the plurality of aggregator circuits disposed on each printed circuit board (110_p, 120_p).

[0075] The second aggregator circuit (120_ag) may have the same or similar structure as the first aggregator circuit (110_ag). For example, the second aggregator circuit (120_ag) may include a second signal converter (120_PS) and a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6). The second signal converter (120_PS) is connected to the first signal converter (110_PS) through wiring of a flexible substrate (100_fb) and can transmit and receive serialized signals. In this regard, the second signal converter (120_PS) may include a serial-to-parallel converter and a parallel-to-serial converter. As an example, the second signal converter (120_PS) can serialize a parallelized signal received from a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6) and transmit it to the first signal converter (110_PS) of the first aggregator circuit (110_ag) through at least some wiring of the flexible substrate (100_fb). The second signal converter (120_PS) can parallelize a serialized signal received from the first signal converter (110_PS) and then transmit it to a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6). The second signal converter (120_PS) can determine the input / output converter to which at least some of the received control signals are transmitted by checking the header of the serialized signal transmitted by the first signal converter (110_PS). The second signal converter (120_PS) can perform header writing on the signals transmitted by a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6), convert them into serialized signals, and then transmit them to the first signal converter (110_PS).

[0076] The second signal converter (120_PS) has the same or similar structure as the first signal converter (110_PS) and can perform the same or similar operations (e.g., transmission and reception operations (e.g., operations required for transmission and reception or reception and transmission)). As an example, the parallel-to-serial converter of the second signal converter (120_PS) can receive L signals (e.g., signals transmitted by multiple electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6)) from multiple second input / output converters (120_c1, 120_c2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) and convert them into K signals (a natural number smaller than L), and then transmit them to the first aggregator circuit (110_ag) through the flexible substrate wiring (100_se) of the flexible substrate (100_fb). The serial-to-parallel converter of the second signal converter (120_PS) can divide M signals received from the first aggregator circuit (110_ag) into N signals and transmit the divided signals to a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) through a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6). Alternatively, the serial-to-parallel converter of the second signal converter (120_PS) may divide L signals received from the first aggregator circuit (110_ag) into K signals and transmit the divided signals to each of the multiple electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) through a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6).

[0077] According to one embodiment, the plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6) may be placed between the second signal converter (120_PS) and the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6). For example, a plurality of second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6) include a seventh input / output converter (120_c1) disposed between the second signal converter (120_PS) and the first electronic element (120_pe1), an eighth input / output converter (120_c2) disposed between the second signal converter (120_PS) and the second electronic element (120_pe2), a ninth input / output converter (120_c3) disposed between the second signal converter (120_PS) and the third electronic element (120_pe3), a tenth input / output converter (120_c4) disposed between the second signal converter (120_PS) and the fourth electronic element (120_pe4), and a converter disposed between the second signal converter (120_PS) and the fifth electronic element (120_pe5). It may include a 12th input / output converter (120_c6) positioned between a 11th input / output converter (120_c5), a 2nd signal converter (120_PS), and a 6th electronic element (120_pe6). The plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) and the plurality of 2nd input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5, 120_c6) may each be connected through a 2nd signal wiring (120_sg) that transmits multiple IO signals.

[0078] FIG. 6 is a diagram showing another example of a structure comprising a processor and aggregator circuits, a flexible substrate and a plurality of electronic elements among the configurations of a foldable electronic device according to one embodiment.

[0079] Referring to FIGS. 1 to 6, a foldable electronic device (100) according to a given example may include a processor (110_ap), a first aggregator circuit (110_ag), a flexible substrate (100_fb), a second aggregator circuit (120_ag), and a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5). Additionally, the foldable electronic device (100) may include a first signal wiring (110_sg) connecting a processor (110_ap) and a first aggregator circuit (110_ag), and a second signal wiring (120_sg) connecting a second aggregator circuit (120_ag) and a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5). The first signal wiring (110_sg) may be placed on a first printed circuit board (e.g., the first printed circuit board (110_p) of FIG. 4) on which the processor (110_ap) is mounted, and the second signal wiring (120_sg) may be placed on a second printed circuit board (e.g., the second printed circuit board (120_p) of FIG. 4) on which the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5) are mounted.

[0080] The processor (110_ap) may include a plurality of input / output control ports as previously described in FIG. 5. As an example, the processor (110_ap) illustrated in FIG. 6 may include a form exemplifying five input / output control ports. The processor (110_ap) may generate a control signal related to the control of a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5), transmit it to the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5), and receive at least a portion of the signal generated during the operation of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5). For example, the processor (110_ap) can generate input / output control signals related to input / output control of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5) and transmit at least some of the generated input / output control signals to the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5) through aggregator circuits (110_ag, 120_ag).

[0081] The first aggregator circuit (110_ag) may include first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5) (or transmit / receive circuits, or signal transmit / receive interfaces) connected to each of the input / output control ports of the processor (110_ap), and a first signal converter (e.g., a first serial-to-parallel converter (110_PS2) and a first parallel-to-serial converter (110_PS1)).

[0082] Among the first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5), the first input / output converter (110_c1) can transmit a signal transmitted from the processor (110_ap) to the first parallel-serial converter (110_PS1) and transmit a signal transmitted from the first serial-parallel converter (110_PS2) to the processor (110_ap). Alternatively, the first input / output converter (110_c1) may be positioned between the processor (110_ap) and the first parallel-serial converter (110_PS1) or between the first serial-parallel converter (110_PS2) and the processor (110_ap). In this regard, the first input / output converter (110_c1) may include an interface circuit for transmitting and receiving signals with a processor (110_ap), a transmitting circuit (TX) for transmitting a signal received from the processor (110_ap) to a first parallel-to-serial converter (110_PS1), and a receiving circuit (RX) for receiving a signal from a first serial-to-parallel converter (110_PS2). The first input / output converter (110_c1) may be configured to transmit and receive signals through a first type input / output control port of the processor (110_ap) (e.g., a port that transmits and receives signals in I2S mode) and a part of the first signal wiring (110_sg).

[0083] Among the first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5), the second input / output converter (110_c2) may have the same or similar structure as the first input / output converter (110_c1). The second input / output converter (110_c2) may be configured to transmit and receive signals with a second type input / output control port of the processor (110_ap) (e.g., a port that transmits and receives signals via SPI). Among the first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5), the third input / output converter (110_c3) may have a structure similar to the first input / output converter (110_c1). The third input / output converter (110_c3) may be configured to transmit and receive signals with a third type input / output control port of the processor (110_ap) (e.g., a port that transmits and receives signals via I2C or I3C). Among the first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5), the fourth input / output converter (110_c4) (or output converter) may include a transmission circuit (TX) configured to transmit a signal received from the processor (110_ap) to the first parallel-to-serial converter (110_PS1). The fourth input / output converter (110_c4) may be configured to transmit and receive signals with a fourth type input / output control port (or output control port) of the processor (110_ap) (e.g., a port that transmits signals via GPIO). The fifth input / output converter (110_c5) (or input converter) among the first input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5) may include a receiving circuit (TX) configured to transmit a signal received from the first serial-to-parallel converter (110_PS2) to a processor (110_ap).The above-mentioned fifth input / output converter (110_c5) can be configured to transmit a signal to a fifth type input / output control port (or input control port) of the processor (110_ap) (e.g., a port that receives a signal via IRQ).

[0084] The first parallel-to-serial converter (110_PS1) can serialize signals (e.g., multiple IO control signals) transmitted by the first input / output converter (110_c1), the second input / output converter (110_c2), the third input / output converter (110_c3), and the fourth input / output converter (110_c4), and then transmit the serialized signals to the second aggregator circuit (120_ag) through the flexible substrate wiring (100_se) of the flexible substrate (100_fb). The first serial-to-parallel converter (110_PS2) can parallelize the serialized signal received through the flexible substrate wiring (100_se) of the flexible substrate (100_fb) and then transmit the parallelized signals to each input / output converter (e.g., first input / output converter (110_c1), second input / output converter (110_c2), third input / output converter (110_c3), fifth input / output converter (110_c5)).

[0085] The flexible substrate (100_fb) connects the first aggregator circuit (110_ag) and the second aggregator circuit (120_ag), and at least a portion may be coupled to or housed in at least one of a hinge housing (e.g., the hinge housing (150) of FIG. 4) or the first hinge device (140). For example, the flexible substrate wiring (100_se) of the flexible substrate (100_fb) may include a first wiring (100_se_t) connecting between a first parallel-to-serial converter (110_PS1) of a first aggregator circuit (110_ag) and a second serial-to-parallel converter (120_PS2) of a second aggregator circuit (120_ag), and a second wiring (100_se_r) connecting between a first serial-to-parallel converter (110_PS2) of the first aggregator circuit (110_ag) and a second parallel-to-serial converter (120_PS1) of the second aggregator circuit (120_ag). The first wiring (100_se_t) of the flexible substrate wiring (100_se) can function as a transmission line on the side of the first aggregator circuit (110_ag) and as a reception line on the side of the second aggregator circuit (120_ag). The second wiring (100_se_r) of the flexible substrate wiring (100_se) can function as a reception line on the side of the first aggregator circuit (110_ag) and as a transmission line on the side of the second aggregator circuit (120_ag).

[0086] The plurality of electronic elements may include, for example, first to fifth electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5). The first to fifth electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5) may include at least some of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) described above in FIG. 5. As an example, the first to fifth electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5) may include at least one of a digitizer, a display (or display driving circuit), a touch panel (or touch control circuit), an audio module, a camera, a sub PMIC, a speaker amplifier, a SIM card, or sensors.

[0087] The second aggregator circuit (120_ag) may include second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5) (or transmit / receive circuits, or signal transmit / receive interfaces) connected to each of the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5), and a second signal converter (e.g., a second serial-to-parallel converter (120_PS1) and a second parallel-to-serial converter (120_PS2)).

[0088] Among the second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5), the seventh input / output converter (120_c1) can transmit a signal transmitted from the first electronic element (120_pe1) to the second parallel-serial converter (120_PS2) and transmit a signal transmitted from the second serial-parallel converter (120_PS1) to the first electronic element (120_pe1). Alternatively, the seventh input / output converter (120_c1) may be placed between the first electronic element (120_pe1) and the second parallel-serial converter (120_PS2) or between the second serial-parallel converter (120_PS1) and the first electronic element (120_pe1). In this regard, the seventh input / output converter (120_c1) may include an interface circuit for transmitting and receiving signals with a first electronic element (120_pe1), a transmitting circuit (TX) for transmitting a signal received from the first electronic element (120_pe1) to a second parallel-to-serial converter (120_PS2), and a receiving circuit (RX) for receiving a signal from the second serial-to-parallel converter (120_PS1). The seventh input / output converter (120_c1) may be configured to transmit and receive a first type input / output control signal (e.g., a control signal according to the I2S method) through a part of the second signal wiring (120_sg).

[0089] Among the second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5), the eighth input / output converter (120_c2) may have the same or similar structure as the seventh input / output converter (120_c1). The eighth input / output converter (120_c2) may be configured to transmit and receive a second type input / output control signal (e.g., a control signal according to the SPI method) of the second electronic element (120_pe2). Among the second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5), the ninth input / output converter (120_c3) may have a structure similar to the seventh input / output converter (120_c1). The ninth input / output converter (120_c3) may be configured to transmit and receive a third type input / output control signal (e.g., a control signal according to the I2C or I3C method) of the third electronic element (120_pe3). Among the second input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5), the tenth input / output converter (120_c4) (or output converter) may include a transmission circuit (TX) configured to transmit a signal received from the fourth electronic element (120_pe4) to the second parallel-to-serial converter (120_PS2). The tenth input / output converter (120_c4) may be configured to transmit a fourth type input / output control signal (e.g., a control signal according to the IRQ method) of the fourth electronic element (120_pe4) to the second parallel-to-serial converter (120_PS2). The 11th input / output converter (120_c5) (or input converter) among the 2nd input / output converters (120_c1, 120_c2, 120_c3, 120_c4, 120_c5) may include a receiving circuit (TX) configured to transmit a signal received from the 2nd serial-to-parallel converter (120_PS1) to the 5th electronic element (120_pe5).The above-mentioned 11th input / output converter (120_c5) can be configured to transmit a 5th type input / output control signal (e.g., a control signal received according to the GPIO method) received from the 2nd serial-parallel converter (120_PS1) to the 5th electronic element (120_pe5).

[0090] The second parallel-to-serial converter (120_PS2) can serialize signals (e.g., multiple IO control signals) transmitted by the seventh input / output converter (120_c1), the eighth input / output converter (120_c2), the ninth input / output converter (120_c3), and the tenth input / output converter (120_c4), and then transmit the serialized signals to the first aggregator circuit (110_ag) through the flexible substrate wiring (100_se) of the flexible substrate (100_fb). The second serial-to-parallel converter (120_PS1) can parallelize the serialized signal received through the flexible substrate wiring (100_se) of the flexible substrate (100_fb) and then transmit the parallelized signals to each input / output converter (e.g., the 7th input / output converter (120_c1), the 8th input / output converter (120_c2), the 9th input / output converter (120_c3), the 11th input / output converter (120_c5)).

[0091] The structure of the aggregator circuits of the foldable electronic device (100) described in FIG. 5 and FIG. 6 above may be applied to the structure of at least some of the various aggregator circuits or aggregator circuit parts described in FIG. 4 or below.

[0092] The structure illustrated in FIG. 6 above illustrates a structure in which a total of eight serial lines (or serial wiring) are applied by implementing a clock (CLK) and a data differential pair (or differential data pair) for transmission (TX) and reception (RX), respectively. The embodiments described herein are not limited thereto, and the foldable electronic device (100) may have a structure including a total of six serial lines, consisting of two I3C (CLK, DATA) ports and one Sound-wire (DATA, CLK) port. Alternatively, if necessary, the foldable electronic device (100) may include an aggregator circuit comprising eight or more or fewer than six various signal lines. The 50 aforementioned signals are serialized in an aggregator circuit (e.g., a first aggregator circuit (110_ag)), and the data converted into serialized signals in correspondence is transmitted to another printed circuit board through an extension board (100_fb), and the 7 to 8 serialized signals transmitted (delivery, propagation, or output) are input to an aggregator circuit (e.g., a second aggregator circuit (120_ag)) placed on the other printed circuit board (e.g., a second printed circuit board (120_p)), and can be converted into 50 low-speed signals suitable for multiple electronic elements (peripheral devices) connected to the output port of the aggregator circuit (e.g., a second aggregator circuit (120_ag)).According to one embodiment, the low speed signal may include signals in the MHz band (e.g., 1 MHz to 20 MHz), and depending on the bandwidth of the serial interface, the processor (110_ap) or the aggregator circuit (110_ag or 120_ag) may determine the aggregated low speed signal data rate. According to one embodiment, the bandwidth of the serial interface may be determined according to the total data rate of the aggregated low speed signals. As described above, when aggregator circuits (110_ag, 120_ag) are applied to the foldable electronic device (100), the 50 lines transmitting signals below a reference speed can be reduced to 6 to 8 serial lines, so the size of the flexible substrate (100_bf) can be reduced to a size smaller than a certain size (e.g., 12 to 14 mm) and additional components (e.g., 78-pin connector components) can also be removed.

[0093] FIG. 7 is a drawing showing another example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0094] Similar to the foldable electronic device (100) shown in FIG. 4, the foldable electronic device (1111) shown in FIG. 7 has other components not shown or simplified to indicate the connection relationship between a plurality of electronic elements according to the embodiment of the present invention, but the foldable electronic device (1111) of the present invention is not limited thereto.

[0095] Referring to FIGS. 1 through 7, a foldable electronic device (1111) according to one embodiment may include a first housing (110) (or first housing portion) on which a second camera module (108) is disposed, a second housing (120) (or second housing portion), a hinge housing (150) (or hinge housing portion), a first hinge device (140) (or hinge assembly), a first printed circuit board (110_p), a second printed circuit board (120_p), and a flexible substrate (100_fb) (or flexible printed circuit board, FPCB). At least a portion of the hinge housing (150) may be disposed between the first housing (110) and the second housing (120). The first hinge device (140) is received in at least a portion of the hinge housing (150), and the first housing (110) and the second housing (120) may be rotatably connected. Additionally, or generally, the foldable electronic device (1111) may include a flexible display (e.g., the first display (160) of FIG. 3 or a flexible display) as previously illustrated in FIG. 1 to 3.

[0096] The first housing (110) may include the same or similar configuration as the first housing (110) described in FIG. 4. Accordingly, the description of the first housing (110) may be replaced or supplemented by the description of the first housing (110) described in FIG. 4.

[0097] According to one embodiment, the first printed circuit board (110_p) may include a processor (110_ap) (or processing circuitry, or at least one processor) in which an aggregator circuit portion (110_agi) (e.g., an embedded aggregator circuit portion configured to be embedded inside the processor (110_ap), or an aggregator circuit portion) is embedded. Meanwhile, in the embodiment of the present invention, only the arrangement of a processor (110_ap) in which an aggregator circuit portion (110_agi) is embedded on the first printed circuit board (110_p) has been illustrated, but the present invention is not limited thereto, and a wider variety of electronic elements may be further arranged.

[0098] The above processor (110_ap) can perform at least one of processing, transmitting, sending, receiving, or deleting various signals related to the execution of various user functions or system operation of, for example, a foldable electronic device (1111). Such a processor (110_ap) may include, for example, at least one of an application processor, a communication processor, or an artificial intelligence processor. As an example, the processor (110_ap) may include an aggregator circuit part (110_agi) and input / output controllers (IO controllers) capable of transmitting and receiving IO (input / output) signals (or control signals). For example, at least a portion of the processor (110_ap) may include at least one input / output controller among an I2C (inter-integrated circuit) controller, an I3C (improved inter-integrated circuit) controller, an I2S (integrated inter-chip sound, or inter IC sound) controller, a SPI (Serial Peripheral Interface) controller, an IRQ (Interrupt Request) controller, and a GPIO (general-purpose input / output) controller. The embedded aggregator circuit portion (110_agi) included in the processor (110_ap) may include a plurality of input / output converters connected to the input / output controllers and a signal converter connected to the plurality of input / output converters. The processor (110_ap) may include N internal signal wires connecting the input / output controllers and the plurality of input / output converters, N internal signal wires connecting the plurality of input / output converters and the signal converter, and may include M (e.g., a natural number smaller than N) input / output ports connected to the signal converter.The input / output ports of the signal converter built into the above processor (110_ap) can be electrically connected to the flexible substrate wiring (100_se) of the flexible substrate (100_fb).

[0099] A processor (110_ap) including the above-described embedded aggregator circuit portion (110_agi) can be designed (or configured) such that the signal wiring (e.g., the first signal wiring (110_sg) of FIG. 4) connecting the aggregator circuit (e.g., the first aggregator circuit (110_ag) of FIG. 4) and the processor (110_ap) is removed, and the input / output controllers inside the processor (110_ap) are directly connected to the input / output converters of the aggregator circuit portion (110_agi) (e.g., the input / output converters (110_c1, 110_c2, 110_c3, 110_c4, 110_c5, or 110_c6) described in FIG. 5 or 6), thereby providing a more simplified foldable electronic device structure. The role of the aggregator circuit portion (110_agi) is as described in FIG. 4 It can perform the same or similar role as the first aggregator circuit (110_ag) described in FIG. 6. For example, the aggregator circuit portion (110_agi) can be configured to transmit and receive multi-IO signals (or control signals) with the input / output controllers of the processor (110_ap). The aggregator circuit portion (110_agi) can perform serialization of the multi-IO signals generated by the processor (110_ap) and transmit them to the second aggregator circuit (120_ag) placed on the second printed circuit board (120_p) through M input / output ports and signal wiring, which are smaller than the number of N multi-IO signals. In this regard, the aggregator circuit portion (110_agi) includes a buffer portion capable of storing N signals generated by the input / output controllers of the processor (110_ap), and a converter portion (or microcontroller, input / output) that converts the received signals. converters), N signals M (M <N 자연수)의 신호들로 직렬화할 수 있는 병렬-직렬 변환 부분 및 수신된 신호들을 병렬화할 수 있는 직렬-병렬 변환 부분을 포함할 수 있다.

[0100] The second housing (120) may include the same or similar configuration as the second housing (120) described above in FIGS. 1 to 4. Accordingly, the description of the second housing (120) may be replaced or supplemented by the description of the second housing (120) of FIGS. 1 to 4 described above.

[0101] The second aggregator circuit (120_ag) may include a configuration identical or similar to the second aggregator circuit (120_ag) described above in FIGS. 1 to 6. Accordingly, the description of the second aggregator circuit (120_ag) may be replaced or supplemented by the description of the second aggregator circuit (120_ag) of FIGS. 4 to 6 described above. As an example, the second aggregator circuit (120_ag) may include K third ports and L (a natural number greater than K) fourth ports. The K third ports may be formed identical or similar to the number of flexible substrate wirings (100_se) of the flexible substrate (100_fb). The L fourth ports may be formed identical or similar to the number of wirings for communication of multiple electronic elements described above in FIGS. 4 to 6. The above K third ports may include the same number as the M ports of the aggregator circuit portion (110_agi), but the present description is not limited thereto. The above L fourth ports may include the same number as the N wires connecting the input / output controllers of the processor (110_ap) and the aggregator circuit portion (110_agi), but the present description is not limited thereto.

[0102] The second printed circuit board (120_p) may include the same or similar configuration as the second printed circuit board (120_p) described above in FIG. 4. Accordingly, the description of the second printed circuit board (120_p) may be replaced or supplemented by the description of the second printed circuit board (120_p) in FIG. 4 described above. As an example, at least one of a first electronic element (120_pe1) communicating via a first type communication channel (e.g., I2C), a second electronic element (120_pe2) communicating via a second type communication channel (e.g., GPIO), a third electronic element (120_pe3) communicating via a third type communication channel (e.g., I2S), a fourth electronic element (120_pe4) communicating via a fourth type communication channel (e.g., SPI), a fifth electronic element (120_pe5) communicating via a fifth type communication channel (e.g., IRQ), and a sixth electronic element (120_pe6) communicating via a sixth type communication channel (e.g., I3C) may be disposed on the second printed circuit board (120_p).

[0103] According to one embodiment, the plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6) may include at least one of a sensor module, a PMIC (power managements IC), an audio module, a display, a touch panel, a display control circuit or a touch control module, a camera, a sub PMIC, a speaker amplifier, or a SIM card or SIM socket.

[0104] The flexible substrate (100_fb) may be positioned to connect the aggregator circuit portion (110_agi) of the processor (110_ap) and the second aggregator circuit (120_ag). The flexible substrate (100_fb) may be partially coupled to the first hinge device (140) or partially accommodated in the hinge housing (150). The flexible substrate (100_fb) may be configured identically or similarly to the flexible substrate (100_fb) described above in FIG. 4 (or at least one of FIG. 5 and FIG. 6), except for connecting the aggregator circuit portion (110_agi) embedded in the processor (110_ap) and the second aggregator circuit (120_ag). Accordingly, the description of the flexible substrate (100_fb) may be replaced or supplemented by the description of the flexible substrate (100_fb) described in the preceding drawings. According to one embodiment, the flexible substrate (100_fb) may include a flexible substrate wiring (100_se) that transmits a serial signal serialized by an aggregator circuit portion (110_agi) to a second aggregator circuit (120_ag) (or transmits a signal serialized by the second aggregator circuit (120_ag) to the aggregator circuit portion (110_agi). The flexible substrate wiring (100_se) may include wirings through which serialized signals are transmitted and received. As an example, other wirings may be disposed on the flexible substrate (100_fb) in addition to the flexible substrate wiring (100_se).

[0105] As described above, a foldable electronic device (1111) according to one embodiment may include a structure in which an aggregator circuit is embedded within a processor (110_ap). In this case, by providing a separate aggregator circuit in a concentrated manner, space related to the placement of a separate aggregator circuit can be saved. For example, the foldable electronic device (1111) of the present invention can reduce the size of the first printed circuit board (110_p) and can provide more stable and better signal transmission and reception performance through the operation of the aggregator circuit portion (110_agi) embedded within the processor (110_ap).

[0106] The second aggregator circuit (120_ag) may include at least a portion of the structure of the aggregator circuit described in FIG. 5 or FIG. 6. The aggregator circuit portion (110_agi) may include at least a portion of the structure of the aggregator circuit described in FIG. 5 or FIG. 6, except for the portion where a separate housing (or epoxy structure) for chip design is removed as the aggregator circuit portion (110_agi) is formed inside the processor (110_ap).

[0107] FIG. 8 is a drawing showing a first example of the arrangement of internal components of a foldable electronic device according to one embodiment. FIG. 9 is a drawing showing at least a portion of a cross-section cut along the A0-A0' cutting line of FIG. 8. According to one embodiment, the cutting line A0-A0' shown in FIG. 8 is schematically depicted in the drawing, but can be arranged to cut specific signal wiring in each component. Additionally, the electronic element (130_pe) shown in FIG. 9 indicates a specific electronic element placed at a position cut by the cutting line A0-A0', and can be any one of a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) that can be placed on a third printed circuit board (130_p). According to one embodiment, at least a portion of the structure of the cut surface described in FIG. 9 can also be applied to FIG. 4 described above. For example, the flexible substrate (100_fb) described in FIG. 4 may be formed identically or similarly to the first flexible substrate (100_fb1) described in FIG. 9, and accordingly, the flexible substrate (100_fb) may include a first connector (100_co1) coupled to the first substrate connector (110_co) of the first printed circuit board (110_p) and a second connector (100_co2) coupled to the second substrate connector (121_co1) of the second printed circuit board (121_p).

[0108] Similar to the foldable electronic device (100) shown in FIG. 4, the foldable electronic device (1112) shown in FIG. 8 (or a second type foldable electronic device, a foldable electronic device that folds two or more times) has other components not shown or simplified to indicate the connection relationship between a plurality of electronic elements according to the embodiment of the present invention, but the foldable electronic device (1112) of the present invention is not limited thereto.

[0109] Referring to FIGS. 1 through 8, a foldable electronic device (1112) may include a first housing (110) (or first housing portion) on which a second camera module (108) is disposed, a second housing (120) (or second housing portion), a third housing (130) (or third housing portion), a first hinge housing (151) (or first hinge housing portion), a second hinge housing (152) (or second hinge housing portion), a first hinge device (140) (or first hinge assembly), a third hinge device (140-2) (or second hinge assembly), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1), and a second flexible substrate (100_fb2).

[0110] The first hinge housing (151) may be partially positioned between the first housing (110) and the second housing (120). The first hinge device (140) may be partially received in the first hinge housing (151), and the first housing (110) and the second housing (120) may be rotatably connected. The second hinge housing (152) may be partially positioned between the second housing (120) and the third housing (130). The third hinge device (140-2) may be partially received in the second hinge housing (152), and the second housing (120) and the third housing (130) may be rotatably connected. Although the above description exemplifies that a single hinge device is disposed in a single hinge housing, the foldable electronic device (1112) described herein is not limited thereto, and a plurality of hinge devices (e.g., 140, 140-1) may be accommodated in a single hinge housing (e.g., 151 or 152). Additionally, the first hinge device (140), which is partially accommodated in the first hinge housing (151), and the third hinge device (140-2), which is partially accommodated in the second hinge housing (152), may be configured in different types. For example, the first hinge device (140) may be configured as an in-folding or inward-fold type hinge device (or an out-folding or outward-fold type hinge device), and the third hinge device (140-2) may be configured as an out-folding type hinge device (or an in-folding type hinge device).

[0111] Additionally or generally, the foldable electronic device (1112) may include a flexible display (e.g., the first display (160) of FIG. 3 or a flexible display) as previously illustrated in FIG. 1 through 4. At least a portion of the flexible display is accommodated in the first housing (110) through the third housing (130) and may be configured to be folded or unfolded according to the folding or unfolding state or flat state of the housings (e.g., the first housing (110), the second housing (120), and the third housing (130)).

[0112] The first housing (110) may include a configuration identical or similar to at least one of the first housings (110) described in FIGS. 1 to 4 and FIG. 7. Accordingly, the specific description of the first housing (110) may be replaced or supplemented by the description of the first housing (110) described above. For example, a first printed circuit board (110_p) may be disposed in the first housing (110).

[0113] According to one embodiment, the first printed circuit board (110_p) may have a processor (110_ap) (or processing circuitry, or at least one processor), a first aggregator circuit (110_ag) (or a first aggregator), a first signal wiring (110_sg), a first substrate wiring (110_s1), a PMIC (110_PM) (or an electric component or component of the first housing (110)), and a second substrate wiring (110_s2) disposed thereon. Meanwhile, in the embodiment of the present invention, only the arrangement of a processor (110_ap), a first aggregator circuit (110_ag), a first signal wiring (110_sg), a first circuit wiring (110_se), a first substrate wiring (110_s1), a PMIC (110_PM), and a second substrate wiring (110_s2) on a first printed circuit board (110_p) has been illustrated, but the present invention is not limited thereto, and a wider variety of electronic elements may be arranged. According to one embodiment, the speed of the signal transmitted through the first substrate wiring (110_s1) and the second substrate wiring (110_s2) may be faster than the speed of the signal transmitted through the first circuit wiring (110_se). Alternatively, a high speed signal (e.g., a GHz band signal) may be transmitted through substrate wiring (e.g., a first substrate wiring (110_s1), a second substrate wiring (110_s2)), and a low speed signal (e.g., a MHz band signal) may be transmitted through circuit wiring (e.g., a first circuit wiring (110_se)). The speed standards of the high speed signal and the low speed signal may vary depending on the hardware specifications (or performance) of the device to which they are applied.

[0114] According to one embodiment, the first printed circuit board (110_p) may include a first board connector (110_co) coupled to a first connector (100_co1) formed on the first flexible board (100_fb1), and a first circuit wiring (110_se) connecting the first aggregator circuit (110_ag) and the first board connector (110_co). The first circuit wiring (110_se) may be used to transmit and receive serialized signals. The first signal wiring (110_sg) is arranged to connect a first part of the processor (110_ap) (or first input / output ports, first input / output leads) to a first aggregator circuit (110_ag), and the first substrate wiring (110_s1) may be arranged to connect a second part of the processor (110_ap) (or second ports, second leads) to a first substrate connector (110_co). The second substrate wiring (110_s2) may be arranged to connect a PMIC (110_PM) to the first substrate connector (110_co). The first substrate wiring (110_s1) and the second substrate wiring (110_s2) can connect the first substrate connector (110_co) and the second part of the processor (110_ap) or the PMIC (110_PM) without passing through the first aggregator circuit (110_ag). The first printed circuit board (110_p) may include a part (e.g., the first substrate connector (110_co)) connected to the first connector (100_co1) disposed at the first end of the first flexible substrate (100_bf1).

[0115] The above processor (110_ap) can perform at least one of processing, transmitting, sending, receiving, or deleting various signals related to the execution of various user functions or system operation of, for example, a foldable electronic device (1112). Such a processor (110_ap) may be identical to or at least partially similar to the processor (110_ap) described above in FIGS. 1 to 7. Accordingly, the description of the processor (110_ap) in FIG. 8 may be replaced or supplemented by the description of the processor (110_ap) described above in FIGS. 1 to 7. According to one embodiment, at least a portion of the processor (110_ap) may be configured to transmit and receive IO signals (input / output signals) (or control signals) with a first aggregator circuit (110_ag) based on at least one communication method among I2C (inter-integrated circuit), I3C (improved inter-integrated circuit), I2S (integrated inter-chip sound, or inter IC sound), SPI (serial peripheral interface), IRQ (interrupt request), and GPIO (general-purpose input / output). In this regard, a first signal wiring (110_sg) for transmitting and receiving multiple IO signals may be arranged between the processor (110_ap) and the first aggregator circuit (110_ag).Additionally or generally, the processor (110_ap) may generate a control signal related to driving a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) disposed on a third printed circuit board (130_p) and transmit it to the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), or receive a signal from the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6). According to one embodiment, the processor (110_ap) may include a port connected to a first substrate wiring (110_s1) for transmitting and receiving a signal (e.g., payload) related to the operation of the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).

[0116] The first aggregator circuit (110_ag) may be housed in the first housing (110) (or housed in the first housing (110) while placed on the first printed circuit board (110_p). The first aggregator circuit (110_ag) may have the same or similar configuration as the first aggregator circuit (110_ag) described earlier in FIG. 4 (or FIG. 5 and 6). Accordingly, the description of the first aggregator circuit (110_ag) in FIG. 8 may be replaced or supplemented by the description of the first aggregator circuit (110_ag) in the preceding drawings. As an example, the first aggregator circuit (110_ag) may include a buffer capable of storing N signals transmitted by a processor (110_ap), converters (or microcontrollers, I / O converters) that convert the received signals, and M signals (M <N 자연수)의 신호들로 직렬화할 수 병렬-직렬 변환기 및 수신된 신호들을 병렬화할 수 있는 직렬-병렬 변환기를 포함할 수 있다. 일 실시 예에 따르면, 상기 제1 애그리게이터 회로(110_ag)는 제1 연성 기판(100_fb1)의 제1 커넥터(100_co1)(또는 제1 인쇄회로기판(110_p)에 배치된 제1 기판 커넥터(110_co)와 연결하는 커넥터)와 제1 회로 배선(110_se)을 통해 연결될 수 있다.

[0117] The second housing (120) may be disposed between the first housing (110) and the third housing (130). At least a portion of the second housing (120) may be made of a metal material. Alternatively, at least a portion of the second housing (120) may be made of a non-metal material (or injection molded material). The second housing (120) may include, for example, an inner bottom having a rectangular (or polygonal, or at least a polygonal shape including a curved surface) shape and side portions formed at the edges of the bottom and formed higher than the bottom. The inner bottom may include a front portion on which a portion of the foldable display is disposed and a rear portion on which a second printed circuit board (121_p) is disposed. As an example, the foldable electronic device (1112) may further include a structure (e.g., boss, adhesive member, adhesive) for fixing the second printed circuit board (121_p) to the bottom (e.g., rear bottom) of the second housing (120). A battery may be placed in the second housing (120). The second housing (120) may be connected to the first housing (110), for example, through a first hinge device (140), and positioned at a certain angle with the first housing (110) according to a folding or unfolding motion. The second housing (120) may be connected to the third housing (130), for example, through a third hinge device (140-2), and positioned at a certain angle with the third housing (130) according to a folding or unfolding motion.

[0118] According to one embodiment, the second printed circuit board (121_p) may be disposed on one side of the second housing (120). The second printed circuit board (121_p) may include a second board connector (121_co1) (or the first board connector of the second printed circuit board (121_p)) connected to a second connector (100_co2) formed on the first flexible board (100_fb1), and a third board connector (121_co2) (or the second board connector of the second printed circuit board (121_p)) connected to a third connector (100_co3) formed on the second flexible board (100_fb2). The second printed circuit board (121_p) may include a second circuit wiring (121_se) connecting a first portion of the second board connector (121_co1) and a first portion of the third board connector (121_co2), a third board wiring (121_s1) connecting a second portion of the second board connector (121_co1) and a second portion of the third board connector (121_co2), and a fourth board wiring (121_s2) connecting a third portion of the second board connector (121_co1) and a third portion of the third board connector (121_co2). The second circuit wiring (121_se) may be connected to the first circuit wiring (110_se) through the wiring of the first flexible board (100_fb1) (e.g., the first flexible board wiring (100_se1)). The third substrate wiring (121_s1) is connected to the first substrate wiring (110_s1) through the wiring of the first flexible substrate (100_fb1), and the fourth substrate wiring (121_s2) can be connected to the second substrate wiring (110_s2) through the wiring of the first flexible substrate (100_fb1).

[0119] The third housing (130) may be positioned to be connected to the second housing (120) via a third hinge device (140-2). The third housing (130) may have the same or similar configuration as the second housing (120) described above in FIGS. 1 to 4. Accordingly, the description of the third housing (130) may be replaced or supplemented with at least a part of the description of the second housing (120) described above. According to one embodiment, the inner bottom of the third housing (130) may include a front surface where a part of the foldable display is placed and a rear surface where the third printed circuit board (130_p) is placed. As an example, the foldable electronic device (1112) may further include a structure (e.g., boss, adhesive member, adhesive) for fixing the third printed circuit board (130_p) to the bottom (e.g., rear bottom) of the third housing (130). A battery may be placed in the third housing (130). The third housing (130) may be connected to the second housing (120), for example, through a third hinge device (140-2), and may be positioned at a certain angle to the second housing (120) according to a folding or unfolding motion.

[0120] According to one embodiment, the third printed circuit board (130_p) may have a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), a third aggregator circuit (130_ag), a fourth board connector (130_co) connected to a fourth connector (100_co4) provided on one side of a second flexible board (100_fb2), a third circuit wiring (130_se), a fifth board wiring (130_s1), a sixth board wiring (130_s2), and a third signal wiring (130_sg) arranged thereon. The third printed circuit board (130_p) may include a portion (e.g., a fourth board connector (130_co)) that is received in the third housing (130) (or the third housing portion) and connected to a connector (e.g., a fourth connector (100_co4)) disposed at the second end of the second flexible board (100_fb2).

[0121] According to one embodiment, the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) may include at least one of a digitizer, a display (or display driving circuit), a touch panel (or touch control circuit), a camera, a sub PMIC, a speaker amplifier, an audio module, a SIM card, or sensors. Referring to the illustrated drawing, the third printed circuit board (130_p) may include at least one of a seventh electronic element (130_pe1) (or first peripheral electronic element) that transmits and receives a control signal (or IO signal) via I2C, an eighth electronic element (130_pe2) (or second peripheral electronic element) that receives a control signal (or IO signal) via GPIO, a ninth electronic element (130_pe3) (or third peripheral electronic element) that transmits and receives a control signal (or IO signal) via I2S, a tenth electronic element (130_pe4) (or fourth peripheral electronic element) that transmits and receives a control signal (or IO signal) via SPI, an eleventh electronic element (130_pe5) (or fifth peripheral electronic element) that transmits a control signal (or IO signal) via IRQ, and a twelfth electronic element (130_pe6) (or sixth peripheral electronic element) that transmits and receives a control signal (or IO signal) via 13C. There are. The plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) may be configured to receive a signal from or transmit to the third aggregator circuit (130_ag) based on any one of the various IO methods described above.

[0122] According to one embodiment, the third printed circuit board (130_p) may include a third signal wiring (130_sg) connecting the third aggregator circuit (130_ag) and the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6). At least a portion of the third signal wiring (130_sg) may be disposed on at least one of the plurality of layers of the third printed circuit board (130_p). The fifth substrate wiring (130_s1) may connect the fourth substrate connector (130_co) with at least some of the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) (e.g., seventh electronic element (130_pe1) (or first peripheral electronic element)), and the sixth substrate wiring (130_s2) may connect the fourth substrate connector (130_co) with at least some of the plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) (e.g., twelfth electronic element (130_pe6) (or sixth peripheral electronic element)). The fifth substrate wiring (130_s1) and the sixth substrate wiring (130_s2) may connect different electronic elements to the fourth substrate connector (130_co) or connect the same electronic element to the fourth substrate connector (130_co). For example, the electronic elements that the fifth substrate wiring (130_s1) and the sixth substrate wiring (130_s2) connect to the fourth substrate connector (130_co) may overlap. The fifth substrate wiring (130_s1) may be connected to the third substrate wiring (121_s1) through the second flexible substrate (100_fb2), and the sixth substrate wiring (130_s2) may be connected to the fourth substrate wiring (121_s2) through the second flexible substrate (100_fb2).

[0123] According to one embodiment, data (e.g., payload) of a first electronic element (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) may be transmitted to a processor (110_ap) or data (e.g., other signals excluding IO control signals) of a processor (110_ap) may be transmitted to the first electronic element (130_pe1) through the first substrate wiring (110_s1), part wiring of the first flexible substrate (100_fb1), third substrate wiring (121_s1), part wiring of the second flexible substrate (100_fb2), and fifth substrate wiring (130_s1). According to one embodiment, the first electronic element (130_pe1) and the processor (110_ap) can transmit and receive an input / output control signal (I / O control signal) through the first signal wiring (110_sg), the signal wiring of the first flexible substrate (100_fb1), the second signal wiring (121_se), the signal wiring of the second flexible substrate (100_fb2), and the third signal wiring (130_sg). According to various embodiments, the first electronic element (130_pe1) and the processor (110_ap) may transmit and receive a payload, an input / output control signal (I / O control signal), and other signals through the first substrate wiring (110_s1), a portion of the wiring of the first flexible substrate (100_fb1), a third substrate wiring (121_s1), a portion of the wiring of the second flexible substrate (100_fb1), and a fifth substrate wiring (130_s1).

[0124] According to one embodiment, the payload of a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) can be transmitted to and received from a processor (110_ap) through a first substrate wiring (110_s1), a portion of the wiring of a first flexible substrate (100_fb1), a third substrate wiring (121_s1), a portion of the wiring of a second flexible substrate (100_fb2), and a fifth substrate wiring (130_s1). According to one embodiment, I / O control signals of a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) can be transmitted to and received with a processor (110_ap) through a first signal wire (110_sg), a first circuit wire (110_se), a signal wire of a first flexible substrate (100_fb1), a second circuit wire (121_se), a signal wire of a second flexible substrate (100_fb2), a third circuit wire (130_se), and a third signal wire (130_sg).

[0125] As an example, power from the PMIC (110_PM) can be supplied to the sixth electronic element (130_pe6) through the second substrate wiring (110_s2), another part of the wiring of the first flexible substrate (100_fb1), the fourth substrate wiring (121_s2), another part of the wiring of the second flexible substrate (100_fb2), and the sixth substrate wiring (130_s2).

[0126] According to one embodiment, although not illustrated, power from the PMIC (110_PM) may be supplied to a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) through the second substrate wiring (110_s2), another part of the wiring of the first flexible substrate (100_fb1), the fourth substrate wiring (121_s2), another part of the wiring of the second flexible substrate (100_fb2), and the sixth substrate wiring (130_s2).

[0127] According to one embodiment, power from the PMIC (110_PM) can be supplied to some electronic elements (e.g., 130_pe2, 130_pe3, 130_pe4, 130_pe5) through a second signal wiring (110_s2), another part of wiring (or signal wiring) of the first flexible substrate (110_fb1), a fourth substrate wiring (121_s2), another part of wiring (or signal wiring) of the second flexible substrate (110_fb2), a third circuit wiring (130_se), and a third signal wiring (130_sg).

[0128] According to one embodiment, power from the PMIC (110_PM) can be supplied to a first electronic element (e.g., 130_pe1) through a second signal wiring (110_s2), a portion of wiring of a first flexible substrate (110_fb1), a second substrate wiring (121_s1) (or a second signal wiring (121_se), or a fourth substrate wiring (121_s2)), a portion of wiring of a second flexible substrate (110_fb2), a fifth substrate wiring (130_s1) (or a third circuit wiring (130_se) and a third signal wiring (130_sg)).

[0129] According to one embodiment, power from the PMIC (110_PM) is transmitted to the third aggregator circuit (130_sg) through a second signal wiring (110_s2), a portion of wiring of the first flexible substrate (110_fb1), a second substrate wiring (121_s1) (or a second signal wiring (121_se), or a fourth substrate wiring (121_s2)), a portion of wiring of the second flexible substrate (110_fb2), a sixth substrate wiring (130_s2), a sixth electronic element (130_pe6), and a third signal wiring (130_sg) (e.g., signal wiring disposed between the third aggregator circuit (130_sg) and the sixth electronic element (130_pe6), and through the third aggregator circuit (130_sg) the first to fifth electronic elements (130_pe1, 130_pe2, It can be supplied to 130_pe3, 130_pe4, 130_pe5).

[0130] According to one embodiment, the first flexible substrate (100_fb1) may be separated into a plurality of flexible substrates. For example, the first flexible substrate (100_fb1) may include a first flexible substrate portion connecting the first substrate wiring (110_s1) and the third substrate wiring (121_s1), a second flexible substrate portion connecting the first circuit wiring (110_se) and the second circuit wiring (121_se), and a third flexible substrate portion connecting the second substrate wiring (110_s2) and the fourth substrate wiring (121_s2). Alternatively, the first flexible substrate (100_fb1) may include a first flexible substrate portion connected to the output portion of the first aggregator circuit (110_ag), and a second flexible substrate portion connected to the first substrate wiring (110_s1) and the second substrate wiring (110_s2). The division of these flexible substrate portions can also be applied to the second flexible substrate (100_fb2) and to the flexible substrate (100_fb) described above in FIG. 4. For example, at least one of the flexible substrate (100_fb) and the second flexible substrate (100_fb2) can be divided into a plurality of flexible substrate portions.

[0131] The third aggregator circuit (130_ag) may be housed in the third housing (130) (or housed in the third housing (130) while placed on the third printed circuit board (130_p). The third aggregator circuit (130_ag) may have the same or similar configuration as the second aggregator circuit (120_ag) described in the previous drawings. Accordingly, the description of the third aggregator circuit (130_ag) may be replaced or supplemented by at least a part of the description of the second aggregator circuit (120_ag) described above. According to one embodiment, the third aggregator circuit (130_ag) may include K third ports connected to a second flexible substrate (100_fb2) and L (a natural number greater than K) fourth ports connected to a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).

[0132] The first flexible substrate (100_fb1) may be arranged to electrically connect the first aggregator circuit (110_ag) and the second printed circuit board (121_p). In this regard, the first flexible substrate (100_fb1) may include a first connector (100_co1) coupled to a first substrate connector (110_co) placed on the first printed circuit board (110_p), a second connector (100_co2) coupled to a second substrate connector (121_co1) placed on the second printed circuit board (121_p), and a flexible body having circuit wiring arranged (or formed) that connects the first connector (100_co1) and the second connector (100_co2) and transmits a serialized signal. In the flexible body region, wirings connected to the first substrate wiring (110_s1) and the second substrate wiring (110_s2) (or wirings connected to the third substrate wiring (121_s1) and the fourth substrate wiring (121_s2)) may also be arranged. At least a portion of the first flexible substrate (100_fb1) may be fixed to the first hinge housing (151) or arranged inside the first hinge housing (151).

[0133] The second flexible substrate (100_fb2) may be arranged to electrically connect the third aggregator circuit (130_ag) and the second printed circuit board (121_p). In this regard, the second flexible substrate (100_fb2) may include a fourth connector (100_co4) coupled to a fourth substrate connector (130_co) placed on the third printed circuit board (130_p), a third connector (100_co3) coupled to a third substrate connector (121_co2) placed on the second printed circuit board (121_p), and a flexible body having circuit wiring arranged (or formed) that connects the third connector (100_co3) and the fourth connector (100_co4) and transmits a serialized signal. In the flexible body region, wirings connected to the fifth substrate wiring (130_s1) and the sixth substrate wiring (130_s2) (or wirings connected to the third substrate wiring (121_s1) and the fourth substrate wiring (121_s2)) may also be arranged. At least a portion of the second flexible substrate (100_fb2) may be fixed to the second hinge housing (152) or arranged inside the second hinge housing (152).

[0134] As described above, in the structure of a multi-foldable electronic device (1112) according to one embodiment, by serializing ports or wiring related to input / output control of a processor (110_ap) or a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), the number of wirings placed on flexible substrates (100_fb1, 100_fb2) can be reduced, and accordingly, more stable operation of the flexible substrates can be supported in the structure of the multi-foldable electronic device (1112).

[0135] As an example, a foldable electronic device (1112) includes a first flexible substrate (100_fb1) and a second flexible substrate (100_fb2) connecting a first printed circuit board (110_p) disposed in a first housing (110) and a second printed circuit board (121_p) disposed in a second housing (120) (or a third printed circuit board (130_p) disposed in a third housing (130)), and at least one of the first flexible substrate (100_fb1) and the second flexible substrate (100_fb2) may include a 78-pin and a 60-pin connector (board-to-board connector). For example, through a flexible substrate (e.g., at least one of a first flexible substrate (100_fb1) and a second flexible substrate (100_fb2)), a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) disposed on a second printed circuit board (121_p) (or a third printed circuit board (130_p)) on a first printed circuit board (110_p) having a processor (110_ap) (e.g., digitizer), display (e.g., LCD (liquid crystal display), OLED (organic light-emitting diode), touch panel (TSP (touch screen panel)), camera), PMIC (power management integrated chips), SIM card, sensors, speaker amplifier (SPK AMP), and various peripherals Data and power can be transmitted to a device (Peripheral IC) or device (or electronic element). Since the flexible substrate passes through hinge components related to folding (e.g., at least one of a hinge device and a hinge housing), the design size of the flexible substrate may be limited, even though various signal and power line designs are required. Additionally, internal wiring cracking issues may occur in the flexible substrate due to repetitive hinge movements.In this regard, the foldable electronic device (1112) of the present invention may provide a structure that effectively reduces or minimizes the number of flexible board wirings by applying an aggregator circuit (e.g., an IO (input / output) aggregator related to signals transmitted and received at a low speed less than a first reference speed in relation to the speed of signals transmitted and received through the output ports of the processor (110_ap)) to each of the first printed circuit board (110_p) and the second printed circuit board (121_p) (or the third printed circuit board). The first reference speed may be, for example, MHz, and the low speed signal may include signals transmitted and received at a speed of MHz or less.

[0136] According to one embodiment, about 50 low-speed signals output from a processor (110_ap) are input to a first aggregator circuit (110_ag), converted into a serial signal through an internal circuit, and signals such as device info and data type of connected electronic elements can be transmitted by adding relevant information to the header of the serial packet data. The serial signal (or serialized signal) can be selected according to the total bandwidth and can be a signal according to I2C, I3C, or LVDS (low voltage differential signaling) format. According to various embodiments, there may be multiple serial interfaces to satisfy the bandwidth required by the foldable electronic device (1112) or for specific interface performance. As an example, serial signal lines placed on a flexible board connecting serial interfaces (e.g., aggregator circuits) may include a total of 6 serial lines, such as 2 I3C (CLK, DATA) ports and 1 Sound-wire (DATA, CLK) port, or a total of 8 serial lines, implemented as differential pairs of clock (CLK) and data (DATA) for transmission (TX) and reception (RX), respectively. Data converted into serial signals passes through the flexible board and is transmitted to a second printed circuit board (121_p) (or a third printed circuit board (130_p)), and to an aggregator circuit of the second printed circuit board (121_p) (or the third printed circuit board (130_p)) (e.g., the second aggregator circuit (121_ag) of FIG. 10 described later). Alternatively, it can be input to the third aggregator circuit (130_ag).An aggregator circuit (e.g., the second aggregator circuit (121_ag) or the third aggregator circuit (130_ag) of FIG. 10 described later) that receives 7 to 8 transmitted serial signals can convert them into 50 low-speed signals corresponding to a peripheral connected to an output port (e.g., a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6)). In this way, the foldable electronic device (1112) can reduce 50 low-speed signal lines to 6 to 8 serial lines by applying the aggregator circuit, thereby reducing the size of the flexible substrate to a certain size or smaller (e.g., 12 to 14 mm) and eliminating additional components (e.g., 78-pin connector components).

[0137] The first aggregator circuit (110_ag) and the third aggregator circuit (130_ag) may include at least a part of the structure of the aggregator circuit described earlier in FIG. 5 or FIG. 6.

[0138] Additionally or generally, as described in FIG. 8, a separate signal line connected to the processor (110_ap) (e.g., a first substrate wiring (110_s1)), a signal line connected to the PMIC (110_PM) (e.g., a second substrate wiring (110_s2)), a third substrate wiring (121_s1) and a fourth substrate wiring (121_s2) disposed on the second printed circuit board (121_p), a fifth substrate wiring (130_s1) and a sixth substrate wiring (130_s2) disposed on the third printed circuit board (130_p), a wiring portion disposed within the first flexible substrate (100_fb1) connecting the first substrate wiring (110_s1) and the third substrate wiring (121_s1), a wiring portion connecting the second substrate wiring (110_s2) and the fourth substrate wiring (121_s2), and a second flexible substrate (100_fb2). At least some of the wiring portions that are disposed within and connect the third substrate wiring (121_s1) and the fifth substrate wiring (130_s1) and the wiring portions that connect the fourth substrate wiring (121_s2) and the sixth substrate wiring (130_s2) may be applied in the same or similarly to at least some of the aforementioned electronic devices (100, 1111, 1112) or the electronic devices described later (e.g., 1113, 1114, 1115, 1116, 1117, 1118, 1119). According to one embodiment, the first transmission speed of a signal transmitted through at least one of the first substrate wiring (110_s1), the third substrate wiring (121_s1), and the fifth substrate wiring (130_s1) may be faster than the second transmission speed of a signal transmitted through at least one of the first circuit wiring (110_se), the second circuit wiring (120_se), and the third circuit wiring (130_se).

[0139] According to one embodiment, a first flexible substrate (100_fb1) and a second flexible substrate (100_fb2) may each include a first wiring portion connected to at least one of substrate wirings (e.g., 110_s1, 110_s2, 121_s1, 121_s2, 130_s1, 130_s2) and a second wiring portion connected to at least one of circuit wirings (110_se, 120_se, 130_se). A first transmission speed of a signal transmitted through the first wiring portion may be faster than a second transmission speed of a signal transmitted through the second wiring portion. Alternatively, the transmission speed of a signal transmitted through the second wiring portion may be slower than the transmission speed of a signal transmitted through the first wiring portion.

[0140] According to one embodiment, the foldable electronic device (1112) includes a connection structure connecting a first aggregator circuit (110_ag) and a third aggregator circuit (130_ag) (or a second aggregator circuit disposed in a third housing (130), and the connection structure includes a first flexible substrate (100_fb1) (or a first flexible printed circuit board (FPCB) portion) that is at least partially coupled to the first hinge device (140) (or a first hinge assembly) or at least partially received in the first hinge housing (151) (or a first hinge housing portion) and a third hinge device (140-2) (or a hinge device connecting the second housing (120) and the third housing (130), or a second hinge assembly) or at least partially received in the second hinge housing (152) (or a second hinge housing portion) and the second control It may include a second flexible substrate (110_fb2) (or a second FPCB portion) configured to transmit a signal (e.g., the output signal of the first aggregator circuit (110_ag)).

[0141] FIG. 10 is a drawing showing a second example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0142] Similar to the foldable electronic device (1112) shown in FIG. 8, the foldable electronic device (1113) shown in FIG. 10 (or a modified form of the second type of foldable electronic device, another example of a foldable electronic device that folds two or more times) has other configurations not shown or simplified to show the connection relationships between multiple electronic elements according to the embodiment of the present invention, but the foldable electronic device (1113) of the present invention is not limited thereto. For example, in the foldable electronic device (1113) shown in FIG. 10, separate substrate wirings (e.g., substrate wirings of FIG. 8 (110_s1, 110_s2, 121_s1, 121_s2, 130_s1, 130_s2)) are not shown, but at least some of the substrate wirings (110_s1, 110_s2, 121_s1, 121_s2, 130_s1, 130_s2) described in FIG. 8 may be added to the foldable electronic device (1113).

[0143] Referring to FIGS. 1 through 10, a foldable electronic device (1113) may include a first housing (110) (or first housing portion), a second housing (120) (or second housing portion), a third housing (130), a first hinge housing (151) (or first hinge housing portion), a second hinge housing (152) (or second hinge housing portion), a first hinge device (140) (or first hinge assembly), a third hinge device (140-2) (or second hinge assembly), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1), and a second flexible substrate (100_fb2).

[0144] Each of the above-mentioned first housing (110), second housing (120), third housing (130), first hinge housing (151), and second hinge housing (152) may have the same or similar configuration as the first housing (110), second housing (120), third housing (130), first hinge housing (151), and second hinge housing (152) described above in FIG. 8. Accordingly, the specific description of the above-mentioned first housing (110), second housing (120), third housing (130), first hinge housing (151), and second hinge housing (152) may be replaced or supplemented by at least a part of the description in FIG. 8. Additionally or generally, the foldable electronic device (1113) may include a flexible display (e.g., the first display (160) of FIG. 3 or a flexible display) as previously illustrated in FIG. 1 to 4. The flexible display applied in FIG. 10 may be folded at least in one place or two places (e.g., a portion placed on top of the first hinge housing (151) of the flexible display, a portion placed on top of the second hinge housing (152) of the flexible display) by folding the first to third housings (110, 120, 130).

[0145] According to one embodiment, the first printed circuit board (110_p) may have a processor (110_ap) (or processing circuitry, or at least one processor), a first aggregator circuit (110_ag) (or a first aggregator), and a first signal wiring (110_sg) disposed thereon. According to one embodiment, the first printed circuit board (110_p) may include a first board connector that engages with a connector formed on the first flexible board (100_fb1). According to one embodiment, the first aggregator circuit (110_ag) may be provided in a form integrated with a part of the first flexible board (100_fb1). In this case, the first connector (100_co1) of the first flexible substrate (100_fb1) described above in FIG. 8 is placed within the first aggregator circuit (110_ag), and the first printed circuit board (110_p) may be formed so as not to include a separate board connector. Additionally, when the first connector of the first flexible substrate (100_fb1) (e.g., the first connector (100_co1) of FIG. 8) is integrated with the first aggregator circuit (110_ag) (or placed within or removed from the first aggregator circuit (110_ag)), the first circuit wiring (e.g., the first circuit wiring (110_se) of FIG. 8) connecting the first connector (100_co1) and the first board connector (110_co) may also be omitted.

[0146] The processor (110_ap) may perform at least one of processing, transmitting, sending, receiving, or deleting various signals related to the execution of various user functions or system operation of, for example, a foldable electronic device (1113). Such a processor (110_ap) may be identical to or at least partially similar to the processor (110_ap) described above in FIGS. 1 to 9. Accordingly, the description of the processor (110_ap) in FIG. 10 may be replaced or supplemented by the description of the processor (110_ap) described above in FIGS. 1 to 9. According to one embodiment, the processor (110_ap) includes a multiple IO controller and multiple IO input / output ports, and a first signal wiring (110_sg) may be arranged to connect the multiple IO input / output ports of the processor (110_ap) and the first aggregator circuit (110_ag). Additionally or generally, the processor (110_ap) generates a control signal related to driving a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) (or at least one electronic element) disposed on a second printed circuit board (121_p) and a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) (or at least one electronic element) disposed on a third printed circuit board (130_p), and transmits it to the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) and the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) or the first and A signal can be received from at least one of the second plurality of electronic elements (121_pe1, 121_pe2, 121_pe3, 130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).According to one embodiment, the processor (110_ap) may include a port connected to a substrate wiring (e.g., the first substrate wiring (110_s1) of FIG. 8) for transmitting and receiving a signal (e.g., payload) related to the driving of the plurality of electronic elements (121_pe1, 121_pe2, 121_pe3, 130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).

[0147] The first aggregator circuit (110_ag) may be housed in the first housing (110) (or housed in the first housing (110) while placed on the first printed circuit board (110_p)). According to one embodiment, the first aggregator circuit (110_ag) may have the same or similar configuration as the first aggregator circuit (110_ag) described in the preceding drawings (e.g., FIG. 8). Accordingly, the description of the first aggregator circuit (110_ag) in FIG. 10 may be replaced or supplemented by the description of the first aggregator circuit (110_ag) in the preceding drawings. As an example, the first aggregator circuit (110_ag) comprises a buffer capable of storing N signals transmitted by a processor (110_ap), converters (or microcontrollers, input / output converters) that convert the received signals, and M signals (M) of the N signals. <N 자연수)의 신호들로 직렬화할 수 병렬-직렬 변환기 및 수신된 신호들을 병렬화할 수 있는 직렬-병렬 변환기를 포함할 수 있다. 상기 제1 애그리게이터 회로(110_ag)는 복수의 포트 그룹을 포함할 수 있다. 예컨대, 제1 애그리게이터 회로(110_ag)는 제3 인쇄회로기판(130_p)에 배치된 제2 복수의 전자 요소들(130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6)과 직렬화된 신호를 송수신할 수 있는 제1 포트(port1), 제2 인쇄회로기판(121_p)에 배치된 제1 복수의 전자 요소들(121_pe1, 121_pe2, 121_pe3)과 직렬화된 신호를 송수신할 수 있는 제2 포트(port2)를 포함할 수 있다.

[0148] According to one embodiment, the first aggregator circuit (110_ag) may be designed so that the serial interface output port can support multiple ports (e.g., port1, port2). The multiple ports (port1, port2) of the first aggregator circuit (110_ag) may be physically separated by serial signal to be transmitted, or the output direction of multiple IO inputs (e.g., port1 or port2) may be determined through software register settings. As described above, the first aggregator circuit (110_ag) can support multiple aggregator circuits (121_ag, 130_ag) using multiple ports.

[0149] According to one embodiment, the first flexible substrate (100_fb1) may be configured to connect the first printed circuit board (110_p) and the second printed circuit board (121_p). For example, one side of the first flexible substrate (100_fb1) may be electrically connected to the input / output ports of the first aggregator circuit (110_ag), and the other side of the first flexible substrate (100_fb1) may include a connector (e.g., connector (100_co2)) that is coupled to a second substrate connector formed on the second printed circuit board (121_p). The first flexible substrate (100_fb1) may include a first flexible substrate wiring (100_se1) that is respectively connected to the first port (port1) and the second port (prot2) of the first aggregator circuit (110_ag) described above. The first flexible substrate wiring (100_se1) may include at least one signal line for transmitting a serialized signal through a first port (port1) and at least one signal line for transmitting a serialized signal through a second port (port2).

[0150] According to one embodiment, the second printed circuit board (121_p) may be placed on one side of the second housing (120). The second printed circuit board (121_p) may include a second board connector (e.g., the second board connector (121_co1) of FIG. 9 (or the first board connector of the second printed circuit board) connected to a second connector (100_co2) formed on the first flexible substrate (100_fb1), and a third board connector (e.g., the third board connector (121_co2) of FIG. 9 (or the second board connector of the second printed circuit board) connected to a third connector (100_co3) formed on the second flexible substrate (100_fb2). The second printed circuit board (121_p) may include at least one of a second aggregator circuit (121_ag) and a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and the second of the first flexible substrate (100_fb1). A second-1 circuit wiring (121_se1) (or the first circuit wiring of the second printed circuit board (121_p)) connecting a connector (100_co2) (or the first board connector of the second printed circuit board (121_p) connected to the second connector (100_co2)) and a third connector (100_co3) of the second flexible board (100_fb2) (or the second board connector of the second printed circuit board (121_p) connected to the third connector (100_co3)), and a second-2 circuit wiring (121_se2) (or the second aggregator circuit (121_ag)) connecting a second connector (100_co2) of the first flexible board (100_fb1) (or the first board connector of the second printed circuit board (121_p) connected to the second connector (100_co2)) and the second aggregator circuit (121_ag). It may include a second circuit wiring of the printed circuit board (121_p). The second-1 circuit wiring (121_se1) and the second-2 circuit wiring (121_se2) may be formed on at least one of the plurality of layers of the second printed circuit board (121_p).The above second-2 circuit wiring (121_se2) can connect the second port (port2) of the second aggregator circuit (121_ag) and a part of the first flexible substrate (100_fb1). The above second-1 circuit wiring (121_se1) and second-2 circuit wiring (121_se2) can be used to transmit and receive serialized signals. The second printed circuit board (121_p) may be accommodated in a second housing (120) (or a second housing portion) and may include portions (e.g., a second board connector (121_co1) and a third board connector (121_co2)) connected to a connector (e.g., a second connector (100_co2)) disposed at a third end opposite to the first end of the first flexible board (100_bf1) and a connector (e.g., a third connector (100_co3)) disposed at a fourth end opposite to the second end of the second flexible board (100_bf2).

[0151] The second aggregator circuit (121_ag) may be connected to a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) through a second signal wiring (121_sg). For example, the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) may include a first electronic element (121_pe1) connected to the second aggregator circuit (121_ag) via an SPI method, a second electronic element (121_pe2) connected to the second aggregator circuit (121_ag) via an IRQ method, and a third electronic element (121_pe3) connected to the second aggregator circuit (121_ag) via an I3C method. At least one of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) may be placed on a second printed circuit board (121_p) or placed in a second housing (120). The second aggregator circuit (121_ag) may be housed in the second housing (120) (or a portion of the second housing) and may be configured to receive at least a portion of a second control signal transmitted by the first aggregator circuit (110_ag) through a fifth number of ports and convert the at least portion of the second control signal into a fourth control signal that can be output through a sixth number of ports, which is greater than the fifth number. The second aggregator circuit (121_ag) may be configured to be electrically connected to at least one component (or electronic element) housed within the second housing (120) to transmit the fourth control signal. The above at least one component may include a sensor module, a PMIC, an audio module, a display control circuit, or a touch control module.

[0152] According to one embodiment, the second flexible substrate (100_fb2) can connect the second printed circuit board (121_p) and the third printed circuit board (130_p). As an example, the second flexible substrate (100_fb2) may include a third connector (100_co3) that is coupled to the second substrate connector of the second printed circuit board (121_p). The second flexible substrate (100_fb2) may include an additional connector that can be connected to the third printed circuit board (130_p). As an example, if one side of the second flexible substrate (100_fb2) is integrated with the third aggregator circuit (130_ag) (or absorbed as part of the third aggregator circuit (130_ag)), the side of the second flexible substrate (100_fb2) may be directly connected to the third aggregator circuit (130_ag) without an additional connector. The second flexible substrate (100_fb2) may include a second flexible substrate wiring (100_se2) connecting the third connector (100_co3) and the third aggregator circuit (130_ag). The number of wires in the second flexible substrate wiring (100_se2) may be smaller than the number of wires in the first flexible substrate wiring (100_se1). For example, the number of wires transmitting and receiving serialized signals among the second flexible substrate wiring (100_se2) can be half the number of wires transmitting and receiving serialized signals among the first flexible substrate wiring (100_se1).

[0153] According to one embodiment, a third printed circuit board (130_p) disposed in the third housing (130) may include a third aggregator circuit (130_ag), a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), and a third signal wiring (130_sg). This third printed circuit board (130_p) may include the same or similar configuration as the third printed circuit board (130_p) described above in FIG. 8. Accordingly, a specific description of the third printed circuit board (130_p) may be replaced or supplemented by at least a part of the description of the third printed circuit board (130_p) described in FIG. 8.

[0154] According to one embodiment, at least one of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) or the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) may include at least one of a digitizer, a sensor module, a PMIC (power managements IC), an audio module, a display (or display control circuit), a touch panel (or touch control module), a camera, a sub PMIC, a speaker amplifier (speaker AMP), a SIM card (or SIM socket), or a type of sensor. The second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) described above may include at least some of the plurality of electronic elements (e.g., the 7th to 12th electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6)) described above in FIG. 8.

[0155] The third aggregator circuit (130_ag) may include a configuration identical or similar to the third aggregator circuit (130_ag) described above in FIG. 8. Accordingly, a specific description of the third aggregator circuit (130_ag) may be replaced or supplemented by at least a part of the description of the third aggregator circuit (130_ag) described above in FIG. 8. According to one embodiment, the third aggregator circuit (130_ag) may include K third ports connected to a second flexible substrate (100_fb2) and L (a natural number greater than K) fourth ports connected to a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).

[0156] The second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) may include at least a part of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6. The first aggregator circuit (110_ag) may include at least a part of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6, except that the ports are separated.

[0157] As described above, a foldable electronic device (1113) according to one embodiment supports transmitting and receiving a control signal through simplified wiring in relation to the transmission and reception (or transmission or reception) of a control signal between at least some of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) disposed in the second housing (120) and a processor (110_ap) through a second aggregator circuit (121_ag) disposed in the second housing (120), and also supports transmitting and receiving the control signal through simplified wiring in relation to the transmission and reception (or transmission or reception) of a control signal between at least some of the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) disposed in the third housing (130). It is possible.

[0158] FIG. 11 is a drawing showing a third example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0159] Before explaining, the foldable electronic device (1114) shown in FIG. 11 may include the same or similar configurations as the foldable electronic device (1113) described in FIG. 10, except for the wiring of the first flexible substrate (100_fb1) and the second printed circuit board (121_p). For example, the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1114) described in FIG. 10 may have the same or similar configuration as the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1113) described in FIG. 10. Accordingly, the description of at least part of the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1114) may be replaced or supplemented by at least part of the description previously provided in FIG. 10. For example, a foldable electronic device (1114) may include a first housing (110) in which a second camera module (108) is disposed, a first printed circuit board (110_p) disposed in the first housing (110), a processor (110_ap) placed on the first printed circuit board (110_p), a first aggregator circuit (110_ag), and a first signal wiring (110_sg).For example, the foldable electronic device (1114) may include a third housing (130), a third printed circuit board (130_p) disposed in the third housing (130), a third aggregator circuit (130_ag) disposed in the third printed circuit board (130_p), a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), and a third signal wiring (130_sg). The specific description of the configurations disposed in the first housing (110) and the configurations disposed in the third housing (130) described above may be replaced or supplemented by at least a part of the description of the configurations related to the first housing (110) and the configurations related to the third housing (130) described in FIG. 10.

[0160] Referring to FIGS. 1 to 11, a foldable electronic device (1114) may include a first flexible substrate (100_fb1) connecting a first aggregator circuit (110_ag) (or a first printed circuit board (110_p)) placed in a first housing (110) and a second aggregator circuit (121_ag) (or a second printed circuit board (121_p)) placed in a second housing (120), a second flexible substrate (100_fb2) connecting a second printed circuit board (121_p) placed in a second housing (120) and a third aggregator circuit (130_ag) (or a third printed circuit board (130_p)) placed in a third housing (130).

[0161] According to one embodiment, the foldable electronic device (1114) of FIG. 11 can support two or more aggregator circuits with a single output port. This foldable electronic device (1114) can reduce the number of signal lines of the serial interface compared to the foldable electronic device (1113) described in FIG. 10. The foldable electronic device (1114) of FIG. 11 has a structure in which a plurality of secondary circuits (e.g., a second aggregator circuit (121_ag) and a third aggregator circuit (130_ag)) are connected to one main circuit (e.g., a first aggregator circuit (110_ag)), and the aggregator circuits (110_ag, 121_ag, 130_ag) can transmit and receive serialized signals in an I3C-based main-secondary manner described in FIG. 17. For example, aggregator circuits (110_ag, 121_ag, 130_ag) can be transmitted by assigning bit values ​​that select the aggregator circuits and distinguish electronic elements to the serial data header or address.

[0162] According to one embodiment, the first flexible substrate (100_fb1) may be configured to connect the first printed circuit board (110_p) and the second printed circuit board (121_p). For example, if the first flexible substrate (100_fb1) has a connector connection structure, the first flexible substrate (100_fb1) may include a first connector (e.g., the first connector (100_co1) of FIG. 9) which is electrically connected to a first substrate connector (e.g., the first substrate connector (110_co) of FIG. 9) disposed on a first printed circuit board (110_p) to which the input / output ports of the first aggregator circuit (110_ag) are connected, and a second connector (e.g., the connector (100_co2) of FIG. 8) which is coupled to a second substrate connector (e.g., the second substrate connector (121_co1) of FIG. 9) formed on a second printed circuit board (121_p). Alternatively, the first connector of the first flexible substrate (100_fb1) may be integrated with the first aggregator circuit (110_ag). The first flexible substrate (100_fb1) may include a first flexible substrate wiring (100_se1) that transmits serialized signals output through a first aggregator circuit (110_ag). The first flexible substrate wiring (100_se1) may serially transmit first control signals for input / output control of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) and second control signals for input / output control of a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6). Control signals transmitted through the first flexible substrate wiring (100_se1) (e.g., first control signals for input / output control of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), second control signals for input / output control of the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6)) can be distinguished through header values.

[0163] According to one embodiment, the second printed circuit board (121_p) may include a second board connector (e.g., the second board connector (121_co1) of FIG. 9 (or the first board connector of the second printed circuit board)) connected to a second connector (100_co2) formed on the first flexible board (100_fb1), and a third board connector (e.g., the third board connector (121_co2) of FIG. 9 (or the second board connector of the second printed circuit board)) connected to a third connector (100_co3) formed on the second flexible board (100_fb2). The second printed circuit board (121_p) comprises at least one of a second aggregator circuit (121_ag) and a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), a second connector (100_co2) of a first flexible substrate (100_fb1) (or a first substrate connector of the second printed circuit board (121_p) connected to the second connector (100_co2)), a third connector (100_co3) of a second flexible substrate (100_fb2) (or a second substrate connector of the second printed circuit board (121_p) connected to the third connector (100_co3)), a second-1 circuit wiring (121_se1) (or a first circuit wiring of the second printed circuit board (121_p)), and a first substrate of the second printed circuit board (121_p). A connector (e.g., the second board connector (121_co1) of FIG. 9) or a second-third circuit wiring (121_se3) (or the third circuit wiring of the second printed circuit board (121_p)) may be included to connect a point of the second-first circuit wiring (121_se1) to the second aggregator circuit (121_ag). According to one embodiment, the second-third circuit wiring (121_se3) may receive a serialized signal transmitted through the second-first circuit wiring (121_se1) connecting the first board connector of the second printed circuit board (121_p) (e.g., the second board connector (121_co1) of FIG. 9) and the second board connector of the second printed circuit board (121_p) (e.g., the third board connector (121_co2) of FIG. 9) and transmit it to the second aggregator circuit (121_ag).

[0164] The second aggregator circuit (121_ag) can parallelize the serialized signal received through the second-third circuit wiring (121_se3), check the header value to extract first control signals associated with the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and transmit the extracted first control signals to the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3).

[0165] The second flexible substrate (100_fb2) is electrically connected to the second-1 circuit wiring (121_se1) and can transmit a serialized signal transmitted through the second-1 circuit wiring (121_se1) to the third aggregator circuit (130_ag). The serialized signal transmitted through the second flexible substrate (100_fb2) may include first signals related to the operation of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) (e.g., first control signals for input / output control) and second signals related to the operation of a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) (e.g., second control signals for input / output control). The number of wires of the second flexible substrate wiring (100_se2) disposed on the second flexible substrate (100_fb2) may be the same as the number of wires of the first flexible substrate wiring (100_se1) disposed on the first flexible substrate (100_fb1).

[0166] The third aggregator circuit (130_ag) can receive signals received through the second flexible substrate (100_fb2) (e.g., signals related to the operation of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) and signals related to the operation of the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6). The third aggregator circuit (130_ag) can extract signals related to the operation of the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) from the received signals through header value verification, and transmit the extracted signals to the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6).

[0167] According to one embodiment, the second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) can control the transmission of signals related to the operation of a plurality of electronic elements by distinguishing the transmission cycle during the process of transmitting signals to the processor (110_ap). For example, during the first half of a preset first transmission cycle, the second aggregator circuit (121_ag) transmits a signal generated during the operation of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) to the first aggregator circuit (110_ag), and during the second half of the first transmission cycle, the third aggregator circuit (130_ag) transmits a signal generated during the operation of the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) to the first aggregator circuit (110_ag). As described above, by distinguishing the transmission cycle, it is possible to prevent a collision between the signal transmitted by the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) to the processor (110_ap) and the signal transmitted by the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) to the processor (110_ap). According to one embodiment, the second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) are allocated a designated transmission interval from the processor (110_ap), and during the allocated interval, they can transmit a signal generated from the operation of the plurality of electronic elements to the processor (110_ap).

[0168] The first aggregator circuit (110_ag), the second aggregator circuit (121_ag), and the third aggregator circuit (130_ag) may include at least a part of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6.

[0169] As described above, the foldable electronic device (1114) according to one embodiment is configured to share a second-1 circuit wiring (121_se1) that transmits a serialized signal, thereby making the number of wirings of the first flexible substrate (100_fb1) that transmits a serialized signal and the number of wirings of the second flexible substrate (100_fb2) the same, so that the lifespan and quality control of the flexible substrates (100_fb1, 100_fb2) can be standardized.

[0170] FIG. 12 is a drawing showing a fourth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0171] Before explaining, the foldable electronic device (1115) shown in FIG. 12 may include identical or similar configurations for the remaining parts, except for the structure of the second printed circuit board (121_p), compared to the foldable electronic device (1114) described in FIG. 11. For example, the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1115) described in FIG. 11 may have the same or similar configuration as the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1114) described in FIG. 11. According to one embodiment, the description of at least part of the first housing (110), second housing (120), third housing (130), first hinge housing (151), second hinge housing (152), first hinge device (140), third hinge device (140-2), first printed circuit board (110_p), and third printed circuit board (130_p) of the foldable electronic device (1115) may be replaced or supplemented by at least part of the description previously provided in FIG. 10 or FIG. 11.

[0172] As an example, a foldable electronic device (1115) may include a first housing (110) in which a second camera module (108) is disposed, a first printed circuit board (110_p) disposed in the first housing (110), a processor (110_ap) placed on the first printed circuit board (110_p), and a first aggregator circuit (110_ag) connected to the processor (110_ap) through a first signal wiring (110_sg). For example, the foldable electronic device (1115) may include a third housing (130), a third printed circuit board (130_p) disposed in the third housing (130), a third aggregator circuit (130_ag) disposed in the third printed circuit board (130_p), and a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) connected to the third aggregator circuit (130_ag) through a third signal wiring (130_sg). A detailed description of the configurations disposed in the first housing (110) and the configurations disposed in the third housing (130) described above may be replaced or supplemented by at least a part of the description of the configurations related to the first housing (110) and the configurations related to the third housing (130) described in FIG. 11 (or the description of the configurations related to the first housing (110) and the configurations related to the third housing (130) described in FIG. 10).

[0173] Referring to FIGS. 1 to 12, a foldable electronic device (1115) may include a first flexible substrate (100_fb1) connecting a first aggregator circuit (110_ag) (or a first printed circuit board (110_p)) placed in a first housing (110) and a second aggregator circuit (121_ag) (or a second printed circuit board (121_p)) placed in a second housing (120), a second flexible substrate (100_fb2) connecting a second printed circuit board (121_p) placed in a second housing (120) and a third aggregator circuit (130_ag) (or a third printed circuit board (130_p)) placed in a third housing (130). According to one embodiment, the first flexible substrate (100_fb1) and the second flexible substrate (100_fb2) may include the same or similar configuration as the first flexible substrate (100_fb1) and the second flexible substrate (100_fb2) described above in FIG. 11, respectively. Accordingly, the specific description of the first flexible substrate (100_fb1) and the second flexible substrate (100_fb2) may be replaced or supplemented by at least a part of the description of the first flexible substrate (100_fb1) described in FIG. 11.

[0174] According to one embodiment, the second printed circuit board (121_p) may include a second board connector (e.g., the second board connector (121_co1) of FIG. 9 (or the first board connector of the second printed circuit board)) connected to a second connector (100_co2) formed on the first flexible board (100_fb1), and a third board connector (e.g., the third board connector (121_co2) of FIG. 9 (or the second board connector of the second printed circuit board)) connected to a third connector (100_co3) formed on the second flexible board (100_fb2). The second printed circuit board (121_p) may include a second-fourth circuit wiring (121_se4) arranged to penetrate the interior of the second aggregator circuit (121_ag) while connecting the second connector (100_co2) of the first flexible substrate (100_fb1) (or the first substrate connector of the second printed circuit board (121_p) connected to the second connector (100_co2)) and the third connector (100_co3) of the second flexible substrate (100_fb2) (or the second substrate connector of the second printed circuit board (121_p) connected to the third connector (100_co3). The above-described second-fourth circuit wiring (121_se4) may include a first wiring portion (121_se41) arranged to connect the second connector (100_co2) (or the second board connector (121_co1) of FIG. 9) and one side of the second aggregator circuit (121_ag), a second wiring portion (121_se42) connecting one side of the second aggregator circuit (121_ag) and the third connector (100_co3) (or the third board connector (121_co2) of FIG. 9), and a third wiring portion (121_se43) arranged inside the second aggregator circuit (121_ag). At least a portion of the above-described second-fourth circuit wiring (121_se4) may be arranged to pass through the interior of the second aggregator circuit (121_ag) in a bypass form.

[0175] The second aggregator circuit (121_ag) may include a second-fifth circuit wiring (121_se5) (or aggregator circuit internal wiring, or circuit internal wiring) that is electrically connected to the second-fourth circuit wiring (e.g., the third wiring portion (121_se43) of the second-fourth circuit wiring (121_se4)). The above-mentioned second-fifth circuit wiring (121_se5) can electrically connect the bypass circuit wiring (e.g., second-fifth circuit wiring (121_se4)) (or the third wiring portion (121_se43) of second-fifth circuit wiring (121_se4)) and a signal converter (e.g., at least one of a serial-to-parallel converter and a parallel-to-serial converter) disposed within the second aggregator circuit (121_ag). The second aggregator circuit (121_ag) checks the header of a signal transmitted through the second-fifth circuit wiring (121_se5) (or a signal transmitted through the second-fifth circuit wiring (121_se4)) to extract a signal (e.g., a control signal, or an input / output control signal) associated with a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and the extracted signal is connected to the first plurality of electronic elements (121_pe1, It can be passed to at least one of 121_pe2, 121_pe3).

[0176] According to one embodiment, the second aggregator circuit (121_ag) can collect signals transmitted by a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) to a processor (110_ap), serialize the collected signals, and then transmit them to the processor (110_ap) through the second-fifth circuit wiring (121_se5), the second-fourth circuit wiring (121_se4), the first flexible substrate (100_fb1), the first aggregator circuit (110_ag), and the first signal wiring (110_sg). The third aggregator circuit (130_ag) can collect signals transmitted to the processor (110_ap) by the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) through at least a portion of the third signal wiring (130_sg), serialize the collected signals, and then transmit them to the processor (110_ap) through the second flexible substrate (100_fb2), the second-fourth circuit wiring (121_se4), the first flexible substrate (100_fb1), the first aggregator circuit (110_ag), and the first signal wiring (110_sg).

[0177] As an example, in relation to preventing collisions between signals transmitted to the processor (110_ap) by the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) and the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), a separate CS (chip select) pin may be assigned to aggregator circuits (e.g., second and third aggregator circuits (121_ag, 130_ag)), and a remote aggregator (e.g., second and third aggregator circuits (121_ag and 130_ag)) to occupy the serial interface may be configured with the state of the assigned pin. As an example, if the processor (110_ap) sets the CS value to 0, the second aggregator When the circuit (121_ag) communicates with the first aggregator circuit (110_ag) and the processor (110_ap) sets the CS value to 1, the third aggregator circuit (130_ag) can communicate with the first aggregator circuit (110_ag).

[0178] According to one embodiment, a sync pin may be placed between the second aggregator circuit (121_ag) and the third aggregator circuit (130_ag). The second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) may determine the main (or primary) and secondary, and based on this, determine the communication order to communicate with the first aggregator circuit (110_ag).

[0179] According to one embodiment, aggregator circuits (121_ag and 130_ag) may be configured to monitor the status of a serial interface internally. The aggregator circuits (121_ag and 130_ag) may monitor a signal wiring (e.g., BUS) connected to a first aggregator circuit (110_ag), withhold data transmission to the first aggregator circuit (110_ag) if the signal wiring is in use, and perform data transmission to the first aggregator circuit (110_ag) if the signal wiring is not in use.

[0180] According to one embodiment, the second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) can each transmit a signal using parts of a preset transmission signal transmission cycle. For example, regarding the transmission of signals by the aggregator circuits, the second aggregator circuit (121_ag) (or the third aggregator circuit (130_ag)) may be configured to transmit a signal to the processor (110_ap) during at least a portion of the preceding 1 / 2 cycle of a preset first transmission cycle, and the third aggregator circuit (130_ag) (or the second aggregator circuit (121_ag)) may be configured to transmit a signal to the processor (110_ap) during at least a portion of the following 1 / 2 cycle of the first transmission cycle. Alternatively, the processor (110_ap) may specify the transmission period of the second aggregator circuit (121_ag) and the transmission period of the third aggregator circuit (130_ag), respectively, and transmit them through the receiving line of the second aggregator circuit (121_ag) and the receiving line of the third aggregator circuit (130_ag). The second aggregator circuit (121_ag) and the third aggregator circuit (130_ag) are allocated a specified transmission interval from the processor (110_ap) and may transmit signals generated from the operation of multiple electronic elements to the processor (110_ap) during the allocated interval.

[0181] The first aggregator circuit (110_ag) and the third aggregator circuit (130_ag) may include at least a portion of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6. The second aggregator circuit (121_ag) may include at least a portion of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6, except for a structure in which a second-fourth circuit wiring (121_se4) for bypass and internal wiring (e.g., a second-fifth circuit wiring (121_se5)) connected to the second-fourth circuit wiring (121_se4) is arranged internally.

[0182] As described above, a foldable electronic device (1115) according to one embodiment can form a second-fourth circuit wiring (121_se4) that transmits a serialized signal inside a second aggregator circuit (121_ag), and is configured to transmit and receive signals through a second-fifth circuit wiring (121_se5) connected to the second-fourth circuit wiring (121_se4), thereby enabling the configuration of a second printed circuit board (121_p) that is more compact and less at risk of damage.

[0183] FIG. 13 is a drawing showing a fifth example of the arrangement of internal components of a foldable electronic device according to one embodiment. FIG. 14 is a drawing showing at least a portion of a cross-section cut along the A1-A1' cutting line of FIG. 13. According to one embodiment, the cutting line A1-A1' shown in FIG. 13 is schematically shown in the drawing, but can be arranged to cut specific signal wiring in each component. Additionally, the electronic element (130_pe) shown in FIG. 14 indicates a specific electronic element placed at a position cut by the cutting line A1-A1', and can be any one of a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) that can be placed on a third printed circuit board (130_p).

[0184] Similar to the foldable electronic device (1112) shown in FIG. 8, the foldable electronic device (1116) shown in FIG. 13 (or a second type foldable electronic device, a foldable electronic device that folds two or more times) has other components not shown or simplified to indicate the connection relationship between a plurality of electronic elements according to the embodiment of the present invention, but the foldable electronic device (1116) of the present invention is not limited thereto.

[0185] Referring to FIGS. 1 through 14, a foldable electronic device (1116) may include a first housing (110) (or first housing portion), a second housing (120) (or second housing portion), a third housing (130) (or third housing portion), a first hinge housing (151) (or first hinge housing portion), a second hinge housing (152) (or second hinge housing portion), a first hinge device (140) (or first hinge assembly), a third hinge device (140-2) (or second hinge assembly), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1), and a second flexible substrate (100_fb2). Among the configurations of the above-mentioned foldable electronic device (1116), the first housing (110), the second housing (120), the third housing (130), the first hinge housing (151), the second hinge housing (152), the first hinge device (140), and the third hinge device (140-2) may have the same or similar configuration as the first housing (110), the second housing (120), the third housing (130), the first hinge housing (151), the second hinge housing (152), the first hinge device (140), and the third hinge device (140-2) described above in FIG. 8. Accordingly, the specific description of the first housing (110), the second housing (120), the third housing (130), the first hinge housing (151), the second hinge housing (152), the first hinge device (140), and the third hinge device (140-2) among the configurations of the foldable electronic device (1116) may be replaced or supplemented by at least some of the descriptions of the configurations described in FIG. 8 and other drawings. Additionally or substantially, the foldable electronic device (1116) may include a flexible display (e.g., the first display (160) of FIG. 3 or a flexible display) as previously illustrated in FIG. 1 to FIG. 4.

[0186] According to one embodiment, the first printed circuit board (110_p) may have a processor (110_ap) (or processing circuitry) with an aggregator circuit portion (110_agi) embedded therein, a first board wiring (110_s1), a PMIC (110_PM) (or electric component or component of the first housing (110)), a first circuit wiring (110_se), and a second board wiring (110_s2) disposed therein. Additionally or substantially, the first printed circuit board (110_p) may have a first board connector (110_co) that engages with a first connector (100_co1) of a first flexible board (100_fb1). The aggregator circuit portion (110_agi) embedded within the processor (110_ap) and the first board connector (110_co) can be electrically connected by the first circuit wiring (110_se). The first circuit wiring (110_se) can be used to transmit and receive serialized signals.

[0187] Meanwhile, in the embodiment of the present invention, only a processor (110_ap) with an aggregator circuit portion (110_agi) embedded in a first printed circuit board (110_p), a first board wiring (110_s1), a PMIC (110_PM), a second board wiring (110_s2), a first circuit wiring (110_se), and a first board connector (110_co) are arranged thereon, but the present invention is not limited thereto and more diverse electronic elements may be arranged thereon.

[0188] According to one embodiment, the first substrate wiring (110_s1) may be arranged to connect the first part of the processor (110_ap) (or the part where ports other than the aggregator circuit part (110_agi) are arranged) and the first substrate connector (110_co). The second substrate wiring (110_s2) may be arranged to connect the PMIC (110_PM) and the first substrate connector (110_co). The first substrate wiring (110_s1) and the second substrate wiring (110_s2) may connect the first substrate connector (110_co) and the first part of the processor (110_ap) or the PMIC (110_PM) without passing through the aggregator circuit part (110_agi).

[0189] The processor (110_ap) may perform at least one of processing, transmitting, sending, receiving, or deleting various signals related to the execution of various user functions or system operation of, for example, a foldable electronic device (1116). The processor (110_ap) may be identical to or at least partially similar to the processor (110_ap) described in FIG. 7 (e.g., a processor (110_ap) with an aggregator circuit portion (110_agi) embedded therein). Accordingly, the description of the processor (110_ap) in FIG. 13 may be replaced or supplemented by at least some of the descriptions of the processor (110_ap) described in FIG. 1 through 7 or the processor described in other figures.

[0190] According to one embodiment, the aggregator circuit portion (110_agi) may be embedded within the processor (110_ap). The structure of the aggregator circuit portion (110_agi) may include at least some configuration of the first aggregator circuit (110_ag) described above in FIG. 5 or FIG. 6. Accordingly, the description of the aggregator circuit portion (110_agi) in FIG. 13 may be replaced or supplemented by at least some of the descriptions of the aggregator circuit portions (110_ag, 121_ag, 130_ag) or the first aggregator circuit (110_ag) in the preceding drawings.

[0191] The first flexible substrate (100_fb1) may be connected to the first printed circuit board (110_p) and the second printed circuit board (121_p), and at least a portion of it may be housed in or coupled to the first hinge housing (151) or the first hinge device (140). The first flexible substrate (100_fb1) may include the same or similar configuration as the first flexible substrate (100_fb1) described above in FIG. 8. According to one embodiment, a specific description of the first flexible substrate (100_fb1) may be replaced or supplemented by at least a portion of the description of the first flexible substrate (100_fb1) described in FIG. 8.

[0192] The second flexible substrate (100_fb2) may be arranged to electrically connect the third aggregator circuit (130_ag) and the second printed circuit board (121_p). The second flexible substrate (100_fb2) may include the same or similar configuration as the second flexible substrate (100_fb2) described above in FIG. 8. According to one embodiment, a specific description of the second flexible substrate (100_fb2) may be replaced or supplemented by at least a part of the description of the second flexible substrate (100_fb2) described in FIG. 8. For example, the second flexible substrate (100_fb2) may include a fourth connector (100_co4) coupled to a fourth substrate connector (130_co) disposed on a third printed circuit board (130_p), a third connector (100_co3) coupled to a third substrate connector (121_co2) disposed on a second printed circuit board (121_p), and a flexible body having circuit wiring disposed (or formed) that connects the third connector (100_co3) and the fourth connector (100_co4) and transmits a serialized signal.

[0193] According to one embodiment, the second printed circuit board (121_p) may be disposed on one side of the second housing (120). The second printed circuit board (121_p) may have the same or similar configuration as the second printed circuit board (121_p) described above in FIG. 8. Accordingly, the specific description of the second printed circuit board (121_p) may be replaced or supplemented by at least a part of the description of the second printed circuit board (121_p) described in FIG. 8. According to one embodiment, the second printed circuit board (121_p) may include a second board connector (121_co1) (or the first board connector of the second printed circuit board) connected to a second connector (100_co2) formed on the first flexible board (100_fb1), and a third board connector (121_co2) (or the second board connector of the second printed circuit board) connected to a third connector (100_co3) formed on the second flexible board (100_fb2). The second printed circuit board (121_p) may include a second circuit wiring (121_se) connecting a first part of the second board connector (121_co1) and a first part of the third board connector (121_co2), a third board wiring (121_s1) connecting a second part of the second board connector (121_co1) and a second part of the third board connector (121_co2), and a fourth board wiring (121_s2) connecting a third part of the second board connector (121_co1) and a third part of the third board connector (121_co2).

[0194] According to one embodiment, the third printed circuit board (130_p) may have a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), a third aggregator circuit (130_ag), a fourth board connector (130_co) connected to a fourth connector (100_co4) provided on one side of a second flexible board (100_fb2), a third circuit wiring (130_se), a fifth board wiring (130_s1), a sixth board wiring (130_s2), and a third signal wiring (130_sg) arranged thereon. The components included in the third printed circuit board (130_p) and the third printed circuit board (130_p), such as the third aggregator circuit (130_ag), board wiring (130_s1, 130_s2), third signal wiring (130_sg), and a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), may be identical or similar to the third aggregator circuit (130_ag), board wiring (130_s1, 130_s2), third signal wiring (130_sg), and a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) described above in FIG. 8. There are. Accordingly, the specific description of the third aggregator circuit (130_ag), substrate wirings (130_s1, 130_s2), third signal wiring (130_sg), and a plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) shown in FIG. 13 may be replaced or supplemented by at least part of the description of the corresponding components described above in FIG. 8. According to one embodiment, the aggregator circuit portion (110_agi) and the third aggregator circuit (130_ag) may include at least part of the structure of the aggregator circuit described above in FIG. 5 or FIG. 6.

[0195] As described above, in the structure of a multi-foldable electronic device (1116) according to one embodiment, the processor (110_ap) incorporates an aggregator circuit (e.g., an aggregator circuit portion (110_agi)) so that the aggregator circuit can be removed on the first printed circuit board (110_p), thereby securing space for the aggregator circuit arrangement, and thus supporting a more diverse structure and a compact printed circuit board design.

[0196] FIG. 15 is a drawing showing a sixth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0197] Referring to FIGS. 1 to 15, the foldable electronic device (1117) illustrated in FIG. 15 may include a first housing (110) on which a second camera module (108) is disposed, a second housing (120), a third housing (130), a first hinge housing (151), a second hinge housing (152), a first hinge device (140), a third hinge device (140-2), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1), and a second flexible substrate (100_fb2). According to one embodiment, FIG. 15 describes a processor (110_ap) having a first aggregator circuit embedded within a first processor (110_ap) and a first aggregator circuit portion (110_agi), and may have a structure in which some wiring of a first flexible substrate (100_fb1) is directly connected to the first aggregator circuit portion (110_agi). In this case, one side of the first flexible substrate (100_fb1) (e.g., the left side of the illustrated drawing) is positioned inside the processor (110_ap) or inside the first aggregator circuit portion (110_agi) so as to be directly connected to the first aggregator circuit portion (110_agi) embedded in the processor (110_ap), and the other side of the first flexible substrate (100_fb1) may extend from one side of the first flexible substrate (100_fb1). According to one embodiment, a processor (110_ap) containing the first aggregator circuit portion (110_agi) is placed at a first location (or first point) of the first printed circuit board (110_p), and the first flexible substrate (100_fb1) can be connected to the first aggregator circuit portion (110_agi) through wiring formed on a certain layer of the first printed circuit board (110_p).In this regard, the first flexible substrate (100_fb1) may include a first connector (e.g., the first connector (100_co1) of FIG. 9) and a second connector (100_co2) on the left and right edges of the drawing as described in FIG. 9, and the first printed circuit board (110_p) may include a board connector (e.g., the first board connector (110_co) of FIG. 9) connected to the first connector (e.g., the first connector (100_co1) of FIG. 9), and the first aggregator circuit portion (110_agi) embedded in the processor (110_ap) may be connected to the first flexible substrate (100_fb1) through the board wiring formed on the first printed circuit board (110_p) and the first board connector (e.g., the board connector (110_co) of FIG. 9).

[0198] According to one embodiment, the illustrated drawings show that the second flexible substrate (100_fb2) includes only the third connector (100_co3), but the embodiments described herein are not limited thereto. For example, the second flexible substrate (100_fb2) may include the fourth connector described in FIG. 9, and correspondingly, the third printed circuit board (130_p) may further include a board connector connected to the fourth connector of the second flexible substrate (100_fb2).

[0199] The configuration of the second housing (120), the third housing (130), the first hinge housing (151), the second hinge housing (152), the first hinge device (140), the third hinge device (140-2), the first printed circuit board (110_p), the second printed circuit board (121_p), the third printed circuit board (130_p), the first flexible substrate (100_fb1), and the second flexible substrate (100_fb2) among the configurations of the above-mentioned foldable electronic device (1117) may be identical or similar to the corresponding configurations described in FIG. 10. Accordingly, the description of the second housing (120), the third housing (130), the first hinge housing (151), the second hinge housing (152), the first hinge device (140), the third hinge device (140-2), the first printed circuit board (110_p), the second printed circuit board (121_p), the third printed circuit board (130_p), the first flexible substrate (100_fb1), and the second flexible substrate (100_fb2) among the configurations of the foldable electronic device (1117) may be supplemented or replaced by at least some of the descriptions described in FIG. 10.

[0200] According to one embodiment, the first housing (110) may have a first printed circuit board (110_p) placed thereon. The first printed circuit board (110_p) may have a processor (110_ap) with an aggregator circuit portion (110_agi) built into it placed (or mounted) thereon. The processor (110_ap) may be connected to a second printed circuit board (121_p) (or a second board connector of the second printed circuit board (121_p) (e.g., the second board connector (121_co1) of FIG. 14)) through a first flexible substrate (100_fb1). In this regard, the first flexible substrate (100_fb1) may include a connector (e.g., the second connector (100_co2) of FIG. 14) that engages with the second board connector (e.g., the second board connector (121_co1) of FIG. 14). The configuration of the first housing (110) described above may be identical or similar to the first housing (110) described in FIG. 10. The configuration of the processor (110_ap) with the aggregator circuit portion (110_agi) embedded therein is the aggregator circuit described in FIG. 7. The configuration of the processor (110_ap) with the part (110_agi) built in, or the processor (110_ap) with the aggregator circuit part (110_agi) built in as described in FIG. 13, may be the same or similar.

[0201] The second housing (120) has a second printed circuit board (121_p) disposed thereon, and on the second printed circuit board (121_p) a second aggregator circuit (121_ag) and a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), a second connector (100_co2) (or the second board connector (121_co1) of FIG. 14, or a first board connector formed on the second printed circuit board (121_p)) and a third connector (100_co3) (or the third board connector (121_co2) of FIG. 14, or a second board connector formed on the second printed circuit board (121_p)), a second-1 circuit wiring (121_se1) that electrically connects the second board connector (e.g., the second board connector (121_co1) of FIG. 14) and the second aggregator It may include a second circuit wiring (121_se2) connecting the circuit (121_ag), and a second signal wiring (121_sg) connecting the second aggregator circuit (121_ag) and the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3). The second printed circuit board (121_p) may include a first group of signal lines (121_se1) (or a plurality of first signal lines) connecting a second board connector (e.g., the second board connector (121_co1) of FIG. 14) and a third board connector (e.g., the third board connector (121_co2) of FIG. 14), and a second group of signal lines (121_se2) (or a plurality of second signal lines) connecting the second board connector (e.g., the second board connector (121_co1) of FIG. 14) and a second aggregator circuit (121_ag).

[0202] The configurations placed on the second housing (120), the second printed circuit board (121_p), and the second printed circuit board (121_p) described above (e.g., the second aggregator circuit (121_ag), the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and wiring) may be identical or similar to the configurations placed on the second printed circuit board (121_p), the second printed circuit board (121_p), and the wiring described above in FIG. 10 (e.g., the second aggregator circuit (121_ag), the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and wiring). Accordingly, the specific description of the configurations related to the second housing (120), the second printed circuit board (121_p), and the second printed circuit board (121_p) may be replaced or supplemented by at least some of the contents described in FIG. 10.

[0203] According to one embodiment, the third housing (130) may have a third printed circuit board (130_p) disposed thereon, and the third printed circuit board (130_p) may include a third aggregator circuit (130_ag) and a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), and a third signal wiring (130_sg) connecting the third aggregator circuit (130_ag) and the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6). The third housing (130), the third printed circuit board (130_p) described above, and the configurations placed on the third printed circuit board (130_p) (e.g., the third aggregator circuit (130_ag), the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), and wiring) may be identical or similar to the configurations placed on the third printed circuit board (130_p) and the third printed circuit board (130_p) described in FIG. 10 (e.g., the third aggregator circuit (130_ag), the second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6), and wiring). Accordingly, the specific description of the configurations related to the third housing (130), the third printed circuit board (130_p), and the third printed circuit board (130_p) may be replaced or supplemented by at least some of the contents described in FIG. 10.

[0204] As described above, a foldable electronic device (1117) according to one embodiment can operate a processor (110_ap) with an aggregator circuit portion (110_agi) embedded therein, and in relation to the operation of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) disposed in a second housing (120), serially connect specific port portions of the aggregator circuit portion (110_agi) and port portions of a second aggregator circuit (121_ag). The second aggregator circuit (121_ag) can process the transmission or reception of a serialized signal with a specific port portion of the aggregator circuit portion (110_agi) embedded in the processor (110_ap) through a second-2 circuit wiring (121_se2).

[0205] FIG. 16 is a diagram showing a seventh example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0206] Referring to FIGS. 1 through 16, the foldable electronic device (1118) illustrated in FIG. 16 comprises a first housing (110) on which a second camera module (108) is disposed, a second housing (120), a third housing (130), a first hinge housing (151), a second hinge housing (152), a first hinge device (140), a third hinge device (140-2), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1) including a second connector (100_co2), a second flexible substrate (100_fb2) including a third connector (100_co3), a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and a second plurality of electronic elements. It may include elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) and wirings (100_se1, 121_se1, 121_se3, 121_sg, 100_se2, 130_sg). The first flexible substrate (100_fb1) may include a first connector as described in other embodiments, and the second flexible substrate (100_fb2) may include a fourth connector.

[0207] The foldable electronic device (1118) shown in FIG. 16 above may have the same configuration as the foldable electronic device (1114) described in FIG. 11 above, except that an aggregator circuit portion (110_agi) is embedded within the processor (110_ap). Additionally, the processor (110_ap) placed on the first printed circuit board (110_p) of the foldable electronic device (1118) may have the same or similar configuration as the processor (110_ap) with the embedded aggregator circuit portion (110_agi) described in FIG. 13 above. Accordingly, among the configurations of the foldable electronic device (1118), a second housing (120), a third housing (130), a first hinge housing (151), a second hinge housing (152), a first hinge device (140), a third hinge device (140-2), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1) including a second connector (100_co2), a second flexible substrate (100_fb2) including a third connector (100_co3), a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4), A detailed description of the wiring (130_pe5, 130_pe6), and the wiring (110_sg, 121_se1, 121_se3, 121_sg, 130_sg) may be replaced or supplemented by at least part of the description of the corresponding configurations described in FIG. 11. A description of the processor (110_ap) which is placed on the first printed circuit board (110_p) among the configurations of the foldable electronic device (1118) and has an aggregator circuit portion (110_agi) embedded therein may be replaced or supplemented by the description of the processor (110_ap) described in FIG. 7 or FIG. 13.

[0208] According to one embodiment, the second printed circuit board (121_p) may include a plurality of first signal lines (121_se1) connecting a second board connector (e.g., the second board connector (121_co1) of FIG. 14) and a third board connector (e.g., the third board connector (121_co2) of FIG. 14), and a plurality of second signal lines (121_se3) connecting the second board connector (e.g., the second board connector (121_co1) of FIG. 14) and a second aggregator circuit (121_ag). Alternatively, the second printed circuit board (121_p) may include a plurality of first signal lines (121_se1) connecting a second board connector (e.g., the second board connector (121_co1) of FIG. 14) and a third board connector (e.g., the third board connector (121_co2) of FIG. 14), and a plurality of second signal lines (121_se3) connecting each of the plurality of first signal lines (121_se1) and a second aggregator circuit (121_ag). The plurality of second signal lines (121_se3) may be separated from the first plurality of first signal lines (121_se1) at a point of the second board connector (e.g., the second board connector (121_co1) of FIG. 14) of the second printed circuit board (121_p) (e.g., leads or pins of the second board connector). According to one embodiment, each of the plurality of first signal lines (121_se1) and the plurality of second signal lines (121_se3) may correspond to each of the second-1 circuit wiring (121_se1) and the second-3 circuit wiring (121_se3) described above in FIG. 11.

[0209] As described above, a foldable electronic device (1118) according to one embodiment can operate a processor (110_ap) with an aggregator circuit portion (110_agi) embedded therein, and in relation to the operation of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) disposed in a second housing (120), by connecting a second aggregator circuit (121_ag) and an aggregator circuit portion (110_agi) through a second-third circuit wiring (121_se3) that overlaps with a second-first circuit wiring (121_se1), thereby processing signal conversion (e.g., serialization of signals or parallelization of signals) and transmission of signals (e.g., control signals, or input / output control signals) required for the operation of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3).

[0210] FIG. 17 is a diagram showing an example of a bus connection between electronic elements of a foldable electronic device according to one embodiment.

[0211] Referring to FIGS. 1 through 17, a foldable electronic device according to one embodiment (e.g., at least one of the foldable electronic devices described above in FIGS. 1 through 16) may include a main block (110_agi_M), a first auxiliary block (121_ag_M), a second auxiliary block (130_ag_M), a first secondary block (110_pe1), a second secondary block (122_pe1), a third secondary block (122_pe2), and a fourth secondary block (131_pe1). The foldable electronic device illustrated in FIG. 17 is an example using an I3C serial interface, and multiple secondary blocks or auxiliary blocks may be connected to a single main block. As the signal transmission structure shown in FIG. 17 can distinguish secondary blocks by address, signal transmission and reception can be performed by sharing a single I3C bus (BUS), and the aggregator circuit (110_ag) can add device information to the header of the serial data.

[0212] The main block (110_agi_M) above may include, for example, an aggregator circuit part embedded in the first aggregator circuit (110_ag) or processor (110_ap) described above in FIGS. 1 to 16 (e.g., the aggregator circuit part (110_agi) of FIG. 7, the aggregator circuit part (110_agi) of FIGS. 13 to 16), and the aggregator circuit part (110_agi) of FIG. 18 described later. The main block (110_agi_M) can transmit a signal to at least one of the first auxiliary block (121_ag_M), the second auxiliary block (130_ag_M), the first secondary block (110_pe1), the second secondary block (122_pe1), the third secondary block (122_pe2), and the fourth secondary block (131_pe1) via a bus, or receive a signal from at least one of the first auxiliary block (121_ag_M), the second auxiliary block (130_ag_M), the first secondary block (110_pe1), the second secondary block (122_pe1), the third secondary block (122_pe2), and the fourth secondary block (131_pe1). For example, the main block (110_agi_M) can transmit and receive signals with at least one of a first auxiliary block (121_ag_M), a second auxiliary block (130_ag_M), a first secondary block (110_pe1), a second secondary block (122_pe1), a third secondary block (122_pe2), and a fourth secondary block (131_pe1) based on the I3C communication method.

[0213] The above bus may include a first bus line (Serial Data, SDA) and a second bus line (Serial Clock, SCL). The first bus line (SDA) may transmit a serialized signal between the main block (110_agi_M) and at least one of the first auxiliary block (121_ag_M), the second auxiliary block (130_ag_M), the first secondary block (110_pe1), the second secondary block (122_pe1), the third secondary block (122_pe2), and the fourth secondary block (131_pe1). The second bus line (SCL) can transmit a clock signal for signal transmission or reception of at least one of the main block (110_agi_M), the first auxiliary block (121_ag_M), the second auxiliary block (130_ag_M), the first secondary block (110_pe1), the second secondary block (122_pe1), the third secondary block (122_pe2), and the fourth secondary block (131_pe1).

[0214] The first auxiliary block (121_ag_M) may include, for example, a second aggregator circuit (121_ag). The first auxiliary block (121_ag_M) is connected to the main block (110_agi_M) via a first bus line (SDA) and a second bus line (SCL), and can transmit and receive serialized data to and from the main block (110_agi_M) according to a clock signal provided by the main block (110_agi_M). For example, the first auxiliary block (121_ag_M) can transmit and receive serialized data related to the operation of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) connected via signal wiring (e.g., 121_sg) to and from the main block (110_agi_M) via a bus (BUS). According to one embodiment, the first auxiliary block (121_ag_M) can transmit and receive signals with the main block (110_agi_M) based on the I3C method.

[0215] The second auxiliary block (130_ag_M) may include, for example, a third aggregator circuit (130_ag). The second auxiliary block (130_ag_M) is connected to the main block (110_agi_M) via the first bus line (SDA) and the second bus line (SCL), and can transmit and receive serialized data with the main block (110_agi_M) according to the clock signal provided by the main block (110_agi_M). For example, the second auxiliary block (130_ag_M) can transmit and receive serialized data related to the operation of a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) connected through signal wiring (e.g., 130_sg) to and from the main block (110_agi_M) via a bus (BUS). According to one embodiment, the second auxiliary block (130_ag_M) can transmit and receive signals to and from the main block (110_agi_M) based on the I3C method.

[0216] The first secondary block (110_pe1) may include, for example, an electronic element that can be placed within the first housing (110). The first secondary block (110_pe1) is connected to the main block (110_agi_M) via a bus (BUS) and can transmit and receive serialized data to and from the main block (110_agi_M) via the bus (BUS). According to one embodiment, the first secondary block (110_pe1) can transmit and receive signals to and from the main block (110_agi_M) based on the I3C method.

[0217] The second secondary block (122_pe1) may include, for example, an electronic element that can be placed within the second housing (120). The second secondary block (122_pe1) is connected to the main block (110_agi_M) via a bus (BUS) and can transmit and receive serialized data to and from the main block (110_agi_M) via the bus (BUS). According to one embodiment, the second secondary block (122_pe1) can transmit and receive signals to and from the main block (110_agi_M) based on the I3C method.

[0218] The third secondary block (122_pe2) may include, for example, an electronic element that can be placed within the second housing (120). The third secondary block (122_pe2) is connected to the main block (110_agi_M) via a bus (BUS) and can transmit and receive serialized data to and from the main block (110_agi_M) via the bus (BUS). According to one embodiment, the third secondary block (122_pe2) can transmit and receive signals to and from the main block (110_agi_M) based on the I2C method.

[0219] The fourth secondary block (131_pe1) may include, for example, electronic elements that can be placed within the third housing (130). The fourth secondary block (131_pe1) is connected to the main block (110_agi_M) via a bus (BUS) and can transmit and receive serialized data to and from the main block (110_agi_M) via the bus (BUS). According to one embodiment, the fourth secondary block (131_pe1) can transmit and receive signals to and from the main block (110_agi_M) based on the I2C method. Meanwhile, the first to fourth secondary blocks (110_pe1, 122_pe1, 122_pe2, 131_pe1) may be a plurality of electronic elements placed in the second housing (120) or a plurality of electronic elements placed in the third housing (130).

[0220] The signal transmission and reception method between the blocks described above can be applied to a communication method between each component of the electronic device of the drawings described in FIGS. 1 to 16 or FIGS. 18 to 20 described later (e.g., aggregator circuits, or a plurality of electronic elements, or an aggregator circuit and a plurality of electronic elements).

[0221] FIG. 18 is a drawing showing the eighth example of the arrangement of internal components of a foldable electronic device according to one embodiment.

[0222] Referring to FIGS. 1 through 18, the foldable electronic device (1119) illustrated in FIG. 18 comprises a first housing (110) on which a second camera module (108) is disposed, a second housing (120), a third housing (130), a first hinge housing (151), a second hinge housing (152), a first hinge device (140), a third hinge device (140-2), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1) including a second connector (100_co2), a second flexible substrate (100_fb2) including a third connector (100_co3), a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and a second plurality of electronic elements. It may include elements (130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6) and wirings (100_se1, 121_se4, 121_se5, 121_sg, 130_sg). The first flexible substrate (100_fb1) may include a first connector (e.g., the first connector (100_co1) of FIG. 9) described in another embodiment (e.g., FIG. 9), and the second flexible substrate (100_fb2) may include a fourth connector (e.g., the fourth connector (100_co4) of FIG. 9).

[0223] The foldable electronic device (1119) shown in FIG. 18 above may have the same configuration as the foldable electronic device (1115) described in FIG. 12 above, except that an aggregator circuit portion (110_agi) is embedded within the processor (110_ap). Additionally, the processor (110_ap) placed on the first printed circuit board (110_p) of the foldable electronic device (1119) may have the same or similar configuration as the processor (110_ap) with the embedded aggregator circuit portion (110_agi) described in FIG. 13 above. Accordingly, among the configurations of the foldable electronic device (1119), a second housing (120), a third housing (130), a first hinge housing (151), a second hinge housing (152), a first hinge device (140), a third hinge device (140-2), a first printed circuit board (110_p), a second printed circuit board (121_p), a third printed circuit board (130_p), a first flexible substrate (100_fb1) including a second connector (100_co2), a second flexible substrate (100_fb2) including a third connector (100_co3), a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3), and a second plurality of electronic elements (130_pe1, 130_pe2, 130_pe3, 130_pe4), A detailed description of the wiring (130_pe5, 130_pe6), and the wiring (100_se1, 121_se4, 121_se5, 121_sg, 130_sg) may be replaced or supplemented by at least part of the description of the corresponding configurations described in FIG. 12. A description of the processor (110_ap) which is placed on the first printed circuit board (110_p) among the configurations of the foldable electronic device (1119) and has an aggregator circuit portion (110_agi) embedded therein may be replaced or supplemented by the description of the processor (110_ap) described in FIG. 7 or FIG. 13.

[0224] According to one embodiment, a second aggregator circuit (121_ag) disposed on a second printed circuit board (121_p) may include a portion of a second-fourth circuit wiring (121_se4) penetrating the interior (e.g., the third wiring portion (121_se43) of FIG. 12) and a second-fifth circuit wiring (121_se5) connected to the portion of the second-fourth circuit wiring (121_se4), identical or similar to the second aggregator circuit (121_ag) described above in FIG. 12. The second-fifth circuit wiring (121_se5) may be connected to a signal converter disposed within the second aggregator circuit (121_ag).

[0225] According to one embodiment, the second printed circuit board (121_p) includes signal lines (121_se4) that are connected from a second board connector (e.g., the second board connector (121_co1) of FIG. 14) through a second aggregator circuit (121_ag) to a third board connector (e.g., the third board connector (121_co2) of FIG. 14), and the second aggregator circuit (121_ag) may be configured to transmit the second control signal to the third board connector (e.g., the third board connector (121_co2) of FIG. 14) without transmitting it to another electronic element received in the second housing (120), when the entire second control signal output from the first aggregator circuit (110_ag) (or aggregator circuit portion (110_agi)) is associated with at least one electronic element received in the third housing (130).

[0226] As described above, a foldable electronic device (1119) according to one embodiment operates a processor (110_ap) with an aggregator circuit portion (110_agi) embedded therein, and in relation to the operation of a first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) disposed in a second housing (120), at least a portion of a second-fourth circuit wiring (121_se4) is formed inside a second aggregator circuit (121_ag), so as to process signal conversion (e.g., serialization of signals or parallelization of signals) and transmission of signals (e.g., control signals, or input / output control signals) required for the operation of the first plurality of electronic elements (121_pe1, 121_pe2, 121_pe3) connected to the second aggregator circuit (121_ag).

[0227] FIG. 19 is a diagram showing an example of the connection relationship between a processor and an aggregator circuit portion of a foldable electronic device and the aggregator circuits according to one embodiment.

[0228] Referring to FIGS. 1 through 19, the arrangement relationship of the processor (110_ap), the aggregator circuit portion (110_agi), and the aggregator circuits (121_ag, 130_ag) shown in FIG. 19 may include the circuit arrangement relationship in the foldable electronic devices shown previously in FIGS. 11, 12, 16, and 18. According to one embodiment, the aggregator circuit portion (110_agi) is embedded inside the processor (110_ap), and each of the plurality of input / output controllers (110_ap_10c) designed within the processor (110_ap) may be connected to the plurality of input / output converters (110_c) formed in the aggregator circuit portion (110_agi) through multiple IO (input / output) wiring. A plurality of input / output converters (110_c) of the aggregator circuit portion (110_agi) can each be connected to a first signal converter (110_PS). The aggregator circuit portion (110_agi) can distinguish aggregator circuits (121_ag, 130_ag) by adding a secondary address bit to the serial data to support a bypass mode. For example, when transmitting a serialized signal, the aggregator circuit portion (110_agi) can distinguish aggregator circuits (121_ag, 130_ag) to receive the signal by writing a specific bit value (e.g., 0 or 1) to the header of the secondary address or serial data. Additionally, the aggregator circuit portion (110_agi) can distinguish the IO ports (input / output ports) of multiple electronic elements connected to a specific aggregator circuit using different bits of the secondary address. The operation of the aggregator circuit portion (110_agi) may be performed by the aggregator circuits described above in FIGS. 4 to 18.

[0229] One side of the aggregator circuit portion (110_agi) is connected to one side of the first flexible substrate (100_fb1), and the first flexible substrate (100_fb1) can connect the aggregator circuit portion (110_agi) and one side of the second aggregator circuit (121_ag) (e.g., the second signal converter (121_PS)). According to one embodiment, the second aggregator circuit (121_ag) is placed on the second printed circuit board, and accordingly, the second aggregator circuit (121_ag) can be connected to the first flexible substrate (100_fb1) through the second-5 circuit wiring (121_se5). The second aggregator circuit (121_ag) may be connected to a plurality of electronic elements (121_pe1, 121_pe2, 121_pe3, …, 121_pe6) through a second signal wiring (121_sg). The second signal wiring (121_sg) is connected to a plurality of input / output converters (120_c) placed in the second aggregator circuit (121_ag), and the plurality of input / output converters (120_c) placed in the second aggregator circuit (121_ag) may be connected to a second signal converter (121_PS).

[0230] Meanwhile, the second-5th circuit wiring (121_se5) is connected to the second-4th circuit wiring (121_se4), and a signal transmitted from the aggregator circuit portion (110_agi) can be transmitted to the third aggregator circuit (130_ag) through the second-4th circuit wiring (121_se4). Alternatively, the second-4th circuit wiring (121_se4) can be connected to the third board connector of the second printed circuit board (121_p) (e.g., the third board connector (121_co2) of FIG. 14), one side of the second flexible board (100_fb2) can be coupled to the third board connector, and the other side of the second flexible board (100_fb2) can be coupled to the fourth board connector of the third printed circuit board (130_p) (e.g., the fourth board connector (130_co) of FIG. 14). Accordingly, the aggregator circuit portion (110_agi) can be connected to the third aggregator circuit (130_ag) via the first flexible substrate (100_fb1), the second-fourth circuit wiring (121_se4), and the second flexible substrate (100_fb2). The third aggregator circuit (130_ag) can be connected to a plurality of electronic elements (130_pe1, …, 130_pe4, 130_pe5, 130_pe6) via the third signal wiring (130_sg). The third signal wiring (130_sg) is connected to a plurality of input / output converters (130_c) arranged in the third aggregator circuit (130_ag), and the plurality of input / output converters (130_c) arranged in the third aggregator circuit (130_ag) can be connected to a third signal converter (130_PS).

[0231] FIG. 20 is a drawing showing an example of a printed circuit board of an interposer structure to which aggregator circuits according to one embodiment are applied.

[0232] Referring to FIGS. 1 to 20, an electronic device (2000) according to one embodiment may include a display (2160), a heat dissipation device (2160_dis), a first adhesive member (2010_t1) (or a first TIM, thermal interface materials), a shielding member (2010_sh), a second adhesive member (2010_t2) (or a second TIM), a processor (2010_ap), a first printed circuit board (2010_p) on which the processor (2010_ap) is placed, a second printed circuit board (2020_p) stacked substantially parallel to the first printed circuit board (2010_p), and an interposer (2030_inp) disposed between the first printed circuit board (2010_p) and the second printed circuit board (2020_p). The stacked structure of a printed circuit board including an interposer of the electronic device (2000) described in FIG. 20 can be applied to at least one of the foldable electronic devices described in FIG. 1 to FIG. 19, or can be applied to various types of electronic devices such as bar-type electronic devices, rollable electronic devices, and foldable (multi-foldable) electronic devices.

[0233] According to one embodiment, the display (2160) can output at least one screen related to the operation of the electronic device (2000). The display (2160) may be folded or rolled. Alternatively, the display (2160) may have a rigid structure and be formed in a bar type. The heat dissipation device (2160_dis) may be configured to receive and dissipate heat generated from the processor (2010_ap) through a first adhesive member (2010_t1), a shielding member (2010_sh), and a second adhesive member (2010_t2). As an example, the heat dissipation device (2160_dis) may dissipate at least a portion of the heat generated from the processor (2010_ap) or dissipate heat through a metal layer (e.g., a copper layer or an aluminum layer) formed on one side of the rear surface of the display (2160). The first adhesive member (2010_t1) may be formed of a material that is positioned between the shielding member (2010_sh) and the heat dissipation device (2160_dis) to transfer heat from the shielding member (2010_sh) to the heat dissipation device (2160_dis) while fixing the heat dissipation device (2160_dis) to the shielding member (2010_sh). The shielding member (2010_sh) may be positioned to surround the processor (2010_ap). At least a portion of the shielding member (2010_sh) may be formed of a metal material. The shielding member (2010_sh) may be connected to a part of the processor (2010_ap) through the second adhesive member (2010_t2). The second adhesive member (2010_t2) is positioned to fill the empty space between the shielding member (2010_sh) and the processor (2010_ap), and can perform the function of transferring heat generated from the processor (2010_ap) to the shielding member (2010_sh). The second adhesive member (2010_t2) may be formed of the same or similar material as the first adhesive member (2010_t1).

[0234] The first printed circuit board (2010_p) may have the processor (2010_ap) placed on one side (e.g., the bottom side based on the illustrated drawing). On the other side of the first printed circuit board (2010_p), another electronic element (2010_pec) or at least one passive element (2010_pas) may be placed. An interposer (2030_inp) may be placed at the edge of the first printed circuit board (2010_p). According to one embodiment, the first printed circuit board (2010_p) may be spaced apart from the second printed circuit board (2020_p) through the interposer (2030_inp). At least one electronic element or at least one passive element may be placed on at least a portion of the front and rear surfaces of the first printed circuit board (2010_p).

[0235] One side of the second printed circuit board (2020_p) may include various electronic elements (2020_pe1, 2020_pe2) necessary for operating the electronic device (2000). Additionally, another electronic element (2020_pec) necessary for operating the electronic device (2000) may be disposed on the other side of the second printed circuit board (2020_p). According to one embodiment, at least one electronic element or at least one passive component may be disposed on at least a portion of the front and rear surfaces of the second printed circuit board (2020_p). A second aggregator circuit (2020_ag) may be disposed on one side of the second printed circuit board (2020_p). The above second aggregator circuit (2020_ag) can be connected to the first electronic element (2020_pe1) through the first signal wiring (2020_sg1) and to the second electronic element (2020_pe2) through the second signal wiring (2020_sg2).

[0236] The above processor (2010_ap) may be the same or similar to the processor (110_ap) described above in FIGS. 1 to 18. According to one embodiment, the processor (2010_ap) may include an aggregator circuit portion (2010_agi).

[0237] The aggregator circuit portion (2010_agi) and the second aggregator circuit (2020_ag) can be connected through wiring (2010_se1, 2010_se2, 2010_se3). For example, the wiring (2010_se1, 2010_se2, 2010_se3) may include a first circuit wiring portion (2010_se1) connected to one side of an aggregator circuit portion (2010_agi) and disposed on a first printed circuit board (2010_p), a second circuit wiring portion (2010_se2) connected to the first circuit wiring portion (2010_se1) and disposed through a part of an interposer (2030_inp) (e.g., at least one via hole of the interposer (2030_inp)), and a third circuit wiring portion (2010_se3) connected to the second circuit wiring portion (2010_se2), disposed on a second printed circuit board (2020_p), and connected to a second aggregator circuit (2020_ag).

[0238] According to one embodiment, the processor (2010_ap) may be placed on the upper surface (or second surface) of the first printed circuit board (2010_p). The second aggregator circuit (2020_ag) may be placed on the lower surface (or first surface) of the second printed circuit board (2020_p).

[0239] Meanwhile, the numbering for describing each component of the foldable electronic device or electronic device described in the above-described figures to 20 is set based on a specific first component, and the numbering may differ if the numbering is performed based on the second component of the foldable electronic device or electronic device described in figures to 20. For example, in figures to 20, the printed circuit board accommodated in the second housing (120) is defined as the second printed circuit board (121_p), but the printed circuit board accommodated in the third housing (130) may be defined as the second printed circuit board (130_p), and in this case, the printed circuit board accommodated in the second housing (120) may be defined as the third printed circuit board.

[0240] The technical problems to be solved in this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this disclosure belongs.

[0241] FIG. 21 is a drawing showing an example of a rollable electronic device structure to which aggregator circuits according to one embodiment are applied.

[0242] Referring to FIGS. 1 to 21, according to one embodiment, a rollable electronic device (2100) (or sliderable electronic device) may include a first housing (2110), a second housing (2120), and a display (2160). The first housing (2110) may be arranged to be slidable in the y-axis direction relative to the second housing (2120). Alternatively, the second housing (2120) may be arranged to be slidable in the -y-axis direction relative to the first housing (2110). The rollable electronic device (2100) may have a first length in a reduced state (S1) where the aligned length of the first housing (2110) and the second housing (2120) is longer than the first length, and an extended state (S2) where the aligned length of the first housing (2110) and the second housing (2120) is longer than the first length.

[0243] In a first state (e.g., a contracted state (S1)), the rollable electronic device (2100) may be positioned so that a first display area (2161) is visually exposed to the outside. In a second state (e.g., an expanded state (S2)), the rollable electronic device (2100) may be positioned so that a first display area (2161) and a second display area (2162) are visually exposed to the outside. One end of the first display area (2161) (e.g., the -y-axis edge) and one end of the second display area (2162) (e.g., the y-axis edge) may be connected to each other. Correspondingly, in the first state, the second display area (2162) may be positioned below the first display area (2161) (e.g., below in the -z-axis direction relative to the first display area (2161)).

[0244] According to one embodiment, in a first state, a first printed circuit board (110_p) is disposed at the bottom of a first display area (2161), and a processor (110_ap), a first aggregator circuit (110_ag), a first signal wiring (110_sg), and a portion of a flexible substrate (100_fb) may be disposed on the first printed circuit board (110_p). In a second state, while a second display area (2162) is disposed to be visually exposed to the outside, a second printed circuit board (120_p) and at least one electronic element (120_peX) are disposed at the bottom of the second display area (2162), and a second aggregator circuit (120_ag) and another portion of a flexible substrate (100_fb) may be disposed on the second printed circuit board (120_p). According to various embodiments, at least a portion of the at least one electronic element (120_peX) may be disposed on the second printed circuit board (120_p). A second signal wiring (120_sg) connecting the second aggregator circuit (120_ag) and the at least one electronic element (120_peX) may be formed (or disposed) on the second printed circuit board (120_p) or provided in the form of a flexible substrate, such that one side of the second signal wiring (120_sg) is connected to the second printed circuit board (120_p) and the other side is connected to the at least one electronic element (120_pex).

[0245] According to various embodiments, the first printed circuit board (110_p) and the second printed circuit board (120_p) may be positioned below the first display area (2161). Correspondingly, when viewed from the z-axis in the direction of the -z-axis, the first printed circuit board (110_p) and the second printed circuit board (120_p) may be positioned to overlap at least partially with the first display area (2161). According to one embodiment, at least a portion of the first printed circuit board (110_p) and the second printed circuit board (120_p) may be positioned to overlap with respect to the z-axis direction.

[0246] The rollable electronic device (2100) described in FIG. 21 above is shown to illustrate that the aggregator circuits described in FIG. 1 to 20 above can be applied in the same or similar way to rollable or sliderable type electronic devices, and is not limited to the internal structure or external form of the rollable electronic device (2100).

[0247] FIG. 22 is a drawing showing an example of a structure improved by applying an aggregator circuit according to one embodiment.

[0248] Referring to FIGS. 1 to 22, an electronic device of various embodiments to which the aggregator circuits described above in FIGS. 1 to 21 are applied can provide the effect of reducing at least some of the number of wires and the thickness of the wires, as shown in FIG. 22.

[0249] According to one embodiment, in the case of a structure that does not use an aggregator circuit (e.g., the first aggregator circuit (110_ag) or aggregator circuit portion (110_agi), the second aggregator circuit (120_ag, 121_ag), or the third aggregator circuit (130_ag) described in FIGS. 4 to 21), as in state 2210a, two board connectors (11_co1, 11_co2) and two boards are used for signal transmission and reception between a processor (e.g., the processor (110_ap) of FIG. 4) disposed on a first printed circuit board (e.g., the first printed circuit board (110_p) of FIG. 4) and a second printed circuit board (e.g., the second printed circuit board (120_p) of FIG. 4 and / or the third printed circuit board (130_p) of FIG. 8). Wiring (11_sg1, 11_sg2) connected to connectors (11_co1, 11_co2) may be required. According to one embodiment, in the case of a structure using an aggregator circuit (e.g., the first aggregator circuit (110_ag) or aggregator circuit part (110_agi), the second aggregator circuit (120_ag, 121_ag), or the third aggregator circuit (130_ag) described in FIGS. 4 to 21), wiring (110_sg) connected to one board connector (110_co) and one board connector (110_co) may be required, as in state 2210b.

[0250] According to one embodiment, in the case of a structure that does not use an aggregator circuit (e.g., the first aggregator circuit (110_ag) or aggregator circuit part (110_agi), the second aggregator circuit (120_ag, 121_ag), or the third aggregator circuit (130_ag) described in FIG. 4 to 21), as in state 2220a, a flexible substrate (e.g., the first flexible substrate (100_fb) of FIG. 4) disposed between printed circuit boards (e.g., the first printed circuit board (110_p) and the second printed circuit board (120_p) of FIG. 4) is provided with two connectors (10_co1, 10_co2) and two connectors (10_co1, Flexible substrate wiring (10_se1, 10_se2) connected to 10_co2) may be required. According to one embodiment, in the case of a structure using aggregator circuits (e.g., aggregator circuits described in FIG. 4 to 21 (110_ag, 110_agi, 120_ag, 121_ag, or 130_ag)), as in state 2220b, a flexible substrate (e.g., the first flexible substrate (100_fb) of FIG. 4, the second flexible substrate (120_p), and / or the third flexible substrate (130_p) of FIG. 8) disposed between printed circuit boards (e.g., the first flexible substrate (100_fb) of FIG. 4, the flexible substrates (100_fb1, 100_fb2) of FIG. 8)) of the printed circuit boards (e.g., 110_p, 120_p (or 121_p), 130_p)) is positioned between printed circuit boards (e.g., the first flexible substrate (100_fb) of FIG. 4, the flexible substrates (100_fb1, 100_fb2) of FIG. 8) For transmission and reception, one connector (100_co) and flexible substrate wiring (100_se) connected to one connector (100_co) may be required. In the case of the flexible substrate, the portion overlapping with the hinge structure (or the portion overlapping with the hinge housing) may be composed of two layers, and the other portion (e.g., the portion overlapping with printed circuit boards) may be composed of one or two layers.

[0251] In relation to the structure described above, when comparing the flexible substrate of state 2220a with the flexible substrate of state 2220b, the width of the flexible substrate can be reduced by approximately 3 to 4.54 mm, and considering the case where the width required for the addition of the aggregator circuit is 1.78 mm, space for embedded elements in the electronic device can be secured. According to one embodiment, when the aggregator circuit is applied, 46 signal lines in various communication methods (e.g., GPIO, I2C, SPI) can be reduced to 10 lines of the aggregator circuit. As described above, when the aggregator circuits of the present invention are applied, the width of the flexible substrate can be reduced by approximately 3.4 mm compared to before, and two 64-pin connectors required for connecting the printed circuit board and the flexible substrate can be replaced with one 78-pin connector. In this way, by removing one connector, the size of the main PCB (e.g., the first printed circuit board) can be reduced, space can be provided for additional placement of other electronic components, or space can be utilized to reduce signal interference.

[0252] FIG. 23 is a block diagram of an exemplary electronic device (2300) capable of performing the operations described in this document.

[0253] Referring to FIG. 23, the electronic device (2300) may be one of various forms of electronic devices, such as a notebook (2390), smartphones (2391) having various form factors (e.g., a bar-type smartphone (2391-1), a foldable-type smartphone (2391-2), or a sliderable (or rollable)-type smartphone (2391-3)), a tablet (2392), a cellular phone (not shown), and other similar computing devices (not shown). The components, their relationships, and their functions illustrated in FIG. 23 are illustrative only and are not intended to limit the implementations described or claimed herein. The electronic device (2300) may be referred to as a mobile device, a user device, a multifunction device, a portable device, or a server.

[0254] The electronic device (2300) may include components comprising at least one processor (2310) (hereinafter referred to as processor (2310)), at least one memory (2320) (hereinafter referred to as memory (2320)), at least one display (2340) (hereinafter referred to as display (2340)), at least one image sensor (2350) (hereinafter referred to as image sensor (2350)), at least one communication circuit (2360) (hereinafter referred to as communication circuit (2360)), and / or at least one sensor (2370) (hereinafter referred to as sensor (2370)). The components are merely exemplary. For example, the electronic device (2300) may include other components (e.g., power management integrated circuitry (PMIC), audio processing circuit, antenna, rechargeable battery, or input / output interface). For example, some components may be omitted from the electronic device (2300). For example, some components can be integrated into a single component.

[0255] The processor (2310) may be implemented as one or more IC (integrated circuit (or circuitry)) chips and may perform various data processing operations. The processor (2310) may include at least one electrical circuit and may process instructions (or programs, data, etc.) stored in memory (2320) individually or collectively in a distributed manner. The processor (2310) may include a processor assembly comprising one or more processing circuits. The processor (2310) may include any processing circuit that is operative to control the performance and operations of one or more components of the electronic device (2300) (e.g., memory (2320), display (2340), image sensor (2350), communication circuit (2360), and / or sensor (2370)). For example, the processor (2310) (e.g., application processor (AP)) may be implemented as a system on chip (SoC) (e.g., a single chip or a chipset). For example, the processor (2310) may be implemented as a plurality of cores (or at least one core circuit), a plurality of chips, or a plurality of chipsets. For example, the processor (2310) may include one or more processing circuits. For example, the processor (2310) may include one or more processing circuits configured to perform the various functions of the present disclosure individually and / or collectively. As an example without limitation, at least a portion of the processor (2310) may be included in a first chip of the electronic device (2300), and at least another portion of the processor (2310) may be included in a second chip of the electronic device (2300) different from the first chip of the electronic device (2300).

[0256] For example, the processor (2310) may include a central processing unit (CPU) (2311), a graphics processing unit (GPU) (2312), a neural processing unit (NPU) (2313), an image signal processor (ISP) (2314), a display controller (2315), a memory controller (2316), a storage controller (2317), a communication processor (CP) (2318), and / or a sensor interface (2319). These components of the processor (2310) are merely exemplary. For example, the processor (2310) may include other components. For example, some components of the processor (2310) may be omitted from the processor (2310). For example, some components of the processor (2310) may be included as separate components of the electronic device (2300) outside of the processor (2310). For example, some components of the processor (2310) (e.g., memory controller (2316)) may be included in other components (e.g., at least part of memory (2320), an interface (e.g. available for connection to at least one component of the electronic device (100)), a display (2340) and / or an image sensor (2350)).

[0257] The processor (2310) may cause other components of the electronic device (2300) to perform various operations by executing instructions stored in memory (2320). The CPU (2311) (or central processing circuit) may be configured to control the components of the processor (2310) based on the execution of instructions stored in memory (2320) (e.g., volatile memory (2321) and / or non-volatile memory (2322)). The GPU (2312) (or graphics processing circuit) may be configured to execute parallel operations (e.g., rendering). The NPU (2313) (or neural processing circuit, or AI (artificial intelligence) chip) may be configured to execute operations for an artificial intelligence model (e.g., convolution computation). An ISP (2314) (or image signal processing circuit) may be configured to process a raw image acquired through an image sensor (2350) into a format suitable for a component within an electronic device (2300) or a component of a processor (2310). A display controller (2315) (or display control circuit, or DPU (display processing unit)) may be configured to process an image acquired from a CPU (2311), GPU (2312), ISP (2314), or memory (2320) (e.g., volatile memory (2321)) into a format suitable for a display (2340). A memory controller (2316) (or memory control circuit) may be configured to control reading data from volatile memory (2321) and writing data to volatile memory (2321). The storage controller (2317) (or storage control circuit) may be configured to control reading data from non-volatile memory (2322) and writing data to non-volatile memory (2322).The CP (2318) (communication processing circuit) may be configured to process data obtained from a component of the processor (2310) into a format suitable for transmitting to another electronic device via the communication circuit (2360), or to process data obtained from another electronic device via the communication circuit (2360) into a format suitable for processing by the component of the processor (2310). For example, the communication circuit (2360) may include one or more communication circuits. The sensor interface (2319) (or sensing data processing circuit, sensor hub) may be configured to process data regarding the state of the electronic device (2300) and / or the state around the electronic device (2300), obtained through the sensor (2370), into a format suitable for the component of the processor (2310).

[0258] Memory (2320) may include one or more storage media (or one or more storage devices). For example, memory (2320) may include a memory assembly comprising one or more storage media. For example, the one or more storage media may include a hard drive, a flash memory, a permanent memory such as ROM (read-only memory) (e.g., non-volatile memory (2322)), a semi-permanent memory such as RAM (random access memory) (e.g., volatile memory (2321)), any other suitable type of storage (or storage assembly), or any combination thereof. Memory (2320) may include a cache memory, which is one or more different types of memory used to temporarily store data for a function or feature of the electronic device (2300). As an example not limited to, the cache memory may be included within the processor (2310). The memory (2320) may be fixedly embedded within the electronic device (2300) or incorporated into one or more suitable types of components (e.g., a SIM (subscriber identity module) card and / or an SD (secure digital) card) that can be repeatedly inserted into and removed from the electronic device (2300).

[0259] For example, memory (2320) may store one or more software applications, such as operating system (or system) software applications, firmware software applications, driver software applications, plugin (e.g., add-in, add-on, and / or applet) software applications, and / or any other suitable software applications. For example, the one or more software applications may include instructions executable by the processor (2310). For example, memory (2320) may store instructions that can be called by an application programming interface (API). For example, memory (2320) may store instructions within a library.

[0260] As described above, according to one embodiment of the present invention, a foldable electronic device (100) according to one embodiment may include a housing comprising a first housing portion (or first housing (110)), a second housing portion (or second housing (120)), and a hinge housing portion (e.g., hinge housing (150)) disposed at least partially between the first housing portion and the second housing portion; a hinge assembly (or first hinge device (140) or second hinge device (140-1)) rotatably connected to the first housing portion and the second housing portion and at least partially received in the hinge housing portion; a flexible display (e.g., first display (160) of FIGS. 1 to 3) received in the first housing portion and the second housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing; and a processor (e.g., processor (110_ap)) received in the first housing portion. The foldable electronic device (100) comprises a first aggregator circuit (110_ag) which is received in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports less than the first number, a second aggregator circuit (120_ag) which is received in the second housing portion and configured to convert the second control signal into a third control signal that can be output through a third number of ports greater than the second number, and a flexible circuit board (FPCB) (e.g., flexible board (100_fb), or flexible printed circuit board) connected to the first aggregator circuit and the second aggregator circuit, and a portion of the FPCB may be at least partially coupled to the hinge assembly or at least partially received in the hinge housing portion and configured to transmit the second control signal.

[0261] According to one embodiment, the foldable electronic device (100) further comprises a first PCB (e.g., a first printed circuit board (110_p) of FIG. 4) which is received in the first housing portion (e.g., a first housing (110)) and connected to a first connector (e.g., a first connector (100_co1) of FIG. 4 or FIG. 9) disposed at a first end of the FPCB (e.g., 100_fb) of FIG. 4), a second PCB (e.g., a second printed circuit board (120_p) of FIG. 4 or a second printed circuit board (121_p) of FIG. 8) which is received in the second housing portion and connected to a second connector (e.g., a second connector (100_co1) of FIG. 4 or FIG. 9) disposed at a second end of the FPCB, and the processor (110_ap) and the first aggregator circuit (110_ag) are the first The second aggregator circuit (120_ag) is placed on the PCB (110_p), and the second aggregator circuit (120_ag) can be placed on the second PCB (120_p or 121_p).

[0262] According to one embodiment, the processor (110_ap) and the first aggregator circuit (e.g., 110_ag of FIG. 4) (or the aggregator circuit portion (110_agi) of FIG. 7) can form a single chipset.

[0263] According to one embodiment, the second aggregator circuit (e.g., 120_ag of FIG. 4) is configured to be electrically connected to a plurality of components (e.g., a plurality of electronic elements (120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6 of FIG. 4) accommodated within the second housing to transmit the third control signal, and each of the plurality of components may include a sensor module, a PMIC, an audio module, a display control circuit, or a touch control module.

[0264] According to one embodiment, the processor (110_ap) and at least one of the plurality of components (e.g., 120_pe1, 120_pe2, 120_pe3, 120_pe4, 120_pe5, 120_pe6 of FIG. 4) are further electrically connected between the processor (110_ap) and at least one of the components, and at least partially coupled to the hinge assembly (e.g., first hinge device (140)) or at least partially accommodated in the hinge housing portion (e.g., hinge housing (150)), and the processor (110_ap of FIG. 8) may be configured to transmit a payload associated with the at least one component to the at least one component through the other FPCB.

[0265] According to one embodiment, the processor (110_ap) may be configured to disable, at least temporarily, the part of the second aggregator circuit (120_ag) connected to the touch control module that processes touch input for the flexible display while the housing is fully folded.

[0266] According to one embodiment, the first control signal may include a first control signal portion corresponding to a first serial communication having a first speed, and a second control signal portion corresponding to a second serial communication having a second speed different from the first speed, and the third control signal may include a third control signal portion corresponding to the first serial communication and a fourth control signal portion corresponding to the second serial communication. The first aggregator circuit (110_ag) or the second aggregator circuit (120_ag) may be configured to transmit the second control signal through the said portion of the FPCB (e.g., 100_fb in FIG. 4) at a third speed faster than the first speed and the second speed.

[0267] According to one embodiment, each of the first serial communication and the second serial communication may include an Inter-Integrated Circuit (I2C), Inter-IC Sound C (I3C), Inter-IC Sound (I2S), Serial Peripheral Interface (SPI), or General Purpose Input / Output (GPIO).

[0268] According to the embodiments of the present invention described above, a foldable electronic device (e.g., 1112 to 1119) according to one embodiment comprises a housing including a first housing portion (e.g., first housing (110)), a second housing portion (e.g., second housing (120)), a third housing portion (e.g., third housing (130)), a first hinge housing portion (e.g., first hinge housing (151)) disposed at least partially between the first housing portion and the second housing portion, and a second hinge housing portion (e.g., second hinge housing (152)) disposed at least partially between the second housing portion and the third housing portion; a first hinge assembly (e.g., first hinge device (140)) rotatably connected to the first housing portion and the second housing portion and at least partially received in the first hinge housing portion; and a second hinge rotatably connected to the second housing portion and the third housing portion and at least partially received in the second hinge housing portion. An assembly (e.g., a second hinge device or a third hinge device (140-2) of FIG. 8), a flexible display (e.g., a first display (160) of FIG. 3) that is received in the first housing portion, the second housing portion, and the third housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing, a processor (110_ap) received in the first housing portion, a first aggregator circuit (110_ag) received in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports less than the first number, a second aggregator circuit received in the third housing portion and configured to receive the second control signal through a third number of ports and convert the second control signal into a third control signal that can be output through a fourth number of ports greater than the third number (e.g., FIG. 8 130_ag),The device includes a connection structure connected to the first aggregator circuit and the second aggregator circuit, wherein the connection structure may include a first flexible printed circuit board (FPCB) portion (e.g., a first flexible substrate (100_fb1)) that is at least partially coupled to the first hinge assembly or at least partially received in the first hinge housing portion, and a second FPCB portion (e.g., a second flexible substrate (100_fb2)) that is at least partially coupled to the second hinge assembly or at least partially received in the second hinge housing portion and configured to transmit the second control signal.

[0269] According to one embodiment, the foldable electronic device (at least one of 1111 to 1119) may further include a first printed circuit board (PCB) (110_p) which is received in the first housing portion and connected to a first connector (e.g., 110_co1 in FIG. 9 or 14) disposed at the first end of the first FPCB portion, and a second PCB (e.g., 130_p in FIG. 9 or 14) which is received in the third housing portion and connected to a second connector (e.g., 110_co4 in FIG. 9 or 14) disposed at the second end of the second FPCB portion. The processor (110_ap) and the first aggregator circuit (110_ag) may be placed on the first PCB (110_p), and the second aggregator circuit (e.g., 130_ag in FIG. 9) may be placed on the second PCB (e.g., 130_p in FIG. 9).

[0270] According to one embodiment, the foldable electronic device (at least one of 1111 to 1119) may further include a third aggregator circuit (e.g., 121_ag of FIG. 10) configured to receive at least a portion of the second control signal through a fifth number of ports and convert the at least portion of the second control signal into a fourth control signal that can be output through a sixth number of ports, which is greater than the fifth number.

[0271] According to one embodiment, the foldable electronic device (at least one of 1111 to 1119) is accommodated in the second housing portion (120) and further comprises a third PCB (121_p) connected to a third connector (e.g., 100_co2 in FIG. 9 or 14) disposed at a third end opposite to the first end of the first FPCB portion (100_fb1) and a fourth connector (e.g., 100_co3 in FIG. 9 or 14) disposed at a fourth end opposite to the second end of the second FPCB portion (100_fb2), and the third aggregator circuit (121_ag in FIG. 10) may be disposed on the third PCB (e.g., 121_p in FIG. 10).

[0272] According to one embodiment, the third aggregator circuit (e.g., 121_ag in FIG. 10) is configured to be electrically connected to at least one component (or electronic element) housed within the second housing to transmit the fourth control signal, and the at least one component may include a sensor module, a PMIC, an audio module, a display control circuit, or a touch control module.

[0273] According to one embodiment, the third PCB (e.g., 121_p in FIG. 10) may include a first group of signal lines connected to the third connector (e.g., 100_co2 in FIG. 9) and the fourth connector (e.g., 100_co3 in FIG. 9), and a second group of signal lines connected between the third connector (e.g., 100_co2 in FIG. 9) and the third aggregator circuit (e.g., 121_ag in FIG. 10).

[0274] According to one embodiment, the third PCB (e.g., 121_p in FIG. 10) may include a plurality of signal lines connecting the third connector (e.g., 100_co2 in FIG. 9) and the fourth connector (e.g., 100_co3 in FIG. 9), and a plurality of signal lines connecting the third connector (e.g., 100_co2 in FIG. 9) and the third aggregator circuit (e.g., 121_ag in FIG. 10).

[0275] According to one embodiment, the third PCB (e.g., 121_p in FIG. 12) includes signal lines connected from the third connector (e.g., 100_co2 in FIG. 9) through the third aggregator circuit (e.g., 121_ag in FIG. 12) to the fourth connector (e.g., 100_co3 in FIG. 9), and the third aggregator circuit (e.g., 121_ag in FIG. 12) if the entirety of the second control signal relates to at least one component (e.g., at least one of the electronic elements 130_pe1, 130_pe2, 130_pe3, 130_pe4, 130_pe5, 130_pe6 in FIG. 12) housed in the third housing (130), the second control signal relates to another component (e.g., the electronic elements in FIG. 12) housed in the second housing (120). It can be configured to be transmitted to the fourth connector (e.g., 100_co3 in FIG. 9) without being transmitted to at least one of 121_pe1, 121_pe2, and 121_pe3.

[0276] According to one embodiment, the processor (110_ap) may be configured to disable at least one of the second aggregator circuit (e.g., 130_ag in FIG. 12) or the third aggregator circuit (e.g., 121_ag in FIG. 12) or to operate in a low-power mode at least temporarily while the housing is fully folded.

[0277] According to one embodiment, the processor (110_ap) may be configured to disable, at least temporarily, the part of the second aggregator circuit (e.g., 130_ag in FIG. 12) or the third aggregator circuit (e.g., 121_ag in FIG. 12) connected to the touch control module that processes touch input for the flexible display (or flexible display) while the housing is fully folded.

[0278] According to one embodiment, the first FPCB portion (e.g., 100_fb1 in FIG. 8) and the second FPCB portion (e.g., 100_fb2 in FIG. 8) can form a single FPCB.

[0279] According to one embodiment, the first control signal includes a first control signal portion corresponding to a first serial communication having a first speed, and a second control signal portion corresponding to a second serial communication having a second speed different from the first speed, and the third control signal includes a third control signal portion corresponding to the first serial communication and a fourth control signal portion corresponding to the second serial communication, and the first aggregator circuit (e.g., 110_ag in FIG. 8) or the second aggregator circuit (e.g., 130_ag in FIG. 8) may be configured to transmit the second control signal through the said portion of the FPCB at a third speed faster than the first speed and the second speed.

[0280] According to the above-described embodiment, a foldable electronic device (100) according to one embodiment of the present invention comprises a first housing (110), a second housing (120), a hinge device (140) connecting the housings, a first printed circuit board (110_p) disposed in the first housing, a second printed circuit board (120_p or 121_p) disposed in the second housing, a flexible substrate (100_bf) connecting the printed circuit boards (110_p, 120_p), a processor (110_ap) and a first aggregator circuit (110_ag) disposed in the first printed circuit board, a second aggregator circuit (120_ag) disposed in the second printed circuit board, and a plurality of electronic elements (120_pe1 to 120_pe6), wherein the first printed circuit board connects the processor and the first aggregator circuit (or the first aggregator). The first circuit wiring (110_se) and the first substrate wiring (110_s1) connecting the processor and the flexible substrate are included, and the processor (110_ap) is configured to transmit N multiple input / output control signals related to the operation of a plurality of electronic elements to a first aggregator circuit through the first circuit wiring (110_se), convert the first aggregator circuit into M serialized signals and transmit them to the second aggregator circuit (or second aggregator) through the flexible substrate, and the speed of the signal transmitted through the first substrate wiring may be greater than the speed of the signal transmitted through the circuit wiring.

[0281] According to one embodiment, the flexible substrate includes a first wiring portion connected to the first substrate wiring and a second wiring portion connected to the first circuit wiring, and the speed of the signal transmitted through the first wiring portion may be greater than the speed of the signal transmitted through the second wiring portion.

[0282] According to one embodiment, the number of signal lines of the first substrate wiring and the number of signal lines of the first wiring portion are the same, and the number of signal lines of the first circuit wiring may be smaller than the number of signal lines of the second wiring portion.

[0283] According to one embodiment, the multiple input / output control signal may include input / output control signals of different communication methods (or different types).

[0284] The effects obtainable from the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs.

[0285] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0286] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of such embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. In this document, phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together with the corresponding phrase, or any possible combination thereof. Terms such as “first,” “second,” or “first” or “second” may be used simply to distinguish a component from another corresponding component and do not limit the components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as "coupled" or "connected" to another (e.g., 2nd) component, with or without the terms "functionally" or "communicationly," it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0287] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0288] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In a foldable electronic device, A housing comprising a first housing portion (110), a second housing portion (120), and a hinge housing portion (150) disposed at least partially between the first housing portion and the second housing portion; A hinge assembly (140) that is at least partially accommodated in the hinge housing portion and rotatably connected to the first housing portion and the second housing portion; A flexible display (160) accommodated in the first housing portion and the second housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing; and A processor (110_ap) housed in the first housing portion above; A first aggregator circuit (110_ag) accommodated in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports that is less than the first number; A second aggregator circuit (120_ag) accommodated in the second housing portion and configured to receive the second control signal through the second number of ports and convert the second control signal into a third control signal that can be output through a third number of ports greater than the second number; and A foldable electronic device comprising a flexible printed circuit board (FPCB) (100_fb) connected to the first aggregator circuit and the second aggregator circuit, wherein a portion of the FPCB is at least partially coupled to the hinge assembly or at least partially received in the hinge housing portion and configured to transmit the second control signal.

2. In Paragraph 1, A first printed circuit board (PCB) accommodated in the first housing portion and connected to a first connector disposed at the first end of the FPCB; and It further includes a second PCB that is accommodated in the second housing portion and connected to a second connector disposed at the second end of the FPCB, and The above processor and the above first aggregator circuit are placed on the above first PCB, and The above second aggregator circuit is a foldable electronic device placed on the above second PCB.

3. In Paragraph 2, A foldable electronic device in which the processor and the first aggregator circuit form a single chipset.

4. In Paragraph 1, The second aggregator circuit is configured to be electrically connected to a plurality of components housed within the second housing portion to transmit the third control signal, and A foldable electronic device in which each of the above plurality of components includes a sensor module, a PMIC (power management integrated circuitry), an audio module, a display control circuit, or a touch control module.

5. In Paragraph 4, It further includes another FPCB electrically connected between the processor and at least one of the plurality of components, and at least partially coupled to the hinge assembly or at least partially received in the hinge housing portion, A foldable electronic device configured such that the processor transmits a payload associated with the at least one component to the at least one component through the other FPCB.

6. In Paragraph 1, A foldable electronic device configured such that, while the housing is fully folded, the processor is configured to disable, at least temporarily, the portion of the second aggregator circuit connected to the touch control module that processes touch input for the flexible display.

7. In Paragraph 1, The first control signal includes a first control signal portion corresponding to a first serial communication having a first speed, and a second control signal portion corresponding to a second serial communication having a second speed different from the first speed. The third control signal includes a third control signal portion corresponding to the first serial communication and a fourth control signal portion corresponding to the second serial communication, and A foldable electronic device in which the first aggregator circuit or the second aggregator circuit is configured to transmit the second control signal through the portion of the FPCB at a third speed faster than the first speed and the second speed.

8. In Paragraph 7, A foldable electronic device in which each of the first serial communication and the second serial communication comprises an Inter-Integrated Circuit (I2C), an improved inter-integrated circuit (I3C), an Inter-IC Sound (I2S), a Serial Peripheral Interface (SPI), or a General Purpose Input / Output (GPIO).

9. In a foldable electronic device, A housing comprising a first housing portion (110), a second housing portion (120), a third housing portion (130), a first hinge housing portion (151) disposed at least partially between the first housing portion and the second housing portion, and a second hinge housing portion (152) disposed at least partially between the second housing portion and the third housing portion; A first hinge assembly (140) that is at least partially received in the first hinge housing portion and rotatably connected to the first housing portion and the second housing portion; A second hinge assembly (140-2) that is at least partially received in the second hinge housing portion and rotatably connected to the second housing portion and the third housing portion; A flexible display (160) accommodated in the first housing portion, the second housing portion, and the third housing portion and configured to be folded or unfolded according to the folding or unfolding of the housing; A processor (110_ap) housed in the first housing portion above; A first aggregator circuit (110_ag) accommodated in the first housing portion and configured to convert a first control signal input from the processor through a first number of ports into a second control signal that can be output through a second number of ports that is less than the first number; A second aggregator circuit (130_ag) accommodated in the third housing portion and configured to receive the second control signal through a third number of ports and convert the second control signal into a third control signal that can be output through a fourth number of ports, which is greater than the third number; and A foldable electronic device comprising a connection structure connected to the first aggregator circuit and the second aggregator circuit, wherein the connection structure comprises a first flexible printed circuit board (FPCB) portion (100_fb1) that is at least partially coupled to the first hinge assembly or at least partially received in the first hinge housing portion, and a second FPCB portion (100_fb2) that is at least partially coupled to the second hinge assembly or at least partially received in the second hinge housing portion and configured to transmit the second control signal.

10. In Paragraph 9, A first printed circuit board (PCB) accommodated in the first housing portion and connected to a first connector disposed at the first end of the first FPCB portion; It further includes a second PCB that is accommodated in the third housing portion and connected to a second connector disposed at the second end of the second FPCB portion, The above processor and the above first aggregator circuit are placed on the above first PCB, and The above second aggregator circuit is a foldable electronic device placed on the above second PCB.

11. In Paragraph 9, A third aggregator circuit that is accommodated in the second housing portion and is configured to receive at least a portion of the second control signal through a fifth number of ports and convert the at least portion of the second control signal into a fourth control signal that can be output through a sixth number of ports, which is greater than the fifth number; It further includes a third PCB that is accommodated in the second housing portion and connected to a third connector disposed at a third end opposite to the first end of the first FPCB portion and a fourth connector disposed at a fourth end opposite to the second end of the second FPCB portion. The above third aggregator circuit is a foldable electronic device placed on the above third PCB.

12. In Paragraph 11, The third aggregator circuit is electrically connected to at least one component housed within the second housing portion and configured to transmit the fourth control signal, and The third PCB includes a first group of signal lines connected to the third connector and the fourth connector, and a second group of signal lines connected between the third connector and the third aggregator circuit, or A foldable electronic device comprising a plurality of signal lines connecting the third connector and the fourth connector, and a plurality of signal lines connecting the third connector and the third aggregator circuit.

13. In Paragraph 11, The third PCB includes signal lines that pass from the third connector through the third aggregator circuit and connect to the fourth connector, and A foldable electronic device configured such that, when the entirety of the second control signal is related to at least one component housed in the third housing portion, the second control signal is not transmitted to another component housed in the second housing portion, but is transmitted to the fourth connector.

14. In Paragraph 11, The processor is configured to disable at least one of the second aggregator circuit or the third aggregator circuit at least temporarily or to operate in a low-power mode while the housing is fully folded, or A foldable electronic device configured such that the processor is configured to temporarily disable the part of the second aggregator circuit or the third aggregator circuit connected to the touch control module that processes touch input for the flexible display while the housing is fully folded.

15. In Paragraph 9, The first control signal includes a first control signal portion corresponding to a first serial communication having a first speed, and a second control signal portion corresponding to a second serial communication having a second speed different from the first speed. The third control signal includes a third control signal portion corresponding to the first serial communication and a fourth control signal portion corresponding to the second serial communication, and A foldable electronic device in which the first aggregator circuit or the second aggregator circuit is configured to transmit the second control signal through the portion of the FPCB at a third speed faster than the first speed and the second speed.

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