Antenna substrate

Abstract

An antenna substrate according to an embodiment comprises: an antenna unit which transmits and receives external signals; and a cable unit which is coupled to the antenna unit and supplies power to the antenna unit, wherein each of the antenna unit and the cable unit includes a stacked plurality of unit layers, and each of the plurality of unit layers may include an insulating layer, a wiring layer disposed on one surface of the insulating layer, and a via which passes through the insulating layer and connects wiring layers on both sides of the insulating layer.

Description

Antenna board

[0001] An example relates to an antenna substrate.

[0002] An antenna package (or Antenna in Package (AiP)) refers to a module that integrates an antenna with a semiconductor chip, RF (Radio Frequency) circuit, signal processing device, etc., to form a single package, and is essential in fields such as 5G, mmWave, IoT, automotive, and satellite communication. Compared to conventional antennas that exist individually, antenna packages can improve performance, reduce size, and increase reliability.

[0003] Referring to FIG. 1, the antenna package (10) may include an antenna substrate (10A) and other package components (50). The other package components (50) may be other components included in the antenna package (10), such as an RF module connected to the antenna substrate (10A) and a connector for connection to a main board, excluding the antenna substrate (10A).

[0004] An antenna substrate (10A) may include an antenna section (20) that includes an antenna circuit for transmitting and receiving external signals, and a cable section (30) that includes a cable circuit for connecting the antenna circuit to an RF module, power supply, etc. Each of the antenna section (20) and the cable section (30) may be a multilayer substrate in which a plurality of insulating layers and wiring layers are arranged alternately, and the plurality of wiring layers may be connected through a plurality of vias. The antenna circuit and the cable circuit may be formed by a plurality of wiring layers and a plurality of vias.

[0005] Since such an antenna substrate (10A) must be capable of transmitting millimeter wave (mmWave, 24–100 GHz) and terahertz (THz, 100 GHz or higher) bands used in 5G and next-generation 6G communication, and must be mounted on devices with significant space constraints such as smartphones, IoT devices, wearables, and AR / VR devices, it is required to be developed to enable ultra-high frequency or high-speed signal transmission, while satisfying low loss and high reliability, and to be miniaturized and slim. In particular, the correction circuit for impedance matching (e.g., a transformer) requires a finer pattern than other wiring due to its characteristics, and there is a need for a method to minimize errors from the design to achieve the intended performance.

[0006] An embodiment provides an antenna substrate having slim and excellent characteristics.

[0007] An antenna substrate according to one embodiment includes an antenna portion that transmits and receives an external signal and a cable portion that supplies power to the antenna portion in conjunction with the antenna portion. Each of the antenna portion and the cable portion includes a plurality of stacked unit layers, and each of the plurality of unit layers includes an insulating layer, a wiring layer disposed on one side of the insulating layer, and a via that penetrates the insulating layer and connects the wiring layers on both sides of the insulating layer. The wiring layer may include first and second electrode layers with different particle sizes.

[0008] For example, the second electrode layer may have a larger particle size than the first electrode layer.

[0009] For example, the wiring layer may include a first interface formed between the first and second electrode layers.

[0010] For example, the thickness of the first electrode layer may be 1.5 μm to 3 μm.

[0011] For example, the thickness of the second electrode layer may be equal to or greater than the thickness of the first electrode layer.

[0012] For example, the via may include a first via whose width increases along a first direction and a second via whose width increases along a second direction different from the first direction.

[0013] For example, the first direction may be upward and the second direction may be downward.

[0014] For example, the reference wiring layer may be further included, and a plurality of unit layers of the antenna section and the cable section may include an upper unit layer positioned above the reference wiring layer and a lower unit layer positioned below the reference wiring layer, the upper unit layer may include a first via, and the lower unit layer may include a second via.

[0015] For example, within the upper unit layer, the wiring layer may be positioned in the first direction of the insulating layer, and within the lower unit layer, the wiring layer may be positioned in the second direction of the insulating layer.

[0016] For example, in the upper and lower unit layers, the first electrode layer may be disposed between the insulating layer and the second electrode layer.

[0017] For example, the roughness of the surface of the first electrode layer in contact with the insulating layer may be greater than the roughness of the remaining surfaces.

[0018] For example, at least a portion of the vias and wiring layers may include a second electrode layer and a third electrode layer with a particle size different from that of the second electrode layer.

[0019] For example, the third electrode layer can be placed between the second electrode layer and the insulating layer.

[0020] For example, the particle size of the third electrode layer may be smaller than that of the second electrode layer.

[0021] For example, the third electrode layer of the via can extend into the wiring layer.

[0022] For example, the via and the wiring layer may include a second interface formed between the second electrode layer and the third electrode layer.

[0023] For example, the wiring layer may include a third interface formed between the first electrode layer and the third electrode layer.

[0024] For example, the antenna section and the cable section can be stacked in a vertical direction.

[0025] For example, the antenna section can have its entire surface area overlapped vertically with the cable section.

[0026] For example, the wiring layer included in the uppermost unit layer of the cable section may be 80% or more of the area of ​​the antenna section.

[0027] For example, the thickness of the wiring layer may be 2 μm to 15 μm.

[0028] For example, the thickness of the insulating layer may be 45 μm to 55 μm.

[0029] An antenna substrate according to one embodiment includes an antenna portion for transmitting and receiving external signals and a cable portion disposed below the antenna portion to supply power to the antenna portion, each of the antenna portion and the cable portion includes a plurality of stacked unit layers, each of the plurality of unit layers includes an insulating layer, a wiring layer disposed above the insulating layer, and a via that penetrates the insulating layer and connects the wiring layer of an adjacent unit layer, the insulating layer of the antenna portion includes a first material, and the insulating layer of the cable portion includes a second material different from the first material, and three or more consecutive unit layers among the plurality of unit layers forming the antenna portion and the cable portion further include a vertical via formed by arranging the unit vias included in each unit layer in a vertical direction, and the center axis of at least some of the unit vias may not overlap with a preset reference center axis.

[0030] For example, the insulating layer of the lowest unit layer of the antenna section may come into contact with the wiring layer of the uppermost unit layer of the cable section.

[0031] For example, it may not include at least one of the bonding member that combines the antenna part and the cable part, and the adhesive member between the plurality of unit layers of the cable part.

[0032] For example, the via may include a first asymmetric via that widens as it goes in a first direction and a second asymmetric via that widens as it goes in a second direction different from the first direction.

[0033] For example, the first direction may be upward and the second direction may be downward.

[0034] For example, the reference wiring layer may be further included, and a plurality of unit layers of the cable section and the antenna section may include an upper unit layer positioned above the reference wiring layer and a lower unit layer positioned below it, the upper unit layer may include a first asymmetric via, and the lower unit layer may include the second asymmetric via.

[0035] For example, the reference wiring layer is included in the cable section, and the uppermost unit layer of the cable section and the lowermost unit layer of the antenna section may both be upper unit layers.

[0036] For example, a vertical via may include a plurality of unit vias included in each of three or more consecutive unit layers, and a plurality of unit wiring layers disposed between each of the plurality of unit vias and at both ends of the vertical via.

[0037] For example, three or more consecutive unit layers may all be included in the antenna section, all be included in the cable section, or some may be included in the antenna section and the remaining parts in the cable section.

[0038] For example, a plurality of unit vias may include at least one of a first asymmetric via and a second asymmetric via.

[0039] For example, multiple unit vias may simultaneously penetrate two consecutive unit layers and further include symmetric vias of constant width.

[0040] For example, a plurality of wiring layers includes a central wiring layer, and the central wiring layer is a wiring layer positioned at the center among the plurality of unit wiring layers when the number of the plurality of unit vias is even, and unit wiring layers positioned at both ends of the unit via positioned at the center among the plurality of unit vias when the number of the plurality of unit vias is odd, and the reference central axis may be the central axis of the central wiring layer.

[0041] For example, the spacing between the center axis and the reference center axis of each of the multiple unit vias may be 1 μm or more and less than or equal to the set length.

[0042] For example, the set length may be a range such that the upper or lower surface of the unit via overlaps at least 30% in the vertical direction with either of the unit wiring layers placed at both ends of the unit via.

[0043] For example, the insulating layer and the wiring layer may contain pure copper with a copper content of 99.99% or more.

[0044] For example, the number of unit layers in the antenna section may be greater than the number of unit layers in the cable section.

[0045] For example, the area of ​​the cable section may be 1.1 times or more the area of ​​the antenna section.

[0046] For example, the first material and the second material may differ in at least one of ductility and dielectric constant.

[0047] For example, the first material may include prepreg, and the second material may include liquid crystal polymer.

[0048] For example, the antenna section may include an antenna circuit formed by wiring layers and vias included in a plurality of unit layers of the antenna section, and the cable section may include a cable circuit formed by wiring layers and vias included in a plurality of unit layers of the cable section that connects the antenna circuit and the main board, and terminal sections disposed at both ends of the cable circuit and electrically connected to the main board.

[0049] For example, it may further include a protective layer covering the remaining surface excluding the terminal portion.

[0050] The antenna substrate according to the embodiment can implement a pattern of high resolution and precision.

[0051] The antenna substrate according to the embodiment can form a multilayer substrate without a separate adhesive or bonding member, thereby providing a slim circuit with high electrical conductivity.

[0052] The antenna substrate according to the embodiment can improve the degree of design freedom by freely adjusting the thickness of the wiring layer and incorporating more wiring through fine patterns and vertical vias that vertically connect three or more layers of the substrate.

[0053] The antenna substrate according to the embodiment can reduce loss during the transmission of high frequency and high speed signals (5G, mmWave, RF circuits, etc.), increase signal integrity, and have high electrical conductivity.

[0054] The effects obtainable in this embodiment are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below.

[0055] FIG. 1 is a perspective view of an antenna package according to an embodiment.

[0056] FIG. 2 is a drawing and a partial cross-sectional enlarged view illustrating an antenna substrate according to an embodiment of the present invention.

[0057] FIG. 3 is a diagram showing a flowchart of the manufacturing process of an antenna substrate according to an embodiment of the present invention and a cross-sectional view of the antenna substrate at each process.

[0058] Figure 4 is a diagram illustrating step S110 of Figure 3.

[0059] Figure 5 is a diagram illustrating step B of S140 of Figure 3.

[0060] Figure 6 is a diagram illustrating step C of S170 of Figure 3.

[0061] Figure 7 is a diagram illustrating step D of S190 of Figure 3.

[0062] FIGS. 8a to 8c are drawings showing a top view of a transformer included in a cable circuit.

[0063] Figure 9 is a diagram illustrating the stacking of unit layers in the upward and downward directions after step S190 of Figure 3.

[0064] FIG. 10 is a drawing illustrating an example of an antenna substrate produced as a result of FIG. 9.

[0065] Figure 11 is a diagram illustrating the case where there are 4 (even) vias forming a vertical via.

[0066] FIG. 12 is a drawing illustrating the case where there are 5 (odd number) vias forming a vertical via.

[0067] FIG. 13 is a drawing illustrating a case where a vertical via includes a symmetrical via with a constant width.

[0068] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0069] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0070] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0071] Furthermore, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “A and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0072] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0073] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, that component may include not only cases where it is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0074] Furthermore, when described as being formed or placed on the “top or bottom” of each component, “top or bottom” includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as “top or bottom,” it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0075] Hereinafter, an antenna substrate (10A) and an antenna package (10) according to an embodiment are described as follows with reference to the attached drawings.

[0076] The drawings were drawn based on the Cartesian coordinate system (x-axis, y-axis, z-axis) for convenience of explanation, but they can also be explained using other coordinate systems. In addition, according to the Cartesian coordinate system, the x-axis, y-axis, and z-axis are orthogonal to each other, but the embodiments are not limited thereto and may include cases where the axes intersect each other.

[0077] In addition, the x-axis direction may be a concept that includes both the +x-axis and the -x-axis, and the y-axis and z-axis directions may also include the +y-axis, the -y-axis and the +z-axis, the -z-axis, respectively.

[0078] In the drawing, the x-axis direction may be the short axis direction of the antenna substrate (10A), the y-axis direction may be the long axis direction of the antenna substrate (10A), and the z-axis direction may be the stacking direction, height direction, or thickness direction of the antenna substrate (10A).

[0079] In this description, the stacking direction may be the direction in which the antenna portion (20) is stacked relative to the cable portion (30), and the antenna portion (20) and the cable portion (30) may be stacked in a vertical direction. That is, the stacking direction may be a vertical direction and may include both an upward direction and a downward direction, or optionally. Referring to FIG. 1, which illustrates an antenna package (10) according to an embodiment of the present invention, the antenna package (10, Antenna-in-Package, AiP) may include an antenna substrate (10A) including an antenna circuit and a cable circuit, and other package components (50). The other package components (50) may be other components included in the antenna package (10), such as an RF module connected to the antenna substrate (10A) and a connector for connection to a main board, in addition to the antenna substrate (10A).

[0080] The antenna substrate (10A) may include an antenna section (20) and a cable section (30). The antenna section (20) may be positioned above, on the upper side or in the upward direction of the cable section (30), and the cable section (30) may be positioned below, on the lower side or in the downward direction of the antenna section (20).

[0081] An antenna circuit for transmitting and receiving external signals (or may be expressed as an antenna pattern, antenna wiring, etc.) is placed in the antenna section (20), and a cable circuit, which is a transmission line connecting the antenna circuit and other package components (50), may be placed in the cable section (30). The antenna circuit and the cable circuit may be electrically connected to each other.

[0082] The cable section (30) may have an upper or lower surface wider than the upper or lower surface of the antenna section (20) to secure space for other package components (50) to be combined, connected, or placed. Alternatively, the cable section (30) may have the same width in the x-axis direction as the antenna section (20), but may have a longer length in the y-axis direction than the antenna section (20). Alternatively, the antenna section (20) may be placed on one side of the cable section (30), in which case the side of the cable section (30) may be aligned with the side of the antenna section (20) or protrude further in the -y direction. For example, the area of ​​the cable section (30) may be at least 1.1 times the area of ​​the antenna section (20), or the area of ​​the antenna section (20) may be 80% or less of the area of ​​the cable section (30). Alternatively, the entire upper surface or entire lower surface of the antenna part (20) may be vertically overlapped with at least a part of the upper surface or at least a part of the lower surface of the cable part (30). The arrangement and size, etc. of the antenna part (20) and the cable part (30) described above are merely examples and are not necessarily limited thereto.

[0083] FIG. 2 is a drawing and a partial cross-sectional enlarged view illustrating an antenna substrate (10A) according to an embodiment of the present invention. FIG. 2 roughly shows the arrangement, arrangement, size, thickness, etc. of the antenna portion (20), cable portion (30), wiring layer (120), and via (130) to aid in understanding the present invention, so the embodiments of the present invention are not limited to the drawing shown in FIG. 2.

[0084] Referring to FIG. 2, each of the antenna section (20) and the cable section (30) includes a plurality of unit layers (100), and each unit layer (100) may include an insulating layer (110), a wiring layer (120) disposed on one side of the insulating layer (110), and a via (130) connecting the wiring layer (120) disposed on the upper and lower sides of the insulating layer (110) through the insulating layer (110) (the wiring layer (120) of its own unit layer (100) and the wiring layer (120) of another unit layer (100)).

[0085] In order to distinguish and represent the multiple unit layers (100), insulating layers (110), wiring layers (120), and vias (130) of the antenna section (20) and the cable section (30), the unit layer (100), insulating layer (110), wiring layer (120), and vias (130) of the antenna section (20) may be represented as "first unit layer (200)", "first insulating layer (210)", "first wiring layer (220)", and "first via (230)", and the unit layer (100), insulating layer (110), wiring layer (120), and vias (130) of the cable section (30) may be represented as "second unit layer (300)", "second insulating layer (310)", "second wiring layer (320)", and "second via (330)".

[0086] However, the antenna part (20) and the cable part (30) can be manufactured in a single manufacturing process using the same manufacturing method, with only the material of the insulating layer (110) being different, so the antenna part (20) and the cable part (30) can have common structural features. Therefore, when expressions such as “multiple unit layers (100),” “insulating layer (110),” and “wiring layer (120)” are used instead of distinct names like “first or second unit layer (200, 300),” “first or second insulating layer (210, 310),” “first or second wiring layer (220, 320),” and “first or second via (230, 330),” it should be accepted as describing features that are common to all of them, such as “first and second unit layers (200, 300),” “first and second insulating layer (210, 310),” “first and second wiring layer (220, 320),” or “first and second via (230, 330).”

[0087] The antenna section (20) may be formed by stacking a plurality of first unit layers (200) on the cable section (30), and the cable section (30) may be formed by stacking a plurality of second unit layers (300). The antenna circuit may be formed by a plurality of first wiring layers (220) and first vias (230) disposed on a plurality of first unit layers (200), and the cable circuit may be formed by a plurality of second wiring layers (320) and second vias (330) disposed on a plurality of second unit layers (300).

[0088] The cable section (30) may include a terminal section (340) that is extended or connected from a cable circuit and exposed to the outside and electrically connected to a power supply section or an RF chip, on the outer surface of the second unit layer (300) located on the outer side, that is, the uppermost and lowermost side among a plurality of second unit layers (300). Additionally, the uppermost second unit layer (300) of the cable section (30) may include a second wiring layer (320) that is at least 80% of the area of ​​the antenna section (20).

[0089] The antenna substrate (10A) or cable portion (30) may further include a passivation layer (40) disposed on the remaining surface excluding the terminal portion (340) and the surrounding area. The passivation layer (40) prevents oxidation of the antenna substrate (10A), protects the antenna substrate (10A) from moisture and dust, and can enhance the durability of the antenna substrate (10A).

[0090] The number of first unit layers (200) may be greater than the number of second unit layers (300). For example, the number of first unit layers (200) may be 5 to 8, and the number of second unit layers (300) may be 3 to 5. For example, the number of first unit layers (200) may be 7, and the number of second unit layers (300) may be 3 or 5. These are merely examples and may be changed depending on the configuration and arrangement position of the cable circuit and antenna circuit, etc.

[0091] The first insulating layer (210) and the second insulating layer (310) may include heterogeneous materials. For example, the first insulating layer (210) may include a first material, and the second insulating layer (310) may include a second material having properties opposite to those of the first material. The first material and the second material may differ in at least one of ductility and dielectric constant. For example, the first material may be hard and the second material may be flexible. For example, the first material may be a high dielectric material and the second material may be a low dielectric material. For example, the first material may include prepreg and the second material may include a liquid crystal polymer (LCP). However, these are merely examples and are not necessarily limited thereto, and various materials used in multilayer substrates, such as Teflon (Polytetrafluoroethylene, PTFE), Rogers, and Polyimide (PI), can also be applied.

[0092] Even though the first insulating layer (210) and the second insulating layer (310) are made of different materials, the antenna portion (20) and the cable portion (30) can be manufactured through the same process. That is, the antenna substrate (10A) can be manufactured by stacking the second unit layer (300) and, in the same process, continuously stacking the first unit layer (200) in the same manner as the second unit layer (300), with only the material of the insulating layer (110) being different. Accordingly, the plurality of first unit layers (200) and the plurality of second unit layers (300) may not include an adhesive member disposed between them to adhere the two unit layers (100), nor may they include a coupling member (60) that combines the antenna portion (20) and the cable portion (30). A detailed explanation regarding this will be provided later.

[0093] An antenna substrate (10A) according to an embodiment of the present invention may include a reference wiring layer (SW). A plurality of unit layers (100), including a first unit layer (200) and a second unit layer (300), may be stacked in at least one direction, either upward or downward, based on the reference wiring layer (SW). That is, the unit layers (100) stacked above the reference wiring layer (SW) may have an upward stacking direction (DR1), and the unit layers (100) stacked below the reference wiring layer (SW) may have a downward stacking direction (DR2).

[0094] The via (130) may have a width that widens as it goes in the stacking direction. Accordingly, unit layers (100) having an upward stacking direction (DR1) may include vias (130) that widen as they go upward, and unit layers (100) having a downward stacking direction (DR2) may include vias (130) that widen as they go downward. That is, the direction of width increase of the via (130) may correspond to the stacking direction (upward or downward).

[0095] The aforementioned features of the antenna substrate (10A) may be the result of the manufacturing method of the antenna substrate (10A). Accordingly, the manufacturing method of the antenna substrate (10A) according to an embodiment of the present invention will be described with reference to FIGS. 3 and FIGS. 4.

[0096] FIG. 3 is a diagram showing a flowchart of the manufacturing process of an antenna substrate (10A) according to an embodiment of the present invention and a cross-sectional view of the antenna substrate (10A) at each process, and FIG. 4 is a diagram showing step S110 of FIG. 3.

[0097] An antenna substrate (10A) according to an embodiment of the present invention can be manufactured by a Modified Semi-Additive Process (MSAP) process. The MSAP process is a technology used in semiconductor or antenna packaging and high-density PCB manufacturing, and is a process that improves the Semi-Additive Process (SAP) to enable the formation of finer patterns.

[0098] The MSAP process includes attaching a seed layer (SCu) on an insulating layer (110), applying a photoresist (PR: Photoresist, 160) on the seed layer (SCu) to form a pattern through an exposure and development process, forming wiring on the exposed seed layer (SCu) along the pattern formed by the photoresist (160) through electroplating, removing the photoresist (160) through a Dielectric Film Removal (DFR) process, and removing the seed layer (SCu) by etching.

[0099] At this time, the seed layer (SCu) serves to form a conductive layer so that current can flow evenly during the electroplating process. The seed layer (SCu) may include copper (Cu), chromium (Cr), titanium (Ti), titanium-tungsten (TiW), nickel (Ni), gold (Au), etc. For example, the seed layer (SCu) may be pure copper with a purity of 99.9%.

[0100] The seed layer (SCu) can be deposited on the insulating layer (110) by methods such as sputtering or chemical vapor deposition (CVD), but is not necessarily limited thereto. The thickness of the seed layer (SCu) deposited by sputtering can be controlled by changing the sputtering time, pressure, power, etc. Additionally, after depositing it thicker than the required thickness, the thickness (ds) of the seed layer (SCu) can be adjusted to an appropriate thickness for plating through etching.

[0101] The method for manufacturing an antenna substrate (10A) according to an embodiment of the present invention generally adopts the MSAP process method, but can attach a thin seed layer (SCu) using a carrier (150) to eliminate the seed layer (SCu) etching process.

[0102] In this case, the thickness (ds) of the seed layer (SCu) to be adhered may be about 1 μm to 3 μm, preferably 1.5 μm. Ultra-thin copper foil (5 μm or less) has a technical problem in that it is difficult to adhere to the insulating layer (110) due to its thin thickness. Accordingly, the antenna substrate (10A) of the present invention can adhere the seed layer (SCu) to the insulating layer (110) by using a carrier (150), which is a temporary support layer to facilitate the attachment of the ultra-thin copper foil to the insulating layer (110). The thickness (dc) of the carrier (150) may be 15 μm to 20 μm (about 18 μm). The step of adhering the seed layer (SCu) of FIGS. 3 and FIGS. 4 to the insulating layer (110), which will be described later, can be performed by pressing the carrier (150) with the seed layer (SCu) attached to the insulating layer (110) and removing the carrier (150). A roughness may be formed at the part where the seed layer (SCu) contacts the insulating layer (110) to improve adhesion, and the seed layer (SCu) and the carrier (150) may have a weak bonding force. Therefore, when the seed layer (SCu) is adhered to the insulating layer (110), only the carrier (150) can be easily separated without damaging the seed layer (SCu).

[0103] Before describing FIG. 3, the step S110 of forming the raw material is described with reference to FIG. 4. The raw material may refer to a structure in which a seed layer (SCu) is attached to both sides of an insulating layer (110), namely the upper and lower surfaces. Referring to FIG. 4, the insulating layer (110) and the seed layer (SCu) may be sequentially adhered to the upper and lower surfaces of a detach core (140) in which a seed layer (SCu) is disposed on both sides. The detach core (140) is a substrate that serves as a base for stable processing, and can be separated and removed after two to four unit layers ('unit layer (100)' refers not to the insulating layer (110) to which the seed layer (SCu) is attached, but to the state in which a wiring layer (120) and vias (130) are formed through steps S150 to S190 of FIG. 3) are stacked.

[0104] The detachment core (140) and the seed layer (SCu) placed on the detachment core (140) may have a weak bonding force, such as the carrier (150) and the seed layer (SCu) attached to the carrier (150). Therefore, when removing the detachment core (140), only the detachment core (140) can be removed without damaging the insulating layer (110) and the attached seed layer (SCu).

[0105] Meanwhile, the thickness (di) of the insulating layer (110) may be 45 μm to 55 μm (about 50 μm).

[0106] The adhesion of the unit layer (100) can proceed on the upper and lower surfaces of the detachment core (140), respectively, and simultaneously. Thus, two raw materials (A in FIG. 4) can be formed per detachment core (140). In this case, one of the two seed layers (SCu) of the raw material (A) can become a reference wiring layer (SW).

[0107] Returning to FIG. 3, the method for manufacturing the antenna substrate (10A) is described further by forming a photoresist (160) pattern on a seed layer (SCu) of the raw material (A) (S120), electroplating the empty space of the photoresist (160) pattern (S130), and then etching the DFR and the seed layer (SCu) (S140) to form a reference wiring layer (SW).

[0108] The reference wiring layer (SW) is used to distinguish the wiring layer (120) that serves as a reference for the direction in which the multiple unit layers (100) are stacked among the multiple wiring layers (120), and may have the same characteristics as the wiring layer (120) included in the multiple unit layers (100). Therefore, the following description regarding the structural characteristics of the reference wiring layer (SW) can be applied equally to other wiring layers (120).

[0109] Referring to FIG. 5, which illustrates an enlarged view of step B of S140, at least a portion of the reference wiring layer (SW) may be a seed layer (SCu) (hereinafter, the seed layer (SCu) that is etched to form wiring is referred to as the 'first electrode layer (E1)'), and the remaining portion may be an electrode layer plated by electroplating (hereinafter referred to as the 'second electrode layer (E2)'). The first electrode layer (E1) and the second electrode layer (E2) are formed by different processes, and since the grain size produced by electroplating is larger than the grain size produced by sputtering or chemical vapor phase processes, the second electrode layer (E2) may have a larger grain size than the first electrode layer (E1). Accordingly, the reference wiring layer (SW) may include the first electrode layer (E1) and the second electrode layer (E2) with different grain sizes. Additionally, the reference wiring layer (SW) may include a first boundary surface (B1) formed between the first electrode layer (E1) and the second electrode layer (E2).

[0110] Since the first electrode layer (E1) corresponds to the seed layer (SCu), it may be equal to or different from the thickness (ds) of the seed layer (SCu) within an error range. Accordingly, the thickness (d1) of the first electrode layer (E1) may be 1.5 μm to 3 μm. If the thickness (dw) of the reference wiring layer (SW) (the same applies to the wiring layer (120)) is too thin, the current capacity may be insufficient or the resistance may increase, leading to increased signal loss, and signal distortion or delay may occur, which may cause problems in high-speed signal transmission. In addition, if the thickness (dw) of the reference wiring layer (SW) is too thick, it hinders the flexibility, miniaturization, and slimming of the substrate and may cause signal reflection or distortion during high-frequency signal transmission. Therefore, it is desirable for the thickness (dw) of the reference wiring layer (SW) to be designed to an appropriate thickness. For example, the thickness (dw) of the reference wiring layer (SW) may be 2 μm to 15 μm. In this case, the thickness (d2) of the second electrode layer (E2) may be the thickness of the first electrode layer (E1) (d1) from the thickness (dw) of the reference wiring layer (SW). For example, it may be equal to or greater than the thickness (d1) of the first electrode layer (E1).

[0111] Since the second electrode layer (E2) is plated on the first electrode layer (E1), the first electrode layer (E1) can be placed between the second electrode layer (E2) and the insulating layer (110). For adhesion with the insulating layer (110), the first electrode layer (E1) may have a roughness (surface roughness) of a certain level or higher formed on the surface (S1) in contact with the insulating layer (110), and the side surface (S2) of the first electrode layer (E1) may have a roughness formed by etching. In this case, the roughness of the side surface (S2) of the first electrode layer (E1) may be lower than the roughness formed on the surface (S1) in contact with the insulating layer (110) of the first electrode layer (E1).

[0112] Immediately after the electroplating is completed (S130), the side and top surfaces of the second electrode layer (E2) may have a lower roughness compared to S1 of the first electrode layer. However, since the surface of the second electrode layer (E2) is also partially etched during the seed layer (SCu) etching process (S140), the side and top surface roughness of the second electrode layer (E2) in state B of FIG. 5 may be equal to or greater than the roughness of the side (S2) of the first electrode layer (E1). However, the side (S2) of the first electrode layer and the side and top surfaces of the second electrode layer may have a lower roughness than S1 of the first electrode layer (E1). As the roughness decreases, signal loss is reduced, precise impedance control is possible, plating uniformity is improved, wiring can be miniaturized, and power consumption can be reduced due to low surface resistance.

[0113] Referring again to FIG. 3, after S140, an insulating layer (110) with a seed layer (SCu) attached can be bonded onto a reference wiring layer (SW) (S150). In the drawing, the insulating layer (110) is indicated by a dotted or solid line to distinguish between multiple insulating layers (110), but since the insulating layer (110) is bonded by applying high pressure and temperature during the bonding process, the insulating layer (110) of the previously stacked unit layer (100) and the insulating layer (110) of the newly stacked unit layer (100) may not melt together to form a boundary surface.

[0114] Afterward, via holes (VH) can be processed from the outside toward the reference wiring layer (SW) (S160). In this case, the width of the via hole (VH) may become narrower as it progresses in the processing direction. The shape of the cross-section of the via hole (VH) perpendicular to the stacking direction may be circular or polygonal. The bottom surface of the via hole (VH) may be the wiring layer (120), and the side surface may be the cut surface of the seed layer (SCu) and the insulating layer (110). Accordingly, before forming the via (130), electroless plating may be performed to form a copper layer for electroplating (S170). The copper layer formed by electroless plating (hereinafter referred to as the 'third electrode layer (E3)') may be placed on the surface of the via hole (VH).

[0115] Referring to FIG. 6, which illustrates an enlarged view of step C of S170, the via hole (VH) can be formed by penetrating the seed layer (SCu) and the insulating layer (110), and the bottom surface of the via hole (VH) can be the reference wiring layer (SW). A third electrode layer (E3) can be deposited by chemical plating on the seed layer (SCu), the insulating layer (110), and the reference wiring layer (SW) exposed by the via hole (VH). The third electrode layer (E3) can form a second boundary surface (B2) with the second electrode layer (E2) of the reference wiring layer (SW), and the third electrode layer (E3) can form a third boundary surface (B3) with the first electrode layer (E1) (seed layer (SCu)). The second boundary surface (B2) and the third boundary surface (B3) can overlap with at least a portion of the surface of the via hole (VH).

[0116] The particle size of the third electrode layer (E3) produced by chemical plating may differ from the particle size of the second electrode layer (E2) produced by electroplating, and the particle size of the third electrode layer (E3) may be smaller than the particle size of the second electrode layer (E2).

[0117] Referring again to FIG. 3, after S170, a photoresist (160) pattern can be formed on the seed layer (SCu), and a pattern to become a via (130) and a wiring layer (120) can be formed through electroplating (S180). Subsequently, a wiring layer (120) can be formed through DFR and etching of the seed layer (SCu) (S190). Accordingly, the via (130) may include an electrode layer formed by chemical plating (hereinafter, 'third electrode layer (E3)') and an electrode layer formed by electroplating (second electrode layer (E2)). In addition, the wiring layer (120) may include a first electrode layer (E1) and a second electrode layer (E2), similar to the reference wiring layer (SW) described above.

[0118] Referring to FIG. 7, which illustrates an enlarged view of D in step S190, the via (130) may include a second electrode layer (E2) and a third electrode layer (E3), and the third electrode layer (E3) may be disposed between the second electrode layer (E2) and the insulating layer (110). As described above, the particle size of the second electrode layer (E2) may be larger than the particle size of the third electrode layer (E3), and the second electrode layer (E2) and the third electrode layer (E3) may form a second boundary surface (B2). Additionally, the via (130) may electrically connect the wiring layer (120) disposed in the stacking direction of the via (130) and the reference wiring layer (SW).

[0119] A wiring layer (120) disposed in the stacking direction of a via (130) may include a first electrode layer (E1) and a second electrode layer (E2), and may include a portion of a third electrode layer (E3) that was chemically plated on the surface of a via hole (VH). That is, the third electrode layer (E3) may be formed by extending into the wiring layer (120). Within the wiring layer (120), the third electrode layer (E3) may come into contact with the first electrode layer (E1) and the second electrode layer (E2), and the third electrode layer (E3) and the first electrode layer (E1) may form a third boundary surface (B3), and the third electrode layer (E3) and the second electrode layer (E2) may form a second boundary surface (B2). The first electrode layer (E1) and the second electrode layer (E2) may also come into contact to form a first boundary surface (B1).

[0120] The wiring layer (120) may ultimately include the first electrode layer (E1), the second electrode layer (E2), the third electrode layer (E3), the first interface (B1), the second interface (B2), and the third interface (B3). The second electrode layer (E2) may have a particle size larger than the particle size of the first electrode layer (E1) and the third electrode layer (E3).

[0121] The first electrode layer (E1) to the third electrode layer (E3) may include the same material. Accordingly, the wiring layer (120) and the via (130) may be formed from the same material. For example, the first electrode layer (E1) to the third electrode layer (E3) or the wiring layer (120) and the via (130) may be formed from pure copper. As the wiring layer (120) and the via (130) are formed from pure copper, the antenna substrate (10A) according to an embodiment of the present invention may have high electrical conductivity, excellent processability and ductility, and may have the advantage of reduced loss of high-frequency signals.

[0122] Since the second electrode layer (E2) is deposited through electroplating, the thickness (d2 or dw) of the second electrode layer (E2) or the wiring layer (120) can be controlled by adjusting the degree of plating. Thus, design freedom can be secured. In addition, since the pattern is formed by plating rather than by etching a thick seed layer (SCu), the cross-section of the wiring layer (120) can have a square shape. That is, it can become a rhombus shape, or the corners of the wiring layer (120) can form a vertical angle without being chamfered or rounded. If the side is not vertical or has a rounded edge, a step difference may occur when stacking the unit layer (100), making it impossible to form a precise pattern; however, since the present invention can form a more precise pattern, high-performance antenna circuits and cable circuits can be formed.

[0123] FIGS. 8a to 8c illustrate a top view of a transformer included in a cable circuit. The transformer can perform impedance matching, signal conversion, minimize power loss, optimize signal transmission characteristics, and remove common mode noise.

[0124] Referring to FIG. 8a, the gray area corresponds to a copper wiring layer (120) and the white area corresponds to an LCP insulating layer (110). In the drawing, TC indicates the capacitance area of ​​the transformer and TI indicates the inductance area. As the size of the space in the capacitance area (TC) and the line in the inductance area (TI) decreases—that is, as finer patterns are formed—the line length of the transformer can be minimized, and the design freedom of the transformer section can be increased. Therefore, the transformer section must be able to form a highly fine pattern compared to other wiring, and it is required to be designed so that the roughness of the wiring is minimized.

[0125] An antenna substrate (10A) according to an embodiment of the present invention can form a fine pattern while maintaining low roughness through a plating process, and since the wiring layer (120) has a rectangular cross-sectional structure, no step difference occurs, allowing for a more precise pattern design. Accordingly, it can include a transformer with superior performance.

[0126] FIG. 8b is a drawing showing a transformer of an antenna substrate (10A) manufactured according to an embodiment of the present invention, and FIG. 8c is a drawing showing a transformer of an antenna substrate (10A) manufactured according to a comparative example (a method used conventionally). In FIG. 8b, the dark gray part is the wiring layer (120) and the blue part is the insulating layer (110), and in FIG. 8c, the light flesh-colored part is the wiring layer (120) and the black part is the insulating layer (110).

[0127] Compared to the transformer shown in FIG. 8c, the edge of the wiring layer (120) of the transformer shown in FIG. 8b is more distinct, and it can be seen that the vertices of the rectangular shape of the capacitor region are not rounded. If the rectangular shape of the capacitor region is worn rounded as in the comparative example, it is difficult to calculate the capacitance, and a gap with the design may widen, making it difficult to achieve the intended effect. However, the transformer according to the embodiment of the present invention can solve these problems and have superior performance.

[0128] FIG. 9 is a diagram illustrating the stacking of a unit layer (100) in an upward and downward direction after step S190 of FIG. 3. An antenna substrate (10A) can be formed by repeating steps S150 to S190 in at least one of the upward and downward directions based on the reference wiring layer (SW) of D formed after step S190 (in FIG. 9, only step S150 is illustrated and steps S160 to S190 are omitted). At this time, the upward stacking process and the downward stacking process may proceed simultaneously or individually.

[0129] If the unit layer (100) positioned above the reference wiring layer (SW) is referred to as the upper unit layer (UL) and the unit layer (100) positioned below it is referred to as the lower unit layer (LL), then a plurality of upper unit layers (100) may have an upward stacking direction (DR1) and a plurality of lower unit layers (LL) may have a downward stacking direction (DR2). As one moves upward relative to the reference wiring layer (SW), the first upper unit layer (UL1), the second upper unit layer (UL2), and the third upper unit layer (UL3) may be stacked, and as one moves downward, the first lower unit layer (LL1), the second lower unit layer (LL2), and the third lower unit layer (LL3) may be stacked. The upper unit layer (UL) and the lower unit layer (LL) may be stacked simultaneously or alternately.

[0130] FIG. 10 is a drawing illustrating an example of an antenna substrate (10A) produced as a result of FIG. 9. Since the insulating layers (110) on both sides of the wiring layer (120) meet each other in the empty space of the wiring layer (120) where no pattern is formed and are bonded while partially melting, the boundary disappears, FIG. 10 shows the unit layers (100) (UL1 to UL3, LL1 to LL3) based on the wiring layer (120), unlike the previous drawings.

[0131] An antenna substrate (10A) may have an insulating layer (110) and a wiring layer (120) alternately arranged based on a reference wiring layer (SW), and vias (130) may be formed by penetrating the insulating layer (110) and electrically connecting the two wiring layers (120). Upper unit layers (UL1 to UL3) arranged above based on the reference wiring layer (SW) are stacked in an upward direction (DR1), and within each upper unit layer (UL), the wiring layer (120) may be arranged in an upward direction (DR1) of the insulating layer (110).

[0132] A plurality of unit layers (100) can be stacked such that the wiring layer (120) is positioned on the outside relative to the reference wiring layer (SW). That is, within each unit layer (100), the wiring layer (120) can be positioned in a stacking direction (upward direction (DR1) or downward direction (DR2)). A plurality of upper unit layers (100) may have an upward stacking direction (DR1), and a plurality of lower unit layers (LL) may have a downward stacking direction (DR2). Within the upper unit layer (UL), the wiring layer (120) can be positioned on the upward side (DR1) of the insulation layer (110), and within the lower unit layer (LL), the wiring layer (120) can be positioned on the downward side (DR2) of the insulation layer (110).

[0133] The via (130) can connect wiring layers (120) included in different unit layers (100) and may include an asymmetric via (410) having a via formation direction in which the width (VW1) widens as it goes toward the stacking direction, and a symmetric via (420) having a constant width (VW2). The symmetric via (420) can penetrate at least two unit layers (100) simultaneously (see FIG. 13).

[0134] The via hole (VH) of the asymmetric via (410) is formed on the outer side of the antenna substrate (10A) toward the reference wiring layer (SW), and thus can be formed so that the width (VW) becomes narrower as it approaches the reference wiring layer (SW). Alternatively, the asymmetric via (410) can be formed so that the width becomes wider as it approaches the stacking direction within each unit layer (100). In other words, the direction of the width increase of the asymmetric via (410) can correspond to the stacking direction (upward or downward direction). Accordingly, the asymmetric via (410) of the upper unit layer (UL) may include an upward asymmetric via (410, UV) having a width (VW) that becomes wider as it goes upward (DR1), and the asymmetric via (410) of the lower unit layer (LL) may include a downward asymmetric via (410, LV) having a width (VW) that becomes wider as it goes downward (DR2). In other words, the asymmetric via (410) of the upper unit layer (100) may have a via formation direction in which the width (VW) increases as it goes upward (DR1), and the asymmetric via (410) of the lower unit layer (LL) may have a via formation direction in which the width (VW) increases as it goes downward (DR2).

[0135] A reference wiring layer (SW) can be placed in the cable section (30). Referring to the enlarged view of FIG. 2, the upper unit layer (UL, Q) immediately above the reference wiring layer (SW) is included in the cable section (30), and the upper unit layer (UL, P) above it is included in the antenna section (20). In this case, the uppermost unit layer (Q) of the cable section (30) and the lowermost unit layer (P) of the antenna section (20) can both correspond to the upper unit layer (UL). Therefore, the asymmetric via (410) of the uppermost unit layer (Q) of the cable section (30) and the asymmetric via (410) of the lowermost unit layer (P) of the antenna section (20) can both be an upward asymmetric via (410, UV).

[0136] As described above, the antenna portion (20) and the cable portion (30) can be laminated using the same process (S150 to S190) with only the material of the insulating layer (110) being different. That is, the antenna substrate (10A) according to the embodiment of the present invention can be formed by laminating the second unit layer (300) of the cable portion (30) and then immediately laminating a plurality of first unit layers (200) of the antenna portion (20) in the same method (S150 to S190). Accordingly, as shown in FIG. 2 or FIG. 10, the plurality of first unit layers (200) and the plurality of second unit layers (300) may not include an adhesive member disposed between them to adhere the two unit layers (100), and may not include a coupling member (60) that combines the antenna portion (20) and the cable portion (30).

[0137] Liquid crystal polymer (LCP) is a thermoplastic material, so unlike prepreg, there was a problem in that it was difficult to process it multiple times. Therefore, to make a multilayer LCP substrate, multiple two-layer LCP substrates were formed and bonded using an adhesive material such as a bonding sheet, or multiple unit layers (100) were formed and stacked and then heat-pressed at once. In the former case, the electrical conductivity of the adhesive material is significantly lower than that of copper, and in the latter case, the vias (130) often contain materials other than pure copper, or have low electrical conductivity due to a large amount of pores and flux. However, the cable portion (30) according to the embodiment of the present invention can realize a three-layer or higher LCP substrate in which the vias (130) and wiring layer (120) are pure copper without an adhesive material, thereby resolving the aforementioned problem.

[0138] In addition, when combining a multilayer substrate including an insulating layer (110) of a different material, the combination is usually done through soldering. However, the present invention allows the insulating layer (110) of the cable section (30) and the insulating layer (110) of a different material to be directly laminated on the uppermost wiring layer (120) of the cable section (30) so that the antenna section (20) and the cable section (30) can be connected and combined without soldering. Accordingly, referring to FIG. 2, the first insulating layer (210) and the first via (230) of the lowest unit layer (P) of the antenna section (20) can be electrically connected by directly contacting the second wiring layer (320) of the uppermost unit layer (Q) of the cable section (30).

[0139] Thus, the antenna substrate (10A) according to the embodiment of the present invention can reduce the thickness of the entire substrate by joining substrates of different materials without a separate joining member, thereby making the antenna substrate (10A) slimmer and smaller, and can improve process efficiency by eliminating some processes such as soldering. In addition, the completeness of the product can be improved by eliminating uncertainty arising from module assembly by manufacturing two modules into one module. Furthermore, a vertical via (500) can be formed to connect a wiring layer (120) that is included within the different substrate and has three or more insulating layers (110) in between.

[0140] Hereinafter, a vertical via (500) of an antenna substrate (10A) according to an embodiment of the present invention will be described with reference to FIGS. 11 to 13. FIG. 11 is a drawing showing the case where there are 4 vias (an even number) forming the vertical via (500). FIG. 12 is a drawing showing the case where there are 5 vias (an odd number) forming the vertical via (500). FIG. 13 is a drawing showing the case where the vertical via (500) includes a symmetrical via (420) with a constant width.

[0141] A vertical via (500) refers to a via in which each via (510) included in three or more unit layers (100) that are stacked consecutively among a plurality of unit layers forming an antenna portion (20) and a cable portion (30) is vertically arranged within a certain range so that current can flow to a wiring layer (520) of a unit layer (100) that is not adjacent to each other.

[0142] A plurality of consecutive unit layers including vertical vias (500) may all be included in the antenna section (20) or the cable section (30), or some may be included in the antenna section (20) and the remaining portion in the cable section (30). That is, at least one vertical via (500) may be placed in at least one of the antenna section (20) and the cable section (30), and may include at least one vertical via (500) that penetrates the antenna section (20) and the cable section (30) simultaneously.

[0143] Additionally, each via (510) forming the vertical via (500) may have its center axis within a certain range so as to be arranged vertically.

[0144] Additionally, each via (510) and wiring layer (520) included in three or more consecutive unit layers (100) containing a vertical via (500) can be electrically connected to each other by coming into contact with each other for a certain portion or more. That is, the vertical via (500) refers to a long via in which the via (510) and wiring layer (520) included in each consecutive unit layer (100) are arranged in a vertical direction to electrically connect unit layers (100) that are separated from each other. Here, "vertical" means that the central axes (VA) of the multiple unit vias (510) do not completely overlap each other, but are located within a certain range so that current can flow in a vertical direction.

[0145] Hereinafter, in order to distinguish between the via (130) and the wiring layer (120) that do not form the vertical via (500), each via forming the vertical via (500) is referred to as a unit via (510), and the wiring layer (120) is referred to as a unit wiring layer (520).

[0146] A vertical via (500) may include a plurality of unit vias (510) included in each of three or more consecutive unit layers (100) and a plurality of unit wiring layers (520) disposed at both ends of the vertical via (500) between each of the plurality of unit vias (510). Accordingly, the number of the plurality of unit wiring layers (520) may be one more than the number of the plurality of unit vias (510).

[0147] Since the antenna section (20) and the cable section (30) are stacked in the z-axis direction, the antenna circuit and the cable circuit must also be electrically connected in the z-axis direction. Therefore, some of the multiple unit vias (510) may be located in the antenna section (20) and the remaining parts may be located in the cable section (30). However, this is not necessarily limited to this, and all of the multiple unit vias (510) may be included in either the cable section (30) or the antenna section (20).

[0148] All of the multiple unit vias (510) may be included in the antenna section (20) or the cable section (30). When the vertical via (500) connects the antenna circuit and the cable circuit, some of the multiple unit vias (510) may be included in the antenna section (20) and the remaining parts may be included in the cable section (30).

[0149] If at least a portion of the vertical via (500) is included in the cable portion (30), one of the plurality of unit wiring layers (520) may be a reference wiring layer (SW). In this case, among the plurality of unit vias (510), the unit via (510) placed above the reference wiring layer (SW) may be an upward asymmetric via (410, UV), and the unit via (510) placed below the reference wiring layer (SW) may be a downward asymmetric via (410, LV). Alternatively, the plurality of unit vias (510) may further include a symmetric via (420) that simultaneously penetrates two consecutive unit layers (100) and has a constant width (see FIG. 13).

[0150] To define a vertical via (500), one of the plurality of wiring layers (120) may be designated as the "center wiring layer (CW)" and the center axis of the center wiring layer (CW) may be set as the "reference center axis (CA)". In other words, the vertical via (500) may be defined as a set of multiple unit vias (510) whose center axes are within a certain range relative to the reference center axis (CA), which is the center axis of the center wiring layer (CW). At this time, the reference center axis (CA) is the center axis of the upper or lower surface of the center wiring layer (CW) and may be parallel to the z-axis.

[0151] The central wiring layer (CW) can be set as a unit wiring layer (520) located in the middle, center, or center among a plurality of unit vias (510) or a plurality of unit wiring layers (520) forming a vertical via (500).

[0152] For example, if the number of multiple unit vias (510) is even (see FIG. 11), the number of multiple unit wiring layers (520) will be odd, so the unit wiring layer (520) located in the center can become the center wiring layer (CW).

[0153] For example, when the number of multiple unit vias (510) is odd (see FIG. 12), each of the unit wiring layers (520) placed at both ends of the unit via (510) (or the unit layer (100)) located in the center can become a central wiring layer (CW1, CW2).

[0154] The setting criteria for the central wiring layer (CW) (or reference central axis (CA)) described above can be applied in the same way even when a symmetric via (420) is included as in FIG. 13. Although the symmetric via (420) penetrates two consecutive unit layers (100), it can be considered as a single via, and the central wiring layer (CW) can be determined according to the criteria described above. For example, since there are four unit vias (510), the unit wiring layer (520) located at the center among the five unit wiring layers (520) can become the central wiring layer (CW).

[0155] The central axis of the central wiring layer (CW) can be defined as the reference central axis (CA), and the central axis (VA) of each of the multiple unit vias (510) can be located within a certain range based on the reference central axis (CA). In the case where there are two central wiring layers (CW1, CW2) as shown in FIG. 12, the unit via (510) located above the unit via (510) located in the middle can be positioned based on the central axis (CA1) of the upper central wiring layer (CW1), and the unit via (510) located below can be positioned based on the central axis (CA2) of the lower central wiring layer (CW2).

[0156] Referring to the enlarged view of FIG. 11, the central axis of at least some of the unit vias (510) or the central axis of each of the multiple unit vias (510) may not overlap with the reference central axis (CA). However, for electrical connection in the vertical direction, the central axis (VA) of each of the multiple unit vias (510) may be located within a certain distance in the x-axis direction or y-axis direction from the reference central axis (CA). For example, the distance (M) between the central axis (VA) of the unit via (510) and the reference central axis (CA) may be 1 μm or more and less than or equal to a set length.

[0157] Here, the set length may be such that the upper surface (VS1) or lower surface (VS2) of the unit via (510) overlaps or contacts at least 30% in the vertical direction with either of the unit wiring layers (520) placed at both ends of the unit via (510). That is, the upper surface (VS1) of the unit via (510) may overlap at least 30% with the unit wiring layer (520) placed at the top, and the lower surface (VS2) of the unit via (510) may overlap at least 30% with the unit wiring layer (520) placed at the bottom. Here, the 30% overlap area is merely an example and is not necessarily limited thereto, and may be set within a range where signal transmission and current flow can occur smoothly.

[0158] An antenna substrate according to an embodiment of the present invention can achieve layer-by-layer alignment through a process of sequentially stacking an insulating layer and a wiring layer, compared to a process of bonding multiple layers at once, thereby enabling the implementation of a precision cable and forming a vertical via (500) that vertically connects three or more consecutive unit layers (100).

[0159] Meanwhile, regarding FIGS. 11 to 13, the reference center axis (CA) is illustrated and described as being set based on the center wiring layer (CW), but the present disclosure is not limited thereto. For example, the reference center axis (CA) can be set by designating one of the plurality of unit vias (510) as the “center via” and setting the center axis of the center via as the reference center axis (CA). In other words, the vertical via (500) can be defined as a set of a plurality of unit vias (510) whose center axis is within a certain range based on the reference center axis (CA), which is the center axis of the center via. In this case, the reference center axis (CA) is the center axis of the upper or lower surface of the center via and can be parallel to the z-axis. The center via can be set as the unit via (510) located in the middle, center, or center among the plurality of unit vias (510) forming the vertical via (500). These fine patterns and vertical vias (500) allow more circuits to be efficiently wired within an area, thereby increasing design flexibility and minimizing signal interference problems. Additionally, the vertical vias provide the shortest path for current, which can reduce power consumption and signal loss issues.

[0160] Although the above description has focused on exemplary embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

[0161] The modes for carrying out the invention have been sufficiently described in the aforementioned "best mode for carrying out the invention."

[0162] The embodiment can be used on an antenna substrate.

Claims

1. An antenna unit for transmitting and receiving external signals; and It includes a cable portion that supplies power to the antenna portion in conjunction with the antenna portion, and Each of the above antenna part and the above cable part is, It includes a plurality of stacked unit layers, and Each of the above plurality of unit layers is, Insulating layer; A wiring layer disposed on one side of the above insulating layer; and It includes vias that penetrate the insulating layer and connect wiring layers on both sides of the insulating layer, The insulating layer of the antenna portion comprises a first material, and the insulating layer of the cable portion comprises a second material different from the first material. The above via is, A first via with increasing width along a first direction; and A second via comprising a second via whose width increases along a second direction different from the first direction mentioned above, Antenna board.

2. In claim 1, the wiring layer is, including first and second electrode layers with different particle sizes, Antenna board.

3. In claim 2, the second electrode layer is, Particle size larger than that of the first electrode layer, Antenna board.

4. In claim 2, at least a portion of the via and the wiring layer is, The second electrode layer above; and A third electrode layer having a particle size different from the second electrode layer, Antenna board.

5. In claim 4, the third electrode layer is, particle size smaller than that of the second electrode layer above, Antenna board.

6. In claim 1, among the plurality of unit layers forming the antenna portion and the cable portion, three or more consecutive unit layers are, It further includes vertical vias formed by arranging unit vias included in each unit layer in a vertical direction, and At least some of the center axes of the above unit vias do not overlap with a preset reference center axis, Antenna board.

7. In claim 1, the insulating layer of the lowest unit layer of the antenna part is, abutting the wiring layer of the uppermost unit layer of the above cable section, Antenna board.

8. In claim 7, not comprising at least one of a coupling member that combines the antenna portion and the cable portion and an adhesive member between the plurality of unit layers of the cable portion. Antenna board.

9. In claim 1, the first material and the second material differ in at least one of ductility and dielectric constant, Antenna board.

10. An antenna unit for transmitting and receiving external signals; and It includes a cable portion that supplies power to the antenna portion in conjunction with the antenna portion, and Each of the above antenna part and the above cable part is, It includes a plurality of stacked unit layers, and Each of the above plurality of unit layers is, Insulating layer; A wiring layer disposed on one side of the above insulating layer; and It includes vias that penetrate the insulating layer and connect wiring layers on both sides of the insulating layer, The insulating layer of the antenna portion comprises a first material, and the insulating layer of the cable portion comprises a second material different from the first material. Among the plurality of unit layers forming the antenna portion and the cable portion, three or more consecutive unit layers further include vertical vias, The above vertical via is, A plurality of unit vias included in each of the three or more consecutive unit layers above; and It includes a plurality of unit wiring layers disposed between each of the plurality of unit vias and at both ends of the vertical vias, and The above plurality of unit vias are, A first asymmetric via that widens as it moves toward the first direction; and A second asymmetric via comprising a second asymmetric via that widens as it moves toward a second direction different from the first direction mentioned above. Antenna board.

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