Change-aware layout-versus-schematic (LVS) processes in electronic design automation (EDA)

Abstract

Systems and methods are presented in support of change-aware layout-versus-schematic (LVS) processes. A method may include steps of identifying a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design and performing a change-aware LVS process. Performing of the change-aware LVS process may include determining a common corresponding cell of the source circuit design and the layout circuit design, wherein the common corresponding cell comprises equivalent hierarchical cells that correspond between the source circuit design and the layout design, and wherein the equivalent hierarchical cells of the common corresponding cell include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells and performing a LVS process on circuit design portions included in the common corresponding cell.

Description

202418221CHANGE-AWARE LAYOUT-VERSUS-SCHEMATIC (LVS) PROCESSES IN ELECTRONIC DESIGN AUTOMATION (EDA)BACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modern society, from automobiles to microwaves to personal computers. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to, during, or after fabrication. EDA applications may implement various EDA procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports change-aware layout-versus-schematic (LVS) processes according to the present disclosure.

[0004] Figure 2 shows an example determination of a common corresponding cell in support of change-aware LVS processes according to the present disclosure.

[0005] Figure 3 shows another example determination of a common corresponding cell in support of change-aware LVS processes according to the present disclosure.

[0006] Figure 4 shows an example generation of a change-aware LVS output according to the present disclosure.

[0007] Figure 5 shows an example determination of an updated common corresponding cell according to the present disclosure.202418221

[0008] Figure 6 shows an example of logic that a system may implement to support change-aware LVS processes according to the present disclosure.

[0009] Figure 7 shows an example of a computing system that supports change-aware LVS processes according to the present disclosure.DETAILED DESCRIPTION

[0010] Electronic circuits, such as integrated circuits (ICs), are used in nearly every facet of modem society, from automobiles to microwaves to personal computers. The design, verification, and physical manufacture of circuit devices often involve several steps, sometimes referred to as a "design flow." The particular steps of a design flow are dependent upon various factors, such as the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator (e.g., foundry) that will manufacture the physical circuit. Typically, software and hardware tools can verify the circuit designs at various stages of the design flow, for example through complex rule checks, software-based simulations, hardware-based emulation, and various other techniques supported by modern EDA technology. These steps of a design flow aid in the discovery of errors in circuit designs, and allow design teams and engineers to correct or otherwise improve the designs prior to, during, or after physical manufacture.

[0011] Several steps are common to most design flows of IC design. Initially, the specification for a new circuit can be transformed into or otherwise generated as a logical design. Logical designs are sometimes referred to as a register transfer level (RTL) description of a circuit. With logical designs, a circuit can be described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high-speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed to confirm that the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as "functional verification."

[0012] After the accuracy of the logical design is confirmed through functional verification, a logical design can be converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, can describe the specific electronic devices (e.g., transistors, resistors, and202418221capacitors) that form the circuit design, along with the interconnections between these electronic devices. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. The relationships between the electronic devices are then analyzed to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as "formal verification." Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.

[0013] Once the electronic devices components and their interconnections are established, the design can again be transformed in a design flow. In particular, the next transformation may be to a physical design that describes specific geometric elements that form the circuit design. This type of physical version of a circuit design is often referred to as a "layout" design or “physical layout” (and may simply be referred to as a “layout”). The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to physically manufacture the circuit. Automated place and route tools can be used to define or generate the physical layouts, especially for wires that will be used to interconnect the circuit devices in the physical representation of the circuit design. Each layer of a circuit can have a corresponding layer representation in the layout design, and the geometric shapes described in a layer representation will define the relative locations of the circuit elements that will make up the circuit device (e.g., of transistors, resistors, capacitors, etc.). For example, shapes in the layer representation of a metal layer will define the locations of the metal wires used to connect the circuit devices.

[0014] Integrated circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional graphical IC layout data. Among other features, GDSII contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other layout formats include an open-source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Siemens EDA (formerly Mentor Graphics Corporation), and the Open Artwork System Interchange Standard (OASIS) format proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in IC layout designs that are employed to202418221manufacture integrated circuits. Once the circuit design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the device using a photolithographic process.

[0015] Typically, a designer will perform a number of verification processes on the layout design. For example, the layout design may be analyzed to confirm that it accurately represents the circuit devices and their relationships described in the device design. In this process, a layout-versus-schematic (LVS) tool can extract a netlist from the layout design and compare it with the netlist taken from the circuit schematic. LVS can be augmented by formal equivalence checking, which checks whether two circuits perform exactly the same function without demanding isomorphism.

[0016] The layout design also may be analyzed to confirm that it complies with various design requirements, such as minimum spacings between geometric elements and minimum linewidths of geometric elements. Such checks may be part of a design rule checking (DRC) process performed on layout design. DRC tools can take, as an input, a physical layout (e.g., in the GDSII or OASIS standard format) as well as a rule deck which specifies the specific rule checks to perform on the layout design. As checks in a DRC process can be specific to a particular circuit fabrication process, rule decks are typically provided by a foundry or circuit manufacturer specifying the particular rules that circuit designs must adhere to for circuit fabrication via the foundry (e.g., at a specified technology node or specific fabrication process parameters). Put another way, foundry-provided rule decks can include a list of rules specific to the semiconductor fabrication process employed by the foundry or otherwise selected for use in circuit manufacture. As such, a set of rules for a particular fabrication process can be referred to as a run-set, rule deck, or just a deck. An example format used for implementation of rule decks is the Standard Verification Rule Format (SVRF) by Siemens EDA (formerly Mentor Graphics Corporation).

[0017] There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive-type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific202418221areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.

[0018] Each time that a layer of material is exposed to radiation, a photomask (mask) must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a physical layout define the relative locations or areas of the circuit wafer that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the design layout, after which the mask can be used in a photolithographic process for fabrication of physical circuits. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. One of these techniques is optical proximity correction (OPC). OPC can be rule-based, model-based, or both. In rule-based OPC, the proximity effects are characterized, and specific solutions are devised for specific geometric configurations. The layout design is then searched using a DRC tool or a geometric-based software engine to find these geometric configurations. Once they are found, the specific solutions are applied. Through various steps of a design flow, the design, manufacture, and fabrication of circuits can be performed and supported through EDA technology.

[0019] While various steps of a design flow are described herein, circuit manufacture processes continue to evolve and may include any additional or alternative flow steps. Moreover, the intricacy of each step in a design flow is immense, especially as circuit designs continue to increase in complexity and as the transistors and other devices that form a circuit are merely a few atoms wide. As such, accurate and effective design flow steps may increase the efficiency of circuit design and improvements at any given step in the design flow can yield significant benefits.202418221

[0020] One aspect of the design flow that can benefit from improved efficiency and effectiveness is the LVS step. In LVS processes, IC design verification can involve comparing two versions of a circuit design to determine whether the compared circuits are equivalent. Often times, LVS involves the comparison of a physical layout with a circuit schematic, digital or logical circuit design (or another design form) in order to verify that the generated physical layout properly effectuates intended design behavior. In some examples, LVS circuit comparison processes can be used to perform layout-to-layout or schematic-to-schematic comparisons. Circuit designs are often represented as a hierarchical structure. In such hierarchical structures, circuit designs can be represented through hierarchical cells (or simply referred to as cells). A hierarchical cell may refer to any circuit design object that can be defined as well as used (e.g., referenced or placed) in the definition of an overall circuit design or in the definition of other cells in the circuit design. As such, the design of a given hierarchical cell may reference or contain instances of other cells, which may in turn reference or contain instances of other different cells, leading to a hierarchy of cells in an overall circuit design. Cells within a circuit design can be referenced any number of times, and each instance, use, or reference to a given cell in a circuit design can be referred to as a placement of the given cell.

[0021] For circuit design equivalence comparisons, one possibility is to compare the “flattened” version or each circuit in which every hierarchical cell instance in each of the compared circuit designs is replaced with the defined contents of the cell. Such a process may be referred to as a “flattening” because hierarchies and cells are replaced with the designed content and the entire circuit design is represented without any cells or hierarchies. However, with the continuously increasing complexities in modem circuit designs that can include billions of circuit elements, often more, the computational latency and resource requirements for such flattening operations to support direct circuit comparisons have become time-prohibitive and cost-prohibitive. Likewise, comparison processes for completely-flattened circuit designs can have incredibly high latencies, rendering LVS and other circuit comparison processes nearimpossible.

[0022] As another possibility for circuit design equivalence comparisons, hierarchybased circuit comparisons have been developed to improved speed and efficiency. In such hierarchy-based circuit comparisons, two different circuit designs are compared202418221on a cell-by-cell basis as specified according to the different hierarchies and cell placements present in the two compared designs. However, with such comparisons, including within an LVS context, the cell hierarchies of the two compared circuit designs typically do not match. This is the case when a one-to-one correspondence does not exist between each hierarchical cell in one compared circuit design to each hierarchical cell in the other compared circuit design. There may be some cell correspondences that exist, but at least some of the cells in one of the compared circuits do not correspond to any cells in the other compared circuit and vice versa. Thus, for any cells in a circuit design without a correspondence to a cell in the other compared circuit design, flattening must be performed in order to properly compare the two circuit designs. Corresponding cells between the layout and source circuit designs need not be flattened, and can be directly equated as equivalent based on specified correspondences. Thus, the greater the degree at which hierarchical cell correspondences are specified between two compared circuits, the less flattening operations need be performed and the greater the efficiency of circuit comparison processes.

[0023] As used herein, a corresponding cell, a cell correspondence, or a correspondence relationship between cells of circuit designs may refer to any form, representation, or description that specifies or otherwise represents an equivalence relationship between the cells. A corresponding cell may thus refer to cells from two circuit designs that are deemed equivalent to one another. In that regard, a corresponding cell may specify that a given cell in a source circuit design corresponds to a given cell in a layout circuit design. Corresponding cells, also referred to as corresponding hierarchical cells or hierarchical cell correspondences, may be specified through user input, determined through circuit analyses, or configured in any other suitable manner. One example form of corresponding cells may be “hcells” as used in Siemens EDA (formerly Mentor Graphics) technologies, such as the Calibre EDA tool. Corresponding cells of the present disclosure may implement, utilize, embody, or otherwise include any technical features of hcells or other forms of corresponding cells in modem EDA tools.

[0024] With the immense complexity of modem circuit designs, corresponding cells offer an efficient mechanism to specify equivalence relationships across entire hierarchical ranges, from low-level hierarchical cells to higher-level hierarchical cells,202418221and possibly even top-level cells. A given cell correspondence may be specified between two particular hierarchical cells of two circuit designs, and each of the particular hierarchical cells may be comprised of (e.g., reference, include instances of, etc.) multiple other cells of hierarchical level(s). Each of the referenced internal cells, which may be referred to as lower hierarchy cells, may include any number of cell ports (such as input ports, output ports, ground or power ports, etc.) A port cross-reference may specify how the ports of corresponding cells map to one another, which may include top-cell level ports, internal ports of referenced or placed lower-hierarchy cells, or combinations of both.

[0025] During circuit design flows, many design changes, modifications, or edits can be required. Verification of modified circuit designs, including LVS verifications, are required to ensure design modifications properly effectuate intended design scope and the changes do not violate design rule or verification requirements. As design edits may be made to address errors detected by baseline LVS processes, to effectuate functionality changes, or for any other purpose or scope, subsequent verification of modified circuit designs may be necessary for each modification made to circuit designs. During iterative circuit design flows, modifications to circuit designs may be numerous and vary in scope, from pinpoint changes to large-scale circuit adaptations. However, conventional LVS systems may require performance of a full-chip LVS verification to properly verify any circuit change, even for small-scale or targeted circuit modifications. Re-run of a full LVS process for each individual modification to circuit designs can be costly and time-prohibitive. However, without LVS circuit verifications, circuit designers may be unsure whether implemented changes result in functional circuit layouts. Thus, for conventional LVS technologies, modifications made to a schematic or layout circuit design after performance of a baseline LVS process may require running another full-chip LVS process for proper circuit verification, which may be cost-prohibitive and cause circuit design delays.

[0026] The disclosure herein may provide systems, methods, devices, and logic for change-aware LVS processes. The various technical features presented herein may be collectively referred to as change-aware LVS technology, and the disclosure herein may support performance of a LVS process on a selected circuit portions of a circuit designs while re-using LVS results from a baseline LVS process. In contrast to conventional limitations that require full-chip LVS processes even for small-scale202418221changes, the change-aware LVS technology of the present disclosure may instead focus performance of a LVS process on a selected sub-portion of circuit designs specifically impacted by circuit modifications, and re-use outputs from the baseline LVS process for other circuit portions not impacted by the modifications.

[0027] Thus, the change-aware LVS technology described herein need not perform a full LVS process on an entire chip, and change-aware LVS processes may limit LVS circuit comparisons to focus on modified areas. The change-aware LVS technology presented herein may do so while maintaining accuracy requirements based on port cross-references and erroneous cells detected during baseline LVS runs. Through such change-aware LVS features as described herein, the cost and time required to perform LVS verifications can be reduced, oftentimes significantly (especially for smaller scale changes). Accordingly, the change-aware LVS technology presented herein may provide tangible technical improvements to EDA computing systems as compared to conventional techniques, e.g., in the form of increased computing efficiency, reduced resource consumption, and reduced LVS process latencies. Such technical benefits may be possible while maintaining LVS verification accuracy, thus yielding direct technical effects on EDA computing systems.

[0028] These and other aspects of the change-aware LVS technology according to the present disclosure and the technical benefits of such are described in greater detail herein.

[0029] Figure 1 shows an example of a computing system that supports change-aware LVS processes according to the present disclosure. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the change-aware LVS technology described herein.

[0030] As an example implementation to support any combination of the change-aware LVS technology described herein, the computing system 100 shown in Figure 1 includes a change-aware LVS engine 110. The computing system 100 may implement the change-aware LVS engine 110 (including components thereof) in202418221various ways, for example as hardware and programming. The programming for the change-aware LVS engine 110 may take the form of processor-executable instructions stored on a non-transitory machine-readable storage medium and the hardware for the change-aware LVS engine 110 may include a processor to execute those instructions. A processor may take the form of single processor or multi-processor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0031] In operation, the change-aware LVS engine 110 may identify a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design, such as the source circuit design 120 and the layout circuit design 130 of Figure 1. The modifications made to the source circuit design 120 and the layout circuit design 130 may have been made after performance of a baseline LVS process between the source circuit design 120 and the layout circuit design 130. As used herein, a source circuit design and layout circuit design may refer to any two different circuit designs that can be compared. As such, the source circuit design 120 and the layout circuit design 130 may be of any format, representation, or produced as part of any step of an EDA design flow. In the LVS context, the source circuit design 120 may take the form of a device schematic or any data representation generated thereof (e.g., an extracted netlist, a graph representation of the cell hierarchy, etc.) and the layout circuit design 130 may take the form of a physical layout or any data representation generated thereof (e.g., an extracted netlist, a graph representation of the cell hierarchy, etc.). The change-aware LVS engine 110 may access the source circuit design 120 and the layout circuit design 130 in any suitable manner, e.g., loading the circuit designs from memory, receiving the circuit designs across a communication network, through user-selection or input designs, etc. In modern EDA contexts, the source circuit design 120 and the layout circuit design 130 may be represented as multi-tier graphs in support of hierarchical circuit comparisons.

[0032] In operation, the change-aware LVS engine 110 may also perform a change-aware LVS process for the source circuit design and the layout circuit design, including by determining a common corresponding cell of the source circuit design and the layout circuit design, wherein the common corresponding cell comprises equivalent hierarchical cells that correspond between the source circuit design and the layout202418221design, and wherein the equivalent hierarchical cells of the common corresponding cell include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells and performing a LVS process on circuit design portions included in the common corresponding cell. In operation, the change-aware LVS engine 110 may further perform the change-aware LVS process by re-using results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell.

[0033] Accordingly, the change-aware LVS technology of the present disclosure may support determination of common corresponding cells, which may be sub-portions of the overall source and layout circuit designs. Change-aware LVS processes can be provided through performance of a LVS process on circuit sections of the common corresponding cell while re-using baseline LVS results from circuit portions outside of the common corresponding cell. By doing so, the change-aware LVS technology described herein may perform circuit comparisons or other LVS verification processes with increased efficiency and reduced computational strain, and may thus improve EDA design turnarounds. These and other technical details, effects, and advantages of the change-aware LVS technology of the present disclosure are described in greater detail next.

[0034] Figure 2 shows an example determination of a common corresponding cell in support of change-aware LVS processes according to the present disclosure. The example of Figure 2 is described using the change-aware LVS engine 110 as an example implementation, and the change-aware LVS engine 110 may determine a common corresponding cell in support of a change-aware LVS process for the source circuit design 120 and layout circuit design 130. Change-aware LVS processes may reference a baseline LVS process (e.g., for result re-uses, to verify accuracy, and in determination of common corresponding cells). As used herein, a baseline LVS process may include any LVS process from that serves as a baseline reference from which a subsequent change-aware LVS process is performed. A baseline LVS process may thus be any suitable LVS process that produces a circuit comparison output. In the example of Figure 2, a baseline LVS process may be performed for the source circuit design 120 and the layout circuit design 130, whether by the change-aware LVS engine 110 or through other processing logic, EDA systems, or circuit verification tool.202418221

[0035] In some implementations, the baseline LVS process may be a full-chip LVS circuit comparison performed between the source circuit design 120 and the layout circuit design 130. The change-aware LVS engine 110 may itself perform a full-chip LVS process as the baseline LVS process and obtain a baseline LVS output accordingly. The change-aware LVS engine 110 may implement, support, or perform any conventional LVS process through which the change-aware LVS engine 110 may perform a baseline LVS process. However, the baseline LVS process need not be a full-chip LVS process. For example, the change-aware LVS engine 110 may perform the baseline LVS process in the form of a change-aware LVS process, e.g., according to any of the various techniques described herein. Such a change-aware baseline LVS process may serve as a baseline reference for a subsequent change-aware LVS process.

[0036] After performance of a baseline LVS process, any number of modifications may be made to the source circuit design 120, the layout circuit design 130, or a combination of both. Design edits may be made to address errors detected by the baseline LVS process, to effectuate functionality changes, or for any other purpose or scope. During iterative circuit design flows, modifications to circuit designs may be numerous and vary in scope, from pinpoint changes to large-scale circuit adaptations. As noted herein, conventional LVS limitations to re-run a full-chip LVS process for individual modifications to circuit designs can be costly and time-prohibitive. However, without LVS circuit verifications, circuit designers may be unsure whether implemented changes result in functional or appropriate circuit layouts. For conventional LVS technologies, modifications made to the source circuit design 120 and the layout circuit design 130 after performance of the baseline LVS process may require running another full-chip LVS process for proper circuit verification.

[0037] In contrast to conventional limitations, the change-aware LVS technology of the present disclosure may instead focus performance of a LVS process on a selected subset of the source and layout circuit designs, and re-use outputs from the baseline LVS process for other circuit portions not impacted by the modifications made to the circuit designs after performance of the baseline LVS process. In support of such change-aware LVS processes, the change-aware LVS engine 110 may identify a set of modified corresponding cells 210. The set of modified corresponding cells 210 may include any corresponding cell that has been changed in the source circuit design 120202418221or layout circuit design 130 by design modifications made since performance of the baseline LVS process.

[0038] Modifications to the source circuit design 120, the layout circuit design 130, or both may be captured, specified, or otherwise represented through the set of modified corresponding cells 210. Note that since a corresponding cell may specify an equivalence between a given cell (or given cells) of the source circuit design 120 and a given cell (or given cells) of the layout circuit design 130, a modification to any individual cell of the equivalence may result in a change to the applicable corresponding cell. The set of modified corresponding cells 210 accessed by the change-aware LVS engine 110 need not specify the actual design changes made to any of the equivalent cells of a corresponding cell. In some implementations, the set of modified corresponding cells 210 may simply indicate that a given corresponding cell has changed from a baseline version of the given corresponding cell that was used in the baseline LVS process. Thus, the set of modified corresponding cells 210 may take the form of a listing of specific corresponding cells for the source and circuit layout designs that have been modified from their baseline versions.

[0039] In some implementations, the change-aware LVS engine 110 may receive the set of modified corresponding cells 210 as a user-input. In such implementations, a circuit designer may flag any modifications by identifying and including any edited cells in a listing that forms the set of modified corresponding cells 210. Additionally or alternatively, the change-aware LVS engine 110 may itself detect modifications made to the source circuit design 120 or the layout circuit design 130, e.g., by performing difference comparisons from modified circuit designs against baseline versions, through change log parsing, or in any other suitable manner. Detected modifications may be identified, correlated to the applicable corresponding cell in which the change(s) were made, and compiled together to form the set of modified corresponding cells 210. Any suitable manner by which cell correspondence modifications to the source circuit design 120 or layout circuit design 130 made from baseline circuit versions can be detected, tracked, or represented are contemplated herein and supported (e.g., can be implemented) by the change-aware LVS engine 110.

[0040] Through the set of modified corresponding cells 210, the change-aware LVS engine 110 may determine a common corresponding cell. In doing so, the change-202418221aware LVS engine 110 may identify a corresponding cell within the source and layout circuit designs that encapsulates the circuit modifications represented through the set of modified corresponding cells 210. As hierarchical circuit designs may include several hierarchy levels, and modified corresponding cells may be located in varying hierarchy levels, determination of a common corresponding cell may involve parsing through different hierarchy levels of the circuit designs to identify a single corresponding cell that includes (e.g., encapsulates or references) each modified corresponding cell in the set of modified corresponding cells 210.

[0041] To illustrate through Figure 2, an example cell design hierarchy is illustrated in which various corresponding cells are depicted. In the example of Figure 2, each hierarchical corresponding cell is illustrated as a rectangle, and any corresponding cell located with the borders of another corresponding cell is included (e.g., placed or referenced) with the other corresponding cell. The top cell represents the overall circuit design and thus includes (e.g., references) all other corresponding cells of the circuit designs. Note that even though the source circuit design 120 and layout circuit design 130 are distinct circuit designs, the illustrated cell design hierarchy is shown as a single cell hierarchy since each individual corresponding cell represents an equivalence between the source circuit design 120 and the layout circuit design 130. Thus, the example cell design hierarchy is a shared hierarchical representation of the source circuit design 120 and the layout circuit design 130.

[0042] Various corresponding cells are illustrated in Figure 2, including corresponding cells labeled with subscript identifiers A-J. In the cell design hierarchy of Figure 2, corresponding cellp directly includes corresponding celln, corresponding celli, and corresponding cellj. Corresponding cello directly includes corresponding cello and corresponding cellp, and thus indirectly includes corresponding celln, corresponding celli, and corresponding cellj through inclusion of corresponding cellp. Corresponding cellc directly includes corresponding cellE and corresponding cello, and thus indirectly includes all of the corresponding cells included within corresponding cello, and so forth. Through such an illustrative hierarchical circuit design example, determination of common corresponding cells can be visually illustrated and understood.

[0043] In the particular example of Figure 2, the set of modified corresponding cells 210 may specify that corresponding celln and corresponding celli have been modified202418221from a baseline version. Accordingly, the change-aware LVS engine 110 may determine a common corresponding cell from the source and layout circuit designs that includes each of the modified corresponding cells, namely that includes corresponding celln and corresponding celli. In the example of Figure 2, the change-aware LVS engine 110 determines corresponding cellp as the common corresponding cell 220 based on the set of modified corresponding cells 210. This may be the case since corresponding cellp comprises equivalent hierarchical cells that correspond between the source circuit design 120 and the layout design 130, and the equivalent hierarchical cells of the common corresponding cell 220 include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells 210 (corresponding celln and corresponding celli in this example).

[0044] In the particular example of Figure 2, the common corresponding cell 220 directly includes the entire set of modified corresponding cells 210. This may be the case as of corresponding cellp (determined as the common corresponding cell 220) directly includes corresponding celln and corresponding celli. It may be the case that a common corresponding cell indirectly includes some (or all) of the modified corresponding cells specified in the set of modified corresponding cells 210. Note that multiple corresponding cells in a cell hierarchy or circuit designs may include the set of modified corresponding cells 210. This may be seen in Figure 2 as any corresponding cell that directly or indirectly includes corresponding cellp also includes (indirectly) corresponding celln and corresponding celli that form the set of modified corresponding cells 210. Thus, corresponding cello and corresponding cellc could also be candidates for selection as a common corresponding cell for the set of modified corresponding cells 210. As the top cell always includes the set of modified corresponding cells 210, it may be understood that the top cell is likewise always a potential common corresponding cell for any modifications made to the source and layout circuit designs.

[0045] In some implementations, the change-aware LVS engine 110 may determines, as a common corresponding cell, a corresponding cell in a lowest hierarchical level that includes all of the set of modified corresponding cells 210. By determining the corresponding cell with the lowest hierarchical level, the change-aware LVS engine 110 may reduce (e.g., minimize) the size footprint of the common corresponding cell, such that a smaller portion of the circuit design is represented202418221through the common corresponding cell and re-use of the output of a baseline LVS process can be applied for a greater portion of the circuit design outside the common corresponding cell. Determined common corresponding cells with a lowest hierarchical level amongst candidate common corresponding cells may also be referred to as a minimal common corresponding cell.

[0046] The change-aware LVS engine 110 may employ, implement, or support any suitable algorithm, technique, or process by which to determine a common corresponding cell for source and circuit designs based on a set of modified corresponding cells. In some implementations, the change-aware LVS engine 110 may apply a top-down approach. In such an implementation, an iterative process may be performed in which corresponding cells are processed from a highest hierarchy level of a circuit design downward until a common corresponding cell is selected. Starting at a top-level cell (which will always be a common corresponding cell candidate), the change-aware LVS engine 110 may go down one hierarchy level and determine if a particular corresponding cell of this lower hierarchy level includes each of the modified corresponding cells of the set of corresponding cells 210. If so, the change-aware LVS engine 110 may continue down hierarchy levels until no corresponding cell of a given hierarchy level includes each of the modified corresponding cells of the set of corresponding cells 210, which thus specifies an end condition of this iterative process. The corresponding cell including the modified corresponding cells in the hierarchy level prior to reaching this end condition is then determined by the change-aware LVS engine 110 as the minimal common corresponding cell.

[0047] Such an iterative top-down determination process can be illustrated through the cell design hierarchy of Figure 2. In Figure 2, the change-aware LVS engine 110 may start with the top cell, go down a hierarchy level, and determine that corresponding cellc includes the set of modified corresponding cells 210 (namely corresponding celln and corresponding celli). Then, the change-aware LVS engine 110 may go down a hierarchy level and evaluate corresponding cello and corresponding cellE included within corresponding cellc. In doing so, the change-aware LVS engine 110 may determine that corresponding cello includes the set of modified corresponding cells 210. Then, the change-aware LVS engine 110 may go down a hierarchy level and evaluate corresponding cellp and corresponding cellc202418221included within corresponding cello. In doing so, the change-aware LVS engine 110 may determine that corresponding cellp includes the set of modified corresponding cells 210. Then, the change-aware LVS engine 110 may go down a hierarchy level and evaluate corresponding celln, corresponding celh, and corresponding cellj included within corresponding cellp. The change-aware LVS engine 110 may detect an end condition has been reached upon evaluating one or more of the modified corresponding cells in this top-down iterative approach. This may be the case since a modified corresponding cell cannot include itself and thus cannot include the entire set of modified corresponding cells 210. In this example, the change-aware LVS engine 110 may thus determine corresponding cellp as the common corresponding cell 220 (e.g., as the minimal common corresponding cell for the set of modified corresponding cells 210).

[0048] As another implementation example, the change-aware LVS engine 110 may employ a bottom-up comparison approach to determine a common corresponding cell (e.g., a minimal common corresponding cell). In such examples, the change-aware LVS engine 110 may start with the hierarchy level of each individual modified corresponding cell, and go up hierarchy levels for corresponding cells that include the individual modified corresponding cell. An ending condition may be reached when a hierarchy level specifies the same corresponding cell for each individual modified corresponding cell. To illustrate through Figure 2, the change-aware LVS engine 110 may start with corresponding and corresponding cel in this approach and go up a hierarchy level. The change-aware LVS engine 110 may determine that, in this incrementally higher hierarchy level, corresponding celln is included within corresponding cellp. For this next highest hierarchy level, the change-aware LVS engine 110 may determine that corresponding celh is included within corresponding cellp. Since the corresponding cell that includes both corresponding celln and corresponding celh is the same, the change-aware LVS engine 110 may determine that an end condition has been reached, and that corresponding cellp is a minimal common corresponding cell for the set of modified corresponding cells 210.

[0049] While some examples of common corresponding determination are presented herein, any additional, alternative, or suitable process is contemplated herein and can be implemented by the change-aware LVS engine 110. In any of the ways described202418221herein, the change-aware LVS engine 110 may determine a common corresponding cell.

[0050] In Figure 2, the change-aware LVS engine 110 may determine the common corresponding cell 220 based on modifications made to a source circuit design or a layout circuit design, e.g., based on the set of modified corresponding cells 210. The example of Figure 2 may be applicable when an output of a baseline LVS process is “clean”, e.g., no LVS errors were detected (e.g., no inconsistencies between the layout and schematic circuit designs). For baseline LVS processes that produced a “dirty” output in which one or more errors were detected, the change-aware LVS engine 110 may account for such errors in determination of a common corresponding cell. Example features by which the change-aware LVS engine 110 may account for the errors in a baseline LVS output are described next with reference to Figure 3.

[0051] Figure 3 shows another example determination of a common corresponding cell in support of change-aware LVS processes according to the present disclosure. In the example of Figure 3, the change-aware LVS engine 110 may access the output of a baseline LVS process, shown as the baseline LVS output 310 of Figure 3. The baseline LVS output 310 may include any relevant data related to a baseline LVS process, such as an overall LVS result indicator for the process (e.g., LVS “clean” or “dirty”), whether any errors (e.g., inconsistent cells) were detected, the specific corresponding cells for which LVS errors (e.g., inconsistency) were detected, etc. In the example of Figure 3, the baseline LVS output 310 may indicate that corresponding cello produced an inconsistency in the LVS circuit comparison, and thus an error was detected for corresponding cello. The change-aware LVS engine 110 also identifies a set of modified corresponding cells 210 in Figure 3, which (as with Figure 2) specifies corresponding celln and corresponding celli as modified from their baseline versions.

[0052] The change-aware LVS engine 110 may determine a common corresponding cell for source and layout circuit designs based on the baseline LVS output 310 and the set of modified corresponding cells 210. In particular, when the baseline LVS output 310 indicates a LVS “dirty” with detected errors in the baseline LVS process, the change-aware LVS engine 110 may determine a common corresponding cell as a corresponding cell in a lowest hierarchical level that includes (i) all of the set of modified corresponding cells and (ii) all placements of erroneous cells detected from the circuit comparison in the baseline LVS process between the source circuit design202418221and the layout circuit design. This may be the determination criteria that the change-aware LVS engine 110 applies to determine a minimal common corresponding cell, particularly when a baseline LVS output specifies erroneous corresponding cells.

[0053] An example of such a determination is shown in Figure 3 in which the change-aware LVS engine 110 determines corresponding cellc as the common corresponding cell 320 for a change-aware LVS process. In the example of Figure 3, corresponding cellc includes each modified corresponding cell in the set of modified corresponding cells 210 (in this example, corresponding celln and corresponding celli) as well as each erroneous cell specified in the baseline LVS output 310 (in this example, corresponding cellc). The change-aware LVS engine 110 may determine corresponding cello as the common corresponding cell 320 in any consistent manner as described herein, including through iterative top-down or bottom-up approaches or other determination algorithms. In the example of Figure 3, the change-aware LVS engine 110 may account for any erroneous cells as well as modified cell correspondences in common corresponding cell determinations. Thus, any corresponding cell identified as modified (through the set of modified corresponding cells) or erroneous (through the baseline LVS output 310) may be processed through a common corresponding cell selection algorithm employed by the change-aware LVS engine 110, including any top-down or bottom-up iterative processes, including those as described herein.

[0054] As seen in Figures 2 and 3, the change-aware LVS engine 110 may determine a common corresponding cell differently based on whether the output of a baseline LVS process detected any errors or not (e.g., whether the baseline LVS process was “clean” or “dirty”). As used herein, “different” determinations may include (but are not limited to) to any difference in how a common corresponding cell is determined, any difference in which corresponding cells are accounted for in such determinations, or any difference in the selected common corresponding cell. When the baseline LVS process does not detect any errors in a circuit comparison between a source circuit design and a layout circuit design, the change-aware LVS engine 110 may determine the common corresponding cell as a corresponding cell in a lowest hierarchical level that includes all of the set of modified corresponding cells. This may be the case as no erroneous cells are included in the circuit cells for a LVS “clean” output. When the baseline LVS process does detect errors in a circuit comparison between the source202418221circuit design and the layout circuit design, the change-aware LVS engine 110 may determine a common corresponding cell as a corresponding cell in a lowest hierarchical level that includes all of the set of modified corresponding cells, and all placements of erroneous cells detected from the circuit comparison in the baseline LVS process between the source circuit design and the layout circuit design.

[0055] As described herein, the change-aware LVS engine 110 may determine a common corresponding cell in various ways. Through a determined common corresponding cell, the change-aware LVS engine 110 may generate an output for a change-aware LVS process. Example features of such a generation are described next with reference to Figure 4.

[0056] Figure 4 shows an example generation of a change-aware LVS output according to the present disclosure. In the example of Figure 4, the change-aware LVS engine 110 determines corresponding cello as a common corresponding cell 410 (e.g., in a consistent manner as common corresponding cell 320 of Figure 3). Through a common corresponding cell, the change-aware LVS engine 110 may generate an output for a change-aware LVS process, part of which is through performance of a LVS process on circuit sections of the common corresponding cell 410 and part which is through re-use of an output of a baseline LVS process.

[0057] In particular, the change-aware LVS engine 110 may perform a change-aware LVS process by performing a LVS process on circuit design portions included in the common corresponding cell 410 and re-using results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell 410. This can be seen in the example of Figure 4, as the circuit design portions outside of the common corresponding cell 410 are shaded in a diagonal pattern. In this example change-aware LVS process, the change-aware LVS engine 110 need not perform a LVS circuit comparison for the diagonally-patterned circuit sections outside of the common corresponding cell 410. Instead, the change-aware LVS engine 110 may re-use the baseline LVS output for these portions of the circuit designs. Such output re-use may reduce time, resources, and costs for performing LVS processes, as entire circuit sections need not be re-assessed through LVS circuit comparisons. Thus, the change-aware LVS engine 110 may perform a change-aware LVS process to generate a change-aware LVS output 420 such that202418221results from a baseline LVS process are re-used for circuit portions outside of the common corresponding cell 410.

[0058] In some implementations, the change-aware LVS engine 110 may re-use the baseline LVS output for some circuit sections within the common corresponding cell 410. For example, the change-aware LVS engine 110 may identify unmodified correct corresponding cells located within the common corresponding cell 410. An unmodified correct corresponding cell may be a corresponding cell that (i) did not produce any errors in the baseline LVS process and (ii) was not modified by the modifications of the source circuit design or the layout circuit design. In the example of Figure 4, the change-aware LVS engine 110 may determine that corresponding cel I j satisfies such criterion, and thus determine corresponding cellj as an unmodified corresponding cell. Note that corresponding celk, corresponding cells, and correspondingE also satisfy the criteria to be determined as unmodified correct corresponding cells, which the change-aware LVS engine 110 may determine. However, the change-aware LVS engine 110 need not assess corresponding cells not included within (e.g., outside of / not referenced within) the common corresponding cell 410.

[0059] In performing the change-aware LVS process, the change-aware LVS engine 110 may exclude any unmodified correct corresponding cells from the circuit design portions included in the common corresponding cell that the LVS process is performed on. Thus, in Figure 4, corresponding cellj is shaded in a diagonal pattern, and the change-aware LVS engine 110 may re-use results of the baseline LVS process for any unmodified correct corresponding cell (in this case, corresponding cellj) included within the common corresponding cell 410. Modem LVS processes may include syntax, functionality, or other features by which certain corresponding cells or circuit portions can be expressly excluded from a LVS process. The “LVS Box” feature of the Siemens EDA’s Calibre tool or other EDA tools is one example of such a technical feature to exclude “boxed” circuit sections from a LVS process. The change-aware LVS engine 110 may employ or utilize any such technique or feature by which to exclude unmodified correct corresponding cells from LVS process performance.

[0060] The change-aware LVS engine 110 may thus perform a LVS process on circuit design portions included in the common corresponding cell 410, including by setting the common corresponding cell 410 as a top cell for the LVS process. As noted202418221above, the circuit design portions upon which the LVS process is performed may exclude any determined unmodified correct corresponding cells. Thus, a change-aware LVS process may perform a LVS process on only a subset of an overall circuit design, with various other circuit portions excluded and processed through baseline LVS output re-uses. As seen in Figure 4, the change-aware LVS engine 110 may reuse the results of a baseline LVS process for any of the diagonally-patterned sections of the circuit designs, including outside of the common corresponding cell 410 and some sections within as well. The non-shaded portions of the common corresponding cell 410 may be the circuit sections for which the change-aware LVS engine 110 performs an LVS process to generate the change-aware LVS output 420. As seen in Figure 4, the non-patterned portions are only a selected subset of the overall circuit design, the change-aware LVS engine 110 may generate the change-aware LVS output 420 with increased efficiency and reduced resource consumption as compared to conventional LVS techniques that would require a full-chip LVS process. Thus, the change-aware LVS technology described herein can provide significant resource savings, reduced design latencies, and provide tangible technical effects and improvements to modem EDA systems.

[0061] As described herein, determined common corresponding cells may be provide a mechanism by which change-aware LVS processes can limit performance of LVS circuit comparisons to a selected subset of a circuit design and re-use baseline LVS results for other circuit portions outside (and at times, within) the common corresponding cell. In some implementations, the change-aware LVS engine 110 may account for other factors in determination of a common corresponding cell, such as port cross-references and top-level changes from a change-aware LVS process. In such scenarios (and more), the change-aware LVS engine 110 may determine an updated common corresponding cell, e.g., of a higher hierarchy level than a minimal common corresponding cell that includes all of the modified cell correspondences and / or erroneous cells. Example features of updated common correspondence cell determinations are described next with reference to Figure 5.

[0062] Figure 5 shows an example determination of an updated common corresponding cell according to the present disclosure. In some examples, the change-aware LVS engine 110 may update the common corresponding cell based on a change-aware LVS output, such as the change-aware LVS output 420 generated in202418221Figure 4. Updates to a common corresponding cell that the change-aware LVS engine 110 may make include selection of a different (e.g., higher hierarchy level) common corresponding cell, re-inclusion of unmodified correct corresponding cells into a LVS process, or a combination of both. The change-aware LVS engine 110 may make updates to a common corresponding cell, and then re-perform a LVS process on the updated common corresponding cell, as explained herein.

[0063] To further illustrate, the change-aware LVS engine 110 may make updates to a common corresponding cell based on the output of a change-aware LVS process. In Figure 5, the change-aware LVS engine 110 updates a common corresponding cell based on the change-aware LVS output 420 of Figure 5. In particular, the change-aware LVS engine 110 updates the determined common corresponding cell 410 to the updated common correspondence cell 510 of Figure 5. Such an update may include updating the common corresponding cell from corresponding cello to corresponding cellc (a change in the corresponding common cell) as well as no longer excluding corresponding cellj from the LVS process performed for circuit portions of the common corresponding cell (re-inclusion of an unmodified correct corresponding cell). The change-aware LVS engine 110 may make such updates based on port cross reference changes detected between the change-aware LVS output 420 and a baseline LVS output.

[0064] In determining to make such updates, the change-aware LVS engine 110 may generate an output for a change-aware LVS process, such as the change-aware LVS output 420. The change-aware LVS engine 110 may determine whether, for a change-aware LVS process, the port cross-reference from the common correspondence cell used for the change-aware LVS process (in this case, corresponding cello) changed. A port cross-reference may include any data or notation indicative of how ports of a cell (whether internal or external) correspond to another corresponding (e.g., equivalent) cell. Thus, a port cross-reference for a corresponding cell may specify how ports of a given cell (or given cells) of one circuit design correspond to the ports of another given cell (or other given cells) in the other circuit design. Responsive to a determination that the port cross-reference for the common corresponding cell used for the change-aware LVS process changed (e.g., through performance of the change-aware LVS process or as indicated through the change-aware LVS output 420), then the change-aware LVS engine 110 may update the common corresponding cell by202418221selecting an updated common corresponding cell that includes all placements of the previous common corresponding cell. In the example of Figure 4, the change-aware LVS output 420 may indicate that the port cross-reference for corresponding cello changed, and thus the change-aware LVS engine 110 may select an updated common corresponding cell that includes corresponding cello (e.g., up one hierarchy level). In the example of Figure 5, the change-aware LVS engine 110 selects corresponding cellc as the updated common corresponding cell 510.

[0065] As another update example, the change-aware LVS engine 110 may update any unmodified correct corresponding cells with changed port cross-references. In a similar manner as described above, the change-aware LVS engine 110 may determine whether the change-aware LVS output 420 specifies that the port cross-reference of any unmodified correct corresponding cells located within the common corresponding cell changed (in this case, whether any unmodified corresponding cells included within corresponding cello changed). If so, the change-aware LVS engine 110 may no longer exclude such unmodified correct corresponding cells from the LVS process performed for circuit sections within the common corresponding cell. For instance, the change-aware LVS engine 110 may make such an update by removing the “LVS Box” for any such unmodified correct corresponding cells with changed port cross-references.

[0066] After any update(s) to the common corresponding cell, the change-aware LVS engine 110 may perform another change-aware LVS process using the updated common corresponding cell. Thus, in Figure 5, the change-aware LVS engine 110 may perform another iteration of a change-aware LVS process using the updated common corresponding cell 510 as a top cell (in this case, corresponding cellc), performing a LVS process on circuit sections of the updated common corresponding cell 510 (which now include corresponding cellj which has been re-included, but excluding corresponding cellE identified as an unmodified correct corresponding cell now located within a common corresponding cell), re-using results from the baseline LVS process for circuit portions outside of the updated common corresponding cell 510 (e.g., outside of corresponding cellc), and re-using results from the baseline LVS process for unmodified correct corresponding cells included in the updated common corresponding cell 510 (in this updated case, corresponding cell ). Then, the change-aware LVS engine 110 may again assess if any port cross-reference changes occurred for the updated common corresponding cell 510 (that is, corresponding cellc)202418221or any unmodified correct corresponding cells (that is, corresponding COIIE). If so, the change-aware LVS engine 110 may further update this updated common corresponding cell 510 and run another change-aware LVS process. The change-aware LVS engine 110 may continue such a sequence of updates and performance of change-aware LVS runs until no port cross-reference changes occur.

[0067] In some implementations, the change-aware LVS engine 110 may determine an updated (e.g., non-minimal) common corresponding cell prior to generation of a change-aware LVS output. In such cases, the change-aware LVS engine 110 may identify that a port cross-reference has changed for a common corresponding cell even before generation of a change-aware LVS output for the common corresponding cell. Some LVS processes include transformation processes from a circuit design to a netlist. As such, the change-aware LVS engine 110 can determine of a global transformation of a modified version of a source circuit design or layout circuit design results in transformed or modified ports for a common corresponding cell. This may be a situation in which the common corresponding cell was not expressly modified (and thus not part of the set of modified corresponding cells), but a port-level change occurred between the baseline version of the determined common corresponding cell and after transformation of the modified source and layout circuit designs. This situation may occur when modifications to directly or indirectly referenced corresponding cells included in such a common corresponding cell caused port-level changes to the common corresponding cell even though the common corresponding cell was not expressly modified. In such cases, the change-aware LVS engine 110 may determine an updated common corresponding cell, e.g., by going up a hierarchy level and selecting an updated common corresponding cell that includes the previous common corresponding cell.

[0068] As described herein, the change-aware LVS technology of the present disclosure may support performance of LVS processes on only a selected subset of overall circuit designs, which can improve EDA system performance and reduce computational strain. LVS verifications can be performed efficiently, especially for small-scale circuit changes in which the change-aware LVS engine 110 can determine a common corresponding cell that covers only a small portion of overall circuit designs. Thus, the change-aware LVS technology of the present disclosure can improve EDA202418221systems that execute or support LVS processes, provide tangible technical effects, and improve EDA technology.

[0069] Any number of applications or subsequent processing based on the performed circuit comparisons are contemplated herein. For example, the change-aware LVS engine 110 may adjust the source circuit design, the layout circuit design, or both, based on the performed circuit comparison (e.g., automatically and / or responsive to user input or based on user-specified modifications). Any suitable adjustments to circuit designs are contemplated herein, including to address issues or other errors detected through the circuit comparison The change-aware LVS engine 110 may implement any additional or alternative practical application or technical effect based on the performed circuit comparison, including further circuit analyses, adaptations, or circuit manufacture / fabrication of compared or adjusted circuit designs.

[0070] Figure 6 shows an example of logic 600 that a system may implement to support change-aware LVS processes according to the present disclosure. For example, the computing system 100 may implement the logic 600 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 600 via the change-aware LVS engine 110, through which the computing system 100 may perform or execute the logic 600 as a method to support performance of change-aware LVS processes according to the present disclosure. The following description of the logic 600 is provided using the change-aware LVS engine 110 as an example implementation. However, other implementation options by computing systems are possible.

[0071] In implementing the logic 600, the change-aware LVS engine 110 may identify a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design (602), and the modifications may be made after performance of a baseline LVS process between the source circuit design and the layout circuit design. In implementing the logic 600, the change-aware LVS engine 110 may also perform a change-aware LVS process for the source circuit design and the layout circuit design (604), including by determining a common corresponding cell of the source circuit design and the layout circuit design (606) and performing a LVS process on circuit design portions included in the common corresponding cell (608), doing so in any of the ways described herein. In some implementations, the change-aware LVS engine 110 may perform the change-aware LVS process further by re-202418221using results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell.

[0072] The logic 600 shown in Figure 6 provides an illustrative example by which a computing system 100 may support or implement various features of the change-aware LVS technology described herein. Additional or alternative steps in the logic 600 are contemplated herein, including according to any of the various features described herein for the change-aware LVS engine 110.

[0073] Figure 7 shows an example of a computing system 700 that supports change-aware LVS processes according to the present disclosure. The computing system 700 may include a processor 710, which may take the form of a single or multiple processors. The processor(s) 710 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 700 may include a machine-readable medium 720. The machine-readable medium 720 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the change-aware LVS instructions 722 shown in Figure 7. As such, the machine-readable medium 720 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0074] The computing system 700 may execute instructions stored on the machine-readable medium 720 through the processor 710. Executing the instructions (e.g., the change-aware LVS instructions 722) may cause the computing system 700 to perform or implement any of the change-aware LVS technology described herein, including according to any aspect of the change-aware LVS engine 110.

[0075] For example, execution of the change-aware LVS instructions 722 by the processor 710 may cause the computing system 700 to identify a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design, the modifications made after performance of a baseline LVS process between the source circuit design and the layout circuit design. Execution of the change-aware LVS instructions 722 may also cause the computing system 700 to perform a change-aware LVS process for the source circuit design and the layout circuit design, including by determining a common corresponding cell of the source202418221circuit design and the layout circuit design and performing a LVS process on circuit design portions included in the common corresponding cell. In some implementations, execution of the change-aware LVS instructions 722 by the processor 710 may further cause the computing system 700 to re-use results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell.

[0076] Any combination of the change-aware LVS technology as described herein may be implemented via the change-aware LVS instructions 722.

[0077] The systems, methods, devices, and logic described above, including the change-aware LVS engine 110, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the change-aware LVS engine 110, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the change-aware LVS engine 110.

[0078] The processing capability of the systems, devices, and engines described herein, including the change-aware LVS engine 110, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).202418221

[0079] While various examples and features have been described above, many more implementations are possible.

Claims

202418221CLAIMS1. A method comprising:by a computing system:identifying a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design, the modifications made after performance of a baseline LVS process between the source circuit design and the layout circuit design; andperforming a change-aware LVS process for the source circuit design and the layout circuit design, including by:determining a common corresponding cell of the source circuit design and the layout circuit design, wherein the common corresponding cell comprises equivalent hierarchical cells that correspond between the source circuit design and the layout design, and wherein the equivalent hierarchical cells of the common corresponding cell include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells; andperforming a LVS process on circuit design portions included in the common corresponding cell.

2. The method of claim 1, wherein performing the change-aware LVS process further comprises:re-using results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell.

3. The method of claim 1 or 2, comprising determining the common corresponding cell differently based on whether the output of the baseline LVS process detected any errors or not.

4. The method of claim 3, comprising, when the baseline LVS process does not detect any errors in a circuit comparison between the source circuit design and the layout circuit design:202418221determining the common corresponding cell as a corresponding cell in a lowest hierarchical level that includes all of the set of modified corresponding cells.

5. The method of claim 3, comprising, when the baseline LVS process does detect errors in a circuit comparison between the source circuit design and the layout circuit design:determining the common corresponding cell as a corresponding cell in a lowest hierarchical level that includes:all of the set of modified corresponding cells, andall placements of erroneous cells detected from the circuit comparison in the baseline LVS process between the source circuit design and the layout circuit design.

6. The method of any of claims 1-5, wherein performing the change-aware LVS process further comprises:determining unmodified correct corresponding cells located within the common corresponding cell, wherein the unmodified correct corresponding cells:did not produce any errors in the baseline LVS process, andwere not modified by the modifications of the source circuit design or the layout circuit design, andexcluding the unmodified correct corresponding cells from the circuit design portions included in the common corresponding cell that the LVS process is performed on; andre-using results of the baseline LVS process for the unmodified correct corresponding cells within the common corresponding cell.

7. The method of any of claims 1-6, wherein performing the LVS process on circuit design portions included in the common corresponding cell comprises setting the common corresponding cell as a top cell for the LVS process.

8. A system comprising:a processor; and202418221a non-transitory machine-readable medium comprising instructions that, when executed by the processor, cause a computing system to:identify a set of modified corresponding cells indicative of modifications made to a source circuit design or a layout circuit design, the modifications made after performance of a baseline LVS process between the source circuit design and the layout circuit design; andperform a change-aware LVS process for the source circuit design and the layout circuit design, including by:determining a common corresponding cell of the source circuit design and the layout circuit design, wherein the common corresponding cell comprises equivalent hierarchical cells that correspond between the source circuit design and the layout design, and wherein the equivalent hierarchical cells of the common corresponding cell include, as internally-referenced lower hierarchy cells, the set of modified corresponding cells; andperforming a LVS process on circuit design portions included in the common corresponding cell.

9. The system of claim 8, wherein the instructions cause the computing system to perform the change-aware LVS process further by:re-using results of the baseline LVS process for other portions of the source circuit design and the layout circuit design outside of the common corresponding cell.

10. The system of claim 8 or 9, wherein the instructions cause the computing system to determine the common corresponding cell differently based on whether the output of the baseline LVS process detected any errors or not.

11. The system of claim 10, wherein the instructions cause the computing system to, when the baseline LVS process does not detect any errors in a circuit comparison between the source circuit design and the layout circuit design:determine the selected correspondence as a corresponding cell in a lowest hierarchical level that includes all of the set of modified corresponding cells.20241822112. The system of claim 10, wherein the instructions cause the computing system to, when the baseline LVS process does detect errors in a circuit comparison between the source circuit design and the layout circuit design:determine the selected correspondence as a corresponding cell in a lowest hierarchical level that includes:all of the set of modified corresponding cells, andall placements of erroneous cells detected from the circuit comparison in the baseline LVS process between the source circuit design and the layout circuit design.

13. The system of any of claims 8-12, wherein the instructions cause the computing system to perform the change-aware LVS process further by:determining unmodified correct corresponding cells located within the common corresponding cell, wherein the unmodified correct corresponding cells:did not produce any errors in the baseline LVS process, and were not modified by the modifications of the source circuit design or the layout circuit design, andexcluding the unmodified correct corresponding cells from the circuit design portions included in the common corresponding cell that the LVS process is performed on; andre-using results of the baseline LVS process for the unmodified correct corresponding cells within the common corresponding cell.

14. The system of any of claims 8-13, wherein the instructions cause the computing system to perform the LVS process on circuit design portions included in the common corresponding cell by setting the common corresponding cell as a top cell for the LVS process.

15. A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause a computing system to perform a method according to any of claims 1-7.

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