Method and apparatus for self-test of ground fault detection circuit

Abstract

A ground fault circuit interrupter (GFCI) detection device that includes self-testing for a peak-detection circuit. A GFCI detection device is configured to control delivery of electrical power between SOURCE terminals (SOURCE) and LOAD terminals (LOAD), and includes a switch (SW1) configured to selectively disconnect power and a switch control circuit (L1, Q1) configured to control the switch (SW1). The GFCI detection device includes a ground fault detection circuit (102) connected to control the switch control circuit (L1, Q1). The ground fault detection circuit has a microcontroller (MCU) configured to monitor and detect ground faults and to periodically perform a self-test. The microcontroller (MCU) is configured to perform the self-test by generating (415, 418) a low test signal (COMP TEST=LOW) and a high test signal (COMP TEST=HIGH) and determining whether test signals are below or above respective thresholds.

Description

202503320METHOD AND APPARATUS FOR SELF-TEST OF GROUND FAULT DETECTION CIRCUITTECHNICAL FIELD

[0001] The present disclosure is directed, in general, to electrical circuit devices, and in particular to testing circuits for electrical breakers.BACKGROUND OF THE DISCLOSURE

[0002] A three-phase Ground Fault Circuit Interrupter (GFCI) breaker is a specialized protective device designed to monitor and disconnect power in a three-phase electrical system when it detects a ground fault. Unlike standard overcurrent protection devices, a GFCI breaker specifically senses leakage currents that may occur when current flows outside the intended circuit — such as through a human body to ground. These devices are sensitive to very small levels of current imbalance, such as 5 mA in personnel protection models, and are essential in applications where wet or conductive environments increase the risk of electric shock.

[0003] The internal design of a three-phase GFCI breaker includes current transformers or sensing coils that encircle all three phase conductors — and sometimes the neutral — to detect any difference between the outgoing and returning current. Under normal conditions, the current in all phases (and neutral, if present) is balanced, resulting in a net zero magnetic field within the transformer. When a ground fault occurs, this balance is disrupted, triggering the trip mechanism. Many three-phase GFCI breakers also include adjustable trip settings and time delays, particularly in industrial or commercial settings, to avoid nuisance tripping during brief imbalances caused by motor startups or inrush currents.

[0004] Applications for three-phase GFCI breakers include commercial kitchens, industrial processing areas, and construction sites where portable equipment is used in damp or hazardous conditions. Their use is critical in compliance with electrical safety codes, such as NEC Article 210.8(B), which mandates GFCI protection in certain202503320commercial and industrial locations. Modern 3-phase GFCIs often integrate features such as self-testing functionality, trip diagnostics, and remote monitoring capabilities, making them more reliable and easier to maintain in complex power distribution systems.

[0005] In a three-phase GFCI breaker, a peak detection circuit plays a crucial role in accurately identifying ground faults, particularly those involving brief or asymmetrical leakage currents. The main function of the peak detection circuit is to capture and respond quickly to a large amplitude differential current between the combined line currents and the neutral (if present). This approach helps the GFCI detect large amplitude leakage events much faster than RMS-based or average detection methods alone.

[0006] The peak detection circuit typically works by amplifying and either biasing or rectifying the output signal from a differential current transformer (CT) that monitors all phase conductors. When a ground fault occurs, the CT outputs a current that is converted into a voltage proportional to the imbalance current. This voltage is fed into the peak detection circuit, often involving a diode and capacitor configuration that captures and holds the highest voltage level reached during a leakage event. The held voltage is compared to a fixed threshold using a comparator. If the peak exceeds the threshold corresponding to the GFCI's trip setting for a large amplitude leakage current (e.g., 20 mA), the circuit triggers the breaker’s trip mechanism.

[0007] This design is especially important in three-phase systems because faults can occur asymmetrically or intermittently across phases. For example, a ground fault might affect only one phase momentarily, generating a short-lived surge in leakage current. A peak detection circuit ensures that such brief but dangerous conditions are not overlooked. It increases the sensitivity and reliability of the breaker by ensuring that a large amplitude ground fault is detected and responded to quickly in real time, thus enhancing personnel and equipment safety.

[0008] Underwriters Labs standard 943 (UL943) requires modern GFCIs to include automonitoring (self-testing) features that periodically verify internal functionality. If a GFCI fails its self-test or becomes unable to provide protection it must prevent power from being supplied, or it must visibly or audibly alert the user in response to failing a push-to-test.202503320These requirements ensure that the GF CI remains a reliable line of defense against electrical shock hazards throughout its installed life. In a conventional three-phase GFCI breaker, the ground fault detection self-test consists of a microprocessor initiating the generation of a pulse of low amplitude current from the DC power supply that is routed through a current transformer configured to sense current delivered and returning from an electrical circuit branch and detecting this test current by sampling the output of the ground fault current sensing circuit. This test current is limited to less than 9 mA so that the ground fault detection self-test can also function as the supervisory circuit as required in UL943.

[0009] However, a much larger amplitude test current, up to five times larger, is needed to test the peak detection circuit. The AC-to-DC power supply used in the three-phase GFCI breaker has a fast turn on time required to meet as fast as 25 ms trip time as required in UL943 and can only supply a limited amount of test current (up to 10 mA), Typically, this would require additional circuitry to generate a larger amplitude test current to test the peak detection circuit, which can significantly affect the manufacturing and cost of such a three-phase GFCI circuit. There is a need in the industry for an efficient and effect means to test the peak detection circuit without generating a large amplitude test current and limiting additional circuitry to a minimum.202503320SUMMARY OF THE DISCLOSURE

[0010] Various disclosed embodiments include a three-phase GFCI circuit breaker with an automatic auto-monitoring peak detection self-test circuit. One disclosed GFCI detection device is configured to control delivery of electrical power between SOURCE terminals (SOURCE) and LOAD terminals (LOAD), and includes a switch (SW1) configured to selectively disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD) and a switch control circuit (LI, QI) configured to control the switch (SW1). The GFCI detection devices includes a ground fault detection circuit (102) connected to control the switch control circuit (LI, QI). The ground fault detection circuit has a microcontroller (MCU) configured to monitor and detect ground faults and to periodically perform a self-test. The microcontroller (MCU) is connected to selectively activate the switch control circuit (LI, QI) to open the switch (SW1) and disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD). The ground fault detection circuit has a peak detection circuit portion (U3) connected to the microcontroller (MCU), which is configured to detect ground fault current that is below a first predetermined threshold (REF 0V9) or above a second predetermined threshold (REF 2V1). The peak detection circuit portion (U3) includes a lower limit comparator (U3B) and an upper limit comparator (U3A). To perform the self-test, the microcontroller is configured to generate a low test signal (COMP TEST=LOW) and determine whether an output of the lower limit comparator (U3B) indicates that the low test signal is below the first predetermined threshold (REF 0V9). The microcontroller is configured to generate a high test signal (COMP TEST=HIGH) and determine whether an output of the upper limit comparator (U3A) indicates that the high test signal is above the second predetermined threshold (REF 2V1). The microcontroller is configured to, in response to determining that the output of the lower limit comparator indicates that the low test signal is not below the first predetermined threshold OR determining that the output of the upper limit comparator indicates that the high test signal is not above the second predetermined threshold, trigger the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD).202503320

[0011] In various embodiments, the low test signal and the high test signal are provided to an amplifier by the microcontroller and used to generate a detection signal connected to the peak detection circuit portion. In various embodiments, the low test signal and the high test signal are generated by a digital-to-analog converter output (DAC OUT) of the microcontroller (MCU). In various embodiments, the low test signal and the high test signal are generated by a tri-state output port (COMP TEST) of the microcontroller (MCU) and a voltage divider network (R6, R7, R8).

[0012] In various embodiments, the microcontroller is further configured to detect when a push-to-test (PTT) button has been activated, and in response, to trigger the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD). This can occur, in some embodiments, when the PTT button is pressed and the self-test passes. In various embodiments, the microcontroller (MCU) is configured to perform the self-test at startup of the GFCI detection device.

[0013] In various embodiments, the microcontroller (MCU) is configured to perform the self-test no more frequently than every 15 minutes or less frequently than every 3 hours. In various embodiments, the test signals are generated for 1 ms. In various embodiments, the microcontroller (MCU) is configured to be delayed for 2 ms between generating the low test signal and generating the high test signal.

[0014] In various embodiments, when the microcontroller (MCU) determines that the output of the lower limit comparator indicates that the low test signal is below the first predetermined threshold and determines that the output of the upper limit comparator indicates that the high test signal is above the second predetermined threshold, the microcontroller resets a test timer and resumes normal operation.

[0015] A GFCI detection device is configured to control delivery of electrical power between SOURCE terminals (SOURCE) and LOAD terminals (LOAD) and includes a switch (SW1) configured to selectively disconnect power and a switch control circuit (LI, QI) configured to control the switch (SW1). The GFCI detection devices includes a ground fault detection circuit (102) connected to control the switch control circuit (LI, QI). The202503320ground fault detection circuit has a microcontroller (MCU) configured to monitor and detect ground faults and to periodically perform a self-test. The microcontroller (MCU) is configured to perform the self-test by generating a low test signal (COMP TEST=LOW) and a high test signal (COMP TEST=HIGH) and determining test signals are below or above respective thresholds.

[0016] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0017] Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and / or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.202503320BRIEF DESCRIPTION OF THE DRAWINGS

[0018] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:

[0019] FIG. 1 illustrates a circuit diagram of a GFCI detection device in accordance with disclosed embodiments;

[0020] FIGS. 2 and 3 illustrate various voltages for the operation of a ground fault detection device in accordance with disclosed embodiments;

[0021] FIG. 4A, FIG. 4B and FIG. 4C illustrate a flow diagram of a process of the operation of a GFCI device in accordance with disclosed embodiments;

[0022] FIG. 5 illustrates exemplary signals of a self-test process in accordance with disclosed embodiments;

[0023] FIG. 6 illustrates another GFCI detection device in accordance with disclosed embodiments; and

[0024] FIG. 7A, 7B and 7C illustrate a flow diagram of a process of the operation of a GFCI device in accordance with disclosed embodiments.202503320DETAILED DESCRIPTION

[0025] The figures discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged device. The numerous innovative teachings of the present application will be described with reference to exemplary non-limiting embodiments.

[0026] Disclosed embodiments include methods and apparatuses for automatic self-testing of a GFCI circuit, and in particular include a three-phase GFCI circuit breaker with an automatic auto-monitoring self-testing peak detection circuit.

[0027] The embodiment of the invention shown in FIG. 1 is a ground fault detection device that includes auto self-test of all the ground fault detection circuitry as well as a manually initiated test to ensure the health of the ground fault detection circuitry.

[0028] FIG. 1 illustrates a circuit diagram of a GFCI detection device 100 in accordance with disclosed embodiments. The ground fault detection device 100 in FIG. 1 includes at least one LINE conductor, a NEUTRAL conductor, and at least one air-gap contact switch SW1 for each LINE conductor disposed between the SOURCE and the LOAD in the each of the Line conductors to supply power from the SOURCE terminals to the LOAD (electrical circuit) terminals when the air-gap contact switch SW1 is closed. Switch SW1 is controllable as described herein to selectively disconnect power between the SOURCE terminals and the LOAD terminals by opening switch SW1.

[0029] The ground fault detection device 100 in FIG. 1 also includes at least one electromagnetic trip mechanism LI and a controllable semiconductor switch or silicon-controlled rectifier (SCR) QI connected in series with each other. Electromagnetic trip mechanism LI and switch QI are disposed between at least one LINE conductor and a Neutral conductor and are configured to open air-gap contact switch SW1 when energized, disconnecting the SOURCE terminals power from the LOAD terminals or electrical circuit202503320branch. Electromagnetic trip mechanism LI and switch QI together comprise a switch control circuit.

[0030] The ground fault detection device 100 in FIG. 1 also includes a power supply U1 disposed between at least one LINE conductor and a NEUTRAL conductor. In this embodiment, power supply U1 converts 120 VAC to +3.3VDC, powers up in less than 1 ms, and supplies +3.3VDC to the electronic circuits. In this example, power supply U1 that has a DC to DC voltage regulator, such as regulator NCP785A manufactured by ON Semiconductor (not shown), an input rectifying diode (not shown), and input and output capacitors (not shown).

[0031] The ground fault detection device 100 in FIG. 1 also includes a ground fault sensing transformer T1 configured such that each of the LINE conductors and a NEUTRAL conductor pass as one-turn windings through the transformer T1 in the same direction between the SOURCE terminals and LOAD terminals, and which can be located either between the SOURCE terminals and the air-gap switch SW1 or between the air-gap switch SW1 and the LOAD terminals. Ground fault sensing transformer T1 is configured with an additional one-turn conductor winding labeled W1 to pass a test current through the transformer Tl, and has a multi -turn conductor winding of approximately 1151 turns that is coupled to the input of a ground fault detection circuit.

[0032] The ground fault detection device 100 in FIG. 1 also includes a ground fault detection circuit 102 that has an optional 2-pole low pass filter FL1, a pair of diodes in a single package DI, such as number BAV99LT manufactured by ON Semiconductor, a burden resistor R2 whose value is approximately 523 Ohms, an amplifier U2, such as part number INA190A2IDCKT manufactured by Texas Instruments, a pair of comparators integrated into a single package integrated circuit (IC) U3, such as part number LM393LVDDFR manufactured by Texas Instruments, resistors R3 and R4 whose value is approximately 100 kilohms, R5 whose value is approximately 75 kilohms, R6 whose value is approximately 12 kilohms, and R7 whose value is approximately 10 kilohms. Ground fault detection circuit 102 also has a microcontroller unit (MCU), such as part number STM32G031G6U6 manufactured by STMicroelectronics NV, that is programed to detect202503320ground faults, assert a trip signal to the gate of the controllable semiconductor switch or SCR QI to energize the electromagnetic trip mechanism LI in response to detecting a ground fault, and perform testing of the ground fault sensing transformer Tl.

[0033] The ground fault detection device 100 in FIG. 1 also includes a push-to-test or push-to-trip (PTT) button switch SW2, such as part number EVQPF306K (available from multiple suppliers).

[0034] The ground fault detection device 100 in FIG. 1 also includes a circuit that generates test current that includes resistor R1 whose value is approximately 422 Ohms, test wire W1 included in sensing transformer Tl described above, and transistor Q2, such as part number DTC124XMT2L manufactured by ROHM Semiconductor, configured in series and disposed between the +3.3VDC output of the power supply U1 and electronics ground with one terminal of resistor R1 connected to the +3.3VDC output of the power supply Ul, the other terminal of resistor R1 connected to one end of test wire Wl, the other end of test wire Wl connected to the collector of transistor Q2, the emitter of the transistor Q2 connected to electronics ground, and the base of the transistor Q2 connected to the terminal labeled GF TEST of the MCU U4.

[0035] The ground fault detection circuit 102 is configured so that the input terminals of the low pass filter FL1 are coupled to the two ends of the multi-turn winding of transformer Tl and the output terminals of the low pass filter FL1 are coupled to a burden resistor R2 of approximately 523 Ohms to convert coupled current to a voltage, to the input of amplifier U2, and to diodes DI configured such that the two diodes are connected in parallel and reverse polarity to each other across the input of the amplifier U2. This prevents the input of amplifier U2 from being exposed to high voltage transients that could damage the amplifier U2 by clamping any high voltage transients to less than 1 V. The amplifier U2 is disposed between the +3.3VDC output of the power supply Ul and electronics ground which is the neutral conductor with the terminal labeled VS connected to the +3.3VDC output of the power supply Ul and the terminal labeled GND connected to electronics ground. Resistors R6 and R7 are connected in series and disposed between the +3.3VDC output of the power supply Ul and electronics ground to create a resistor202503320divider reference voltage REF 1V5 of approximately +1.5VDC at the node connecting R6 to R7. This node is connected to the terminal of U2 labeled REF. This voltage signal at the terminal labeled REF of the amplifier U5 is used to provide a common mode voltage on the terminal labeled OUT of the amplifier U2 equal to the voltage at the terminal labeled REF.

[0036] The ground fault detection device 100 in FIG. 1 also includes a peak detection testing circuit that tests the peak detection circuit portion of the ground fault detection circuit 102 described below.

[0037] Peak detection circuit portion of ground fault detection circuit 102 includes an IC U3 disposed between the +3.3VDC output of the power supply U1 and electronics ground with the terminal labeled V+ connected to the +3.3VDC output of the power supply U1 and the terminal labeled GND connected to electronics ground. The ground fault detection circuit 102 is configured so that the pair of comparators U3A and U3B of IC U3 have open drain outputs and are configured as a window comparator circuit as part of the peak detection circuit portion to quickly detect large amplitude ground fault current approximately greater than 20 mA. Resistors R3, R4, and R5 are connected in series and disposed between the +3.3VDC output of the power supply U1 and electronics ground to create resistor divider reference voltages REF 2V1 of approximately +2.1VDC at the node connecting R3 to R4, and REF 0V9 of approximately +0.9VDC at the node connecting R4 to R5. The node REF 2V1 is also connected to the non-inverting input of U3A for the upper threshold of the window comparator, and the node REF 0V9 is also connected to the inverting input of U3B for the lower threshold of the window comparator.

[0038] Peak detection testing circuit, in this embodiment, includes resistor R8 whose value is approximately 5 kilohms with one terminal connected to a terminal labeled COMP TEST of the MCU U4 and the other terminal connected to node labeled REF I V5. Resistors R6, R7, and R8 act as a voltage divider network controlled by the COMP TEST terminal of the MCU. This voltage divider network allows the MCU to generate a low test signal and a high test signal as described herein by changing the voltage output at COMP TEST.202503320

[0039] The output terminal OUT of the amplifier U2 is connected to terminal labeled ADC IN of the MCU U4 which is configured to couple the detection signal on this node labeled GF MON to an Analog-to-digital converter (ADC) inside the MCU U4. The output terminal labeled OUT of the amplifier U2 is also connected to the inverting input terminal of comparator U3A and the non-inverting terminal of comparator U3B, coupling the detection signal on this node labeled GF MON to the input of the window comparator. The open drain outputs of U3A and U3B are connected to complete the window comparator circuit configuration to function as a peak detection circuit for large ground fault current. The outputs of U3A and U3B are also connected to a terminal labeled PK DETECT of the MCU U4 that is configured internally as a pull-up.

[0040] When a ground fault exists in the load or electrical circuit branch, i.e. the current going to the load does not equal the current returning from the load, an imbalance in the magnetic field is generated in the core of the transformer Tl, which in turn generates a corresponding current in the multi-turn winding which is coupled through an optional low pass filter FL1 to the burden resistor R2 that converts the current representative of the ground fault current into a voltage which is applied to the input of the amplifier U2. This signal is amplified by a gain of 50 V / V by the amplifier and biased onto a common mode voltage of +1.5 VDC and output as the detection signal on the terminal labeled OUT of the amplifier U2 which is on the node labeled GF MON. This detection signal on node GF MON is routed to a terminal labeled ADC IN on the MCU U4 and to IC U3.

[0041] In particular, the detection signal is connected to the inverting input terminal of comparator U3A and the non-inverting input terminal of U3B, forming the input of a peak detection circuit portion that includes IC U3 and its comparators U3A and U3B configured as a window comparator. The output of the window comparator, which consists of the connected open drain output terminals of comparator U3 A and U3B, is routed to a terminal labeled PK DETECT of the MCU U4.

[0042] The MCU U4 is programmed to actively monitor and detect ground faults, referred to herein as “mission mode.” and periodically perform a self-test of the ground fault detection circuitry referred to as auto self-test or auto-monitoring.202503320

[0043] For mission mode, the MCU U4 is programmed to configure a tri-state (set to a high impedance state) output port at the terminal of the MCU U4 labeled COMP TEST such that the voltage at node REF 1V5 is determined only by resistors R6 and R7 and not R8, thus resulting in a voltage of +1.5VDC connected to the terminal labeled REF of the amplifier U2.

[0044] For mission mode, the MCU U4 is also programmed to configure a pull-up input port at the terminal labeled PK DETECT of the MCU U4. For mission mode, the MCU U4 is also programmed to configure an output typically logic 0 or LOW at the terminal labeled TRIP of the MCU U4 which is connected to the gate of the controllable semiconductor / SCR QI to control the energizing of the electromagnetic trip mechanism LI. For mission mode, the MCU U4 is also programmed to configure a pull-up input port at the terminal labeled PTT of the MCU U4 to monitor if the push-to-test button SW2 has been pressed.

[0045] For mission mode, the MCU U4 is also programmed to configure the input terminal labeled ADC IN to be coupled to an internal ADC that samples the voltage detection signal on GF MON representative of the ground fault current. For mission mode, the MCU U4 is also programmed to determine if a ground fault greater than 5 mA exists and in response to detecting a ground fault assert a trip signal on the node labeled TRIP typically by asserting a logic 1 or HIGH to the terminal labeled TRIP of the MCU U4 to turn on the SCR QI and energize the trip electromagnet LI which disconnects power from the load. The MCU U4 is programmed to determine a ground fault by processing the sampled data of the voltage detection signal on GF MON and respond by asserting a trip signal in time less than that defined by the equation t = (20 / 1)1.43, where t is expressed in seconds and I is ground fault current expressed milliamperes for peak-to-peak signal amplitudes greater than 320 mV which is representative of a ground fault current greater than 5 mA rms, and to monitor the input terminal labeled PK DETECT for a logic 0 or LOW which occurs for large ground fault currents greater than 20 mA rms and respond by asserting a trip signal immediately.

[0046] FIG. 2 illustrates various voltages for the operation of the ground fault detection device 100 in accordance with disclosed embodiments.202503320

[0047] FIG. 2 illustrates a ground fault current 202 of 5 mA on the top graph. FIG. 2 also illustrates, on the middle graph, the resulting voltage detection signal 204 at the output terminal OUT of amplifier U2 on node GF MON in FIG. 1 that is approximately 320 mV peak-to-peak on a common mode voltage of approximately +1.5VDC along with the peak detector / window comparator reference voltages REF 0V9 208 of approximately +0.9VDC and REF 2V1 206 of approximately +2.1VDC. FIG. 2 also illustrates, on the bottom graph, the output 210 of the peak detector / window comparator on node PK DETECT in FIG I.

[0048] In this example, the MCU U4 samples and processes this signal, determines there is a ground fault of 5 mA and asserts a trip signal in less than approximately 7 seconds consistent with the equation t = (20 / 1)1.43. The output signal of the peak detector on PK DETECT is at approximately +3.3VDC or logic level 1 or HIGH and remains HIGH since the signal on GF_MODE stays between +0.9V and +2.2V, REF_0V9 and REF_2V2 respectively.

[0049] FIG. 3 illustrates various voltages for the operation of the ground fault detection device 100 in accordance with disclosed embodiments.

[0050] In the top graph, FIG. 3 illustrates a ground fault current 302 of 20 mA. FIG. 3 illustrates, in the middle graph, the resulting voltage detection signal 304 at the output terminal OUT of amplifier U2 on node GF MON in FIG. 1, that is approximately 1280 mV peak-to-peak on a common mode voltage of approximately +1.5VDC, along with the peak detector / window comparator reference voltages REF 0V9 308 of approximately +0.9VDC and REF 2V1 306 of approximately +2.1VDC. FIG. 3 illustrates, in the bottom graph, the output 310 of the peak detector / window comparator on node PK DETECT in FIG. 1.

[0051] In this example, the MCU U4 samples and processes output 304 on node GF MON, determines there is a ground fault of 20 mA, and would normally assert a trip signal in less than approximately 1 second consistent with the equation t = (20 / 1)1.43. However, the output signal of the peak detector on PK DETECT transitions from approximately +3.3VDC to 0VDC or from logic level 1 or HIGH to logic 0 or LOW when the detection202503320signal on GF MON exceeds approximately +2.1VDC or REF 2V1 or is less than +0.9VDC or REF 0V9 and returns back to approximately +3.3VDC or logic 1 or HIGH when the detection signal on GF_MON returns to a voltage level between +0.9V and +2.2V, REF 0V9 and REF_2V2 respectively.

[0052] So, in this example, the MCU U4 detects a logic 0 or LOW on node PK DETECT at terminal port labeled PK DETECT of the MCU and asserts a trip signal immediately which ultimately results in asserting a trip signal within approximately 8 milliseconds depending upon the starting phase of the onset of a ground fault current (maximum time elapsed between one peak to the next peak) instead of approximately 1 second from as a result of sampling and processing the signal input at the terminal ADC IN of the MCU. This faster trip time feature is needed to meet the trip time requirements in UL943 described by the equation t = (20 / 1)1.43 when a grounded neutral exists in the load or electrical circuit, which can reduce the sensed ground fault to just 15% of the actual ground fault current.

[0053] The ground fault detection device 100 is to be automatically and periodically tested as required by the auto-monitoring provisions of UL943. This includes testing the additional peak detection circuit of ground fault detection circuit 102. As shown in FIG. 1, this is accomplished by automatically and periodically generating a test current into 1 turn of conductor test wire W1 through the ground fault current sensing transformer T1 by programming the MCU U4 to automatically and periodically assert typically a logic level 1 or HIGH or approximately +3.3VDC on node GF TEST to briefly turn on transistor circuit Q2.

[0054] However, if the same test current is used for a manually initiated self-test by a user pressing a push-to test or push-to-trip (PTT) button SW2, the test current amplitude is limited to 9 mA as required in the Supervisory circuit section of UL943. Unfortunately, a test current of at least 20 mA which translates to 28 mA peak is required to test the peak detection circuit. In addition, the AC to DC power supply U1 used as the source for the test current in this embodiment can only supply up to 10 mA of current at the +3.3VDC output terminal of the power supply.202503320

[0055] The embodiment of FIG. 1, along with an exemplary flow diagram in FIG. 4, discussed below, and corresponding exemplary test signals shown in FIG. 5 describe an improved circuit and method to test the peak detection circuit of the ground fault detection circuit.

[0056] FIG. 4A, FIG. 4B and FIG. 4C illustrate a flow diagram of a process 400 of the operation of a GFCI device in accordance with disclosed embodiments, such as GFCI detection device 100. At step 401, the process begins.

[0057] At step 402, at power on, the MCU U4 is programmed for mission mode to configure ports and internal circuitry to detect ground faults. This can include setting TRIP = Output LOW, GF TEST = Output LOW, COMP TEST = Output tn-state, PK DETECT = Input Pull-up, PTT = Input Pull-up, ADC IN = ADC Input channel, and configure ADC and sample rate.

[0058] At step 403, a logic variable or flag called “PTT Pressed” is created which is used to store a detected PTT button press at terminal PTT of the MCU and initially set to FALSE.

[0059] At step 404, a 15 -minute timer is configured to automatically and periodically start self-test and is set to expired so that the initial self-test is performed upon powering on and not delayed by 15 minutes. Note that this timer could be as long as 3 hours as allowed by UL943 for auto-monitoring.

[0060] At step 405, the MCU enters into a loop to determine whether a ground fault exists. In this example, this is accomplished by determining whether processed data at ADC IN indicates ground fault OR whether PK DETECT port = LOW.

[0061] If FALSE at 405 (no ground fault exists), then at step 406, the GFCI device determines whether the PTT button is pressed, when the PTT port = LOW.

[0062] If FALSE at 406 (PTT is not pressed), then at step 407, the GFCI device determines whether the timer for self-test has expired (reached 15 minutes in this example).

[0063] If FALSE at 407 (timer has not expired), the process returns to step 405.202503320

[0064] If TRUE at 405 (ground fault exists), then the process proceeds to step 422, below.

[0065] If TRUE at 406 (PTT is pressed), then at step 408, the MCU changes or sets the variable or flag to TRUE and enters test mode by proceeding to START self-test at step 411.

[0066] If TRUE at 407 (timer has expired), then the MCU enters test mode by proceeding to START self-test at step 411.

[0067] At step 411, the GFCI device STARTS a self-test (enters test mode) and proceeds to step 412.

[0068] At step 412, in test mode, the MCU U4 turns on test current for approximately 1 ms to test the ground fault detection circuit, excluding the peak detection circuit, and asserts output port GF TEST = HIGH for approximately 1 ms while monitoring the detection signal output of amplifier U2 GF MON on port ADC IN.

[0069] At step 413, in test mode, the MCU determines whether the test current detected on ADC IN is greater than a predetermined upper threshold OR is less than a predetermined lower threshold in response to setting GF TEST = HIGH during the 1 ms test period.

[0070] If TRUE at step 413, then at step 414, the process delays for approximately 2 millisecond delay before proceeding to step 415.

[0071] If FALSE at step 413, then the process proceeds to step 420B, described below.

[0072] At step 415, after the 2 millisecond delay in step 414, the MCU generates a low test signal by lowering the reference voltage at REF 1V5 into the REF terminal of the amplifier U2 below the voltage at REF 0V9 (a first predetermined voltage threshold) for 1 ms to test lower limit comparator U3B of the peak detection circuit. The MCU asserts output port COMP TEST = LOW for 1 ms and then returns to tri-state while monitoring the output of the peak detection circuit PK DET on port PK DETECT. In this way, the MCU determines whether the peak detection circuit portion correctly determines that the low test signal exceeds the first predetermined voltage threshold.202503320

[0073] At step 416, the MCU determines whether input port PK DETECT = LOW at the output of lower limit comparator U3B in response to COMP TEST = LOW during the 1 ms test period is TRUE.

[0074] If TRUE at step 416 (PK DETECT = LOW in response to COMP TEST = LOW), then at step 417, the process delays for approximately 2 millisecond delay before proceeding to step 418. If TRUE at step 416, the peak detection circuit portion has correctly determined that the low test signal exceeds the first predetermined voltage threshold.

[0075] If FALSE at step 416 (PK DETECT is not LOW in response to COMP TEST = LOW), then the process proceeds to step 420B, described below.

[0076] At step 418, after the 2 millisecond delay in step 417, the MCU generates a high test signal by increasing the reference voltage at REF 1V5 into the REF terminal of the amplifier U2 above the voltage at REF 2V 1 (a second predetermined voltage threshold) for 1 ms to test upper limit comparator U3A of the peak detection circuit. This is accomplished by asserting output port COMP TEST = HIGH for 1 ms and then return to tri-state while monitoring the output of the peak detection circuit PK DET on port PK DETECT. In this way, the MCU determines whether the peak detection circuit portion correctly determines that the high test signal exceeds the second predetermined voltage threshold.

[0077] At step 419, the MCU determines whether input port PK DETECT = LOW at the output of upper limit comparator U3A in response to COMP TEST = HIGH during the 1 ms test period.

[0078] If FALSE at step 419 (PK DETECT is not LOW in response to COMP TEST = HIGH) then the process proceeds to step 420B, described below.

[0079] If TRUE at step 419 (PK DETECT = LOW in response to COMP TEST = HIGH) then at step 420A, the MCU determines whether variable or flag called “PTT Pressed” equal to TRUE. If TRUE at step 419, the peak detection circuit portion has correctly determined that the high test signal exceeds the second predetermined voltage threshold.202503320

[0080] If TRUE at step 420A (PTT Pressed = TRUE), then self-test passed after initiation by user pressing PTT button SW2 and the process proceeds to step 422, described below. That is, the self-test has passed, but the GFCI will be tripped in response to the PTT button.

[0081] If FALSE at step 420A (PTT Pressed is not TRUE), then at step 421, the MCU determines that the self-test was passed after initiation by the expiration of the self-test timer and the MCU is programmed to exit self-test mode and proceed to step 409.

[0082] If FALSE at step 413, FALSE at step 416, or FALSE at step 419, then at step 420B, the MCU determines whether the variable or flag called “PTT Pressed” equal to TRUE.

[0083] If TRUE at step 420B (PTT Pressed = TRUE), then self-test failed after initiation by user pressing PTT button SW2 and the process proceeds to step 424, described below.

[0084] If FALSE at step 420B (PTT Pressed is not TRUE), then self-test failed and the process proceeds to step 422, described below.

[0085] Note that the PTT test performed at steps 420A and 420B are effectively the same, but the response differs depending on the results of the threshold testing.

[0086] At step 409, after successfully passing self-test, the MCU resets the start of selftest timer before returning to step 405.

[0087] At step 422, the MCU is programmed to assert output port TRIP = HIGH to energize electromagnetic trip mechanism to disconnect power from the load, thereby “tripping” the ground fault detection circuit 102. In the context of FIG. 1, setting TRIP to HIGH activates electromagnetic trip mechanism LI and switch QI to open air-gap contact switch SW1 and disconnect the LINE from the LOAD. After step 422, the GFCI has been tripped, and the process STOPs at step 423.

[0088] At step 424, the MCU can activate a visual or audible alert to indicate that PTT has been pressed and the GFCI device is operating correctly. After step 424, whether or not it is performed, the process STOPs at step 423.202503320

[0089] Note that the order of testing the ground fault detection excluding the peak detection circuit and testing of the peak detection circuit comparators is not critical and may be performed in a different order. Also, the test times and delay times may be shorter or longer as long as the self-test does not significantly interrupt detection of a ground faults within the time constraints of the equation t = (20 / 1)1.43 as described in UL943.

[0090] FIG. 5 illustrates exemplary signals of a self-test process in accordance with disclosed embodiments. The top graph of FIG. 5 illustrates a ground fault test current 502 in wire Wl of FIG 1, approximately 7.8 mA peak and 1 millisecond in duration, corresponding to step 412 of the flow chart in FIG. 4. The test pulse current is generated by the MCU U4 asserting a logic level 1 or HIGH at output port terminal GF TEST of the MCU which results in approximately +3.3VDC on the base of transistor circuit Q2 turning on the test current pulse in wire Wl. The peak current of approximately 7.8 mA is set by resistor R1 connected between wire Wl and the +3.3VDC supply.

[0091] The second graph from the top of FIG. 5 illustrates test signal 504 on node COMP TEST of FIG. 1, used to test the peak detector (window comparator) circuit corresponding to step 415 and 418 of the flow chart of FIG. 4 is shown on the second graph from the top in FIG. 5. Approximately 2 milliseconds after the ground fault test current pulse test is completed, the signal on COMP TEST is driven LOW or approximately 0VDC for 1 millisecond, set back to tri-state (high impedance state) for 2 milliseconds, driven HIGH or approximately +3.3VDC for 1 millisecond, and then set back to tri-state.

[0092] The third graph from the top of FIG. 5 illustrates resulting signal 506 on the node REF 1V5 of FIG. 1, responsive to the signal imposed by the MCU U4 on node COMP TEST.

[0093] The fourth graph from the top of FIG. 5 illustrates resulting voltage detection signal 508 at the output terminal OUT of amplifier U2 on node GF MON of FIG. 1 in response to the above test stimuli along with the peak detector / window comparator reference voltages REF 0V9 512 of approximately +0.9VDC and REF 2V1 510 of approximately +2.1VDC. The first pulse corresponds to the 1 millisecond test current pulse in wire Wl and is approximately a 177 mV peak voltage pulse relative to the common mode voltage202503320of +1.5VDC which is greater than a predetermined upper threshold of approximately 160 mV detected by the MCU U4 in step 413 of FIG. 4. The following second and third pulses on the detection signal at node GF MON correspond to the resulting signal on REF I V5 caused by the MCU U4 driving a LOW and HIGH signal on node COMP TEST.

[0094] The fifth graph from the top of FIG. 5 illustrates the output 514 of the peak detector / window comparator on node PK DETECT of FIG. 1. The output 514 of the peak detector / window comparator on node PK DETECT of FIG. 1 transitions from a logic level 1 or HIGH which is approximately +3.3VDC to a logic 0 or LOW which is approximately OVDC twice for 1 millisecond corresponding to the second and third pulse of the detection signal on node GF MON 508 of FIG 1. The second pulse of the detection signal on node GF_MON 508 drops to approximately +0.7VDC peak voltage which is less than the voltage on node REF 0V9 or +0.9VDC (lower limit voltage for comparator U3B) of FIG 1. This results in the first transition from HIGH to LOW for 1 millisecond at the output 514 on node PK DETECT and is detected on terminal PK DETECT of the MCU U4 of FIG. 1 by the MCU in step 416 of the flow diagram of FIG. 4. The third pulse of the detection signal on node GF_M0N 508 increases to approximately +2.4 VDC peak voltage which is greater the voltage on node REF 2V1 or +2.1 VDC (upper limit voltage for comparator U3 A) in FIG. 1. This results in the second transition from HIGH to LOW for 1 millisecond at the output 514 on node PK DETECT and is detected on terminal PK DETECT of the MCU U4 of FIG. 1 by the MCU in step 419 of the flow diagram of FIG. 4.

[0095] To summarize, the generation of the test current in wire W1 tests the ground fault detection circuit from the ground fault current sensing transformer to the output of amplifier U2 and input terminal ADC IN of the MCU U4 of FIG. 1. The generation of the signal on COMP TEST tests the ground fault detection circuit from the output of amplifier U2 to the output of the peak detection circuit, i.e. the output of comparators U3A and U3B and input terminal PK DETECT of the MCU U4 of FIG. 1. The self-test allows the test current limited to less than 9 milliamperes to be used as the supervisory circuit for a user-initiated push-to-test as required by UL943. Testing of the additional peak detection circuit was implemented by adding one resistor at a cost of 0.1 cents and minimal additional programming of the MCU.202503320

[0096] FIG. 6 illustrates another GFCI detection device 600 in accordance with disclosed embodiments. GFCI detection device 600 is similar to the GFCI detection device 100 except the voltage generated on node labeled REF 1V5 is generated using an alternative MCU U5 that includes a Digital-to-Analog Convertor or DAC instead of the resistor divider circuit network consisting of R6 and R7. A terminal labeled DAC OUT of the MCU U5 is connected to the terminal labeled REF of the amplifier U2. The resistor R8 is no longer necessary to alter the voltage on node REF 1V5 for self-test of the peak detection circuit / window comparator.

[0097] FIG. 7A, FIG. 7B and FIG. 7C illustrate a flow diagram of a process 700 of the operation of a GFCI device in accordance with disclosed embodiments, such as GFCI detection device 600. At step 701, the process begins.

[0098] At step 702, at power on, the MCU U5 is programmed for mission mode to configure ports and internal circuitry to detect ground faults by setting TRIP = Output LOW, GF TEST = Output LOW, DAC OUT = DAC Output channel (instead of COMP TEST = Output tri-state as described in step 402 in FIG. 4), PK DETECT = Input Pull-up, PTT = Input Pull-up, ADC IN = ADC Input channel, and configure ADC and sample rate, and additionally configure DAC to output +1.5VDC (which differs from step 402 of process 400).

[0099] At step 703, a logic variable or flag called “PTT Pressed” is created which is used to store a detected PTT button press at terminal PTT of the MCU and initially set to FALSE.

[0100] At step 704, a 15-minute timer is configured to automatically and periodically start self-test and is set to expired so that the initial self-test is performed upon powering on and not delayed by 15 minutes. Note that this timer could be as long as 3 hours as allowed by UL943 for auto-monitoring.

[0101] At step 705, the MCU enters into a loop to determine whether a ground fault exists. In this example, this is accomplished by determining whether processed data at ADC IN indicates ground fault OR whether PK DETECT port = LOW.202503320

[0102] If FALSE at 705 (no ground fault exists), then at step 706, the GFCI device determines whether the PTT button is pressed, when the PTT port = LOW.

[0103] If FALSE at 706 (PTT is not pressed), then at step 707, the GFCI device determines whether the timer for self-test has expired (reached 15 minutes in this example).

[0104] If FALSE at 707 (timer has not expired), the process returns to step 705.

[0105] If TRUE at 705 (ground fault exists), then the process proceeds to step 722, below.

[0106] If TRUE at 706 (PTT is pressed), then at step 708, the MCU changes or sets the variable or flag to TRUE and enters test mode by proceeding to START self-test at step 711.

[0107] If TRUE at 707 (timer has expired), then the MCU enters test mode by proceeding to START self-test at step 711.

[0108] At step 711, the GFCI device STARTS a self-test (enters test mode) and proceeds to step 712.

[0109] At step 712, in test mode, the MCU U4 turns on test current for approximately 1 ms to test the ground fault detection circuit, excluding the peak detection circuit, and asserts output port GF TEST = HIGH for approximately 1 ms while monitoring the detection signal output of amplifier U2 GF MON on port ADC IN.

[0110] At step 713, in test mode, the MCU determines whether the test current detected on ADC IN is greater than a predetermined upper threshold OR is less than a predetermined lower threshold in response to setting GF TEST = HIGH during the 1 ms test period.

[0111] If TRUE at step 713, then at step 714, the process delays for approximately 2 millisecond delay before proceeding to step 715.202503320

[0112] If FALSE at step 713, then the process proceeds to step 720B, described below.

[0113] At step 715, after the 2 millisecond delay in step 714, the MCU generates a low test signal by lowering the reference voltage at REF I V5 into the REF terminal of the amplifier U2 below the voltage at REF 0V9 for 1 ms (REF 1V5 is LOW) to test lower limit comparator U3B of the peak detection circuit. This is accomplished by configuring the DAC output to +0.7VDC for 1 ms and then returning to +1.5VDC (differing from step 415 of process 400) while monitoring the output of the peak detection circuit PK DET on port PK DETECT.

[0114] At step 716, the MCU determines whether input port PK DETECT = LOW in response to REF 1V5 = LOW during the 1 ms test period is TRUE.

[0115] If TRUE at step 716 (PK DETECT = LOW in response to REF 1V5 = LOW), then at step 717, the process delays for approximately 2 millisecond delay before proceeding to step 718.

[0116] If FALSE at step 716 (PK DETECT is not LOW in response to REF I V5 = LOW), then the process proceeds to step 720B, described below.

[0117] At step 718, after the 2 millisecond delay in step 717, the MCU generates a high test signal by increasing the reference voltage at REF 1V5 into the REF terminal of the amplifier U2 above the voltage at REF 2V1 for 1 ms (REF I V5 is HIGH) to test upper limit comparator U3A of the peak detection circuit. This is accomplished by configuring the DAC output to +2.2VDC for 1 ms and then returning to +1.5VDC (instead of asserting output port COMP TEST = HIGH for 1 ms and then returning to tri-state as described in step 418 of process 400) while monitoring the output of the peak detection circuit PK DET on port PK DETECT.

[0118] At step 719, the MCU determines whether input port PK DETECT = LOW in response to REF 1V5 = HIGH during the 1 ms test period.202503320

[0119] If FALSE at step 719 (PK DETECT is not LOW in response to REF I V5 = HIGH) then the process proceeds to step 720B, described below.

[0120] If TRUE at step 719 (PK DETECT = LOW in response to REF 1V5 = HIGH) then at step 720A, the MCU determines whether variable or flag called “PTT Pressed” equal to TRUE.

[0121] If TRUE at step 720A (PTT Pressed = TRUE), then self-test passed after initiation by user pressing PTT button SW2 and the process proceeds to step 722, described below.

[0122] If FALSE at step 720A (PTT Pressed is not TRUE), then at step 721, the MCU determines that the self-test was passed after initiation by the expiration of the selftest timer and the MCU is programmed to exit self-test mode and proceed to step 709.

[0123] If FALSE at step 713, FALSE at step 716, or FALSE at step 719 (PK DETECT is not LOW in response to REF 1V5 = HIGH) then at step 720B, the MCU determines whether the variable or flag called “PTT Pressed” equal to TRUE.

[0124] If TRUE at step 720B (PTT Pressed = TRUE), then self-test failed after initiation by user pressing PTT button SW2 and the process proceeds to step 724, described below.

[0125] If FALSE at step 720B (PTT Pressed is not TRUE), then self-test failed and the process proceeds to step 722, described below.

[0126] Note that the PTT test performed at steps 720A and 720B are effectively the same, but the response differs depending on the results of the threshold testing.

[0127] At step 709, after successfully passing self-test, the MCU resets the start of self-test timer before returning to step 705.

[0128] At step 722, the MCU is programmed to assert output port TRIP = HIGH to energize electromagnetic trip mechanism to disconnect power from the load, thereby “tripping” the ground fault detection circuit 102. In the context of FIG. 1, setting TRIP to202503320HIGH activates electromagnetic trip mechanism LI and switch QI to open air-gap contact switch SW1 and disconnect the LINE from the LOAD. After step 722, the GFCI has been tripped, and the process STOPs at step 723.

[0129] At step 724, the MCE can activate a visual or audible alert to indicate that PTT has been pressed and the GFCI device is operating correctly. After step 724, whether or not it is performed, the process STOPs at step 723.

[0130] The exemplary signals of the self-test for GFCI detection device 600 are similar to those shown in FIG. 5.

[0131] Of course, those of skill in the art will recognize that, unless specifically indicated or required by the sequence of operations, certain steps in the processes described above may be omitted, performed concurrently or sequentially, or performed in a different order. Similarly, those of skill in the art will recognize that the specific components, combinations of components, and circuit structures used to describe the exemplary embodiments are not limited to those components and structures, and circuit elements, components, and structures can be replaced by functional equivalents by those of skill in the art and remain within the scope of the claims. The labels used herein for specific signals, nodes, and connections are arbitrary.

[0132] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all circuits and components suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a device as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of the circuits and devices disclosed herein may conform to any of the various current implementations and practices known in the art.

[0133] It is important to note that while the disclosure includes a description in the context of a fully functional device, those skilled in the art will appreciate that at least portions of the mechanism of the present disclosure are capable of being distributed in the form of instructions contained within a machine-usable, computer-usable, or computer-202503320readable medium in any of a variety of forms, including embedded in the microcontrollers and other devices described herein, and that the present disclosure applies equally regardless of the particular type of instruction or signal bearing medium or storage medium utilized to actually carry out the distribution. Examples of machine usable / readable or computer usable / readable mediums include: nonvolatile, hard-coded type mediums such as read only memories (ROMs) or erasable, electrically programmable read only memories (EEPROMs), and user-recordable type mediums.

[0134] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0135] None of the descriptions in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims. Moreover, none of these claims are intended to invoke 35 USC §112(f) unless the exact words "means for" are followed by a participle. The use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “apparatus,” “machine,” “system,” “processor,” or “controller,” within a claim is understood and intended to refer to structures known to those skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.S.C. §112(f).

Claims

202503320CLAIMS1. A ground fault circuit interrupter (GF CI) detection device (100) configured to control delivery of electrical power between SOURCE terminals (SOURCE) and LOAD terminals (LOAD), comprising:a switch (SW1) configured to selectively disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD);a switch control circuit (LI, QI) configured to control the switch (SW1);a ground fault detection circuit (102) connected to control the switch control circuit (LI, QI), the ground fault detection circuit having:a microcontroller (MCU) configured to monitor and detect ground faults and to periodically perform a self-test, the microcontroller (MCU) connected to selectively activate the switch control circuit (LI, QI) to open the switch (SW) and disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD), anda peak detection circuit portion (U3) connected to the microcontroller (MCU), configured to detect ground fault current that is below a first predetermined threshold (REF 0V9) or above a second predetermined threshold (REF 2V1), the peak detection circuit portion (U3) including a lower limit comparator (U3B) and an upper limit comparator (U3A);wherein, to perform the self-test, the microcontroller is configured to:generate (415) a low test signal (COMP TEST=LOW) and determine whether an output of the lower limit comparator (U3B) indicates that the low test signal is below the first predetermined threshold (REF 0V9);generate (418) a high test signal (COMP TEST=HIGH) and determine whether an output of the upper limit comparator (U3A) indicates202503320that the high test signal is above the second predetermined threshold (REF_2V1); andin response to determining that the output of the lower limit comparator indicates that the low test signal is not below the first predetermined threshold OR determining that the output of the upper limit comparator indicates that the high test signal is not above the second predetermined threshold, trigger (422) the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD).

2. The GF CI detection device (100) of claim 1, wherein the low test signal and the high test signal are provided to an amplifier (U2) by the microcontroller and used to generate a detection signal connected to the peak detection circuit portion.

3. The GF CI detection device (100) of claim 1 or 2, wherein the low test signal and the high test signal are generated by a digital-to-analog converter output (DAC OUT) of the microcontroller (MCU).

4. The GFCI detection device (100) of claim 1, 2 or 3, wherein the low test signal and the high test signal are generated by a tri-state output port (COMP TEST) of the microcontroller (MCU) and a voltage divider network (R6, R7, R8).

5. The GFCI detection device (100) of any of the preceding claims 1 to 4, wherein the microcontroller is further configured to detect (420A / 420B) when a push-to-test button (SW2) has been activated, and in response to detecting that the push-to-test button has been activated, to trigger (422) the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD).2025033206. The GFCI detection device (100) of any of the preceding claims 1 to 5, wherein the microcontroller (MCU) is configured to perform the self-test at startup of the GFCI detection device.

7. The GFCI detection device (100) of any of the preceding claims 1 to 6, wherein the microcontroller (MCU) is configured to perform the self-test no more frequently than every 15 minutes.

8. The GFCI detection device (100) of any of the preceding claims 1 to 7, wherein the microcontroller (MCU) is configured to perform the self-test no less frequently than every 3 hours.

9. The GFCI detection device (100) of any of the preceding claims 1 to 8, wherein the low test signal is generated for 1 ms.

10. The GFCI detection device (100) of any of the preceding claims 1 to 9, wherein the high test signal is generated for 1 ms.

11. The GFCI detection device (100) of any of the preceding claims 1 to 10, wherein the microcontroller (MCU) is configured to delay (422) for 2 ms between generating the low test signal and generating the high test signal.

12. The GFCI detection device (100) of any of the preceding claims 1 to 11, wherein when the microcontroller (MCU) determines that the output of the lower limit comparator indicates that the low test signal is below the first predetermined threshold AND determines that the output of the upper limit comparator indicates that the high test signal is above the second predetermined threshold, the microcontroller resets (409) a test timer and resumes normal operation.20250332013. A method (400) for performing self-testing of a GFCI detection device (100) configured to control delivery of electrical power between SOURCE terminals (SOURCE) and LOAD terminals (LOAD), comprising:providing a switch (SW1) configured to selectively disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD); providing a switch control circuit (LI, QI) configured to control the switch (SW1); providing a ground fault detection circuit (102) connected to control the switch control circuit (LI, QI), the ground fault detection circuit having:a microcontroller (MCU) configured to monitor and detect ground faults and to periodically perform a self-test, the microcontroller (MCU) connected to selectively activate the switch control circuit (LI, QI) to open the switch (SW) and disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD), anda peak detection circuit portion (U3) connected to the microcontroller (MCU), configured to detect ground fault current that is below a first predetermined threshold (REF 0V9) or above a second predetermined threshold (REF 2V1), the peak detection circuit portion (U3) including a lower limit comparator (U3B) and an upper limit comparator (U3A);generating (415), by the microcontroller (MCU), a low test signal (COMP TEST=LOW) and determining whether an output of the lower limit comparator (U3B) indicates that the low test signal is below the first predetermined threshold (REF 0V9);generating (418), by the microcontroller (MCU), a high test signal (COMP TEST=HIGH) and determining whether an output of the upper limit comparator (U3A) indicates that the high test signal is above the second predetermined threshold (REF 2V1); andin response to determining that the output of the lower limit comparator indicates that the low test signal is above the first predetermined threshold OR determining that the output of the upper limit comparator indicates that the202503320high test signal is below the second predetermined threshold, triggering (422), by the microcontroller (MCU), the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD).

14. The method (400) of claim 13, further comprising detecting, by the microcontroller (MCU), when a push-to-test button (SW2) has been activated, and in response, triggering (422) the switch control circuit to control the switch to disconnect power between the SOURCE terminals (SOURCE) and the LOAD terminals (LOAD).

15. The method (400) of claim 13 or 14, further comprising, when the microcontroller (MCU) determines that the output of the lower limit comparator indicates that the low test signal is below the first predetermined threshold AND determines that the output of the upper limit comparator indicates that the high test signal is above the second predetermined threshold, resetting (409), by the microcontroller (MCU) a test timer and resuming normal operation.

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