Compensation elements for parasitic capacitance

Abstract

Disclosed herein are compensation elements for parasitic capacitance. In some implementations, a compensation element comprises a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region couples a plasma interaction region of a semiconductor fabrication station to a radio frequency (RF) filter box. The compensation element may comprise a coupling mechanism configured to couple the shunt reactance element between the coupling region and the node.

Description

Docket No. LAM1P116WOCOMPENSATION ELEMENTS FOR PARASITIC CAPACITANCEINCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes.BACKGROUND

[0002] Many semiconductor fabrication apparatuses utilize plasma-based operations which rely on radio frequency (RF) signals provided to the process station or process chamber to strike plasma used to perform the operations (e.g., plasma-based deposition or etching operations). Control of RF power to the station or chamber is important e.g., to control uniformity of the fabrication operations, mitigate wafer defects, etc. However, it can be difficult to achieve optimal conveyance of RF signals.

[0003] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] Disclosed herein are compensation elements for parasitic capacitances.

[0005] In some embodiments, a compensation element for plasma-based semiconductor fabrication stations comprises a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region couples a plasma interaction region of a semiconductor fabrication station to a radio frequency (RF) filter box. The compensation element may comprise a coupling mechanism configured to couple the shunt reactance element between the coupling region and the node.

[0006] In some examples, the coupling region comprises a portion of a pedestal stem that connects the RF filter box to a pedestal of the semiconductor fabrication station. In some examples, the parasitic capacitance is between a path delivering heater power to the pedestalDocket No. LAM1P116WOand the portion of the pedestal stem.

[0007] In some examples, the shunt reactance element comprises at least one capacitor and / or at least one inductor. In some examples, the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

[0008] In some examples, the shunt reactance element is coupled in series with the parasitic capacitance.

[0009] According to some embodiments, a semiconductor fabrication apparatus comprises: a process chamber; a pedestal disposed in the process chamber configured to support a wafer undergoing processing; radio frequency (RF) circuity comprising an RF filter box; a pedestal stem configured to connect the pedestal and the RF filter box; and a compensation element. The compensation element may comprise a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region comprises a portion of the pedestal stem.

[0010] In some examples, the apparatus may further comprise one or more heaters disposed in the pedestal. In some examples, the parasitic capacitance is between a path delivering heater power to the one or more heaters and the portion of the pedestal stem.

[0011] In some examples, the shunt reactance element comprises at least one capacitor and / or at least one inductor. In some examples, the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

[0012] In some examples, the shunt reactance element is coupled in series with the parasitic capacitance.

[0013] Other aspects and advantages of the disclosures herein will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate by way of example the principles of the disclosures.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a simplified schematic cross-sectional diagram showing a plasma processing system used for deposition operations, in accordance with one embodiment.

[0015] FIG. 2A and 2B illustrate an ideal implementation of a filter in connection with a process chamber in accordance with some embodiments.

[0016] FIG. 3A and 3B illustrate a parasitic capacitance associated with an actual filter implementation and the effects of the parasitic capacitance.

[0017] FIG. 4A is a block diagram of an ideal implementation of an RF blocking filter inDocket No. LAM1P116WOaccordance with some embodiments.

[0018] FIG. 4B is a block diagram that illustrates the system shown in FIG. 4A and a parasitic circuit associated with a portion of a process chamber.

[0019] FIG. 5 is a block diagram of a system that includes a compensation element in accordance with some embodiments.

[0020] FIG. 6 is a diagram that illustrates one example implementation of a compensation element in accordance with some embodiments.DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the example embodiments. However, it will be apparent to one skilled in the art that the example embodiments may be practiced without some of these specific details. In other instances, process operations and implementation details have not been described in detail, if already well known.

[0022] FIG. 1 is a simplified schematic cross-sectional diagram showing a plasma processing system used for deposition operations, in accordance with one embodiment. The plasma processing system 100 includes a chamber 102 in which a gas distribution showerhead 104, which has a plurality of openings 104a through which process gases can flow, and a substrate support 106 are disposed. The chamber 102 has a processing region 108 that is located between the showerhead 104 and the substrate support 106. For a plasma enhanced chemical vapor deposition (PECVD) process, the substrate support 106 can be a pedestal for supporting a substrate, e.g., a wafer, during deposition. Heaters 110 are provided in the substrate support 106 to heat the substrate, with each heater being coupled to a heater power controller 112. One end portion of radio frequency (RF) input rod 114 is coupled to substrate support 106 to provide RF power to an electrode that forms part of the substrate support, e.g., pedestal. The other end portion of RF input rod 114 is connected to a thermal choke rod 116, which includes an annular cap 116a.

[0023] A radio frequency (RF) strap 118 is also connected to thermal choke rod 116. The RF strap 118 is coupled to impedance matching network 120 via a suitable wire connector. Radio frequency (RF) generator system 122, which includes one or more RF generators, is coupled to impedance matching network 120 via a suitable wire connector. In operation, RF generator system 122 generates an RF signal that is transmitted to an input of impedance matching network 120. The impedance matching network 120 matches the impedance of a load coupled to an output of the matching network with the impedance of a source coupled to an input of theDocket No. LAM1P116WOmatching network and generates a modified RF signal. The modified RF signal is transmitted from the impedance matching network 120 to the thermal choke rod 116 via the wire connector and the RF strap 118. The modified RF signal (RF current) is then conducted, for the most part, along the outer surface of the thermal choke rod 116 and is transmitted to the RF input rod 114 via the electrical connection created where the thermal choke rod contacts the RF input rod. RF input rod 114 may be within a pedestal stem (not shown in FIG. 1) that connects to a base of substrate support 106. The pedestal stem may also include a path of providing heater power to the pedestal. Note that heater power signals may be AC or DC signals.

[0024] A parasitic capacitance may exist between a coupling region and a node. For example, the coupling region may couple a plasma interaction region of a semiconductor fabrication station or chamber to an RF filter box. For example, the RF filter box may prevent RF signals from reaching a heater power controller. For example, an RF filter may be between heater power controller 112 and substrate support 106 in FIG. 1, and may function to prevent RF signals from reaching heater power controller 112. As a more particular example, in the system shown in FIG. 1, the coupling region may include a portion of a pedestal stem that connects an RF filter box to a pedestal of the semiconductor station, as shown in and described above in connection with FIG. 1. In the example shown in FIG. 1, the plasma interaction region may include portions of processing region 108 above substrate support 106. Continuing with this example, the parasitic capacitance may be between a path delivering heater power to the pedestal and the portion of the pedestal stem. The parasitic capacitance may create issues, particularly at relatively high RF operating frequencies (e.g., at RF frequencies above 13 MHz, above 27 MHz, etc.). In particular, while an RF filter may be configured to block RF signals from reaching a non-RF signal source (e.g., as shown in and described below in connection with FIG. 2A), due to the parasitic capacitance, current may flow through the parasitic circuit which reduces the RF power to the station. This may cause non-uniformities that are difficult or impossible to control in the wafer undergoing plasma-based operations.

[0025] Disclosed herein are compensation elements for compensating the shunt parasitic capacitance. The compensation element may include a shunt reactance element that has a reactance value that is approximately an additive inverse of a reactance associated with the parasitic capacitance. Note that “approximately” as used herein may be mean “substantially equivalent to,” or within a predetermined percentage of similarity (e.g., within + / - 1%, within + / - 5 %, etc.). The compensation element may be coupled between the coupling region associated with the parasitic capacitance such that the compensation element and the parasitic capacitance are both to the same node (e.g., electrical ground). Referring to FIG. 1, theDocket No. LAM1P116WOcompensation element may be anywhere between the path of heaters 110 disposed in the substrate support 106 and heater power controller 112. In some embodiments, the compensation element may be part of a heater power controller (e.g., heater power controller 112 of FIG. 1). The compensation element may include a reactance element, such as one or more capacitors and / or one or more inductors. In some cases, the compensation element may include passive elements such as one or more transformers and / or resistors.

[0026] For some context, “impedance” is composed of a real part (referred to as “resistance”) and an imaginary part (referred to as “reactance”). The imaginary part, reactance, is dependent on frequency. The reactance of a capacitor having a capacitance C may be determined using 1the equation: X = — , where / refers to the frequency in Hertz. Similarly, the reactanceof an inductor having an inductance L may be determined using the equation X = 2nfL. A reactive element, such as a capacitor or an inductor, will also have a real resistance such that the impedance of the reactive element is a combination of the real resistance and the imaginary reactance. However, as per design intent, the real resistance is minimized and may be negligible. Accordingly, in the techniques disclosed herein, the impedance associated with the parasitic capacitance and the compensation element is generally discussed in terms of the imaginary reactance.

[0027] Although not shown in FIG. 1, a plasma processing system may have an RF blocking filter configured to block RF from reaching non-RF signal source. This RF blocking filter may be between heater power controller 112 and substrate support 106, and may function to prevent RF signals from reaching heater power controller 112 in the system shown in FIG. 1. FIG. 2A illustrates a portion of such a plasma processing system in an ideal case. As illustrated, chamber 202 (which may include one or more process stations) is operatively coupled to RF blocking filter 204 via at least wiring 206. For example, wiring 206 may operatively coupled RF blocking filter 204 to a pedestal disposed in chamber 202 (or within a station of chamber 202). RF blocking filter 204 is illustrated in FIG. 2 A as a lumped-element circuit comprising an inductor and a capacitor in parallel.

[0028] FIG. 2B illustrates the ideal behavior of RF blocking filter 204 as shown in FIG. 2A. The plot in FIG. 2B illustrates the input impedance of the RF blocking filter as well as the S21 scattering parameter as a function of frequency. The S21 scattering parameter corresponds to the forward power of RF signal through the RF blocking filter 204. Note that in the ideal scenario illustrated in FIGS. 2A and 2B (i.e., a scenario without any parasitic capacitances), the frequency where the impedance is at a maximum and at which the S21 parameter is at aDocket No. LAM1P116WOminimum are aligned at frequency 252. Frequency 252 corresponds to an operating frequency of the RF source, e.g., at 14 MHz, 27 MHz, 40 MHz, etc. The S21 parameter being at a minimum corresponds to ideal behavior of the RF blocking circuit, as the S21 parameter corresponds to the forward delivered signal and indicates RF signal being entirely or almost entirely blocked. The impedance being at a maximum at frequency 252 corresponds to the Sil scattering parameter, or the reflection scattering parameter, being high at frequency 252. In this case, the measured impedance Z is effectively directly equivalent to the series impedance responsible for the dip in transmission indicated in the S21 parameter plus the termination impedance of the port measurement device. Because the Sil input impedance is at a maximum, the current applied to the RF blocking filter must be at a minimum per Ohm’s Law, and therefore, the dissipation in the upstream circuit is also relatively low.

[0029] FIGS. 2 A and 2B illustrate an ideal implementation of an RF blocking filter with no parasitic capacitances in the system. However, in actual systems, a parasitic shunt capacitance will be present in parallel to the RF blocking filter. This has the effect of altering the Sil reflection scattering parameter in a non-ideal manner. In particular, the maximum impedance of an actual system with a parasitic shunt capacitance is shifted such that the maximum impedance occurs at a lower frequency than the operating frequency of the system, (assuming that in the limit the parasitic shunt capacitance appears capacitive due to lack of transmission line effects). This results in reduced impedance at the drive frequency, which leads to increased RF current into the RF filter circuit path, which in turn causes power loss in the path between the plasma reactor and the RF filter according to P = I2R.. In other words, this decreases efficacy of the plasma operations occurring in the associated process station or process chamber. Moreover, because the effect of the parasitic shunt capacitance is not intended as part of the filter assembly, it may vary based on the specifics of the wiring used to operatively coupled the chamber to the RF blocking filter, the reflected RF power may vary in ways that are unknown, which causes downstream negative effects on wafers undergoing plasma-based operations within the process station or process chamber.

[0030] FIGS. 3A and 3B are diagrams which depict the effects of a parasitic shunt capacitance. FIG. 3A illustrates a parasitic shunt capacitance 302 which is in parallel with RF blocking filter 204. Together, parasitic shunt capacitance 302 and RF blocking filter 204 behave as a lumped reactive circuit with the characteristics illustrated in FIG. 3B. As illustrated, while the S21 parameters remain at a minimum at operating frequency 252 (representing complete or near complete filtering of RF at the operating frequency), the peak of the impedance has shifted lower, to frequency 352. Note that frequency 352 is lower than operating frequency 252,Docket No. LAM1P116WOcorresponding to a decrease in the Sil, or reflection, parameters. This in turn causes reduced RF power, which causes problems for wafers undergoing plasma-based processing operations.

[0031] The examples shown in FIGS. 2A and 3A relate to processing apparatuses in which the pedestal receives RF power (e.g., as shown in the processing system depicted in FIG. 1). However, the techniques disclosed herein may be broadly applicable to any processing system that provides RF, whether to a pedestal, showerhead, or the like. FIGS. 4 A and 4B are similar to FIGS. 2 A and 3 A, but generalize the concepts shown in FIGS. 2 A and 3 A, respectively, to other types of systems other than ones in which RF signals are delivered to a pedestal. Other applications which could suffer loss due to unwanted RF current in the filtered path may also benefit from the compensation elements described herein.

[0032] FIG. 4A illustrates an ideal implementation of an RF blocking filter 404 between an RF plasma interaction region 402 and a non-RF signal source 406. As illustrated, ideally, the RF blocking filter 404 fully blocks RF signals at a given frequency (e.g., an operating frequency, such as 27 MHz, 40 MHz, 100 MHz, etc.) from being passed through to the non-RF signal source, whereas other signals may pass through. The other signals, represented as “signals” in FIG. 4A, may include heater power signals, thermocouple signals, etc. The signals that pass through may include AC signals, DC signals, or the like.

[0033] FIG. 4B illustrates an actual implementation of RF blocking filter 404. As illustrated, a parasitic circuit 408 exists in parallel with RF blocking filter 404. While RF blocking filter 404 continues to block RF signals, due to parasitic circuit 408, some current passes through parasitic circuit 408 (i.e., the parasitic shunt capacitance shown in and described above in connection with FIGS. 3 A and 3B), which reduces the RF power available in RF plasma interaction region 402, often in unpredictable ways.

[0034] Disclosed herein is a compensation element which compensates for the impedance of the parasitic shunt circuit (e.g., a parasitic shunt capacitance). In particular, the compensation element is configured to have a reactance that is approximately an additive inverse of a reactance associated with the parasitic capacitance at a particular operating frequency. By way of example, in an instance in which the parasitic shunt capacitance has a value of C = 100 pF at 27 MHz (e.g., where the RF generator is providing a 27 MHz signal), the reactance is X = -58. In particular, the reactance may be determined as:1X = - 7- 2nfC

[0035] Accordingly, the compensation element may be one that has a reactance of X = +58, effectively canceling the reactance of the parasitic capacitance. In one example, theDocket No. LAM1P116WOcompensation element may be an inductor having a value of approximately L = 347 nH, where the reactance is determined by:X = 2 fL

[0036] Note that, the reactance of the compensation element may be approximately the determined value, e.g., the reactance may be within + / - 1% of the determined value, + / - 5% of the determined value, + / - 10% of the determined value, etc.

[0037] In some implementations, the compensation element may be any suitable combination of capacitors and / or inductors. Note that the value of the parasitic capacitance is measured. The values of capacitors and / or inductors which make up the compensation element may be tuned based on the measured parasitic capacitance. For example, in some embodiments, the value of the parasitic capacitance may be measured after a system is fully built, e.g., to account for lengths of couplings between various system elements which contribute to the parasitic capacitance. In some implementations, a value of a parasitic capacitance may be determined using modeling, e.g., by modeling the parasitic capacitance as a capacitor and simulating effects of the parasitic capacitance as part of a circuit at different frequencies. Continuing with this example, the compensation element may be tuned based on the measured parasitic capacitance. In some implementations, a compensation element may consist of one or more variable capacitors and / or variable inductors which may be tuned based on measured parasitic capacitance. Additionally, such elements may be tuned based on an operating frequency, because the value of the parasitic capacitance is dependent on the operating frequency.

[0038] FIG. 5 is a block diagram of an example system that includes a compensation element in accordance with some embodiments. As illustrated, compensation element 502 is in parallel with parasitic circuit 408. As described above, compensation element 502 may comprise any suitable circuit elements that provide a reactance that is approximately an additive inverse of the reactance of parasitic circuit 408 at a particular operating frequency. As illustrated in FIG.5, due to compensation element 502, at the operating frequency, there may be a substantially reduced magnitude of current to ground through parasitic circuit 408. For example, in the diagram shown in FIG. 4B, there may be substantial current through parasitic circuit 408 (e.g., greater than 5 Amps, greater than 10 Amps, etc.), whereas in the implementation shown in FIG.5, due to the compensation element, the sum of current through parasitic circuit 408 and compensation element 502 may be substantially reduced, e.g., to less than 200 mill-Amps, to less than 100 milli-Amps, to less than 50 milli-Amps, etc. Note that compensation element 502 causes an equal and opposite current to flow through compensation element 502 relative to the current through parasitic circuit 408 in an ideal implementation.Docket No. LAM1P116WO

[0039] It should be noted that the effect of the compensation element shown in FIG. 5 may be to shift the peak of the impedance to a frequency that is more aligned with the operating frequency. For example, without the compensation element described herein, the peak of the impedance may be at a frequency that is lower than the operating frequency, as shown in and described above in connection with FIG. 3. With inclusion of the compensation element, the effect of the compensation element may be to shift the peak of the impedance to a frequency that is closer to the operating frequency. In some cases, the effect of the compensation element may be to shift the peak of the impedance to a frequency that is within, e.g., + / - 1%, + / -%5, etc. of the operating frequency. As described above in connection with FIG. 3, such a shift in the peak of the impedance indicates improved power delivery.

[0040] FIG. 6 illustrates an example implementation of a compensation element in accordance with some embodiments. FIG. 6 illustrates the parasitic capacitance depicted in FIG. 3 A, with an example implementation of compensation element 602. Compensation element 602 comprises an inductor, which, as described above, has a reactance that is approximately an additive inverse of the capacitance associated with parasitic capacitance 302. Although compensation element 602 is depicted as one inductor, other implementations are possible, such as multiple inductors, one or more capacitors in series with the inductor, one or more passive elements (e.g., one or more transformers), or any combination thereof.

[0041] The compensation elements described herein may be of increasing usefulness at increasing RF operating frequencies. In particular, due to the dependence on frequency for the value of the reactance associated with a parasitic capacitance, the compensation element described herein is of increasing importance at higher RF operating frequencies. For example, operating frequencies above, e.g., 40 MHz may simply not be operable without some compensating element to cancel the parasitic capacitance. Accordingly, the techniques and circuits described herein enable operating frequencies of above 27 MHz (e.g., 40 Mhz, 60 MHz, 100 MHz, etc.).

[0042] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.Docket No. LAM1P116WO

[0043] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0044] With the above embodiments in mind, it should be understood that the embodiments can employ various computer-implemented operations involving data stored in computer systems. These operations are those requiring physical manipulation of physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations. The embodiments also relates to a device or an apparatus for performing these operations. The apparatus may be specially constructed for the required purpose, such as a special purpose computer. When defined as a special purpose computer, the computer can also perform other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose. Alternatively, the operations may be processed by a general purpose computer selectively activated or configured by one or more computer programs stored in the computer memory, cache, or obtained over a network. When data is obtained over a network the data may be processed by other computers on the network, e.g., a cloud of computing resources.

[0045] One or more embodiments can also be fabricated as computer readable code on a computer readable medium. The computer readable medium is any data storage device that can store data, which can be thereafter be read by a computer system. Examples of the computer readable medium include hard drives, network attached storage (NAS), read-only memory, random-access memory, CD-ROMs, CD-Rs, CD-RWs, magnetic tapes and other optical and non-optical data storage devices. The computer readable medium can include computer readable tangible medium distributed over a network-coupled computer system so that the computer readable code is stored and executed in a distributed fashion.

[0046] Although the method operations were described in a specific order, it should be understood that other housekeeping operations may be performed in between operations, or operations may be adjusted so that they occur at slightly different times, or may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of the overlay operations are performed in the desired way.

[0047] Example Embodiments:Docket No. LAM1P116WO

[0048] Embodiment 1: A compensation element for plasma-based semiconductor fabrication stations, comprising: a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region couples a plasma interaction region of a semiconductor fabrication station to a radio frequency (RF) filter box; and a coupling mechanism configured to couple the shunt reactance element between the coupling region and the node.

[0049] Embodiment 2: The compensation element of embodiment 1, wherein the coupling region comprises a portion of a pedestal stem that connects the RF filter box to a pedestal of the semiconductor fabrication station.

[0050] Embodiment 3: The compensation element of embodiment 2, wherein the parasitic capacitance is between a path delivering heater power to the pedestal and the portion of the pedestal stem.

[0051] Embodiment 4: The compensation element of any one of embodiments 1-3, wherein the shunt reactance element comprises at least one capacitor and / or at least one inductor.

[0052] Embodiment 5: The compensation element of embodiment 4, wherein the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

[0053] Embodiment 6: The compensation element of any one of embodiments 1-5, wherein the shunt reactance element is coupled in series with the parasitic capacitance.

[0054] Embodiment 7: A semiconductor fabrication apparatus, comprising: a process chamber; a pedestal disposed in the process chamber configured to support a wafer undergoing processing; radio frequency (RF) circuity comprising an RF filter box; a pedestal stem configured to connect the pedestal and the RF filter box; and a compensation element. The compensation element comprises: a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region comprises a portion of the pedestal stem.

[0055] Embodiment 8: The semiconductor fabrication apparatus of embodiment 7, further comprising one or more heaters disposed in the pedestal.

[0056] Embodiment 9: The semiconductor fabrication apparatus of embodiment 8, wherein the parasitic capacitance is between a path delivering heater power to the one or more heaters and the portion of the pedestal stem.

[0057] Embodiment 10: The semiconductor fabrication apparatus of embodiment 9, wherein the path delivering heater power comprises a heater power controller, and wherein the RF filterDocket No. LAM1P116WObox is configured to block RF signals from the heater power controller.

[0058] Embodiment 11: The semiconductor fabrication apparatus of embodiment 10, wherein the compensation element is operatively coupled to the heater power controller.

[0059] Embodiment 12: The semiconductor fabrication apparatus of any one of embodiments 7-11, wherein the shunt reactance element comprises at least one capacitor and / or at least one inductor.

[0060] Embodiment 13: The semiconductor fabrication apparatus of embodiment 12, wherein the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

[0061] Embodiment 14: The semiconductor fabrication apparatus of embodiment 7, wherein the shunt reactance element is coupled in series with the parasitic capacitance.

[0062] Accordingly, the disclosure of the example embodiments is intended to be illustrative, but not limiting, of the scope of the disclosures, which are set forth in the following claims and their equivalents. Although example embodiments of the disclosures have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the following claims. In the following claims, elements and / or steps do not imply any particular order of operation, unless explicitly stated in the claims or implicitly required by the disclosure.

Claims

Docket No. LAM1P116WOCLAIMSWhat is claimed is:

1. A compensation element for plasma-based semiconductor fabrication stations, comprising:a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region couples a plasma interaction region of a semiconductor fabrication station to a radio frequency (RF) filter box; anda coupling mechanism configured to couple the shunt reactance element between the coupling region and the node.

2. The compensation element of claim 1, wherein the coupling region comprises a portion of a pedestal stem that connects the RF filter box to a pedestal of the semiconductor fabrication station.

3. The compensation element of claim 2, wherein the parasitic capacitance is between a path delivering heater power to the pedestal and the portion of the pedestal stem.

4. The compensation element of any one of claims 1-3, wherein the shunt reactance element comprises at least one capacitor and / or at least one inductor.

5. The compensation element of claim 4, wherein the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

6. The compensation element of any one of claims 1-3, wherein the shunt reactance element is coupled in series with the parasitic capacitance.

7. A semiconductor fabrication apparatus, comprising:a process chamber;a pedestal disposed in the process chamber configured to support a wafer undergoing processing;radio frequency (RF) circuity comprising an RF filter box;a pedestal stem configured to connect the pedestal and the RF filter box; andDocket No. LAM1P116WOa compensation element comprising:a shunt reactance element having a reactance value that is approximately an additive inverse of a reactance associated with a parasitic capacitance between a coupling region and a node, wherein the coupling region comprises a portion of the pedestal stem.

8. The semiconductor fabrication apparatus of claim 7, further comprising one or more heaters disposed in the pedestal.

9. The semiconductor fabrication apparatus of claim 8, wherein the parasitic capacitance is between a path delivering heater power to the one or more heaters and the portion of the pedestal stem.

10. The semiconductor fabrication apparatus of claim 9, wherein the path delivering heater power comprises a heater power controller, and wherein the RF filter box is configured to block RF signals from the heater power controller.

11. The semiconductor fabrication apparatus of claim 10, wherein the compensation element is operatively coupled to the heater power controller.

12. The semiconductor fabrication apparatus of any one of claims 7-11, wherein the shunt reactance element comprises at least one capacitor and / or at least one inductor.

13. The semiconductor fabrication apparatus of claim 12, wherein the at least one capacitor is a variable capacitor and / or wherein the at least one inductor is a variable inductor.

14. The semiconductor fabrication apparatus of any one of claims 7-11, wherein the shunt reactance element is coupled in series with the parasitic capacitance.

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