Fine resolution, high dynamic range, and low phase variation temperature compensated digital step attenuator

Abstract

Apparatus is provided to reduce phase variation across attenuation settings. A plurality of attenuator cells are coupled in cascade between an attenuator input and an attenuator output to provide binary-weighted attenuation steps. Each attenuator cell includes a T-type attenuation cell having a first shunt resistor coupled to a ground reference, and a Pi-type attenuation cell having a series resistor coupled in series between a Pi-type attenuation cell input and a Pi-type attenuation cell output, a second shunt resistor and a third shunt resistor each electrically coupled to the ground reference, a second phase-compensating capacitor, and a third phase-compensating capacitor. In one embodiment, the first T-type attenuator cell further comprises a first phase-compensating capacitor electrically coupled in parallel with the first shunt resistor. SOI switch transistors are back gate biased with a temperature-dependent bias to reduce ON-resistance variation and reduce attenuation / phase variation across temperature.

Description

KI I-012-PCT PATENTFINE RESOLUTION, HIGH DYNAMIC RANGE, AND LOW PHASE VARIATION TEMPERATURE COMPENSATED DIGITAL STEP ATTENUATORCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U. S. C.§119 from U. S. Provisional Application Number 63 / 764, 716 entitled " Fine Resolution, High Range, and Low Phase Variation Gain Compensated Digital Step Attenuator, " filed on Feb. 28, 2025, the subject matter of which is incorporated herein by reference.TECHNICAL FIELD

[0002] This disclosure generally relates to a high dynamic range, fine resolution, and temperature compensated digital step attenuator, which can be used in beamforming integrated circuits.BACKGROUND

[0003] In wireless communication systems, beamforming integrated circuits (BFIC) are used to provide electronic phase shifting and amplitude adjustment for electronic steered phased arrays. Current BFICs may use several active variable gain amplifiers that consume significant energy while not achieving the required phase gain orthogonality. Alternately, BFICs may use a digital step attenuator as a passive variable gain block. Traditional digital step attenuators may incorporate multiple unit attenuator cells cascaded with binary-weighted gain steps. However, these traditional digital step attenuators have large phase variation over gain states in addition toKI I-012-PCT PATENThaving large variations of gain, differential non-linearity, and integral non-linearity versus temperature.

[0004] There is a need for an improved digital step attenuator that addresses these issues.SUMMARY

[0005] A high dynamic range, fine resolution, and temperature compensated digital step attenuator for use in beamforming applications and a method of designing such an attenuator is provided. In one novel aspect, one or more phase-compensating capacitors are used to attenuate a signal with reduced phase variation.

[0006] Aspects of the present disclosure provide an attenuator and a method for attenuating a signal with reduced phase variation. In one aspect, an attenuator includes an attenuator input, an attenuator output, and a plurality of attenuator cells coupled in cascade between the input and the output. The cells are configured to provide binary-weighted attenuation steps. The plurality of attenuator cells includes a first T-type attenuator cell having a first shunt resistor coupled to a ground reference. The plurality of cells further includes a Pi-type attenuator cell having a series resistor coupled in series between a cell input and a cell output, along with a second shunt resistor and a third shunt resistor coupled to the ground reference. The Pi-type attenuation cell includes a second phase-compensating capacitor electrically coupled across the second shunt resistor and a third phasecompensating capacitor electrically coupled across the third shunt resistor. In one embodiment, the first T-type attenuator further comprises a first phase-compensatingKI I-012-PCT PATENTcapacitor electrically coupled in parallel with the first shunt resistor.

[0007] In some embodiments, the first phase-compensating capacitor is coupled in parallel with the first shunt resistor. Similarly, the second and third phasecompensating capacitors may be coupled in parallel with the second and third shunt resistors, respectively.

[0008] According to some aspects, the binary-weighted attenuation step provided by the first T-type attenuator cell is smaller than the step provided by the Pi-type attenuator cell. Furthermore, the plurality of attenuator cells may include a second T-type attenuator cell configured to provide a binary-weighted attenuation step that is smaller than that of the first T-type attenuation cell (e. g., a fine-resolution or LSB step), wherein the second T-type attenuator cell omits a phase-compensating capacitor.

[0009] In certain embodiments, the first T-type attenuator cell includes a first shunt transistor coupled in series with the first shunt resistor to the ground reference. The first shunt transistor is configured to be turned off in a reference state and turned on in an attenuation state. The Pi-type attenuator cell may include a series transistor coupled in parallel with the series resistor, and a pair of second shunt transistors coupled in series with the second and third shunt resistors, respectively, to the ground reference. In the reference state, the series transistor is turned on and the pair of second shunt transistors are turned off. In the attenuation state, these states are inverted.

[0010] In some implementations, the transistors are silicon-on-insulator (SOI ) transistors. The attenuator mayKI I-012-PCT PATENTfurther include a back gate bias circuit configured to apply respective back gate biasing voltages to the transistors. These back gate biasing voltages may decrease as temperature increases using a complementary-to-absolute-temperature (CTAT) source, thereby applying higher voltages at lower temperatures and lower voltages at higher temperatures. This control mitigates variation of ON resistance (RON) to minimize attenuation and phase variation across temperature.

[0011] In further embodiments, at least two of the attenuator cells are electrically coupled via an inductor to provide impedance matching.

[0012] According to another aspect, a method for attenuating a signal is provided. The method includes propagating the signal through a plurality of cascaded attenuator cells and controlling the cells to apply discrete attenuation steps by selectively setting each cell to a reference state or an attenuation state. The method involves utilizing a first attenuator cell with a phasecompensating capacitor coupled across a shunt resistor to reduce phase difference between states, and utilizing a second attenuator cell with at least one phase-compensating capacitor coupled across a corresponding shunt resistor to reduce phase difference between states.

[0013] In some method embodiments, the first cell is a T-type attenuation cell and the second cell is a Pi-type attenuation cell. The method may further include using a fine-resolution T-type attenuation cell that omits a phasecompensating capacitor when its phase difference is below a predetermined threshold. The method may also involve stabilizing transistor performance by generating CTAT-basedKI I-012-PCT PATENTback gate biasing voltages and applying them to the back gate terminals of SOI switching transistors.

[0014] Other embodiments and advantages are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Fig. 1 illustrates an exemplary diagram of an attenuator that includes phase-compensated attenuation cells configured to provide reduced phase variation across attenuation settings.

[0016] FIG. 2A illustrates an exemplary diagram for multibit ( 8-bit ) digital step attenuator including a plurality of attenuator cells coupled in cascade between an input and an output.

[0017] FIG. 2B illustrates exemplary diagrams for a simplified T-type attenuator cell and corresponding reference and attenuation state representations.

[0018] FIG. 2C illustrates exemplary diagrams for a Pi-type attenuator cell and corresponding reference and attenuation state representations.

[0019] FIG. 3 illustrates exemplary diagrams for transistor structure and operating concepts used to reduce temperature-driven variation by employing silicon-on-insulator ( SOI ) devices with back gate bias capability.

[0020] FIG. 4 is a chart showing implementation results demonstrating the performance of the attenuator across a wide temperature range when utilizing the back gate biasing techniques described herein.

[0021] FIG. 5 illustrates an exemplary diagram for back gate bias voltage generation by different transistors.KI I-012-PCT PATENT

[0022] FIG. 6 is a flow chart for attenuating a signal with reduced phase variation across attenuation settings with a high dynamic range, fine resolution, and temperature compensated for an attenuator.DETAILED DESCRIPTION

[0023] Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0024] Embodiments described herein provide a digital step attenuator featuring fine resolution, high dynamic range, and ultra-low phase variation across attenuation states, making it particularly suitable for use in a variable gain block within a Beamforming IC (BFIC). In an exemplary implementation, the improved digital step attenuator provides a resolution of better than 0.5 dB, a dynamic range of greater than 30 dB, and a phase variation of less than 2-degrees. Notably, the attenuator maintains this performance stability across an ambient temperature range from -40 °C to 125 °C. When utilized within a BFIC, these characteristics contribute to improved side lobe levels, thereby enabling high-fidelity beamforming.

[0025] To achieve extremely low phase variation across gain states, the digital step attenuator includes phasecompensating capacitors coupled across selected attenuation cells (e. g., coarse attenuation steps ). In some embodiments, the phase variation is maintained at less than 1.5 degrees across a 32 dB attenuation range. This ultralow phase variation allows BFIC to achieve side lobe re jection without necessitating complex phase calibration.

[0026] In addition to minimizing phase variation, the disclosed attenuator significantly mitigates temperature-KI I-012-PCT PATENTdependent attenuation variation, for example, reducing the typical variation of 6 dB to less than 1 dB across the full temperature range, -40 °C to 125 °C. This stability is achieved by controlling the threshold voltages of the series and shunt transistors within each attenuation cell via back gate control. This mechanism mitigates the variation of ON-resistance (RON), which in turn minimizes both attenuation and phase variation across temperature.

[0027] Fig. 1 illustrates an exemplary diagram of an attenuator that includes phase-compensated attenuation cells configured to provide reduced phase variation across attenuation settings. The exemplary attenuator includes a simplified T-type attenuator cell 101 and a Pi-type attenuator cell 102. A set of phase-compensating capacitors (Ccomp) 110 is shown conceptually and includes individual capacitors, such as Ccomp 111, 112, and 113, placed across respective shunt resistors of the cells.

[0028] The T-type attenuator cell 101 includes a T-type attenuation cell input 161, a T-type attenuation cell output 162, and a first shunt resistor 121 that is electrically coupled to the ground reference and a first phase-compensating capacitor 111. The first phasecompensating capacitor 111 is electrically coupled in parallel with the first shunt resistor 121. The T-type attenuator cell 101 may also include a first shunt transistor 131, which is in series with the first shunt resistor 121 and electrically coupled to the ground reference. The phase-compensating capacitor 111 is chosen to minimize the phase difference between the attenuation state and the reference state. If the phase difference between the attenuation state and the reference state isKI I-012-PCT PATENTbelow a threshold phase difference, a compensation capacitor is not needed.

[0029] The Pi-type attenuator cell 102 includes a series resistor 141 in series with a Pi-type attenuation cell input 171 and a Pi-type attenuation cell output 172. It also includes a second shunt resistor 122 and a third shunt resistor 123, both of which are electrically coupled to the ground reference. The Pi-type attenuator cell 102 also has a second phase compensating capacitor 112 and a third phase compensating capacitor 113. The second phase-compensating capacitor 112 may be electrically coupled in parallel with second shunt resistor 122, and the third phase-compensating capacitor 113 may be electrically coupled in parallel with third shunt resistor 123. The phase-compensating capacitors are chosen to minimize the phase difference between the attenuation state and the reference state. I f the phase difference between the attenuation state and the reference state is below a threshold phase difference, a compensation capacitor is not needed.

[0030] The Pi-type attenuator cell 102 may also include a series transistor 151 and a pair of second shunt transistors 132 and 133. In another embodiment, transistors 132 and 133 can be a single transistor. The series transistor 151 is in series with the Pi-type attenuation cell input and 171 and the Pi-type output 172, and parallel with the series resistor 141. The pair of second shunt transistors 132 and 133 are in series with the second shunt resistor 122 and the third shunt resistor 123 as well as being electrically coupled to the ground reference.

[0031] In an exemplary control scheme, in a reference state of the Pi-type attenuation cell 102, the series transistorKI I-012-PCT PATENT151 is turned on, there is a low resistance, and the shunt transistors 132 and 133 are turned off, there is a large resistance and thereby, providing a low-loss path (e. g., bypassing the series resistor 141 ) while the shunt branches are inactive. In an attenuation state, the series transistor 151 is turned off and the shunt transistors 132 and 133 are turned on, thereby inserting the resistive Pi network ( including the series resistor 141 and shunt resistors 122, 123 ) while the phase-compensating capacitors 112, 113 reduce phase change between the states. As illustrated, the first phase-compensating capacitor 111 is configured to reduce a phase difference between the reference and attenuation states of the T-type attenuation cell 101; and the second and third phase-compensating capacitors 112, 113 are configured to reduce a phase difference between the reference and attenuation states of the Pi-type attenuation cell 102.

[0032] FIG. 2A illustrates an exemplary diagram for multibit ( 8-bit ) digital step attenuator including a plurality of attenuator cells coupled in cascade between an input and an output. The plurality of attenuator cells includes both a fine attenuator cell and a coarse attenuator cell, with the fine attenuator cell having a lower attenuation value than the coarse attenuator cell. In one embodiment, the fine attenuator cell comprises the first T-type attenuator cell while the coarse attenuator cell comprises the Pi-type attenuator cell. Both the first T-type attenuator cell and the Pi-type attenuator cells have a phase compensation cap.

[0033] In another embodiment, the first T-type attenuator cells are finer steps than the Pi-type attenuator cells. In a third embodiment, the fine attenuator cell may have an attenuation value less than or equal to 1dB, while theKI I-012-PCT PATENTcoarse attenuator cell has an attenuation value greater than 1dB.

[0034] The plurality of attenuator cells may also include a second T-type attenuator cell. The attenuation value of the second T-type attenuator cell is lower than the first T type attenuator cell. For example, the attenuation value of the second T-type attenuator cell may be less than or equal to 0.5 dB. As a second example, the attenuation value of the second T-type attenuator may be 0. 125 dB.

[0035] An exemplary 8-bit attenuator is illustrated. The exemplary attenuator has 31. 875 dB gain range and 0. 125 dB steps with 256 attenuation steps. A plurality of attenuators, 201-208, are coupled in cascade between an attenuator input 211 and an attenuator output 212. As an example, attenuator input 211 impedance is 100-ohm differential, and attenuator output 212 impedance is 100-ohm differential. The attenuator is configured to include BIT2 cell 201 configured as a T-type cell providing a 0.5 dB step; BIT6 cell 202 configured as a Pi-type cell providing an 8 dB step; An LSB cell 203 configured as a T-type cell providing a 0. 125 dB step; BIT4 cell 204 configured as a Pi-type cell providing a 2 dB step; BIT3 cell 205 configured as a T-type cell providing a 1 dB step; BIT5 cell 206 configured as a Pi-type cell providing a 4 dB step; BIT1 cell 207 configured as a T-type cell providing a 0. 25 dB step; MSB cell 208 configured as a Pi-type cell providing a 16 dB step. The above step magnitudes collectively provide fine resolution (e. g., including a 0. 125 dB least-significant-bit stage ) and a large overall range (e. g., approximately 32 dB total range with 256 discrete combinations in an 8-bit implementation). The ordering of the stages shown in FIG. 2A is illustrative; inKI I -012 -PCT PATENTvarious implementations, the ordering of cell types and / or bit weights along the cascade may be selected to support impedance matching, bandwidth, layout constraints, and / or phase and gain performance objectives.

[0036] As an example, Pi-type attenuators 202, 204, 206, and 208 have phase-compensating capacitors. First T-type attenuator 205 has phase-compensating capacitor. Second T-type attenuators 201, 203, and 207 omit dedicated phasecompensating capacitors. This selective application of dedicated phase compensation, where capacitors are present in specific cells (e.g., 8dB, 2dB, 1dB, 4dB, and 16dB) but omitted in others (e.g., 0.5dB, 0.125 dB, 0.25 dB), optimizes the circuit area while ensuring the total phase variation remains within the target specification across the attenuation range. In one embodiment, as illustrated, the dedicated phase-compensating capacitor is omitted where the phase difference between reference and attenuation states is below a predetermined threshold.

[0037] At least two o f the plurality of attenuator cells (first T-type, second T-type, and Pi-type) may be electrically coupled via an inductor, e.g. inductors 215-219, for impedance matching. These inductors are configured to provide impedance matching between the respective attenuator cells. For example, the Pi-type attenuator cell 202 (8dB, BIT6) is coupled via a first inductor 215 to the T-type attenuator cell 201 (0.5dB, BIT2) and via a second inductor 216 to the T-type attenuator cell 203 (0.125dB, LSB). Additionally, the Pi-type attenuator cell 206 (4dB, BIT5) is coupled via inductor 217 to the T-type attenuator cell 205 (1dB, BIT3) and via inductor 218 to the T-type attenuator cell 207 (0.25dB, BIT1), with the T-type attenuator cell 207KI I-012-PCT PATENT( 0.25dB) having a lower attenuation step magnitude than the T-type attenuator cell 205 ( IdB). These are only examples of how different attenuator cells may be electrically coupled by an inductor.

[0038] While Fig. 2A depicts an 8-bit attenuator, the improved digital step attenuator is not limited to only an 8-bit attenuator. These examples are illustrative rather than limiting. By including phase-compensating capacitors across shunt resistors in both low-attenuation ( fine ) and high-attenuation (coarse ) cells, the attenuator is capable of achieving extremely low phase variation across attenuation settings (gain states ), such as less than about 1.5 degrees across an approximately 32 dB gain / attenuation range in an example implementation, which is beneficial for beamforming systems.

[0039] FIG. 2B illustrates exemplary diagrams for a simplified T-type attenuator cell and corresponding reference and attenuation state representations.Simplified T-type attenuator cell 220a is analyzed in two distinct states: a reference state 220b, and an attenuation state 220c. Simplified T-type attenuator cell 220a illustrates a shunt branch coupled from the signal path to a ground reference. The shunt branch includes a shunt resistor Rp222a, and a shunt transistor 223a coupled to the ground reference.

[0040] In the reference state 220b, the shunt transistor is turned OFF. The reference state model includes the shunt resistor Rp222b coupled to a node that is coupled to the ground reference through the capacitor 221b. This capacitor 221b represents the effective off-state capacitance associated with the shunt switching device (e. g., drain / source capacitances and / or other parasitic inKI I-012-PCT PATENTthe OFF state ), and may also represent an effective capacitance COFFseen at that node.

[0041] In the attenuation state 220c, the shunt transistor is turned ON. Ideally acting as a short circuit, the transistor instead presents a finite ON-resistance RON2225c. Attenuation state 220c includes the shunt resistor Rpis represented as 222c, and the additional series resistance RON2225c coupled to the ground reference.

[0042] The interaction between the shunt resistor, the parasitic R0N2and the system impedance ( Zn) defines the attenuation factor ( S2i) and reflection coefficient (Sn ). In one embodiment 220,S21= (2RP+ 2RON2) / (2RP+ 2RON2+ Z0)S11= (-Z0) / (2RP+ 2RON2+ Z0)Wherein RPis the shunt resistance; RON2is the ON-resistance of the shunt transistor.

[0043] FIG. 2C illustrates exemplary diagrams for a Pi-type attenuator cell and corresponding reference and attenuation state representations. Pi-type attenuator cell 230a is analyzed in two distinct states: a reference state 230b, and an attenuation state 230c. Pi-type attenuator cell 230a includes a series resistor 241a coupled between the cell' s input and output nodes. Series transistor 251a coupled between the input and output nodes and in parallel with the series resistor 241a (i. e., a bypass switch around the series resistor. Pi-type attenuator cell 230a further includes a first shunt branch comprising a second shunt resistor 261a coupled to a first shunt transistor 271a, and a second shunt branch comprising a third shunt resistor 262a coupled to a second shunt transistor 272a.

[0044] In the reference state 230b, the series transistor is configured to be turned ON to bypass the series resistorKI I-012-PCT PATENT241b. Ideally, this creates a lossless through-path.However, the series transistor 251b introduces a finite 0N-resistance RON 251b in parallel with series resistor 241b. Simultaneously, the pair of shunt transistors are configured to be turned OFF. In this state, the shunt transistors do not behave as perfect open circuits but are modeled as parasitic capacitors 281b and 282b coupled in series with the shunt resistors 261b and 262b, respectively. These parasitic capacitances COFFcreate leakage paths to ground, affecting the phase linearity and input / output impedance matching of the cell in the reference state.

[0045] In the attenuation state 230c, the series transistor is configured to be turned OFF, forcing the signal through the series resistor 241c. The parasitic OFF-state capacitance of the series transistor 251c effectively appears in parallel with the series resistor 241c, allowing high-frequency signal components to bleed through.Concurrently, the pair of shunt transistors are configured to be turned ON to activate the attenuation resistors 261c and 262c. In this model, the ON-state shunt transistors are represented as parasitic resistors 291c and 292c, corresponding to their ON-resistance RON. These parasitic resistances add to the nominal values of the shunt resistors 261c and 262c, shifting the effective attenuation level and modifying the driving impedance seen by adjacent cells.

[0046] FIG. 3 illustrates exemplary diagrams for transistor structure and operating concepts used to reduce temperature-driven variation by employing silicon-on-insulator ( SOI ) devices with back gate bias capability.The first shunt transistor 131, the pair of secondKI I-012-PCT PATENTtransistors 132, 133, and series transistor 151 illustrated in FIG. l may be a SOI fabricated on a silicon layer above an insulator.

[0047] Diagram 300 illustrates a perspective view of a SOI transistor. An ultra-thin silicon 301 is located above a thin buried oxide 302. The thin buried oxide 302 includes an ultra-shallow junction 303. In one embodiment 304, the back gate is electrically isolated from the channel. This configuration provides body biasing capabilities. In other words, a different voltage can be applied to back gate 304, which is electrically isolated from the channel, in order to shift the transistor' s threshold voltage (Vt). For each transistor, there are two modes of body biasing that may be applied. Forward back gate biasing may be used to reduce the transistor' s Vtin order to allow higher drive and faster switching capabilities. Reverse back gate biasing may be used to increase the transistor' s Vtto allow lower leakage.

[0048] Bulk 310 and SOI 350 are illustrated for comparison. In the Bulk 310 structure, leakage currents can flow from the source ( S ) and drain (D) deep into the substrate, particularly at elevated temperatures or smaller geometries. SOI 350 similarly depicts an SOI transistor with S, G, and D terminals. In the SOI 350 structure, the buried oxide layer, box 351, acts as a physical barrier. This configuration prevents vertical leakage paths, meaning that punch-through is limited by box 351. This structural isolation contributes to the high linearity and low insertion loss required for the attenuator cells.

[0049] In a fully depleted channel operation 320, the SOI configuration reduces leakage currents relative to bulk operation. Since the silicon film is ultra-thin, theKI I-012-PCT PATENTchannel is fully depleted of charge carriers when OFF, resulting in significantly lower leakage currents compared to partially depleted or bulk devices.

[0050] Diagram 330 illustrates application of a back gate bias voltage 331 to the body of the SOI device. The illustrated biasing indicates that a voltage applied to the electrically isolated region can modulate device characteristics by shifting Vt. Two general biasing modes may be used: forward back gate biasing to reduce Vt(enabling higher drive and faster switching) and reverse back gate biasing to increase Vt(enabling lower leakage ). Back gate bias voltage 331 is provided by the back gate bias circuit utilizing a complementary-to-absolute-temperature (CTAT) source. As the operating temperature increases, the CTAT source lowers the body bias voltage 331. This adjustment compensates for the natural decrease in the transistor ' s threshold voltage and the increase in ON-resistance RON that would otherwise occur at high temperatures. Consequently, the application of the temperature-dependent back gate bias voltage 331 stabilizes the RON of the switching transistors (e. g., 131, 132, 133, and 151 ), thereby minimizing variations in gain and phase across the operating temperature range.

[0051] FIG. 4 illustrates exemplary diagrams showing implementation results demonstrating the performance of the attenuator across a wide temperature range when utilizing the back gate biasing techniques described herein.Temperature correlates to the operating junction temperature (T j ) with the applied back gate bias voltages (Vbg) and the resulting RF performance metrics.

[0052] Diagram 410 illustrates an exemplary diagram for insertion loss variation and phase variation versusKI I-012-PCT PATENTtemperature with Vbg adjustment. On the horizontal axis are the temperature variations from -40°C to 120°C.Horizontal axis also proportionally represents the back gate bias, with Vbgmax 401a and Vbgmin 402a. Vertical axis shows S21 in dB ( for 411 ) or phase variation in degrees ( for 412 ). Curve 411 illustrates the insertion loss variation from nominal. Curve 412 illustrates the phase variation from reference state in degrees. Diagram 430 illustrates worst case return loss versus temperature with Vbg adjustment. On the horizontal axis are the temperature variations from -40°C to 120 °C. Horizontal axis also proportionally represents the back gate bias, with Vbgmax 401b and Vbgmin 402b. Vertical axis shows S11, S22 in dB. Curve 431 illustrates Mag S11 in dB. Curve 432 illustrates Mag S22 in dB.

[0053] The data illustrates the operation of the Complementary-To-Absolute-Temperature (CTAT ) source. The relationship between Temperature (T ) and Back Gate Bias Voltage (Vbg) is described below,• At a low temperature, for example -40 °C, the Vbg is set to a maximum value, for example, 2.7 V• At room temperature ( 25 °C), Vbg is reduced, for example, to 1. 9 V• At a high temperature, for example 120 °C, Vbg decreases to a minimum value, for example, 0 V

[0054] This inverse relationship confirms the CTAT behavior, where the bias voltage is actively lowered as temperature increases. By modulating the threshold voltage of the SOI transistors in this manner, the system maintains consistent performance. For instance, the PHASE VARIATION is maintained between approximately 1.7 degrees and 3. 8 degrees across the entire 160-degree Celsius span.KI I-012-PCT PATENTSimilarly, the insertion loss variation remains stable, varying approximately ±0. 1 dB, effectively mitigating the variation in ON-resistance RON.

[0055] FIG. 5 illustrates an exemplary diagram for back gate bias voltage generation by different transistors. The attenuator is configured with circuit 500 to generate a body biasing voltage that decreases with temperature, circuit 500 operates from a supply voltage VDD (e. g., 3V). It comprises a current source 501 coupled to a voltage reference branch consisting of a resistor 511 and a diode-connected transistor 512 coupled in series to a ground reference. Transistor 512, typically an SOI device, exhibits a negative temperature coefficient ( its threshold voltage or diode drop decreases as temperature rises ).Consequently, the voltage potential generated at the node above the resistor 511 decreases as the operating temperature of the chip increases.

[0056] This temperature-dependent reference voltage is fed into the input of a buffer 522, which includes an amplifier 521. The buffer 522 provides the necessary current drive capability to isolate the reference generator from the load. The output of the buffer is the back gate bias voltage Vbg 520. This voltage Vbg 520 is then distributed to the back bias terminals of the switching transistors to dynamically adjust their threshold voltages.

[0057] The body biasing voltage that decreases with temperature using a CTAT voltage source. For example, at a temperature of -40 °C, the Vbg is a higher value such as 2. 7V, while at a temperature of 120 °C, the Vbg is a lower value such as 0V. More generally, each transistor is configured to apply higher biasing voltages that are lower temperatures and lower biasing voltages at higherKI I-012-PCT PATENTtemperatures. By applying these biasing voltages to the transistors, Vtmay be calibrated in order to reduce variation of ON resistance (RON). By using back gate bias, the RON variation can be reduced from about ±25% to about ±5% where the variation is based on the total variation of the resistance value about the average resistance without and with back gate bias. As variation of RON is reduced, attenuation and phase variation across temperature is also reduced. Thus, ultra-low phase variation over all gain states for the digital step attenuator may be achieved when RON variation is minimized.

[0058] Although the present invention has been described in connection with certain specific embodiments for instructional purposes, the present invention is not limited thereto. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

KI I-012-PCT PATENTCLAIMSWhat is claimed is:

1. An attenuator, comprising:an attenuator input;an attenuator output; anda plurality of attenuator cells coupled in cascade between the attenuator input and the attenuator output, configured to provide binary-weighted attenuation steps, the plurality of attenuator cells comprising:a first T-type attenuator cell comprising a first shunt resistor electrically coupled to a ground reference; anda Pi-type attenuator cell comprising a series resistor coupled in series between a Pi-type attenuation cell input and a Pi-type attenuation cell output, a second shunt resistor and a third shunt resistor each electrically coupled to the ground reference, a second phase-compensating capacitor, and a third phase-compensating capacitor.

2. The attenuator of claim 1, wherein the first T-type attenuator cell further comprising a first phasecompensating capacitor, and wherein the first phasecompensating capacitor is electrically coupled in parallel with the first shunt resistor.

3. The attenuator of claim 1, wherein the second phasecompensating capacitor is electrically coupled in parallel with the second shunt resistor, and the third phasecompensating capacitor is electrically coupled in parallel with the third shunt resistor.KI I-012-PCT PATENT4. The attenuator of claim 1, wherein a binary-weighted attenuation step provided by the first T-type attenuator cell is smaller than a binary-weighted attenuation step provided by the Pi-type attenuator cell.

5. The attenuator of claim 1, wherein the plurality of attenuator cells further comprises a second T-type attenuator cell configured to provide a binary-weighted attenuation step that is smaller than the binary-weighted attenuation step provided by the first T-type attenuator cell, and wherein the second T-type attenuator cell omits a dedicated phase-compensating capacitor.

6. The attenuator of claim 1, wherein the first T-type attenuator cell further comprises a first shunt transistor coupled in series with the first shunt resistor between a node of the first T-type attenuator cell and the ground reference.

7. The attenuator of claim 6, wherein the first shunt transistor is configured to be turned off in a reference state and turned on in an attenuation state.

8. The attenuator of claim 6, wherein the Pi-type attenuator cell further comprises a series transistor coupled between the Pi-type attenuation cell input and the Pi-type attenuation cell output and in parallel with the series resistor, and a pair of second shunt transistors, a first transistor of the pair being coupled in series with the second shunt resistor to the ground reference and a second transistor of the pair being coupled in series with the third shunt resistor to the ground reference.

9. The attenuator of claim 8, wherein:KI I-012-PCT PATENTin a reference state of the Pi-type attenuator cell, the series transistor is configured to be turned on and the pair of second shunt transistors are configured to be turned off; andin an attenuation state of the Pi-type attenuator cell, the series transistor is configured to be turned off and the pair of second shunt transistors are configured to be turned on.

10. The attenuator of claim 8, wherein each of the first shunt transistor, the series transistor, and each of the pair of second shunt transistors is a silicon-on-insulator ( SOI ) transistor fabricated on a silicon layer above an insulator.

11. The attenuator of claim 10, further comprising a back gate bias circuit configured to apply, to the first shunt transistor, the series transistor, and each transistor of the pair of second shunt transistors, respective back gate biasing voltages that decrease as temperature increases using a complementary-to-absolute-temperature (CTAT ) source, such that higher back gate biasing voltages are applied at lower temperatures and lower back gate biasing voltages are applied at higher temperatures.

12. The attenuator of claim 11, wherein the back gate bias circuit is configured to control threshold voltages of the first shunt transistor, the series transistor, and each transistor of the pair of second shunt transistors to mitigate variation of ON resistance (RON) and thereby minimize attenuation and phase variation across temperature.KI I -012 -PCT PATENT13. The attenuator of claim 1, wherein at least two of the plurality of attenuator cells are electrically coupled via an inductor.

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