Self-test mechani SM for phase calibration of millimeter wave beamformers

Abstract

A phase calibration circuit and method for radio frequency (RF) signal paths utilize a modular architecture comprising one or more calibration units and at least one analog-to-digital converter (ADC). Each calibration unit is associated with a corresponding RF signal path and includes a first coupler to sample a first signal at a first node and a second coupler to sample an second signal at a second node. An I / Q generation circuit produces orthogonal components from the second signal, which are mixed with the first signal to generate differential in-phase and quadrature signals. The ADC digitizes these signals to provide digital values for phase offset analysis. The resulting phase offset determination is independent of transmit channel gain and design-for-test (DFT) path gain. The architecture supports multi-polarization channels and multi-frequency calibration, with offsets stored in memory to adjust phase shifters in a beamforming array.

Description

KI I -013-PCT PATENTSELF-TEST MECHANI SM FOR PHASE CALIBRAT ION OF MILLIMETER WAVE BEAMFORMERSCROS S REFERENCE TO RELATED APPLICAT IONS

[0001] Thi s appl icat ion claims priority under 35 U. S. C.§11 9 from U. S. Provi sional Appl icat ion Number 63 / 764, 748 ent it led " Sel f-Test Mechanism for Phase Cal ibrat ion o f mmWave Beamformers, " fi led on Feb. 28, 2025, the sub j ect matter o f which i s incorporated herein by reference.TECHNICAL F IELD

[0002] Thi s di sclosure generally relates to a novel architecture that enables a sel f test mechani sm for phase cal ibrat ion o f mi l l imeter wave beamformers that is independent o f channel gain and Des ign for Test (DFT ) path gain.BACKGROUND

[0003] In wireles s communi cat i on systems, beamforming integrated ci rcuit s (BF IC ) are used to provi de electroni c pha se shi ft ing for e lectron ic steered phased arrays. These blocks rely on elect ronic phase shi fters and variable gain ampl i f iers to synthesi ze di f ferent beams cover ing di f ferent angles, shapes, and power. However, one i s sue with BF ICs i s that there i s systemat ic phase mi smatch between di f ferent channel s, even when the di f ferent channel s are on the same chip. Convent ional phase calibrat ion methods depend upon channe l ga in and design- f or-test (DFT ) path gain. An improved phase calibrat ion method is needed to addres s these i ssues.KII-013-PCT PATENTSUMMARY

[0004] Methods and apparatus are provided to enable a selftest mechanism for phase calibration of millimeter wave (mmWave ) BFICs that is independent of channel gain and DFT path gain. In one embodiment, the phase calibration circuit includes one or more calibration units, each calibration unit being associated with a corresponding RF signal path. Each calibration unit includes a first coupler configured to sample an RF signal at a first node of the corresponding RF signal path and a second coupler configured to sample an RF signal at a second node of the corresponding RF signal path. The second coupler is coupled to an in-phase / quadrature ( I / Q) generation circuit that generates in-phase and quadrature-phase components from the sampled signal at the second node. A mixer receives ( i ) the sampled signal from the first node and ( ii ) the in-phase and quadrature-phase components derived from the sampled signal at the second node and generates a differential in-phase signal and a differential quadrature-phase signal that represent a relative phase between the first node and the second node. At least one analog-to-digital converter (ADC) digitizes the differential in-phase signal and the differential quadrature-phase signal for at least one calibration unit to provide corresponding digital values for phase offset analysis. From the digitized differential in-phase and differential quadrature-phase values, a phase offset between the first node and the second node is determinable and is independent of, or substantially independent of, gain of the RF signal path between the first and second nodes and gain of a design-f or-test (DFT ) calibration path that delivers the sampled and processed signals for digitization.KII-013-PCT PATENT

[0005] In some embodiments, the mixer produces differential quadrature signals, a positive in-phase signal ( Ip), a negative in-phase signal ( In), a positive quadrature-phase signal (Qp), and a negative quadrature-phase signal (Qn). In some embodiments, the phase offset is determined by the arctangent of (Qp-Qn) / ( Ip-In).

[0006] In other embodiment, the phase calibration circuit further includes a low-pass filter coupled between the mixer and the ADC to attenuate higher-frequency components of the mixer output prior to digitization. In some embodiments, the phase calibration circuit further includes at least one of ( i ) a first transformer coupled between the first coupler and the mixer to transform the sampled signal from the first node into a differential sampled signal for application to the mixer, and ( ii ) a second transformer coupled between the second coupler and the I / Q generation circuit to transform the sampled signal from the second node into a differential sampled signal for I / Q generation. In some embodiments, the I / Q generation circuit comprises one of a polyphase filter, a hybrid coupler, an LC-based quadrature amplitude filter, an RC polyphase filter, a GmC polyphase filter, or a switched-based polyphase filter. In some embodiments, one or more amplifiers are coupled between one or more of ( 1 ) the first coupler and the mixer, ( ii ) the second coupler and the I / Q generation circuit, or ( iii ) the I / Q generation circuit and the mixer to compensate sampling loss and / or to drive the mixer.

[0007] In yet another embodiment, the one or more RF signal paths may be configured for a first polarization, for example a horizontal-polarization, or a second polarization, for example, a vertical-polarization.KII-013-PCT PATENT

[0008] Other embodiments and advantages are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 illustrates exemplary diagrams for phase calibration system with phase calibration circuit for multi-channel RF signal.

[0010] Fig. 2 illustrates exemplary diagrams of the components of the phase calibration circuit within the channel of the BFIC.

[0011] FIG. 3 illustrates an exemplary apparatus including a RF channel and an associated phase calibration circuit.

[0012] FIG. 4 illustrates a chart showing the output of the mixer of the phase calibration circuit.

[0013] FIG. 5 illustrates a chart showing the output of the ADC of the phase calibration circuit.

[0014] FIG. 6 is a flow chart to determine the phase offset using a phase calibration circuit.DETAILED DESCRIPTION

[0015] Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0016] Beamforming integrated circuits (BFICs ) are used to provide electronic phase shifting for electronic steered phased arrays. These blocks rely on electronic phase shifters and variable gain amplifiers to synthesize different beams covering different angles, shapes, and power. As a BFIC may have multiple channels, calibration is needed to align the phases of each channel.KII-013-PCT PATENTConventional methods have strong dependency on both channel gain and DFT path gain while also calibrating based upon computing the absolute phase per channel, despite the channel to channel variations and die to die variations.

[0017] Disclosed herein is a phase calibration circuit or design-f or-test (DFT ) circuit that has a self-test mechanism for phase calibration that is independent of channel gain and DFT path gain. The phase calibration circuit compares the relative phase between the splitter / combiner port and antenna port of each and every channel. This is done by mixing the two signals and then applying the output of the mixer to a low pass filter (also referred to as a low pass buffer), which generates the differential quadrature signals in-phase, Ip and In, and quadrature, Qp and Qn. These signals are then digitized by the analog-digital converter (ADC) and read by the bus to determine the actual phase difference. This enables phase calibration that is reliable across multiple channels while being independent of process and mismatch variations. The phase calibration circuit may be used by mmWave transceivers, mmWave BFICs, and general purpose variable gain and phase systems. When used within such systems, it enables ideal beam patterns with both extremely low side lobe levels and extremely low channel-to-channel phase variation.

[0018] FIG. 1 illustrates exemplary diagrams for phase calibration system with phase calibration circuit for a multi-channel BFIC. The phase calibration circuit includes one or more calibration units, such as calibration unit 100a, 100b, and 100d. Each calibration unit samples signals at the splitter combiner port and antenna port from a corresponding RF signal path of a plurality of RF signalKII-013-PCT PATENTpaths. Each RE signal path corresponding to a transmit or receive channel, such as channel 101. Each calibration unit is coupled to a corresponding RF signal path. An RF signal 103, if a transmit signal, is distributed to these channels via a splitter / combiner 131, or, if a receive signal, is combined from these channels via a splitter / combiner 131. In one embodiment splitter / combiner 131 comprises a Wilkinson power divider / combiner configured to operate as both a splitter and a combiner. A power detector 132 and an RF buffer 133 are coupled to the input network for monitoring and buffering the signal 103.

[0019] For each channel, a first coupler 110a samples an RF signal at a first node. This signal is processed by an RF phase buffer 111 and a transformer 112 to produce a differential sampled input signal. Transmission line 113 routes this signal to a mixer 114. Simultaneously, a second coupler 110b samples an RF signal at a second node proximate to antenna ports 105a-105d. This signal is processed by an RX / TX antenna phase buffer 119 and a transformer 118, which is coupled via transmission line 117 to an I / Q generation circuit 116.

[0020] Each RF signal path corresponds to a respective calibration unit, such as 100a - 100d. Each calibration unit samples signals at a first node and a second node of the corresponding path to produce differential in-phase and quadrature-phase signals. The first node is located at a splitter / combiner node of channel 101, while the second node is located at an antenna port node near the antenna ports 105a-105d. On the splitter / combiner side, a first coupler 110a samples an RF signal that is processed through an RF phase buffer 111 and a transformer 112 to provide a differential sampled input signal to mixer 114. In oneKII-013-PCT PATENTembodiment, a sampled splitter / combiner port signal from the first coupler 110a is provided to an RF phase buffer 111. RF phase buffer 111 is configured to buffer and / or amplify the sampled input signal ( for example, to compensate for coupling loss and to provide appropriate impedance and drive capability for downstream circuitry) while preserving phase information.

[0021] On the antenna port side of one or more RF signal paths, such as channel 101, a power detector 121 (e. g., an RX / TX power detector) and an antenna buffer 122 may be provided. Power detector 121 may be configured to sense an RF output level, and antenna buffer 122 may be configured to provide buffering and / or drive capability to the antenna port s / element s 105a-105d. A second coupler 110b samples an antenna port signal that is processed through an antenna phase buffer 119, a transformer 118, and an I / Q generation circuit 116 to generate orthogonal components, i. e. the in-phase and quadrature-phase components from the sampled output signal. In one embodiment, the I / Q generation circuit 116 produces orthogonal components that are amplified by dedicated amplifiers 115a and 115b before being delivered to the mixer 114. In another embodiment, the output of antenna phase buffer 119 is differential and is electrically coupled to an I / Q generation circuit 116.

[0022] I / Q generation circuit 116 (also referred to herein as an IQ separator) is coupled to receive the sampled output signal (e. g., a differential sampled output signal from transformer 118 ) and is configured to generate in-phase and quadrature-phase components from the sampled output signal. In the illustrated embodiment, I / Q generation circuit 116 may comprise a polyphase filter. In other embodiments, I / Q generation circuit 116 may compriseKII-013-PCT PATENTanother quadrature generation structure, such as a hybrid coupler, an LC-based quadrature amplitude filter, an RC polyphase filter, a GmC polyphase filter, or a switched-based polyphase filter.

[0023] Mixer 114 is coupled to receive (i ) the sampled input signal (e. g., via RF phase buffer 111, transformer 112, and transmission line 113 ) and ( ii ) the in-phase and quadrature-phase components generated from the sampled output signal (e. g., via I / Q generation circuit 116 and amplifiers 115a, 115b). Mixer 114 mixes these inputs to generate a differential in-phase signal and a differential quadrature-phase signal representative of a relative phase between the first node and the second node of the RF signal path. In some embodiments, mixer 114 generates differential in-phase and quadrature-phase signals including a positive in-phase signal ( Ip), a negative in-phase signal ( In), a positive quadrature-phase signal (Qp), and a negative quadrature-phase signal (Qn).

[0024] A low-pass buf fer / f ilter 123 is coupled to receive outputs from mixer 114. Low-pass buf fer / f ilter 123 is configured to attenuate higher-frequency components of mixer outputs (e. g., second-harmonic components ) and to provide filtered differential in-phase and differential quadrature-phase signals suitable for digitization. A readout bus 135 is coupled to receive calibration signals from low-pass buf fer / f ilter 123. Readout bus 135 may include selection and / or multiplexing circuitry. In a multi-channel implementation, readout bus 135 may be configured to select calibration signals from a selected channel 101 (and its associated calibration unit / phase calibration circuit ) for conversion by at least one ADC 136. ADC 136 is configured to digitize the differentialKII-013-PCT PATENTin-phase and differential quadrature-phase signals and to provide corresponding digital values for phase offset analysis. In some embodiments, ADC 136 is shared among multiple calibration units; in other embodiments, separate ADCs may be provided per channel.

[0025] In one embodiment, the digitized differential in-phase and differential quadrature-phase values may be processed ( for example, by on-chip logic or by external test equipment ) to determine a phase offset between the first node and the second node. In example embodiments, the phase offset determination is independent of, or substantially independent of, gain of the RF signal path between the first and second nodes and gain of the DFT calibration path, because the phase offset is determined from the differential in-phase and differential quadraturephase information rather than from absolute amplitude.

[0026] When calibration is being performed, the signal is sensed at the input and output of the channel, and afterwards mixed. Cos (<p), where cp is the phase offset, can be then determined from low pass filtering and the following formula:cos (a) * cos (b) = (cos (a-b) + cos (a+b) )

[0027] Fig. 2 illustrates exemplary diagrams of the components of the phase calibration circuit within the channel of the BFIC. A conceptual model for a representative path (CHANNEL Hl 201 ) is illustrated. The input signal 205 and output signal 206 are sampled at respective nodes. The sampled input is processed by buffer 211, transformer 212, and transmission line 213. The sampled output is processed by buffer 219, transformer 218, and transmission line 217 before reaching the I / Q generation circuit 216. The quadrature components areKI I -013-PCT PATENTampli f ied by ampl i f iers 215a and 215b and mixed at mixer 214. The low-pas s buf f er / fi lter 221 provides a phase detector output.

[0028] The relat ive phase i s used in the compari son instead o f the absolute value o f the phase. The output o f the mixer i s appl ied to the low-pas s f i lter, and the fol lowing i s the output o f the phase detector are the Ip-Qp-In-Qn s ignal s:Ip = A*B* cos ( cp )Qp = A*B* s in ( cp )In = - A*B* cos ( cp )Qn = - A*B* s in ( cp )A - B • cos ( cp )A - B - sin ( cp )tan ( cp ) = (A - B - cos ( cp ) ) / (A - B - s in (cp ) ) Where, <p is the phase o f f set, A is the channel gain, and B i s the DFT gain. The periodicity i s 271.tan ( cp ) = ( Qp - Qn ) / ( Ip - In ) =2A*B* s in ( cp ) / 2 *A*B*cos ( <p ) =Qp / Ip= arctan ( (Qp - Qn ) / ( Ip - In ) ) = arctan ( Qp / Ip )

[0029] The Ip-Qp- In-Qn signals are pas sed to an ADC to be digiti zed be fore being read through a bus. An FPGA then calculates the phase of f set by the following:cp = Arctan ( ( Qp-Qn ) / ( Ip - In ) )The phase of f set i s determined based on the results o f Arctan calculat ion. Whi le the example de f ined the s ignal at 205 as an input s ignal and the s ignal at 20 6 as an output s ignal, the result wi l l be the same i f the input s ignal i s 20 6 and the output s ignal i s 205.

[0030] F IG. 3 i l lustrates an exemplary apparatus including a RF channel and an associated phase cal ibrat ion circuit.KII-013-PCT PATENTIn the illustrated embodiment, RF channel 301a (CHNL) is electrically coupled to a splitter / combiner at a first node and an antenna port 302a at a second node. RF channel 301a includes a phase shifter 305a configured to adjust a phase of the RF signal propagating through the channel and may include one or more gain stages, such as amplifier 306a. In some embodiments, a plurality of RF channels 301a are provided, and each transmit channel has a corresponding phase calibration unit as described below.

[0031] A phase calibration circuit 300 is coupled to RF channel 301a. Phase calibration circuit 300 includes a first coupler 311a configured to sample an RF signal at a first node of the RF signal path (e. g., at a splitter / combiner port of channel 301a or a node electrically coupled thereto) and a second coupler 311b configured to sample an RF signal at a second node of the RF signal path (e. g., at an antenna port of channel 301a or a node electrically coupled thereto, such as near antenna port 302a). In one embodiment, for multiple RF channels, each RF channel is associated with a corresponding first and second coupler. As illustrated, first coupler 311a includes exemplary Cla, C2a, and C3a for each corresponding RF channels, and second coupler 311b includes exemplary Clb, C2b, and C3b for each corresponding RF channels.

[0032] A sampled signal from first coupler 311a may be amplified by an amplifier 312a to compensate coupling loss and to provide drive capability to downstream circuitry. A signal-conditioning network 313a couples the sampled inputside signal to mixer 314. In some embodiments, signalconditioning network 313a includes one or more transformers and / or matching networks configured to provide differentialKII-013-PCT PATENTsignaling, impedance transformation, and / or controlled phase delay (e. g., via transmission line routing).

[0033] A signal from the second node is sampled signal from second coupler 311b may be amplified by an amplifier 312b to compensate coupling loss and to provide drive capability to downstream I / Q generation. A signal-conditioning network 313b transforms the output of amplifier 312b from single ended to differential,, alternatively, amplifier 312b can perform the signal conditioning of 313b, and couples the sampled antenna port signal to an I / Q generation circuit 316. In the illustrated embodiment, I / Q generation circuit 316 comprises a polyphase filter (POLY PHASE) configured to generate in-phase and quadrature-phase components from the sampled antenna port signal. In other embodiments, I / Q generation circuit 316 may comprise any suitable quadrature generation structure, such as a hybrid coupler, an LC-based quadrature amplitude filter, an RC polyphase filter, a GmC polyphase filter, or a switched-based polyphase filter.

[0034] Amplifiers 315a and 315b are coupled between I / Q generation circuit 316 and mixer 314 and may be configured to compensate for insertion loss and to drive mixer 314 with the in-phase and quadrature-phase components. Mixer 314 receives ( i ) the signal from the sampled splitter / combiner signal from a first node that is sampled at the first coupler 311a may be amplified by amplifier 312a, and converted from a single ended signal to a differential signal by signal-conditioning network 313a, alternatively, amplifier 312a can perform the signal conditioning of 313a and ( ii ) the in-phase and quadraturephase components derived from the sampled antenna port signal (e. g., via coupler 311b, amplifier 312b, I / QKII-013-PCT PATENTgeneration circuit 316, and amplifiers 315a, 315b). Mixer 314 mixes these signals and generates a differential in-phase signal and a differential quadrature-phase signal representative of a relative phase between the first node and the second node.

[0035] In some embodiments, mixer 314 generates a differential in-phase signal comprising a positive in-phase signal ( Ip), a negative in-phase signal ( In), and a differential quadrature-phase signal comprising a positive quadrature-phase signal (Qp), and a negative quadraturephase signal (Qn). In some embodiments, a low-pass filter (not shown in FIG. 3 ) is coupled between mixer 314 and ADC 331 to attenuate higher-frequency mixing products prior to digitization.

[0036] At least one ADC 331 is coupled to phase calibration circuit 300 to digitize the differential in-phase and differential quadrature-phase signals for at least one calibration unit and to provide corresponding digital values for phase offset analysis. In a multi-channel implementation, the at least one ADC 331 may be shared among multiple calibration units ( for example, via selection circuitry and / or a readout bus, not shown). In other implementations, separate ADCs may be provided per channel.

[0037] A test circuit 332 (e. g., on-chip logic, a controller, or external test equipment such as an FPGA) is coupled to receive the digitized values from ADC 331 and to determine a phase offset between the first node and the second node. In example embodiments, the phase offset determination is independent of, or substantially independent of, gain of the RF signal path between the sampled nodes and gain of the calibration / DFT path becauseKII-013-PCT PATENTthe phase offset is determined from differential in-phase and differential quadrature-phase information. In some embodiments, the phase offset is determined using an arctangent operation based on (Qp-Qn) / ( Ip-In).

[0038] In some embodiments, an RF signal 303 at the first node of channel 301a is coupled from a power divider / combiner 304 that in a transmit mode splits an RF signal into a plurality of input signals directed to a plurality of transmit channels, and in a receive mode combines RF signal from a plurality of receive channels. In an example embodiment, the power divider comprises a Wilkinson power divider.

[0039] In an example calibration method supported by FIGS.1-3, calibration circuitry is enabled in a calibration mode. For a corresponding RF signal path, a first RF signal is sampled at a first node, and a second RF signal is sampled at a second node. In-phase and quadrature-phase components are generated from the sampled second RF signal, and the sampled first RF signal is mixed with the in-phase and quadrature-phase components of the second RF signal to generate a differential in-phase signal and a differential quadrature-phase signal representative of a relative phase between the nodes. The differential signals are optionally low-pass filtered and digitized by at least one ADC to obtain corresponding digital values, and a phase offset is determined from the digital values based on the differential in-phase and differential quadrature-phase information. The phase offset may be stored as a calibration value and applied to adjust a phase setting of a phase shifter (e. g., phase shifter 306a) in the corresponding RF signal path. In some embodiments, the sampling, mixing, digitizing, and determining are repeatedKI I -013-PCT PATENTat a plurality of frequencies within an operating band and the phase offset is stored as a function of frequency.

[0040] FIG. 4 illustrates a chart showing the output of the mixer of the phase calibration circuit. Chart 400 shows each of the Ip-Qp-In-Qn signals, which are then applied to the ADC. Chart 400 illustrating example waveforms corresponding to the orthogonal output signals produced by the phase calibration circuit (e.g., the mixer / phase detector output of a calibration unit described with respect to FIGS. 1-3). In the illustrated example, the horizontal axis represents Channel PHASE DEGREE (e.g., a swept transmit / channel phase setting), and the vertical axis represents output amplitude (e.g., normalized output level). As illustrated, the four plotted waveforms correspond to the mixer / phase-detector outputs Ip, In, Qp, and Qn, and are identified by the legend in chart 400 as follows:• A corresponds to Ip (positive in-phase signal)• B corresponds to In (negative in-phase signal)• C corresponds to Qp (positive quadrature-phase signal)• D corresponds to Qn (negative quadrature-phase signal)

[0041] FIG. 5 illustrates a chart showing the output of the ADC of the phase calibration circuit. Exemplary measurement results are illustrating, corresponding to digitization and phase-offset analysis performed using the outputs of the phase calibration circuit. The two diagrams illustrate an example DFT phase measurement nominal process plot 510, and an example DFT phase measurement error nominal process plot 520.

[0042] In diagram 510, the horizontal axis represents CHANNEL PHASE (e.g., the commanded or swept phase setting of a corresponding RF signal path, such as a phase shifterKII-013-PCT PATENTsetting in a transmit channel ), and the vertical axis represents DETECTED PHASE as produced by phase-offset analysis based on the digitized calibration signals. The detected phase in plot 510 increases generally linearly as channel phase is swept and exhibits a discontinuity (wraparound) near the ±180-degree boundary. This wrap-around behavior is consistent with phase extraction using an arctangent / at an2-type computation that produces a principal-value phase result over a bounded angular range (e. g., -180 ° to +180 ° ). In the claimed and disclosed architecture, at least one ADC digitizes, for at least one calibration unit, the differential in-phase and differential quadrature-phase signals and provides corresponding digital values for phase offset analysis. A test circuit, processor, FPGA, or other digital logic (which may be on-chip or off-chip) can process these digital values to determine the phase offset between the first sampled node and the second sampled node.

[0043] Diagram 520 illustrates an example measurement error (or detected-phase deviation) versus channel phase under nominal conditions. In the illustrated example, the error remains small across a substantial portion of the channelphase sweep, demonstrating that the digitized differential I / Q signals provide a reliable basis for phase-offset determination. A discontinuity may appear at the wraparound boundary (corresponding to the principal-value nature of arctangent / atan2 outputs ), and in some embodiments an unwrapping operation may be applied to provide a continuous phase response across 2π.

[0044] FIG. 6 is a flow chart to determine the phase offset using a phase calibration circuit. At step 601, the apparatus samples, at a first coupler, a first signal of aKII-013-PCT PATENTcorresponding RF signal path. At step 602, the apparatus samples, at a second coupler, a second signal of the corresponding RF signal path. At step 603, the apparatus generates, using an in-phase / quadrature ( I / Q) generation circuit, differential in-phase and quadrature-phase components from the sampled second signal. At step 604, the apparatus mixes, at a mixer, ( i ) the sampled first signal processed to be a differential signal and (ii ) the in-phase and quadrature-phase components to generate a differential in-phase signal and a differential quadraturephase signal representative of a relative phase between the first signal and the second signal. At step 605, the apparatus digitizes, at an analog-to-digital converter (ADC), the differential in-phase signal and the differential quadrature-phase signal to obtain corresponding digital values. At step 606, the apparatus determines from the corresponding digital values based on the differential in-phase signal and the differential quadrature-phase signal, a phase offset between the first signal and the second signal, wherein the phase offset is independent of channel gain and design-f or-test (DFT ) path gain.

[0045] Although the present invention has been described in connection with certain specific embodiments for instructional purposes, the present invention is not limited thereto. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

KII-013-PCT PATENTCLAIMSWhat is claimed is:

1. An apparatus for phase calibration, comprising:a radio frequency (RF ) channel including a phase shifter, the phase shifter configured to adjust a phase of a signal; anda phase calibration circuit for the RF channel, the phase calibration circuit comprising:a first coupler configured to sample a first RF signal at a first node of the RF channel to generate a first differential signal;a second coupler configured to sample a second RF signal at a second node of the RF channel to generate a second differential signal;circuitry to generate a first differential quadrature signal from the second differential signal; anda mixer configured to mix the first differential signal and the first differential quadrature signal to obtain a second differential quadrature signal comprising a positive in-phase signal Ip, a negative in-phase signal In, a positive quadrature-phase signal Qp, and a negative quadrature-phase signal Qn.

2. The apparatus of claim 1, wherein the phase calibration circuit further comprises a first buffer amplifier and a first transformer, the first transformer configured to generate the first differential signal from the sampled first RF signal at the first node.

3. The apparatus of claim 1, wherein the phase calibration circuit further comprises a second bufferKII-013-PCT PATENTamplifier and a second transformer, the second transformer configured to generate the second differential signal.

4. The apparatus of claim 1, wherein the phase calibration circuit further comprises a polyphase filter configured to generate the first differential guadrature signal from the second differential signal.

5. The apparatus of claim 4, where the polyphase filter is one of: a hybrid coupler, an inductor-capacitor (LC-based) quadrature amplitude filter, a resistor-capacitor (RC) polyphase filter, a transconductor-capacitor (GmC) polyphase filter, or a switched filed-effect transistor (FET) based polyphase filter.

6. The apparatus of claim 1, wherein a phase offset between the first RF signal and the second RF signal is determined by Arctan ( (Qp-Qn) / ( Ip-In) ).

7. The apparatus of claim 1, wherein the phase calibration circuit further comprises a low-pass filter configured to attenuate higher-frequency components of a mixer output prior to digitization.

8. The apparatus claim 1, wherein the RF channel further comprises a horizontal channel for horizontal polarization and a vertical channel for vertical polarization, and wherein the one or more calibration units comprise a first calibration unit for the horizontal channel and a second calibration unit for the vertical channel.

9. The apparatus of claim 1 further comprising a power divider configured to split an RF signal into a pluralityKII-013-PCT PATENTof input signals directed to a plurality of RF channels, and wherein each of the plurality of RF channels is associated with a corresponding phase calibration circuit.

10. The apparatus of claim 9, wherein the power divider is configured to operate as both a splitter and a combiner.

11. A method for performing a phase calibration for one or more radio frequency (RF ) signal paths, comprising:sampling, at a first coupler, a first signal of a corresponding RF signal path;sampling, at a second coupler, a second signal of the corresponding RF signal path;generating, using an in-phase / quadrature ( I / Q) generation circuit, differential in-phase and quadraturephase components from the sampled second signal;mixing, at a mixer, ( i ) the sampled first differential signal and ( ii ) the in-phase and quadrature-phase components to generate a differential in-phase signal and a differential quadrature-phase signal representative of a relative phase between the first signal and the second signal;digitizing, at an analog-to-digital converter (ADC), the differential in-phase signal and the differential quadrature-phase signal to obtain corresponding digital values; anddetermining, from the corresponding digital values based on the differential in-phase signal and the differential quadrature-phase signal, a phase offset between the first signal and the second signal, wherein the phase offset is independent of channel gain and design-for-test (DFT ) path gain.KII-013-PCT PATENT12. The method of claim 11, wherein mixing comprises generating a positive in-phase signal Ip, a negative in-phase signal In, a positive quadrature-phase signal Qp, and a negative quadrature-phase signal Qn, and forming the differential in-phase signal as ( Ip-In) and the differential quadrature-phase signal as (Qp-Qn).

13. The method of claim 12, wherein the phase offset between the first signal and the second signal is determined by Arctan ( (Qp-Qn) / ( Ip-In) ).

14. The method of claim 11, further comprising converting, the sampled first signal into a differential format via a first transformer prior to the mixing.

15. The method of claim 11, further comprising converting the sampled second signal into a differential format via a second transformer prior to applying to the I / Q generation circuit.

16. The method of claim 11, further comprising amplifying at least one of the sampled first signal to compensate for coupling loss, the sampled second signal to compensate for coupling loss and driving the mixer.

17. The method of claim 11, further comprising:splitting an RF signal via a power divider into a plurality of signals directed to a plurality of transmit channels; anddetermining a corresponding phase offset for each RF signal path of the plurality of RF signal paths.KII-013-PCT PATENT18. The method of claim 17, wherein the plurality of transmit channels comprises at least one horizontalpolarization transmit channel and at least one verticalpolarization transmit channel.

19. The method of claim 11, further comprising storing the phase offset as a calibration value and applying the calibration value to adjust a phase setting of a phase shifter in the corresponding RF signal path.

20. The method of claim 19, further comprising repeating the sampling, mixing, digitizing, and determining at a plurality of frequencies within an operating band and storing the phase offset as a function of frequency.

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