Apparatus and method to mitigate gain variation over temperature due to local heating

Abstract

Apparatus and methods are provided to mitigate gain variation over temperature caused by localized heating. Biasing circuitry provides a baseline reference current compensated for ambient temperature variations. A temperature difference is estimated between a localized heating zone of the core circuitry and a thermally decoupled region of the biasing circuitry. Current slope control adjusts a temperature dependence of the baseline reference current based on the estimated temperature difference to generate an adjusted reference current that biases the core circuitry. In embodiments, the temperature difference is estimated using a sensing transistor thermally coupled to the localized heating zone and a bulk transistor disposed in the thermally decoupled region, and the adjusted reference current is generated by combining a correction current dependent on the temperature difference with the baseline reference current.

Description

KI I-014-PCT PATENTAPPARATUS AND METHOD TO MITIGATE GAIN VARIATION OVER TEMPERATURE DUE TO LOCAL HEATINGCROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U. S. C.§119 from U. S. Provisional Application Number 63 / 764, 890 entitled " Apparatus and Method to Mitigate Gain Variation Over Temperature Due to Local Heating, " filed on Feb. 28, 2025, the subject matter of which is incorporated herein by reference.TECHNICAL FIELD

[0002] This disclosure generally relates to an apparatus and method for reducing gain variation over temperature range in transceiver systems. Specifically, the disclosure relates to an apparatus and method for mitigating gain variation by dynamically adjusting reference currents based on localized thermal gradients.BACKGROUND

[0003] In wireless communicat ion systems, transceiver systems conventionally compensate for gain variation by using a fixed proportional to absolute temperature (PTAT) current source to boost the reference current entering the bias cel l. However, this does not consider the heat generated by devices such as amplif iers and power amplifiers causing localized temperature variations across the substrate so gain variat ion due to heating persists in such systems. In modern semiconductor devices, high-power core circuitry— such as amplification stages in radio frequency (RF) front-ends—frequently experiences localizedKI I-014-PCT PATENTheating during operation. This localized heat generation creates a "hot zone" on the die that can be at a significantly higher temperature than the rest of the integrated circuit.

[0004] There is a need for an improved solut ion to mit igate gain variation over temperature due to local heating.SUMMARY

[0005] Apparatus and methods are provided to mitigate gain variation over temperature caused by localized heating. In one novel aspect, a temperature-compensated baseline reference current is generated in biasing circuitry and supplied toward core circuitry that processes signals. A current-slope control modifies a temperature dependence of the baseline reference current to produce an adjusted reference current used to bias the core circuitry. The slope control is determined from an estimated temperature difference between a localized heating region associated with the core circuitry and a region associated with the biasing circuitry that is thermally decoupled from the localized heating region. In one embodiment, sensing transistor ( SNS ) is thermally coupled to the localized heating zone. A bulk transistor (BULK) is electrically coupled to the SNS transistor and disposed within the region of the biasing circuitry that is thermally decoupled from the localized heating zone and the estimated temperature difference corresponds to a temperature difference between the BULK transistor and the SNS transistor. In one embodiment, the adjusted reference current based on the baseline reference current and a correction current having a magnitude proportional to the estimated temperature difference. In one embodiment,KI I-014-PCT PATENTemitter size of the BULK transistor and / or the SNS transistor is selected for substantially constant gain over a temperature range. In another embodiment, a first bias current through the SNS transistor and a second bias current through the BULK transistor are substantially equal. The transistors can be bipolar junction transistors (BJT) or field effect transistors (FET).

[0006] In one embodiment, the core circuitry comprises amplification circuitry. In one embodiment, the amplification circuitry comprises a common emitter (CE ) transistor and at least one of a common base (CB) transistor or common source (CS ) transistor and at least one of a common gate (CG) transistor. In one embodiment, the SNS transistor is exposed to a temperature increase in response to local heating of an amplification stage of the amplification circuitry. The BULK transistor is exposed to a different thermal condition compared to the amplification stage of the amplification circuitry.

[0007] In one embodiment, the temperature-compensated current source is a combination of a proport ional-to-absolute-temperature (PTAT ) current source and a complementary-to-absolute-temperature (CTAT ) current source. In another embodiment, the current slope control circuitry is configured to set the temperature dependence of the adjusted reference current by controlling an emitter resistance, a source resistance, and / or a bias current source associated with the biasing circuitry or the core circuitry.

[0008] Other embodiments and advantages are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.KI I-014-PCT PATENTBRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. l illustrates a block diagram of an example transceiver system having exemplary localized heating zones with different temperature from the master bias ambient temperature.

[0010] Fig. 2 illustrates exemplary top level diagrams showing the basic operation of the apparatus and method.

[0011] FIG. 3 illustrates one embodiment of the apparatus and method to mitigate gain variation due to local heating.

[0012] FIG. 4 illustrates another embodiment and method to adjust the reference current to mitigate gain variation due to local heating.

[0013] FIG. 5 illustrates a third embodiment to adjust the reference current to mitigate gain variation due to local heating.

[0014] FIG. 6 illustrates exemplary charts for results using the disclosed temperature-difference-based slopecontrol.

[0015] FIG. 7 illustrates a flow chart for methods of mitigating gain variation due to local heating based on estimated temperature differences between a localized heating zone and thermally decoupled zone.DETAILED DESCRIPTION

[0016] Reference will now be made in detail to some embodiments of the invention, examples of which are illustrated in the accompanying drawings.

[0017] In wireless communication systems, transceiver systems conventionally compensate for gain variation by using a fixed proport ional-to-absolute-temperature (PTAT) current source to boost the reference current entering aKI I-014-PCT PATENTbias cell. However, this does not take into account the heat generated by devices such as amplifiers and power amplifiers. Therefore gain variation due to heating persists in such systems. In certain amplification stages, especially those having relatively large power dissipation, the core cell heats up significantly more than the bias generation block resulting in the reference current being lower than necessary to maintain the desired gain at higher temperatures.

[0018] Described herein are an apparatus and method for mitigating gain variation due to differences in local heating. The apparatus and method provide accurate current slope control for a reference current based on the estimated temperature difference between the core circuitry and the bias generation block. This is achieved by detecting the temperature difference between a bulk transistor, tracking ambient die temperature, and a sensing ( SNS ) transistor thermally coupled to the core circuitry. A correction current proportional to this temperature difference is then provided to a reference device to adjust the slope of the reference current.

[0019] More specifically, within a transceiver system, different components within the die may be at different junction temperatures. For each block, a relative temperature gradient between ambient temperature (Tambient) and junction temperature (Tjunction) is sensed. A reference current appropriate for the junction temperature is then determined based on the relative temperature gradient, thereby improving RF performance. The proposed apparatus and method do not limit the usable bandwidth of the system and do not add significant power consumption to the system budget. Accordingly, the apparatus and method are suitableKI I-014-PCT PATENTfor use in amplifiers that consume significant power and thereby cause substantial heating in the core device. While the examples provided show bipolar junction transistors (BJT), field effect transistors (FET ) are equally applicable.

[0020] FIG. l illustrates a block diagram of an example transceiver system having exemplary localized heating zones with different temperature from the master bias ambient temperature. Operating Temperature 101 represents an operating temperature distribution across the die (or package ), which may vary spatially as a function of block activity and power dissipation. A master bias— ambient temperature 102 block, represents ambient / global temperature conditions including bias generation circuitry, which is configured to generate a baseline reference current. This system has two amplifiers, amplifier-1 111 and amplifier-2 112, both of which have higher temperatures at the input and the output stages. For example, when the input stage of each amplifier may have a temperature that is 10 °C to 20 °C greater than the master bias ambient temperature. The output stage of each amplifier may have a temperature that is 20 °C to 40 °C greater than the master bias ambient temperature. In embodiments described herein, the current reference of the master bias block, disposed in the zone of master bias temperature block 102, is substantially independent of local heating of remote amplification stages because the master bias block is physically distant from the heating sources. The proposed method more accurately accounts for local heating and the resulting variation in gain by assuming local heating rather than global heating per amplification.KI I-014-PCT PATENT

[0021] Fig. 2 illustrates exemplary top level diagrams showing the basic operation of the apparatus and method. A master bias generation block has a local reference PTAT. FIG. 2 depicts a baseline reference current component I_REF_PTAT 201, a delta_T sensor 220 located in proximity of a device which is located at a distance from the bias generation block, a correction current component I_CORRECTION 202, and a resulting total (adjusted) reference current I_REF_TOTAL 210. When the device is active, delta_ T sensor 220 determines the change in temperature, and this AT is the basis of a local correction factor, I_Correction 202. This local correction factor is combined with the local reference PTAT in order to obtain the total local reference current, I_REF_Total 210.

[0022] In one mode of operation, I_REF_PTAT 201 represents a baseline reference current that is compensated for ambient / global temperature variation, for example, a PTAT-based current generated in biasing circuitry that may also include CTAT compensation in other embodiments. In yet other embodiments, CTAT compensation may be used instead of PTAT. A device or core circuit block that is located at a distance from the bias generation block may therefore be associated with such a baseline reference current that is not corrected for local hot-spot heating effects. When the device or core block is active and experiences local heating, the DELTA_T SENSOR 220 determines a change in temperature (AT ) that characterizes a difference between a locally heated region (e. g., a core / amplif ier area) and a thermally different region associated with bias generation which will typically be at a lower temperature. In embodiments described elsewhere in the disclosure, the AT sensor can be implemented using the thermal characteristicsKI I-014-PCT PATENTof transistor devices, for example, a sensing device thermally coupled to a heated core region and aref erence / bulk device located in a thermally different region.

[0023] In one embodiment, the AT determined by the DELTA_T SENSOR 220 is used as the basis of a local correction factor, which is implemented in FIG. 2 as a correction current I_CORRECTION 202. In some embodiments, the magnitude of the correction current is determined based on AT (and may be proportional to AT). The correction current I_CORRECTION 202 is combined with the baseline reference current I_REF_PTAT 201 to obtain the total local reference current source I_ REF_ TOTAL 210. The resultingtotal / ref erence current ( I_REF_TOTAL 210 ) may be used to bias a corresponding core circuit block, thereby providing an adjusted reference current whose effective temperature dependence ( slope) closely tracks the local junction temperature of that core block to minimize gain variation over temperature rather than a reference current based only the master bias ambient temperature. Using the AT-based correction to adjust reference-current slope can improve gain stability over temperature in systems having substantial localized heating (e. g., high-power amplification stages ), while not significantly increasing power consumption or limiting usable bandwidth.

[0024] FIG. 3 illustrates an embodiment of bias circuit, AT sensor, and I_Correction. The emitter size of the bulk or bias transistors or the temperature sensor transistor can be selected to generate the adjusted reference current to mitigate gain variation due to local heating. The apparatus has both biasing circuitry and core circuitry. The biasing circuitry is configured to provide a referenceKI I-014-PCT PATENTcurrent that is compensated for temperature-induced gain variations. The core circuitry is coupled to the biasing circuitry. The core circuitry is configured to process signals based on the reference current, which is adjusted through current slope control. The current slope control is determined based on an estimated temperature difference between the biasing circuitry and core circuitry.

[0025] The biasing circuitry includes a PTAT block 311 and a CTAT block 312 that cooperates to generate baseline, ambient-compensated reference current. Biasing elements 313a and 313b (e. g., scaling and / or mirroring elements ) couple the PTAT and CTAT components to form a baseline reference current at node IREFO 310. In some embodiments, the baseline reference current is provided by a temperature-compensated current source formed by a combination of PTAT and CTAT current sources.

[0026] The core circuitry disposed, at least in part, within a localized heating zone 301. The localized heating zone 301 represents a portion of the die / package that experiences elevated junction temperature during operation due to power dissipation by one or more active devices (e. g., amplifier devices ). The core circuitry includes an amplification stage comprising a common source (CS ) transistor 331 and a common gate (CG) transistor 333. A replica circuit 332 and associated matching network 334 are further disposed within the localized heating zone 301 to mirror the thermal and electrical states of the primary amplification stage. The replica circuit is configured to mimic behavior of one or more portions of the amplification circuitry, such as CS 331 and CG 333, to provide stable bias voltage and / or reference current. The core circuitry is coupled to an output network that may include inductorKI I-014-PCT PATENT383, capacitor 382, and an output node 381 (e. g., a load and / or antenna connection).

[0027] The current slope control circuitry generates an adjusted reference current by modifying the temperature dependence of the baseline current 310. This circuitry comprises a differential sensing pair including a sensing ( SNS ) transistor 322 and a bulk (BULK) transistor 321. The SNS transistor 322 is thermally coupled / exposed to the localized heating zone 301, such as the local heating of amplification stage of the amplification circuitry. SNS transistor 322 tracks core temperature changes, such as temperature increases of amplification stage of the amplification circuitry. The BULK transistor 321 may be exposed to a different thermal condition than the SNS transistor 322 and the amplification stage. The BULK transistor 321 (including sub-elements 321a and 321b) is disposed in a region thermally decoupled from the localized heating zone 301 to track ambient die temperature.

[0028] In operation 320, the slope control circuitry uses the estimated temperature difference between the SNS transistor 322 and the BULK transistor 321 to adjust the temperature dependence of the baseline reference current (e. g., IREF0 310 ) so that an adjusted reference current is delivered locally to the core circuitry. The adjusted reference current is applied at node 335, which feeds at least a portion of the amplification circuitry and / or replica circuit, thereby biasing the core circuitry based on an adjusted reference current that more closely matches temperature of the localized heating zone 301. In some embodiments, the slope control circuitry generates a correction current as a function of the estimated temperature difference and combines the correction currentKI I-014-PCT PATENTwith the baseline reference current to form the adjusted reference current.

[0029] In some embodiments 330, the temperature dependence of the adjusted reference current may be set by selecting specific emitter sizes for the SNS transistor 322 or BULK transistor 321. The apparatus is configured such that an emitter size of at least one of the SNS transistor 331 or the BULK transistor 332 is selected and / or trimmed to achieve substantially constant gain and / or substantially constant transconductance over temperature (e. g., "flat gain" or "constant Gm" operation). Such sizing can be implemented, for example, by selecting the number and / or geometry of transistor segments 322 and / or 321a / 322b.

[0030] FIG. 4 is another embodiment adding emitter resistors, source resistors if using FETs, to better control the local temperature slope to mitigate gain variation due to local heating. In one embodiment, the temperature-sensing and slope-setting approach is realized using a SNS device and a BULK device biased in a controlled manner, and in which additional slope-setting parameters, emitter resistors, are used to tune the PTAT slope at a given ambient temperature.

[0031] The biasing circuitry utilizes PTAT 411 and CTAT 412 sources with summing blocks 413a and 413b to provide the baseline current to the summation node 425. The core circuitry is situated in a localized heating zone 401 and includes Temp Delta transistor 421b, amplification transistors 431 and 433, a replica circuit 432, and matching / coupling networks 434 and 435. The output signal is transmitted via output node 481 (e. g., a load and / or antenna connection) through passive components, such as inductor 483 and capacitor 482.KI I-014-PCT PATENT

[0032] The current slope control circuitry in this embodiment emphasizes electrical tuning of the current slope. The BULK transistor 421a and a corresponding delta temperature sensing transistor 421b thermally coupled to the localized heating zone 401 determine the temperature difference between the ambient temperature and core device temperature. In this high-precision configuration 420, the SNS and BULK transistors are biased with substantially equal currents ( Ibl = Ib2 ) using bias current sources 422a and 422b. This equal biasing minimizes current-density errors, ensuring the sensing logic responds purely to thermal gradients. The temperature dependence of the adjusted reference current is set by controlling at least one of an emitter resistance, or source resistance if FETs are used, via adjustable resistors 423a and 423b. By adjusting these resistances in conjunction with the bias current sources ( 420 ), the slope of the reference current can be precisely "tilted" to counteract gain droop at specific ambient temperatures. This allows for dynamic calibration of the slope without requiring physical changes to the transistor emitter sizes. In an embodiment, the emitter resistors 423a and / or 423b can be a series bank of resistors or a parallel bank of resistors or a combination of series and parallel resistors. In another embodiment, the emitter resistor values can be determined at the factory and stored to be recalled for use to minimize gain variations. In another embodiment, the emitter resistors can be tuned during operation for specific ambient and local temperatures to minimize gain variations.

[0033] FIG. 5 is another embodiment of the bias generation and Iref correction circuitry where where bulk CE / CS, replica device and SNS device generate the adjustedKI I-014-PCT PATENTreference current to mitigate gain variation due to local heating. The biasing circuitry comprises a PTAT current source 511 and a CTAT current source 512, which are weighted by adjustable blocks 513a and 513b to provide baseline reference current to a summation node 525. The current slope control circuitry utilizes a multi-transistor BULK assembly 521, which includes transistors 521a, 521b, and 521c, each associated with a respective adjustable emitter, or source resistance if FETs are used, 523a, 523b, and 523c. These BULK transistors are disposed in a thermally decoupled region to track the ambient die temperature for the master bias block. An SNS transistor 522 is disposed within a hot zone 501, which is thermally coupled to the heat-generating elements of the core circuitry. The sensing pair is biased by current sources 520, which are configured to maintain substantially equal currents, denoted as Ibl = Ib2, to minimize gain errors resulting from current density mismatches.

[0034] The core circuitry is situated within a localized heating zone 501 and comprises a primary amplification stage including a common emitter transistor 531 and a common base transistor 533. To ensure accurate bias tracking, a replica circuit 532 is provided within the same localized heating zone 501, coupled through matching and coupling networks 534 and 535. The processed output signal is delivered to an antenna 581 via an output matching network comprising an inductor 583 and a capacitor 582. By adjusting the resistances 523a, 523b, and 523c, as well as the adjustable resistance 523 associated with the SNS transistor 522, the apparatus enables the electrical tuning of the PTAT slope of the reference current to specifically counteract the transconductance degradation of theKI I-014-PCT PATENTamplification stage caused by localized junction heating. In an embodiment, one or more of the emitter resistors 523a, 523b, 523c, and 522 can be a series bank of resistors or a parallel bank of resistors or a combination of series and parallel resistors. In another embodiment, the emitter resistor values can be determined at the factory and stored to be recalled for use to minimize gain variations. In another embodiment, the emitter resistors can be tuned during operation for specific ambient and local temperatures to minimize gain variations.

[0035] FIG. 6 illustrates exemplary charts for results using the disclosed temperature-difference-based slopecontrol. Illustrated is a graphical representation of the corrected reference current magnitude, Iref_corr (m), relative to the operating temperature, illustrating the dynamic tuning capabilities of the slope control circuitry. The curve 601 represents the uncorrected baseline reference current, Iref_uncorr, which typically exhibits a standard PTAT slope derived from the biasing circuitry without localized adjustment. The graph 611 demonstrates a set of slopes that can be obtained for various junction temperatures at a first bulk temperature of 30 °C. Graph 612 demonstrates a set of slopes that can be obtained for various junction temperatures at a second bulk temperature of 120 °C. The differing families of corrected traces illustrate that, for a given ambient reference-side temperature (Tbulk), the slope-control mechanism can be configured to provide an adjusted reference current having an altered temperature dependence ( slope ) relative to the uncorrected reference current, thereby providing bias current behavior that better matches local junction temperature behavior of the core circuitry. InKI I-014-PCT PATENTembodiments, such slope adjustment can be achieved using the equal-current biasing approach (e. g., Ibl = Ib2 ) together with controlled resistances and / or bias current sources to tune the slope at a given ambient temperature, consistent with the described implementations.

[0036] A constant Gm can be achieved with accurate current slope control. This in turn limits gain variation across temperature. Using the AT-based reference-current slope control, improved bias-current tracking can be achieved across temperature, enabling substantially constant transconductance and / or reduced gain variation over temperature for a gain stage subject to localized heating.

[0037] FIG. 7 illustrates a flow chart for methods of mitigating gain variation due to local heating based on estimated temperature differences between a localized heating zone and thermally decoupled zone. At step 701, the apparatus provides, at biasing circuitry, a baseline reference current compensated for ambient temperature variations. At step 702, the apparatus estimates a temperature difference between (i ) a localized heating zone containing at least a portion of core circuitry and ( ii ) a region of the biasing circuitry that is thermally decoupled from the localized heating zone. At step 703, the apparatus generates, at current slope control circuitry, an adjusted reference current by adjusting a temperature dependence of the baseline reference current based on the estimated temperature difference. At step 704, the apparatus processes signals at the core circuitry, based on the adjusted reference current.

[0038] Although the present invention has been described in connection with certain specific embodiments for instructional purposes, the present invention is notKI I-014-PCT PATENTlimited thereto. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

KI I-014-PCT PATENTCLAIMSWhat is claimed is:

1. An apparatus for mitigating gain variation over temperature, comprising:biasing circuitry configured to provide a baseline reference current compensated for ambient temperature variations;current slope control circuitry configured to generate an adjusted reference current by adjusting a temperature dependence of the baseline reference current based on an estimated temperature difference between ( i ) a localized heating zone containing at least a portion of a core circuitry and (ii ) a region of the biasing circuitry that is thermally decoupled from the localized heating zone; and core circuitry electrically coupled to the biasing circuitry and configured to process signals based on the adjusted reference current derived from the baseline reference current such that a gain variation is minimized.

2. The apparatus of claim 1, further comprising a sensing ( SNS ) transistor thermally coupled to the localized heating zone.

3. The apparatus of claim 2, further comprising a bulk (BULK) transistor electrically coupled to the SNS transistor and disposed within the region of the biasing circuitry that is thermally decoupled from the localized heating zone, wherein the estimated temperature difference corresponds to a temperature difference between the BULK transistor and the SNS transistor.

4. The apparatus of claim 3, wherein the current slope control circuitry is configured to generate the adjustedKI I-014-PCT PATENTreference current based on the baseline reference current and a correction current having a magnitude proportional to the estimated temperature difference.

5. The apparatus of claim 3, wherein an emitter size of at least one of the BULK transistor or the SNS transistor is selected for substantially constant gain over a temperature range.

6. The apparatus of claim 3, wherein a first bias current through the SNS transistor and a second bias current through the BULK transistor are substantially equal.

7. The apparatus of claim 3, wherein the core circuitry comprises amplification circuitry.

8. The apparatus of claim 7, wherein the amplification circuitry comprises a common gate (CG) transistor and at least one of a common source (CS ) transistor or a common emitter (CE) device.

9. The apparatus of claim 7, wherein the amplification circuitry further comprises a replica circuit.

10. The apparatus of claim 7, wherein the SNS transistor is exposed to a temperature increase in response to local heating of an amplification stage of the amplification circuitry.

11. The apparatus of claim 10, wherein the BULK transistor is exposed to a different thermal condition compared to the amplification stage of the amplification circuitry.KI I-014-PCT PATENT12. The apparatus of claim 1, wherein the biasing circuitry comprises a temperature-compensated current source.

13. The apparatus of claim 12, wherein the temperature-compensated current source is a combination of aproport ional-t o-absolute-temperature (PTAT ) current source and a complementary-to-absolute-temperature (CTAT ) current source.

14. The apparatus of claim 1, wherein the current slope control circuitry is configured to set the temperature dependence of the adjusted reference current by controlling at least one of an emitter resistance, a source resistance, or a bias current source associated with the biasing circuitry or the core circuitry.

15. A method for mitigating gain variation over temperature, comprising:providing, at biasing circuitry, a baseline reference current compensated for ambient temperature variations;estimating a temperature difference between (i ) a localized heating zone containing at least a portion of core circuitry and ( ii ) a region of the biasing circuitry that is thermally decoupled from the localized heating zone;generating, at current slope control circuitry, an adjusted reference current by adjusting a temperature dependence of the baseline reference current based on the estimated temperature difference; andprocessing signals, at the core circuitry, based on the adjusted reference current.KI I-014-PCT PATENT16. The method of claim 15, wherein estimating the temperature difference comprises detecting a temperature difference between a sensing ( SNS ) transistor thermally coupled to the localized heating zone and a bulk (BULK) transistor disposed in the thermally decoupled region.

17. The method of claim 16, further comprising biasing the SNS transistor and the BULK transistor with substantially equal currents.

18. The method of claim 16, further comprising tuning a slope of the adjusted reference current by at least one procedure comprising (i ) selecting an emitter size of at least one of the SNS transistor or the BULK transistor, or ( ii ) controlling at least one of an emitter resistance, a source resistance, or a bias current source associated with at least one of the core circuitry or the biasing circuitry.

19. The method of claim 15, wherein generating the adjusted reference current comprises combining a correction current with the baseline reference current, the correction current having a magnitude proportional to the estimated temperature difference.

20. The method of claim 15, wherein the baseline reference current is provided by a combination of a proportional to absolute temperature (PTAT ) current source and a complementary to absolute temperature (CTAT ) current source.

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