Shift register unit, display substrate and display apparatus

Abstract

Provided in the present disclosure are a shift register unit, a display substrate and a display apparatus. In the shift register unit, a first output circuit is separately coupled to a first output node, a first level signal input terminal and a gate driving signal output terminal of the shift register unit; a pull-down coupling control circuit is separately coupled to the first output node, a first coupling node and a first clock signal input terminal; and a reset circuit is separately coupled to a reset signal input terminal, a second level signal input terminal and a first input node.

Description

Shift register unit, display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a shift register unit, a display substrate, and a display device. Background Technology

[0002] Currently, the development of display products is characterized by high integration and low cost. A crucial technology employed in display products is the mass production of GOA (Gate Driver on Array) technology. GOA technology integrates the gate driver circuit onto the array substrate of the display panel, thus eliminating the need for the gate driver integrated circuit itself, thereby reducing product costs in terms of both materials and manufacturing processes. This gate driver circuit integrated onto the array substrate using GOA technology is also called a GOA circuit or shift register circuit, where each shift register circuit within the gate driver circuit is also called a shift register unit. Summary of the Invention

[0003] The purpose of this disclosure is to provide a shift register unit, a display substrate, and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] The first aspect of this disclosure provides a shift register unit, including: a first input node, a first output node, a first coupling node, a first output circuit, a pull-down coupling control circuit, and a reset circuit;

[0006] The first output circuit is coupled to the first output node, the first level signal input terminal, and the gate drive signal output terminal of the shift register unit, respectively; it is used to control the electrical connection between the first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first output node.

[0007] The pull-down coupling control circuit is coupled to the first output node, the first coupling node, and the first clock signal input terminal respectively; it is used to control the electrical connection between the first coupling node and the first clock signal input terminal to be turned on or off under the control of the potential of the first output node; it is also used to control the potential of the first output node according to the potential of the first coupling node.

[0008] The reset circuit is coupled to the reset signal input terminal, the second level signal input terminal, and the first input node, respectively; it is used to control the electrical connection between the second level signal input terminal and the first input node to be turned on or off under the control of the reset signal input at the reset signal input terminal.

[0009] Optionally, the shift register unit further includes: a second coupling node, a second input node, a coupling node control circuit, and a first control circuit;

[0010] The coupling node control circuit is coupled to the second coupling node, the first clock signal input terminal, the first input node, and the second level signal input terminal, respectively; it is used to control the potential of the second coupling node according to the clock signal input from the first clock signal input terminal; and it is also used to control the electrical connection between the second level signal input terminal and the second coupling node to be turned on or off under the control of the potential of the first input node.

[0011] The first control circuit is coupled to the first input node, the second input node, the second coupling node, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second input node to be turned on or off under the control of the potential of the first input node; it is also used to control the electrical connection between the first level signal input terminal and the second input node to be turned on or off under the control of the potential of the second coupling node.

[0012] Optionally, the shift register unit further includes a second output node and a second output circuit; the second output circuit is coupled to the second output node, the gate drive signal output terminal, and the second level signal input terminal respectively; it is used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off under the control of the second output node; the second input node is directly coupled to the second output node.

[0013] Optionally, the shift register unit further includes a second output node and a second output circuit; the second output circuit is coupled to the second output node, the gate drive signal output terminal, and the second level signal input terminal respectively; it is used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off under the control of the second output node.

[0014] The shift register unit further includes a second control circuit, which is coupled to the first clock signal input terminal, the second input node and the second output node respectively, and is used to control the electrical connection between the second input node and the second output node to be turned on or off under the control of the first clock signal input to the first clock signal input terminal.

[0015] Optionally, the shift register unit further includes a first input circuit, a third control circuit, a fourth control circuit, and a transmission circuit;

[0016] The first input circuit is coupled to the second clock signal input terminal, the input signal terminal, and the first input node, respectively; it is used to control the electrical connection between the input signal terminal and the first input node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal.

[0017] The third control circuit is coupled to the first input node, the second input node, the second level signal input terminal, and the first clock signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the first input node to be turned on or off under the control of the potential of the second input node and the first clock signal input to the first clock signal input terminal.

[0018] The fourth control circuit is coupled to the first input node, the second level signal input terminal and the second output node respectively, and is used to control the electrical connection between the second level signal input terminal and the second output node to be turned on or off under the control of the potential of the first input node.

[0019] The transmission circuit is coupled to the first level signal input terminal, the first input node, and the first output node respectively, and is used to control the electrical connection between the first input node and the first output node to be turned on or off under the control of the first level signal input to the first level signal input terminal.

[0020] Optionally, the first output circuit includes a first output transistor, the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first level signal input terminal, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal.

[0021] The pull-down coupling control circuit includes an eighth control transistor and a second capacitor; the gate of the eighth control transistor is coupled to the first output node, the first terminal of the eighth control transistor is coupled to the first clock signal input terminal, and the second terminal of the eighth control transistor is coupled to the first coupling node; the first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node.

[0022] The reset circuit includes a reset transistor, the gate of which is coupled to the reset signal input terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the first input node.

[0023] Optionally, the coupling node control circuit includes a first capacitor and a third control transistor; the first plate of the first capacitor is coupled to the first clock signal input terminal, and the second plate of the first capacitor is coupled to the second coupling node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal input terminal, and the second electrode of the third control transistor is coupled to the second coupling node.

[0024] The first control circuit includes a first control transistor and a second control transistor. The gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to the first level signal input terminal, and the second terminal of the first control transistor is coupled to the second input node. The gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to the second level signal input terminal, and the second terminal of the second control transistor is coupled to the second input node.

[0025] Optionally, the second output circuit includes a second output transistor, the gate of which is coupled to the second output node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal.

[0026] The second control circuit includes a fourth control transistor, the gate of which is coupled to the first clock signal input terminal, the first terminal of which is coupled to the second input node, and the second terminal of which is coupled to the second output node.

[0027] Optionally, the first input circuit includes an input transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the input signal terminal, and the second terminal of which is coupled to the first input node;

[0028] The third control circuit includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first terminal of the fifth control transistor is coupled to the second level signal input terminal, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second terminal of the sixth control transistor is coupled to the first input node.

[0029] The fourth control circuit includes a seventh control transistor, the gate of which is coupled to the first input node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the second output node.

[0030] The transmission circuit includes a transmission transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the first input node, and the second terminal of which is coupled to the first output node.

[0031] Based on the above-described shift register unit technical solution, a second aspect of this disclosure provides a display substrate, including a first level signal line, a second level signal line, and a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units. Each shift register unit includes a first output node, a first coupling node, a first output transistor, and a second capacitor. The gate of the first output transistor is coupled to the first output node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the gate driving signal output terminal. The first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node.

[0032] The orthographic projection of the second level signal line on the substrate of the display substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the first output transistor on the substrate.

[0033] Optionally, the shift register unit further includes a second output node, a second output transistor, and a third capacitor. The gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal. The first plate of the third capacitor is coupled to the gate of the second output transistor, and the second plate of the third capacitor is coupled to the second level signal line.

[0034] The orthographic projection of the second plate of the third capacitor onto the substrate at least partially overlaps with the orthographic projection of the second level signal line onto the substrate.

[0035] Optionally, the second level signal line extends along a first direction; the active layers of the first output transistor and the second output transistor are arranged along the first direction; the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the active layer of the second output transistor on the substrate are arranged along a second direction, and the second direction intersects the first direction.

[0036] Optionally, the second level signal line extends along the first direction; the shift register unit further includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second electrode of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

[0037] Optionally, the shift register unit further includes a first input node, a second input node, a second control transistor, and a seventh control transistor;

[0038] The gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to the second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the seventh control transistor is coupled to the first output node in the shift register unit, the first terminal of the seventh control transistor is coupled to the second level signal line, and the second terminal of the seventh control transistor is coupled to the second output node in the shift register unit.

[0039] The gate of the seventh control transistor is formed as an integral structure with the gate of the second control transistor.

[0040] Optionally, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive two rows of sub-pixel rows; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the seventh control transistor on the substrate are arranged along a first direction;

[0041] At least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the second plate of the second capacitor onto the substrate and the orthographic projection of the active layer of the seventh control transistor onto the substrate.

[0042] Optionally, the shift register unit further includes a reset transistor, the gate of which is coupled to a reset signal input terminal, the first terminal of which is coupled to the second level signal line, and the second terminal of which is coupled to the first input node; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the reset transistor on the substrate are arranged along a first direction; at least a portion of the orthographic projection of the active layer of the reset transistor on the substrate and the orthographic projection of the second plate of the third capacitor on the substrate are arranged along a second direction.

[0043] Optionally, the shift register unit further includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to a first clock signal input terminal, the first terminal of the fifth control transistor is coupled to a second level signal line, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to a second input node, and the second terminal of the sixth control transistor is coupled to a first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer extending along a second direction; the orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the integral active layer on the substrate; and / or,

[0044] The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to a first level signal line, and the second terminal of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to a second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second coupling node. The fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node. The orthographic projections of the second electrode of the second capacitor, the active layer of the fourth control transistor, the active layer of the second control transistor, and the active layer of the third control transistor on the substrate are arranged sequentially along the first direction. The orthographic projection of the active layer of the second control transistor on the substrate is located between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the second level signal line on the substrate.

[0045] Optionally, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive one row of sub-pixel rows; at least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the active layer of the seventh control transistor onto the substrate and the orthographic projection of the second level signal line onto the substrate.

[0046] Optionally, the shift register unit further includes a reset transistor, the gate of which is coupled to a reset signal input terminal, the first terminal of which is coupled to the second level signal line, and the second terminal of which is coupled to the first input node; the orthographic projection of the second plate of the second capacitor on the substrate is offset from the orthographic projection of the active layer of the reset transistor on the substrate along a first direction; at least a portion of the orthographic projection of the active layer of the reset transistor on the substrate and the orthographic projection of the second plate of the third capacitor on the substrate are aligned along a second direction.

[0047] Optionally, the shift register unit further includes a fourth control transistor, a fifth control transistor, and a sixth control transistor; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first electrode of the fourth control transistor is coupled to a second input node, and the second electrode of the fourth control transistor is coupled to a second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to a second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer extending along a first direction; at least a portion of the orthographic projection of the active layer of the fourth control transistor onto the substrate is located between the orthographic projection of the second electrode of the second capacitor onto the substrate and the orthographic projection of the integral active layer onto the substrate; at least a portion of the active layer of the seventh control transistor is located between the integral active layer and the active layer of the fourth control transistor; and / or,

[0048] The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to a first level signal line, and the second electrode of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to a second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layers of the first control transistor and the active layers of the eighth control transistor; the active layers of the first control transistor and the active layers of the third control transistor are arranged along the first direction, and at least a portion of the active layer of the second control transistor is located between the active layers of the first control transistor and the active layers of the third control transistor; the active layers of the first control transistor, the active layers of the second control transistor, and the active layers of the third control transistor are sequentially coupled to form a single structure.

[0049] Optionally, the first level signal line and the second level signal line in the display substrate are arranged along a second direction; the orthographic projection of the other transistor structures in the shift register unit, excluding the first output transistor and the second output transistor, on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate.

[0050] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0051] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0052] Figure 1 is a schematic diagram of the circuit module of the shift register unit provided in an embodiment of this disclosure;

[0053] Figure 2 is a circuit schematic diagram of a shift register unit provided in an embodiment of this disclosure;

[0054] Figure 3 is a timing diagram of the shift register unit provided in an embodiment of this disclosure;

[0055] Figure 4 is a signal waveform diagram of node N3 provided in an embodiment of this disclosure;

[0056] Figure 5 is a schematic diagram of the layout of the active layer in a shift register unit provided in an embodiment of this disclosure;

[0057] Figure 6 is a schematic diagram of the layout of the first gate metal layer in a shift register unit provided in an embodiment of the present disclosure;

[0058] Figure 7 is a schematic diagram of the layout of the second gate metal layer in a shift register unit provided in an embodiment of this disclosure;

[0059] Figure 8 is a schematic diagram of the layout of an active layer, a first gate metal layer, and a second gate metal layer in a shift register unit provided in an embodiment of this disclosure;

[0060] Figure 9 is a schematic diagram of the layout of the first source-drain metal layer in a shift register unit provided in an embodiment of this disclosure;

[0061] Figure 10 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 8;

[0062] Figure 11 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 8;

[0063] Figure 12 is a schematic diagram of the layout of the active layer in another shift register unit provided in an embodiment of this disclosure;

[0064] Figure 13 is a schematic diagram of the layout of the first gate metal layer in another shift register unit provided in an embodiment of this disclosure;

[0065] Figure 14 is a schematic diagram of the layout of the second gate metal layer in another shift register unit provided in an embodiment of this disclosure;

[0066] Figure 15 is a schematic diagram of the layout of an active layer, a first gate metal layer, and a second gate metal layer in another shift register unit provided in an embodiment of this disclosure.

[0067] Figure 16 is a schematic diagram of the layout of the first source-drain metal layer in another shift register unit provided in an embodiment of this disclosure;

[0068] Figure 17 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 15;

[0069] Figure 18 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 15;

[0070] Figure 19 is a schematic diagram of the layout of two shift register units provided in the embodiments of this disclosure;

[0071] Figure 20 is another circuit schematic diagram of the shift register unit provided in the embodiments of this disclosure. Detailed Implementation

[0072] To further illustrate the shift register unit, display substrate, and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0073] In related technologies, shift register units suffer from unstable output gate drive signals. This problem can easily lead to differences in pixel emission time and charging time in the driven display products, resulting in Mura risk.

[0074] Please refer to Figures 1 to 19. This disclosure provides a shift register unit 10, including: a first input node N1, a first output node N3, a first coupling node N0, a first output circuit 82, a pull-down coupling control circuit 80, and a reset circuit 88.

[0075] The first output circuit 82 is coupled to the first output node N3, the first level signal input terminal VGL, and the gate drive signal output terminal OUT of the shift register unit 10, respectively; it is used to control the electrical connection between the first level signal input terminal VGL and the gate drive signal output terminal OUT under the control of the potential of the first output node N3.

[0076] The pull-down coupling control circuit 80 is coupled to the first output node N3, the first coupling node N0, and the first clock signal input terminal CKB, respectively; it is used to control the electrical connection between the first coupling node N0 and the first clock signal input terminal CKB to be turned on or off under the control of the potential of the first output node N3; it is also used to control the potential of the first output node N3 according to the potential of the first coupling node N0.

[0077] The reset circuit 88 is coupled to the reset signal input terminal VEL, the second level signal input terminal VGH, and the first input node N1, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the first input node N1 to be turned on or off under the control of the reset signal input at the reset signal input terminal VEL.

[0078] For example, the first output circuit 82 includes a first output transistor T10, the gate 310 of which is coupled to the first output node N3, the first terminal of which is coupled to the first level signal input terminal VGL, and the second terminal of which is coupled to the gate drive signal output terminal OUT. For example, the first output transistor T10 includes a P-type transistor, and when the potential of the first output node N3 is low, the first output transistor T10 is turned on, controlling the electrical connection between the first level signal input terminal VGL and the gate drive signal output terminal OUT.

[0079] For example, the pull-down coupling control circuit 80 includes an eighth control transistor T11 and a second capacitor C2; the gate 311 of the eighth control transistor T11 is coupled to the first output node N3, the first terminal of the eighth control transistor T11 is coupled to the first clock signal input terminal CKB, and the second terminal of the eighth control transistor T11 is coupled to the first coupling node N0; the first plate C21 of the second capacitor C2 is coupled to the first output node N3, and the second plate C22 of the second capacitor C2 is coupled to the first coupling node N0. For example, the eighth control transistor T11 includes a P-type transistor, and when the potential of the first output node N3 is low, the eighth control transistor T11 is turned on, controlling the electrical connection between the first coupling node N0 and the first clock signal input terminal CKB. For example, the second capacitor C2 controls the potential of the first output node N3 according to the potential of the first coupling node N0. By adopting the above-described structure, the pull-down coupling control circuit 80 can not only achieve the beneficial effects of fast reset of the gate drive signal output terminal OUT and enhance the driving capability of the shift register unit 10, but also simplify the circuit structure of the shift register unit 10.

[0080] For example, the reset circuit 88 includes a reset transistor T13, the gate 313 of which is coupled to the reset signal input terminal VEL, the first terminal of which is coupled to the second level signal input terminal VGH, and the second terminal of which is coupled to the first input node N1. For example, the reset transistor T13 includes a P-type transistor; when the reset signal is low, the reset transistor T13 is turned on, controlling the electrical connection between the second level signal input terminal VGH and the first input node N1. For example, when the shift register unit 10 is applied to a display substrate, the display substrate also includes a reset signal line Rst, and the reset signal input terminals VEL of each cascaded shift register unit 10 are all coupled to the reset signal line Rst.

[0081] As can be seen from the specific structure of the shift register unit 10 described above, in the shift register unit 10 provided in this embodiment, the pull-down coupling control circuit 80 can control the electrical connection between the first coupling node N0 and the first clock signal input terminal CKB to be turned on or off, so that the potential of the first coupling node N0 can be the same as the potential of the clock signal input to the first clock signal input terminal CKB; at the same time, the pull-down coupling control circuit 80 can control the potential of the first output node N3 according to the potential of the first coupling node N0; thus, when resetting the gate drive signal output terminal OUT, the first coupling node can be controlled to have a suitable potential by controlling the input of a signal with a suitable potential to the first clock signal input terminal CKB, thereby controlling the potential of the first output node N3 to be pulled down quickly, eliminating the step formed during the process of the potential of the first output node N3 being pulled down, so that the gate drive signal output terminal OUT can be output stably, effectively reducing the disturbance of the output waveform.

[0082] In the shift register unit 10 provided in this embodiment, the shift register unit 10 includes a reset circuit 88, which can reset the first input node N1. Furthermore, when the shift register unit 10 is applied to a display substrate, the reset signal line Rst in the display substrate can control each level of the shift register unit 10 to simultaneously reset the first input node N1.

[0083] As shown in Figures 1 to 19, in some embodiments, the shift register unit 10 further includes: a second coupling node N4, a second input node N2, a coupling node control circuit 84, and a first control circuit 85;

[0084] The coupling node control circuit 84 is coupled to the second coupling node N4, the first clock signal input terminal CKB, the first input node N1, and the second level signal input terminal VGH, respectively; it is used to control the potential of the second coupling node N4 according to the clock signal input at the first clock signal input terminal CKB; it is also used to control the electrical connection between the second level signal input terminal VGH and the second coupling node N4 to be turned on or off under the control of the potential of the first input node N1.

[0085] The first control circuit 85 is coupled to the first input node N1, the second input node N2, the second coupling node N4, the first level signal input terminal VGL, and the second level signal input terminal VGH, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the second input node N2 under the control of the potential of the first input node N1; it is also used to control the electrical connection between the first level signal input terminal VGL and the second input node N2 under the control of the potential of the second coupling node N4.

[0086] For example, the coupling node control circuit 84 includes a first capacitor C1 and a third control transistor T4; the first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and the second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the gate 34 of the third control transistor T4 is coupled to the first input node N1, the first terminal of the third control transistor T4 is coupled to the second level signal input terminal VGH, and the second terminal of the third control transistor T4 is coupled to the second coupling node N4; for example, the third control transistor T4 includes a P-type transistor, and when the potential of the first input node N1 is low, the third control transistor T4 is turned on, controlling the electrical connection between the second level signal input terminal VGH and the second coupling node N4. The first capacitor C1 can control the potential of the second coupling node N4 according to the clock signal input at the first clock signal input terminal CKB.

[0087] For example, the first control circuit 85 includes a first control transistor T2 and a second control transistor T3. The gate 32 of the first control transistor T2 is coupled to the second coupling node N4, the first terminal of the first control transistor T2 is coupled to the first level signal input terminal VGL, and the second terminal of the first control transistor T2 is coupled to the second input node N2. The gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal input terminal VGH, and the second terminal of the second control transistor T3 is coupled to the second input node N2.

[0088] For example, the first control transistor T2 includes a P-type transistor. When the potential of the second coupling node N4 is low, the first control transistor T2 is turned on, controlling the electrical connection between the first level signal input terminal VGL and the second input node N2. The second control transistor T3 includes a P-type transistor. When the potential of the first input node N1 is low, the second control transistor T3 is turned on, controlling the electrical connection between the second level signal input terminal VGH and the second input node N2.

[0089] In the shift register unit 10 described above, by setting the coupling node control circuit 84 and the first control circuit 85, the potential of the second input node N2 can be controlled by the potential of the first input node N1 and the first clock signal input at the first clock signal input terminal CKB.

[0090] As shown in Figures 1 to 19, in some embodiments, the shift register unit 10 further includes a second output node N5 and a second output circuit 83; the second output circuit 83 is coupled to the second output node N5, the gate drive signal output terminal OUT, and the second level signal input terminal VGH, respectively; it is used to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH to be turned on or off under the control of the second output node N5; the second input node N2 is directly coupled to the second output node N5.

[0091] For example, the second output circuit 83 includes a second output transistor T9. The gate 39 of the second output transistor T9 is coupled to the second output node N5. The first terminal of the second output transistor T9 is coupled to the second level signal input terminal VGH, and the second terminal of the second output transistor T9 is coupled to the gate drive signal output terminal OUT. For example, the second output transistor T9 includes a P-type transistor. When the potential of the second output node N5 is low, the second output transistor T9 is turned on, controlling the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH.

[0092] For example, the second output circuit 83 further includes a third capacitor C3, the first plate C31 of the third capacitor C3 being coupled to the gate 39 of the second output transistor T9, and the second plate C32 of the third capacitor C3 being coupled to the second level signal input terminal VGH.

[0093] The above configuration directly couples the second input node N2 and the second output node N5, meaning that no other circuit structure is added between the second input node N2 and the second output node N5. This not only ensures the normal operation of the shift register unit 10, but also simplifies the circuit structure of the shift register unit 10. When the shift register unit 10 is applied to a display product, it helps to reduce the layout space occupied by the shift register unit 10.

[0094] As shown in Figures 1 to 19, in some embodiments, the shift register unit 10 further includes a second output node N5 and a second output circuit 83; the second output circuit 83 is coupled to the second output node N5, the gate drive signal output terminal OUT, and the second level signal input terminal VGH, respectively; it is used to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH to be turned on or off under the control of the second output node N5;

[0095] The shift register unit 10 further includes a second control circuit 89, which is coupled to the first clock signal input terminal CKB, the second input node N2 and the second output node N5 respectively, and is used to control the electrical connection between the second input node N2 and the second output node N5 to be turned on or off under the control of the first clock signal input to the first clock signal input terminal CKB.

[0096] For example, the second output circuit 83 includes a second output transistor T9. The gate 39 of the second output transistor T9 is coupled to the second output node N5. The first terminal of the second output transistor T9 is coupled to the second level signal input terminal VGH, and the second terminal of the second output transistor T9 is coupled to the gate drive signal output terminal OUT. For example, the second output transistor T9 includes a P-type transistor. When the potential of the second output node N5 is low, the second output transistor T9 is turned on, controlling the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGH.

[0097] For example, the second output circuit 83 further includes a third capacitor C3, the first plate C31 of the third capacitor C3 being coupled to the gate 39 of the second output transistor T9, and the second plate C32 of the third capacitor C3 being coupled to the second level signal input terminal VGH.

[0098] For example, the second control circuit 89 includes a fourth control transistor T5. The gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB. The first terminal of the fourth control transistor T5 is coupled to the second input node N2, and the second terminal of the fourth control transistor T5 is coupled to the second output node N5. For example, the fourth control transistor T5 includes a P-type transistor. When the first clock signal input to the first clock signal input terminal CKB is low, the fourth control transistor T5 is turned on, controlling the electrical connection between the second input node N2 and the second output node N5.

[0099] The shift register unit 10 described above also includes a second control circuit 89, which couples the second input node N2 and the second output node N5 together. In this way, the second control circuit 89 can control whether to conduct the electrical connection between the second input node N2 and the second output node N5, thereby improving the stability of the shift register unit 10.

[0100] As shown in Figures 1 to 19, in some embodiments, the shift register unit 10 further includes a first input circuit 86, a third control circuit 87, a fourth control circuit 810, and a transmission circuit 81.

[0101] The first input circuit 86 is coupled to the second clock signal input terminal CK, the input signal terminal STV and the first input node N1 respectively; it is used to control the electrical connection between the input signal terminal STV and the first input node N1 to be turned on or off under the control of the second clock signal input to the second clock signal input terminal CK.

[0102] The third control circuit 87 is coupled to the first input node N1, the second input node N2, the second level signal input terminal VGH, and the first clock signal input terminal CKB, respectively; it is used to control the electrical connection between the second level signal input terminal VGH and the first input node N1 under the control of the potential of the second input node N2 and the first clock signal input to the first clock signal input terminal CKB.

[0103] The fourth control circuit 810 is coupled to the first input node N1, the second level signal input terminal VGH and the second output node N5 respectively, and is used to control the electrical connection between the second level signal input terminal VGH and the second output node N5 to be turned on or off under the control of the potential of the first input node N1.

[0104] The transmission circuit 81 is coupled to the first level signal input terminal VGL, the first input node N1 and the first output node N3 respectively, and is used to control the electrical connection between the first input node N1 and the first output node N3 to be turned on or off under the control of the first level signal input to the first level signal input terminal VGL.

[0105] For example, the first input circuit 86 includes an input transistor T1, the gate 31 of which is coupled to the second clock signal input terminal CK, the first terminal of which is coupled to the input signal terminal STV, and the second terminal of which is coupled to the first input node N1. For example, the first input transistor T1 includes a P-type transistor. When the second clock signal input to the second clock signal input terminal CK is low, the first input transistor T1 is turned on, controlling the electrical connection between the input signal terminal STV and the first input node N1 to be connected.

[0106] For example, the third control circuit 87 includes a fifth control transistor T6 and a sixth control transistor T7; the gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal input terminal VGH, and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; the gate 37 of the sixth control transistor T7 is coupled to the second input node N2, and the second terminal of the sixth control transistor T7 is coupled to the first input node N1;

[0107] For example, the fifth control transistor T6 includes a P-type transistor. When the first clock signal input at the first clock signal input terminal CKB is low, the fifth control transistor T6 is turned on, controlling the electrical connection between the second level signal input terminal VGH and the first terminal of the sixth control transistor T7. The sixth transistor includes a P-type transistor. When the potential of the second input node N2 is low, the sixth control transistor T7 is turned on, controlling the electrical connection between the second terminal of the fifth control transistor T6 and the first input node N1.

[0108] For example, the fourth control circuit 810 includes a seventh control transistor T8, the gate 38 of which is coupled to the first input node N1, the first terminal of which is coupled to the second level signal input terminal VGH, and the second terminal of which is coupled to the second output node N5. For example, the seventh control transistor T8 includes a P-type transistor, and when the potential of the first input node N1 is low, the seventh control transistor T8 is turned on, controlling the electrical connection between the second level signal input terminal VGH and the second output node N5 to be turned on.

[0109] For example, the transmission circuit 81 includes a transmission transistor T12, the gate 312 of which is coupled to the first level signal input terminal VGL, the first terminal of which is coupled to the first input node N1, and the second terminal of which is coupled to the first output node N3. For example, the transmission transistor T12 includes a P-type transistor, and under the control of the first level signal input to the first level signal input terminal VGL, the transmission transistor T12 is turned on, controlling the electrical connection between the first input node N1 and the first output node N3 to be established.

[0110] It is worth noting that the shift register unit 10 provided in the above embodiments is applicable to LTPS, LTPO, or all-oxide display products. The shift register unit 10 can be used for EM GOA (Emitting Light Control Shift Register Unit), Reset GOA (Reset Control Shift Register Unit), and Scan GOA (Gate Scan Drive Shift Register Unit).

[0111] It should be noted that the types of transistors included in the shift register unit 10 are diverse and are not limited to P-type transistors. For example, N-type transistors can also be used, but this is not the only option.

[0112] As shown in Figures 1 to 3, taking EM GOA as an example, the operation of the shift register unit 10 is as follows:

[0113] During phase P1, the input signal STV is at a low level, the second clock signal CK is at a high level, the first clock signal CKB is at a low level, the first reset transistor T10 is turned on, and the gate drive signal output OUT outputs the first level signal.

[0114] During the P2 phase, the input signal terminal STV is at a high level, the second clock signal input terminal CK is at a low level, the first clock signal input terminal CKB is at a high level, the input transistor T1 and the sixth control transistor T7 are turned on, and the gate drive signal output terminal OUT maintains the potential of the first level signal.

[0115] During P3 and P4 stages, the signal input at the input signal terminal STV is high, the second clock signal input at the second clock signal input terminal CK is high, the first clock signal input at the first clock signal input terminal CKB is low, the second output transistor T9 is turned on, and the gate drive signal output terminal OUT outputs the second level signal.

[0116] During the phase between P3 and P4, the signal input at the input signal terminal STV is at a high level, the second clock signal input at the second clock signal input terminal CK alternates between high and low levels, the first clock signal input at the first clock signal input terminal CKB alternates between high and low levels, and the gate drive signal output terminal OUT continuously outputs the second level signal.

[0117] During the P5 phase, the signal input at the input signal terminal STV is low, the second clock signal input at the second clock signal input terminal CK is low, the first clock signal input at the first clock signal input terminal CKB is high, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs the first level signal.

[0118] During the P6 phase, the signal input at the input signal terminal STV is low, the second clock signal input at the second clock signal input terminal CK is high, the first clock signal input at the first clock signal input terminal CKB is low, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs the first level signal.

[0119] As shown in Figures 5 to 19, this embodiment of the present disclosure also provides a display substrate, including a first level signal line VGL', a second level signal line VGH', and a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units 10 provided in the above embodiments. The shift register unit 10 includes: a first output node N3, a first coupling node N0, a first output transistor T10, and a second capacitor C2. The gate 310 of the first output transistor T10 is coupled to the first output node N3, the first terminal of the first output transistor T10 is coupled to the first level signal line VGL', and the second terminal of the first output transistor T10 is coupled to the gate driving signal output terminal OUT. The first plate C21 of the second capacitor C2 is coupled to the first output node N3, and the second plate C22 of the second capacitor C2 is coupled to the first coupling node N0.

[0120] The orthographic projection of the second level signal line VGH' on the substrate of the display substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the substrate.

[0121] For example, the first level signal line VGL' is used to transmit a first level signal, and the second level signal line VGH' is used to transmit a second level signal; for example, the first level signal includes a low level signal, and the second level signal includes a high level signal, but is not limited to this.

[0122] For example, the first level signal line VGL' extends along a first direction, and the second level signal line VGH' extends along the first direction. The orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate is located on the second side of the orthographic projection of the second level signal line VGH' onto the substrate along a second direction, and the orthographic projection of the first output transistor T10 onto the substrate is located on the first side of the orthographic projection of the second level signal line VGH' onto the substrate along a second direction, wherein the second direction intersects the first direction.

[0123] For example, the gate 310 of the first output transistor T10 and the first plate C21 of the second capacitor C2 are formed as an integral structure, and the orthographic projection of the integral structure on the substrate overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0124] As shown in Figures 5 to 11 and Figures 13 to 18, exemplarily, the orthographic projection of the second level signal line VGH' on the substrate is located between the orthographic projection of the first level signal line VGL' on the substrate and the orthographic projection of the output transistor on the substrate. The shift register unit further includes an eleventh conductive connection portion 42, which is coupled to the first terminal of the first output transistor T10 and the first level signal line VGL', respectively. The orthographic projection of the eleventh conductive connection portion 42 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0125] As shown in Figures 5 to 11, exemplarily, the shift register unit further includes a first conductive connection portion 51, which is coupled to the first terminal of the input transistor T1 and a tenth conductive connection portion 41, respectively. The tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous stage shift register unit. The orthographic projection of the first conductive connection portion 51 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0126] As shown in Figures 13 to 18, exemplarily, the shift register unit further includes a twelfth conductive connection portion 61. This twelfth conductive connection portion 61 is coupled to the first terminal of the input transistor T1 and a tenth conductive connection portion 41, which is coupled to the gate drive signal output terminal of the previous-stage shift register unit. The orthographic projection of the twelfth conductive connection portion 61 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0127] As shown in Figures 5 to 11, for example, the distance between the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 onto the substrate and the orthographic projection of the tenth conductive connection 41 onto the substrate is greater than the distance between the orthographic projection of the active layer 29 of the second output transistor T9 onto the substrate and the orthographic projection of the tenth conductive connection 41 onto the substrate. This arrangement allows the plate of the third capacitor C3 to be moved away from the tenth conductive connection 41, thereby effectively reducing the coupling effect of the signal transmitted by the tenth conductive connection 41 on the third capacitor C3.

[0128] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, by setting the orthographic projection of the second level signal line VGH' on the substrate of the display substrate to be located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the substrate, the second capacitor C2 is positioned near the second level signal line VGH', effectively reducing the coupling effect of other AC signals on the second capacitor C2. Furthermore, the above arrangement allows the second level signal line VGH' to separate the second capacitor C2 and the first output transistor T10, reducing the coupling effect of other AC signals on the gate 310 potential of the first output transistor T10 through the second capacitor C2, reducing the coupling capacitance of the gate 310 of the first output transistor T10, thereby effectively reducing the step formed during the process of the potential of the first output node N3 being pulled down, enabling the gate drive signal output terminal OUT to output stably, and effectively reducing the disturbance effect of the output waveform.

[0129] Therefore, the display substrate provided in this embodiment effectively improves the voltage stability of the internal nodes (such as the first output node N3) of the shift register unit 10, and at the same time improves the stability of the output signal of the shift register unit 10.

[0130] More specifically, as shown in Figure 4, in the existing layout of the shift register unit 10, the waveform has a large step (such as L1) during the process of the first output node N3 being pulled low; in the layout of the shift register unit 10 of the display substrate provided in this embodiment, the step height of the waveform is greatly reduced (such as L2) during the process of the first output node N3 being pulled low.

[0131] As shown in Figures 5 to 19, in some embodiments, the shift register unit 10 further includes a second output node N5, a second output transistor T9, and a third capacitor C3. The gate 39 of the second output transistor T9 is coupled to the second output node N5, the first terminal of the second output transistor T9 is coupled to the second level signal line VGH', and the second terminal of the second output transistor T9 is coupled to the gate drive signal output terminal OUT. The first plate C31 of the third capacitor C3 is coupled to the gate 39 of the second output transistor T9, and the second plate C32 of the third capacitor C3 is coupled to the second level signal line VGH'.

[0132] The orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' onto the substrate.

[0133] For example, the first plate C31 of the third capacitor C3 and the gate 39 of the second output transistor T9 are formed as an integral structure. The orthographic projection of the first plate C31 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0134] For example, the display substrate further includes multiple rows of sub-pixel rows; when the shift register unit 10 is used to drive two rows of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along a first direction; when the shift register unit 10 is used to drive one row of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along a second direction.

[0135] For example, the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate is located inside the orthographic projection of the first plate C31 of the third capacitor C3 onto the substrate.

[0136] The above-mentioned configuration of the second plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthogonal projection of the second level signal line VGH' on the substrate, which better saves the overall layout space occupied by the shift register unit 10 and is conducive to the display substrate to achieve a narrow bezel.

[0137] As shown in Figures 5 to 19, in some embodiments, the second level signal line VGH' extends along a first direction; the active layer 210 of the first output transistor T10 and the active layer 29 of the second output transistor T9 are arranged along the first direction; the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate and the orthographic projection of the active layer 29 of the second output transistor T9 on the substrate are arranged along a second direction, and the second direction intersects the first direction.

[0138] For example, the orthographic projection of the second output transistor T9 onto the substrate is located on the first side of the orthographic projection of the second level signal line VGH' onto the substrate along the second direction. This arrangement allows the second level signal line VGH' to separate the first output transistor T10 and the second output transistor T9 from other functional structures (such as other transistors, capacitors, etc.), reducing interference from other functional structures to the first output transistor T10 and the second output transistor T9, and better ensuring the output stability of the first output transistor T10 and the second output transistor T9.

[0139] The above arrangement makes the third capacitor C3 adjacent to the second output transistor T9, which effectively reduces the difficulty of connecting the third capacitor C3 and the second output transistor T9 and ensures the reliability of the connection between the third capacitor C3 and the second output transistor T9.

[0140] As shown in Figures 5 to 19, in some embodiments, the second level signal line VGH' extends along the first direction; the shift register unit 10 further includes an eighth control transistor T11; the gate 311 of the eighth control transistor T11 is coupled to the first output node N3, the first terminal of the eighth control transistor T11 is coupled to the first clock signal input terminal CKB, and the second terminal of the eighth control transistor T11 is coupled to the first coupling node N0; the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate are arranged along the first direction.

[0141] For example, the eighth control transistor T11 includes a dual-gate transistor structure, but is not limited to this.

[0142] For example, the active layer 211 of the eighth control transistor T11 extends along the first direction, which helps to reduce the layout space occupied by the eighth control transistor T11 as a whole along the second direction.

[0143] For example, along the first direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is adjacent to the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate; along the second direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is adjacent to the orthographic projection of the second level signal line VGH' on the substrate.

[0144] For example, the gate 311 of the eighth control transistor T11, the gate 310 of the first output transistor T10, and the first plate C21 of the second capacitor C2 are formed into an integral structure.

[0145] The above arrangement allows the eighth control transistor T11, the second capacitor C2 and the first output transistor T10 to be arranged in a concentrated manner, which not only reduces the difficulty of connecting the three and ensures the reliability of the connection, but also helps to reduce the overall layout space occupied by the shift register unit 10, and helps to achieve a narrow bezel on the display substrate.

[0146] As shown in Figures 5 to 19, in some embodiments, the shift register unit 10 further includes a first input node N1, a second input node N2, a second control transistor T3, and a seventh control transistor T8;

[0147] The gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal line VGH', and the second terminal of the second control transistor T3 is coupled to the second input node N2; the gate 38 of the seventh control transistor T8 is coupled to the first output node N3 in the shift register unit 10, the first terminal of the seventh control transistor T8 is coupled to the second level signal line VGH', and the second terminal of the seventh control transistor T8 is coupled to the second output node N5 in the shift register unit 10;

[0148] The gate 38 of the seventh control transistor T8 and the gate 33 of the second control transistor T3 are formed as an integral structure.

[0149] For example, the active layer 28 of the seventh control transistor T8 extends along the second direction.

[0150] For example, the display substrate further includes multiple rows of sub-pixel rows; when the shift register unit 10 is used to drive two rows of sub-pixel rows, the active layer 23 of the second control transistor T3 extends along a second direction, and the active layer 28 of the seventh control transistor T8 and the active layer 23 of the second control transistor T3 are arranged along a first direction; when the shift register unit 10 is used to drive one row of sub-pixel rows, the active layer 23 of the second control transistor T3 extends along a first direction, and the active layer 23 of the second control transistor T3 and the active layer 28 of the seventh control transistor T8 are arranged along a second direction.

[0151] The above arrangement allows for a compact layout of the seventh control transistor T8 and the second control transistor T3, ensuring the connection performance between them while reducing the difficulty of connecting them and narrowing the bezel width of the display substrate.

[0152] As shown in Figures 2, 5 to 11, in some embodiments, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit 10 is used to drive two rows of sub-pixel rows; the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 28 of the seventh control transistor T8 on the substrate are arranged along a first direction;

[0153] At least a portion of the orthographic projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 onto the substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate and the orthographic projection of the active layer 28 of the seventh control transistor T8 onto the substrate.

[0154] For example, the display area of ​​the display substrate includes multiple rows of subpixel rows, each row of subpixel rows including multiple subpixels arranged along a second direction. When the shift register unit 10 is used to drive two rows of subpixel rows, the shift register unit 10 can provide driving signals to the two rows of subpixel rows.

[0155] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, which is beneficial for the display substrate to achieve a narrow bezel.

[0156] As shown in Figures 2, 5 to 11, in some embodiments, the shift register unit 10 further includes a reset transistor T13. The gate 313 of the reset transistor T13 is coupled to the reset signal input terminal VEL. The first terminal of the reset transistor T13 is coupled to the second level signal line VGH'. The second terminal of the reset transistor T13 is coupled to the first input node N1. The orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 213 of the reset transistor T13 on the substrate are arranged along a first direction. At least a portion of the orthographic projection of the active layer 213 of the reset transistor T13 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate are arranged along a second direction.

[0157] For example, the active layer 213 of the reset transistor T13 extends along a first direction, and at least a portion of the orthographic projection of the active layer 213 of the reset transistor T13 onto the substrate is located between the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate.

[0158] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, which is beneficial for the display substrate to achieve a narrow bezel.

[0159] As shown in Figures 2, 5 to 11, in some embodiments, the shift register unit 10 further includes an input transistor T1. The gate 31 of the input transistor T1 is coupled to the second clock signal input terminal CK. The first terminal of the input transistor T1 is coupled to the input signal terminal STV. The second terminal of the input transistor T1 is coupled to the first input node N1 of the shift register unit 10. At least a portion of the orthographic projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 211 of the input transistor T1 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate; and / or,

[0160] The shift register unit 10 further includes a transfer transistor T12, the gate 312 of which is coupled to a first level signal line VGL', the first terminal of which is coupled to a first input node N1, and the second terminal of which is coupled to a first output node N3; the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 onto the substrate and the orthographic projection of the active layer 212 of the transfer transistor T12 onto the substrate are arranged along the first direction; and / or,

[0161] The shift register unit 10 further includes a fifth control transistor T6 and a sixth control transistor T7; the gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal line VGH', and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; the gate 37 of the sixth control transistor T7 is coupled to the second input node N2, and the second terminal of the sixth control transistor T7 is coupled to the first input node N1; the active layer 26 of the fifth control transistor T6 is coupled to the sixth control transistor T7. The active layer 27 of the body transistor T7 is formed as an integral active layer extending along the second direction; the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the integral active layer on the substrate; the orthographic projection of the active layer 212 of the transmission transistor T12 on the substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the integral active layer on the substrate; and / or,

[0162] The shift register unit 10 further includes a second coupling node N4, a first control transistor T2, a second control transistor T3, a third control transistor T4, and a fourth control transistor T5; the gate 32 of the first control transistor T2 is coupled to the second coupling node N4, the first terminal of the first control transistor T2 is coupled to the first level signal line VGL', and the second terminal of the first control transistor T2 is coupled to the second input node N2; the gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal line VGH', and the second terminal of the second control transistor T3 is coupled to the second input node N2; the gate 34 of the third control transistor T4 is coupled to the first input node N1, the first terminal of the third control transistor T4 is coupled to the second level signal line VGH', and the second terminal of the third control transistor T5 is coupled to the second input node N2; Coupled to node N4; the gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, the first terminal of the fourth control transistor T5 is coupled to the second input node N2, and the second terminal of the fourth control transistor T5 is coupled to the second output node N5; the orthographic projections of the second plate C22 of the second capacitor C2, the active layer 25 of the fourth control transistor T5, the active layer 23 of the second control transistor T3, and the active layer 24 of the third control transistor T4 on the substrate are arranged sequentially along the first direction; the orthographic projection of the active layer 23 of the second control transistor T3 on the substrate is located between the orthographic projection of the active layer 22 of the first control transistor T2 on the substrate and the orthographic projection of the second level signal line VGH' on the substrate; and / or,

[0163] The shift register unit 10 further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and the second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along the second direction.

[0164] For example, the active layer 21 of the input transistor T1 extends along the first direction, the active layer 212 of the transmission transistor T12 extends along the first direction, and the active layer 212 of the transmission transistor T12 is at least partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0165] For example, the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate, the orthographic projection of the active layer 211 of the eighth control transistor T11 onto the substrate, the active layer of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 forming an integral structure, the orthographic projection of the active layer 25 of the fourth control transistor T5 onto the substrate, the orthographic projection of the active layer 23 of the second control transistor T3 onto the substrate, and the orthographic projection of the active layer 24 of the third control transistor T4 onto the substrate are arranged sequentially along the first direction.

[0166] For example, the active layer 23 of the second control transistor T3 and the active layer 22 of the first control transistor T2 are formed as an integral structure extending along the second direction.

[0167] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, which is beneficial for the display substrate to achieve a narrow bezel.

[0168] As shown in Figures 5 to 11, the shift register unit further includes a first conductive connection portion 51, which is coupled to the first pole of the input transistor T1 and the tenth conductive connection portion 41, respectively. The tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous shift register unit.

[0169] The shift register unit further includes a second conductive connection portion 52, which is coupled to the first plate C21 of the second capacitor C2 and the second electrode of the transmission transistor T12.

[0170] The shift register unit further includes a third conductive connection part 53, which is coupled to the second plate C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11.

[0171] The shift register unit further includes a fourth conductive connection portion 54, which is coupled to the second terminal of the input transistor T1, the first terminal of the transmission transistor T12, the second terminal of the sixth control transistor T7, and the gate of the seventh control transistor T8, respectively.

[0172] The shift register unit further includes a fifth conductive connection portion 55, which is coupled to the first terminal of the eighth control transistor T11 and the gate of the fifth control transistor T6, respectively.

[0173] The shift register unit further includes a sixth conductive connection portion 56, which is coupled to the gate of the sixth control transistor T7, the first terminal of the fourth control transistor T5, the second terminal of the first control transistor T2, and the second terminal of the second control transistor T3, respectively.

[0174] The shift register unit further includes a seventh conductive connection portion 57, which is coupled to the second terminal of the fourth control transistor T5, the gate of the second output transistor T9, and the second terminal of the fourth control transistor T8, respectively.

[0175] The shift register unit further includes an eighth conductive connection portion 58, which is coupled to the second plate C21 of the first capacitor C1, the gate 32 of the first control transistor T2, and the second electrode of the third control transistor T4, respectively.

[0176] The shift register unit further includes a ninth conductive connection portion 59, which is coupled to the second terminal of the reset transistor T13 and the gate 34 of the third control transistor T4, respectively.

[0177] The shift register unit further includes an eleventh conductive connection part 42, which is coupled to the first pole of the first output transistor T10 and the first level signal line VGL'.

[0178] As shown in Figures 2, 12 to 18, in some embodiments, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit 10 is used to drive one row of sub-pixel rows; at least a portion of the orthographic projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 28 of the seventh control transistor T8 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate.

[0179] For example, the display area of ​​the display substrate includes multiple rows of subpixel rows, each row of subpixel rows including multiple subpixels arranged along a second direction. When the shift register unit 10 is used to drive a row of subpixel rows, the shift register unit 10 can provide a driving signal to that row of subpixel rows.

[0180] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the first direction, and reduces the layout difficulty of the multi-level shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixel rows.

[0181] As shown in Figures 2 and 12 to 18, in some embodiments, the shift register unit 10 further includes a reset transistor T13. The gate 313 of the reset transistor T13 is coupled to the reset signal input terminal VEL. The first terminal of the reset transistor T13 is coupled to the second level signal line VGH'. The second terminal of the reset transistor T13 is coupled to the first input node N1. The orthographic projection of the second plate C22 of the second capacitor C2 on the substrate is offset from the orthographic projection of the active layer 213 of the reset transistor T13 on the substrate along a first direction. At least a portion of the orthographic projection of the active layer 213 of the reset transistor T13 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate are aligned along a second direction.

[0182] For example, the active layer 28 of the seventh control transistor T8 and the active layer 213 of the reset transistor T13 are arranged along the first direction.

[0183] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the first direction, and reduces the layout difficulty of the multi-level shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixel rows.

[0184] As shown in Figures 2 and 12 to 18, in some embodiments, the shift register unit 10 further includes an input transistor T1. The gate 31 of the input transistor T1 is coupled to the second clock signal input terminal CK. The first terminal of the input transistor T1 is coupled to the input signal terminal STV. The second terminal of the input transistor T1 is coupled to the first input node N1 of the shift register unit 10. At least a portion of the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 21 of the input transistor T1 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate; and / or,

[0185] The shift register unit 10 further includes a transfer transistor T12, the gate 312 of which is coupled to a first level signal line VGL', the first electrode of which is coupled to a first input node N1, and the second electrode of which is coupled to a first output node N3; at least a portion of the orthographic projection of the active layer 212 of the transfer transistor T12 onto the substrate is located between the orthographic projection of the active layer 21 of the input transistor T1 onto the substrate and the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate; and / or,

[0186] The shift register unit 10 further includes a fourth control transistor T5, a fifth control transistor T6, and a sixth control transistor T7; the gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, the first terminal of the fourth control transistor T5 is coupled to the second input node N2, and the second terminal of the fourth control transistor T5 is coupled to the second output node N5; the gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal line VGH', and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; the gate 37 of the sixth control transistor T7 is coupled to... The second input node N2 is coupled, and the second electrode of the sixth control transistor T7 is coupled to the first input node N1; the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 are formed as an integral active layer extending along a first direction; at least a portion of the orthographic projection of the active layer 25 of the fourth control transistor T5 onto the substrate is located between the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate and the orthographic projection of the integral active layer onto the substrate; at least a portion of the active layer 28 of the seventh control transistor T8 is located between the integral active layer and the active layer 25 of the fourth control transistor T5; and / or,

[0187] The shift register unit 10 further includes a second coupling node N4, a first control transistor T2, a second control transistor T3, and a third control transistor T4; the gate 32 of the first control transistor T2 is coupled to the second coupling node N4, the first terminal of the first control transistor T2 is coupled to the first level signal line VGL', and the second terminal of the first control transistor T2 is coupled to the second input node N2; the gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal line VGH', and the second terminal of the second control transistor T3 is coupled to the second input node N2; the gate 34 of the third control transistor T4 is coupled to the first input node N1, and the first terminal of the third control transistor T4 is coupled to the second input node N2. The two-level signal line VGH' is coupled, and the second terminal of the third control transistor T4 is coupled to the second coupling node N4; the active layer 28 of the seventh control transistor T8 is located between the active layer 22 of the first control transistor T2 and the active layer 211 of the eighth control transistor T11; the active layers 22 of the first control transistor T2 and the active layers 24 of the third control transistor T4 are arranged along the first direction, and at least a portion of the active layer 23 of the second control transistor T3 is located between the active layers 22 of the first control transistor T2 and the active layers 24 of the third control transistor T4; the active layers 22 of the first control transistor T2, the active layers 23 of the second control transistor T3, and the active layers 24 of the third control transistor T4 are sequentially coupled to form a single structure; and / or,

[0188] The shift register unit 10 further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and the second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along a second direction.

[0189] For example, the active layer 21 of the input transistor T1 extends along the second direction, and the active layer 212 of the transmission transistor T12 extends along the second direction. The active layer 212 of the transmission transistor T12 is partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0190] For example, the second plate C22 of the second capacitor C2 includes a plate body and a plate protrusion. The plate body extends along the first direction, and the plate protrusion protrudes from the plate body along the second direction. The orthographic projection of the plate body on the substrate is located between the orthographic projection of the plate protrusion on the substrate and the orthographic projection of the second level signal line VGH' on the substrate.

[0191] For example, the orthographic projection of the active layer 212 of the transmission transistor T12 onto the substrate is offset from the orthographic projection of the electrode protrusion onto the substrate along the second direction.

[0192] For example, the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 form an integral structure, the active layer 28 of the seventh control transistor T8 and the active layer 25 of the fourth control transistor T5 are sequentially coupled to form an integral structure.

[0193] For example, the active layer 22 of the first control transistor T2 extends along the second direction, the active layer 24 of the third control transistor T4 extends along the second direction, and the active layer 23 of the second control transistor T3 extends along the first direction.

[0194] For example, at least a portion of the orthographic projection of the active layer 213 of the reset transistor T13 onto the substrate is located between the orthographic projection of the active layer 24 of the third control transistor T4 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate.

[0195] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the first direction, and reduces the layout difficulty of the multi-level shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixel rows.

[0196] As shown in Figures 12 to 18, the shift register unit further includes a twelfth conductive connection part 61, which is coupled to the first pole of the input transistor T1 and the tenth conductive connection part 41, respectively. The tenth conductive connection part 41 is coupled to the gate drive signal output terminal of the previous shift register unit.

[0197] The shift register unit also includes a thirteenth conductive connection part 62, which is coupled to the second electrode of the transmission transistor T12 and the first plate C21 of the second capacitor C2.

[0198] The shift register unit further includes a fourteenth conductive connection portion 63, which is coupled to the gate of the sixth control transistor T7 and the first electrode of the fourth control transistor T5, respectively.

[0199] The shift register unit also includes a fifteenth conductive connection part 64, which is coupled to the second plate C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11.

[0200] The shift register unit further includes a sixteenth conductive connection portion 65, which is coupled to the second terminal of the input transistor T1, the first terminal of the transmission transistor T12, the gate of the second control transistor T3, and the gate of the third control transistor T4, respectively.

[0201] The shift register unit further includes a seventeenth conductive connection portion 66, which is coupled to the second electrode of the second control transistor T3 and the gate of the sixth control transistor T7, respectively.

[0202] The shift register unit further includes an eighteenth conductive connection portion 67, which is coupled to the gate of the seventh control transistor T8 and the second electrode of the reset transistor T13, respectively.

[0203] The shift register unit further includes a nineteenth conductive connection part 68, which is coupled to the second plate C12 of the first capacitor C1, the second electrode of the third control transistor T4, and the gate of the first control transistor T2, respectively.

[0204] The shift register unit further includes a twentieth conductive connection portion 69, which is coupled to the second level signal line VGH', the first terminal of the reset transistor T13, the first terminal of the third control transistor T4, the first terminal of the seventh control transistor T8, and the first terminal of the second control transistor T3, respectively.

[0205] The shift register unit further includes a twenty-first conductive connection portion 610, which is coupled to the first terminal of the eighth control transistor T11 and the gate of the fourth control transistor T5, respectively.

[0206] The shift register unit also includes a 22nd conductive connection part 611, which is coupled to the first plate C31 of the third capacitor C3 and the second plate of the seventh control transistor T8.

[0207] As shown in Figures 10 and 17, in some embodiments, the first level signal line VGL' and the second level signal line VGH' in the display substrate are arranged along a second direction; the orthographic projection of the other transistor structures in the shift register unit 10, excluding the first output transistor T10 and the second output transistor T9, is located between the orthographic projection of the first level signal line VGL' on the substrate and the orthographic projection of the second level signal line VGH' on the substrate.

[0208] The above method enables the other transistor structures included in the shift register unit 10 to be centrally located between the first level signal line VGL' and the second level signal line VGH', so that the distribution density of CNT vias around each other transistor structure is uniform, avoiding the increase in regional characteristic differences caused by the effect of hydrogen removal on the layout area due to the uneven distribution of vias.

[0209] For example, the display substrate further includes a frame start signal line (e.g., ESTV, RSTV), a first clock signal line (e.g., ECB, RCB), and a second clock signal line (e.g., ECK, RCK); the frame start signal line, the first clock signal line, the second clock signal line, the reset signal line Rst, the first level signal line VGL', and the second level signal line VGH' are arranged sequentially along a second direction. It is worth noting that the reset signal line Rst can transmit the same signal as the second clock signal line.

[0210] For example, in a cascaded plurality of shift register units 10, the first terminal of the first input transistor T1 in the first-stage shift register unit 10 is coupled to the frame start signal line, and the first terminal of the first input transistor T1 in the (n+1)th-stage shift register unit 10 is coupled to the gate drive signal output terminal OUT of the nth-stage shift register unit 10; n is an integer greater than or equal to 1.

[0211] For example, in one of the odd-level shift register units 10 and the even-level shift register unit 10, the first clock signal input terminal CKB is coupled to the first clock signal line, and the second clock signal input terminal CK is coupled to the second clock signal line; in the other of the odd-level shift register units 10 and the even-level shift register unit 10, the first clock signal input terminal CKB is coupled to the second clock signal line, and the second clock signal input terminal CK is coupled to the first clock signal line.

[0212] For example, as shown in Figure 19, the display substrate includes two types of shift register units 10. The first type of shift register unit 10 is used to drive two rows of pixel units simultaneously, specifically as EM GOA. The second type of shift register unit 10 is used to drive one row of pixel units simultaneously, specifically as Reset GOA. In actual layout, the Reset GOA can be placed between the EM GOA and the display area. It should be noted that the display area in Figure 19 is located on the far right.

[0213] For example, as shown in Figures 5 to 11 and Figures 13 to 19, the width of the first type of shift register unit along the first direction is greater than the width of the second type of shift register unit along the first direction, and the width of the first type of shift register unit along the second direction is less than the width of the second type of shift register unit along the second direction.

[0214] The width of the second plate C32 of the third capacitor C3 in the first type of shift register unit along the first direction is greater than the width of the second plate C32 of the third capacitor C3 in the second type of shift register unit along the first direction; the width of the second plate C32 of the third capacitor C3 in the first type of shift register unit along the second direction is less than the width of the second plate C32 of the third capacitor C3 in the second type of shift register unit along the second direction.

[0215] The width of the second plate C22 of the second capacitor C2 in the first type of shift register unit along the first direction is greater than the width of the second plate C22 of the second capacitor C2 in the second type of shift register unit along the first direction; the width of the second plate C22 of the second capacitor C2 in the first type of shift register unit along the second direction is less than the width of the second plate C22 of the second capacitor C2 in the second type of shift register unit along the second direction.

[0216] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0217] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0218] In the display substrate provided in the above embodiments, by setting the orthographic projection of the second level signal line VGH' on the substrate of the display substrate to be located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the substrate, the second capacitor C2 is positioned near the second level signal line VGH', effectively reducing the coupling effect of other AC signals on the second capacitor C2. Furthermore, this arrangement allows the second level signal line VGH' to separate the second capacitor C2 and the first output transistor T10, reducing the coupling effect of other AC signals on the gate 310 potential of the first output transistor T10 through the second capacitor C2, reducing the coupling capacitance of the gate 310 of the first output transistor T10, thereby effectively reducing the step formed during the pull-down of the potential of the first output node N3, enabling the gate drive signal output terminal OUT to output stably, and effectively reducing the disturbance effect of the output waveform. Therefore, in the display substrate provided in the above embodiments, the voltage stability of the internal nodes of the shift register unit 10 is effectively improved, and the stability of the output signal of the shift register unit 10 is also improved.

[0219] The display device provided in this disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0220] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0221] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0222] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0223] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0224] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0225] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0226] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0227] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register unit, comprising: The circuit comprises a first input node, a first output node, a first coupling node, a first output circuit, a pull-down coupling control circuit, and a reset circuit. The first output circuit is coupled to the first output node, the first level signal input terminal, and the gate drive signal output terminal of the shift register unit, respectively; it is used to control the electrical connection between the first level signal input terminal and the gate drive signal output terminal to be turned on or off under the control of the potential of the first output node. The pull-down coupling control circuit is coupled to the first output node, the first coupling node, and the first clock signal input terminal respectively; it is used to control the electrical connection between the first coupling node and the first clock signal input terminal to be turned on or off under the control of the potential of the first output node. It is also used to control the potential of the first output node based on the potential of the first coupling node; The reset circuit is coupled to the reset signal input terminal, the second level signal input terminal, and the first input node, respectively; it is used to control the electrical connection between the second level signal input terminal and the first input node to be turned on or off under the control of the reset signal input at the reset signal input terminal.

2. The shift register unit according to claim 1, wherein, The shift register unit further includes: a second coupling node, a second input node, a coupling node control circuit, and a first control circuit; The coupling node control circuit is coupled to the second coupling node, the first clock signal input terminal, the first input node, and the second level signal input terminal, respectively; it is used to control the potential of the second coupling node according to the clock signal input from the first clock signal input terminal; and it is also used to control the electrical connection between the second level signal input terminal and the second coupling node to be turned on or off under the control of the potential of the first input node. The first control circuit is coupled to the first input node, the second input node, the second coupling node, the first level signal input terminal, and the second level signal input terminal, respectively; it is used to control the electrical connection between the second level signal input terminal and the second input node to be turned on or off under the control of the potential of the first input node; it is also used to control the electrical connection between the first level signal input terminal and the second input node to be turned on or off under the control of the potential of the second coupling node.

3. The shift register unit according to claim 2, wherein, The shift register unit further includes a second output node and a second output circuit; the second output circuit is coupled to the second output node, the gate drive signal output terminal and the second level signal input terminal, respectively. Used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output node; the second input node is directly coupled to the second output node.

4. The shift register unit according to claim 2, wherein, The shift register unit further includes a second output node and a second output circuit; the second output circuit is coupled to the second output node, the gate drive signal output terminal and the second level signal input terminal, respectively. Used to control the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the second output node; The shift register unit further includes a second control circuit, which is coupled to the first clock signal input terminal, the second input node and the second output node respectively, and is used to control the electrical connection between the second input node and the second output node to be turned on or off under the control of the first clock signal input to the first clock signal input terminal.

5. The shift register unit according to claim 3 or 4, wherein, The shift register unit further includes a first input circuit, a third control circuit, a fourth control circuit, and a transmission circuit; The first input circuit is coupled to the second clock signal input terminal, the input signal terminal, and the first input node, respectively; it is used to control the electrical connection between the input signal terminal and the first input node to be turned on or off under the control of the second clock signal input at the second clock signal input terminal. The third control circuit is coupled to the first input node, the second input node, the second level signal input terminal and the first clock signal input terminal respectively; Under the control of the potential of the second input node and the first clock signal input at the first clock signal input terminal, the electrical connection between the second level signal input terminal and the first input node is controlled to be turned on or off. The fourth control circuit is coupled to the first input node, the second level signal input terminal and the second output node respectively, and is used to control the electrical connection between the second level signal input terminal and the second output node to be turned on or off under the control of the potential of the first input node. The transmission circuit is coupled to the first level signal input terminal, the first input node, and the first output node respectively, and is used to control the electrical connection between the first input node and the first output node to be turned on or off under the control of the first level signal input to the first level signal input terminal.

6. The shift register unit according to claim 1, wherein, The first output circuit includes a first output transistor, the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first level signal input terminal, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal. The pull-down coupling control circuit includes an eighth control transistor and a second capacitor; The gate of the eighth control transistor is coupled to the first output node, the first terminal of the eighth control transistor is coupled to the first clock signal input terminal, and the second terminal of the eighth control transistor is coupled to the first coupling node; the first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node. The reset circuit includes a reset transistor, the gate of which is coupled to a reset signal input terminal, the first terminal of which is coupled to a second level signal input terminal, and the second terminal of which is coupled to the first input node.

7. The shift register unit according to claim 2, wherein, The coupling node control circuit includes a first capacitor and a third control transistor; the first plate of the first capacitor is coupled to the first clock signal input terminal, and the second plate of the first capacitor is coupled to the second coupling node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal input terminal, and the second electrode of the third control transistor is coupled to the second coupling node. The first control circuit includes a first control transistor and a second control transistor. The gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to the first level signal input terminal, and the second terminal of the first control transistor is coupled to the second input node. The gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to the second level signal input terminal, and the second terminal of the second control transistor is coupled to the second input node.

8. The shift register unit according to claim 4, wherein, The second output circuit includes a second output transistor, the gate of which is coupled to the second output node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal. The second control circuit includes a fourth control transistor, the gate of which is coupled to the first clock signal input terminal, the first terminal of which is coupled to the second input node, and the second terminal of which is coupled to the second output node.

9. The shift register unit according to claim 5, wherein, The first input circuit includes an input transistor, the gate of which is coupled to the second clock signal input terminal, the first terminal of which is coupled to the input signal terminal, and the second terminal of which is coupled to the first input node; The third control circuit includes a fifth control transistor and a sixth control transistor; The gate of the fifth control transistor is coupled to the first clock signal input terminal, the first terminal of the fifth control transistor is coupled to the second level signal input terminal, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second terminal of the sixth control transistor is coupled to the first input node. The fourth control circuit includes a seventh control transistor, the gate of which is coupled to the first input node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the second output node. The transmission circuit includes a transmission transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the first input node, and the second terminal of which is coupled to the first output node.

10. A display substrate, comprising a first-level signal line, a second-level signal line, and a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded shift register units as described in any one of claims 1 to 9; the shift register unit comprises: First output node, first coupling node, first output transistor, and second capacitor; The gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first level signal line, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal; the first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node. The orthographic projection of the second level signal line on the substrate of the display substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the first output transistor on the substrate.

11. The display substrate according to claim 10, wherein, The shift register unit further includes a second output node, a second output transistor, and a third capacitor. The gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal. The first plate of the third capacitor is coupled to the gate of the second output transistor, and the second plate of the third capacitor is coupled to the second level signal line. The orthographic projection of the second plate of the third capacitor onto the substrate at least partially overlaps with the orthographic projection of the second level signal line onto the substrate.

12. The display substrate according to claim 11, wherein, The second level signal line extends along the first direction; the active layer of the first output transistor and the active layer of the second output transistor are arranged along the first direction; the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the active layer of the second output transistor on the substrate are arranged along the second direction, and the second direction intersects the first direction.

13. The display substrate according to claim 10, wherein, The second level signal line extends along the first direction; the shift register unit further includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second electrode plate of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

14. The display substrate according to any one of claims 10 to 13, wherein, The shift register unit further includes a first input node, a second input node, a second control transistor, and a seventh control transistor; The gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to the second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the seventh control transistor is coupled to the first output node in the shift register unit, the first terminal of the seventh control transistor is coupled to the second level signal line, and the second terminal of the seventh control transistor is coupled to the second output node in the shift register unit. The gate of the seventh control transistor is formed as an integral structure with the gate of the second control transistor.

15. The display substrate according to claim 14, wherein, The display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive two rows of sub-pixel rows; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the seventh control transistor on the substrate are arranged along a first direction; At least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the second plate of the second capacitor onto the substrate and the orthographic projection of the active layer of the seventh control transistor onto the substrate.

16. The display substrate according to claim 15, wherein, The shift register unit further includes a reset transistor, the gate of which is coupled to a reset signal input terminal, the first terminal of which is coupled to a second level signal line, and the second terminal of which is coupled to a first input node; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the reset transistor on the substrate are arranged along a first direction; at least a portion of the orthographic projection of the active layer of the reset transistor on the substrate and the orthographic projection of the second plate of the third capacitor on the substrate are arranged along a second direction.

17. The display substrate according to claim 15, wherein, The shift register unit further includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to a first clock signal input terminal, the first terminal of the fifth control transistor is coupled to a second level signal line, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to a second input node, and the second terminal of the sixth control transistor is coupled to a first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed into an integral active layer, which extends along a second direction; The orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate. And / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to a first level signal line, and the second electrode of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to the second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to a second output node; the orthographic projections of the second electrode plate of the second capacitor, the active layer of the fourth control transistor, the active layer of the second control transistor, and the active layer of the third control transistor on the substrate are arranged sequentially along the first direction; The orthographic projection of the active layer of the second control transistor on the substrate is located between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the second level signal line on the substrate.

18. The display substrate according to claim 14, wherein, The display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive one row of sub-pixel rows; at least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the active layer of the seventh control transistor onto the substrate and the orthographic projection of the second level signal line onto the substrate.

19. The display substrate according to claim 18, wherein, The shift register unit further includes a reset transistor, the gate of which is coupled to a reset signal input terminal, the first terminal of which is coupled to the second level signal line, and the second terminal of which is coupled to the first input node; the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the reset transistor on the substrate are offset along a first direction. At least a portion of the orthographic projection of the active layer of the reset transistor onto the substrate is aligned with the orthographic projection of the second plate of the third capacitor onto the substrate along a second direction.

20. The display substrate according to claim 18, wherein, The shift register unit further includes a fourth control transistor, a fifth control transistor, and a sixth control transistor; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first electrode of the fourth control transistor is coupled to a second input node, and the second electrode of the fourth control transistor is coupled to a second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to a second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer extending along a first direction; at least a portion of the orthographic projection of the active layer of the fourth control transistor onto the substrate is located between the orthographic projection of the second electrode of the second capacitor onto the substrate and the orthographic projection of the integral active layer onto the substrate; at least a portion of the active layer of the seventh control transistor is located between the integral active layer and the active layer of the fourth control transistor; And / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to a first level signal line, and the second terminal of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to a second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layers of the first control transistor and the active layers of the eighth control transistor; The active layers of the first control transistor and the third control transistor are arranged along the first direction, and at least a portion of the active layer of the second control transistor is located between the active layers of the first control transistor and the third control transistor. The active layers of the first control transistor, the second control transistor, and the third control transistor are sequentially coupled to form a single structure.

21. The display substrate according to any one of claims 10 to 13, wherein, The first level signal line and the second level signal line in the display substrate are arranged along a second direction; the orthographic projection of the other transistor structures in the shift register unit, excluding the first output transistor and the second output transistor, is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate.

22. A display device comprising a display substrate as claimed in any one of claims 10 to 21.

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