Data computing system, model deployment method and related apparatus
Patent Information
- Application Number
- PCT/CN2025/082585
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2026-09-17
Smart Images
Figure CN2025082585_17092026_PF_FP_ABST
Abstract
Description
Data computing system, model deployment method and related device TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of data storage, and in particular to a data computing system, a model deployment method and related devices. BACKGROUND
[0002] At present, the computing system of a data processing device is designed based on the Von Neumann architecture, and the computing and storage are physically separated. Data is extracted from a storage unit, transmitted to a processing unit (a location for computing), and then transmitted back to the storage unit for storage. The rate of data transmission between the processing unit and the storage unit becomes a limitation of the computing speed, i.e., the so-called "memory wall", "power wall", etc. Especially with the continuous development of artificial intelligence technology, it is obvious that the current computing system cannot meet the requirements of its development. SUMMARY
[0003] In view of the above problems, the present application provides a data computing system, a model deployment method and related devices to achieve the purpose of improving data computing speed and efficiency. The specific scheme is as follows:
[0004] The first aspect of the present application provides a data computing system, comprising: a data processing unit, a data transmission unit and at least two kinds of memristor array units;
[0005] The at least two kinds of memristor array units are connected through the data transmission unit and the data processing unit respectively;
[0006] The data processing unit is configured to map the weight parameters used in each inference process in a neural network model to a corresponding kind of memristor array unit;
[0007] Each of the memristor array units is configured to perform matrix-vector multiplication calculation on the matrix data sent by the data processing unit according to the weight parameters.
[0008] In a possible implementation, the at least two kinds of memristor array units include a magnetic random access memory array unit and a resistive random access memory array unit. The resistive random access memory array unit is configured to perform matrix-vector multiplication calculation on the matrix data of a convolution layer sent by the data processing unit according to the weight parameters of the convolution layer. The magnetic random access memory array unit is configured to perform matrix-vector multiplication calculation on the matrix data of a fully connected layer sent by the data processing unit according to the weight parameters of the fully connected layer.
[0009] In a possible implementation, the resistive memory array unit includes a plurality of resistive memory array sub-units, each of the resistive memory array sub-units corresponding to processing matrix-vector multiplication calculation of one convolution layer.
[0010] The second aspect of the present application provides a model deployment method, applied in the data computing system of the first aspect or any implementation manner of the first aspect, including:
[0011] obtaining weight parameters of each network layer in the neural network model;
[0012] According to the correspondence between each network layer and each memristor array unit, the data processing unit is controlled to map the weight parameters of each network layer to the corresponding memristor array unit.
[0013] In a possible implementation, the model deployment method further includes:
[0014] When training the neural network model, the data processing unit is controlled to read first matrix-vector multiplication calculation result data from the resistive memory array unit, and perform activation processing on the first matrix-vector multiplication calculation result data based on an activation function to obtain activation result data;
[0015] The data processing unit is controlled to input the activation result data into the resistive memory array unit to perform matrix-vector multiplication calculation of a next convolution layer, the next convolution layer being a first convolution layer in two adjacent convolution layers, the first matrix-vector multiplication calculation result data being calculation result data of a target convolution layer read from the resistive memory array unit, the target convolution layer being a second convolution layer in the two adjacent convolution layers, and the second convolution layer performing matrix-vector multiplication calculation earlier than the first convolution layer.
[0016] In a possible implementation, the model deployment method further includes:
[0017] The data processing unit is controlled to read second matrix-vector multiplication calculation result data from the magnetic random memory array unit.
[0018] The weight parameters of the full connection layer are updated according to the second matrix-vector multiplication calculation result data, and the data processing unit is controlled to map the updated weight parameters to the magnetic random memory array unit.
[0019] In a possible implementation, when the data processing unit is controlled to map the weight parameters of the convolution layer to the resistive memory array unit, the method includes:
[0020] controlling the data processing unit to gradually increase a resistance state level of a corresponding resistive random access memory in the resistive random access memory array unit until a resistance value of the corresponding resistive random access memory is consistent with a target resistance value.
[0021] The third aspect of the present application provides a model deployment device, comprising:
[0022] a weight parameter obtaining module, configured to obtain weight parameters of each layer network in the neural network model; and
[0023] a weight parameter mapping module, configured to control a data processing unit to map the weight parameters of each layer network to corresponding memristor array units according to a correspondence between each layer network and each memristor array unit.
[0024] The fourth aspect of the present application provides a computer program product, comprising computer readable instructions, which, when executed on an electronic device, cause the electronic device to implement the model deployment method of the second aspect or any implementation manner of the second aspect.
[0025] The fifth aspect of the present application provides an electronic device, comprising at least one processor and a memory connected to the processor, wherein:
[0026] the memory is configured to store a computer program;
[0027] the processor is configured to execute the computer program, so that the electronic device can implement the model deployment method of the second aspect or any implementation manner of the second aspect.
[0028] The sixth aspect of the present application provides a computer storage medium, which carries one or more computer programs, which, when executed by an electronic device, can cause the electronic device to implement the model deployment method of the second aspect or any implementation manner of the second aspect.
[0029] Through the above technical solution, the data calculation system provided by the present application comprises a data processing unit, a data transmission unit and at least two kinds of memristor array units. Each kind of memristor array unit is connected through the data transmission unit and the data processing unit. The data processing unit is configured to map weight parameters used in each inference process in the neural network model to a corresponding kind of memristor array unit. Each kind of memristor array unit is configured to perform matrix-vector multiplication calculation on matrix data sent by the data processing unit according to the weight parameters. By utilizing the in-memory computing characteristics of the memristor, the weight used in the neural network model is effectively distributed to the corresponding memristor array, so that the matrix calculation is directly performed in the memristor array, thereby eliminating the process of frequent data transmission between the calculation region and the storage region, reducing the distance between the calculation and the storage, and improving the calculation speed and efficiency. BRIEF DESCRIPTION OF DRAWINGS
[0030] The above and other features, aspects and advantages of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. Throughout the drawings, the same or like reference numerals are used to represent the same or like elements. It is to be understood that the drawings are schematically showing the components and elements, which are not necessarily drawn to scale.
[0031] FIG. 1 is an architecture diagram of a data computing system provided by the present application;
[0032] FIG. 2 is a structural diagram of a neural network model provided by the present application;
[0033] FIG. 3 is a structural diagram of a speech recognition system provided by the present application;
[0034] FIG. 4 is a characteristic comparison diagram of two memristor array units provided by the present application;
[0035] FIG. 5 is a data flow diagram of speech recognition provided by the present application;
[0036] FIG. 6 is a simulation result diagram of accuracy changing with the number of defects provided by the present application;
[0037] FIG. 7 is a flowchart of a model deployment method provided by the present application;
[0038] FIG. 8 is a structural diagram of a model deployment device provided by the present application;
[0039] FIG. 9 is a structural diagram of an electronic device provided by the present application. DETAILED DESCRIPTION
[0040] The embodiments of the present application are described below in conjunction with the accompanying drawings. The terms used in the embodiment part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application.
[0041] The embodiments of the present application are described below in conjunction with the accompanying drawings. It is known to those of ordinary skill in the art that, as technology develops and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.
[0042] The terms "first", "second", and the like in the description and in the claims of the present application and above-described drawings are used to distinguish similar objects and are not necessarily used to describe a specific sequential or chronological order. It should be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the present application are capable of functioning in other sequences than described or otherwise illustrated herein. Moreover, the terms "comprise", "have" and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, system, product or apparatus that comprises a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such process, method, system, product or apparatus.
[0043] To solve the problem of increasing latency and power consumption of data transmission between processing units and memories in current computing architecture, which limits the computing speed and efficiency, embodiments of the present application provide a data computing system. The data computing system of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0044] Referring to FIG. 1, FIG. 1 is a structural schematic of a data computing system provided by an embodiment of the present application. As shown in FIG. 1, the data computing system provided by an embodiment of the present application includes a data processing unit 101, a data transmission unit 102, and at least two memristor array units 103.
[0045] The at least two memristor array units 103 are connected through the data transmission unit 102 and the data processing unit 101, respectively.
[0046] The data processing unit 101 is configured to map the weight parameters used in each inference process in a neural network model to a corresponding memristor array unit.
[0047] Each memristor array unit 103 is configured to perform matrix-vector multiplication calculation on the matrix data sent by the data processing unit 101 according to the weight parameters.
[0048] In one specific embodiment, in-memory computing technology is a major component of the memory-compute integrated architecture, which allows direct execution of computing tasks within the memory unit, thereby significantly reducing the loss caused by data transmission, and thus improving computing efficiency and data processing capacity. As a key device for implementing in-memory computing, the memristor has the advantages of low power consumption, high integration, and low read-write delay.
[0049] Memristors can be divided into various types according to their implementation principles, for example, as shown in FIG. 4, in which RRAM (Resistive Random-Access Memory) relies on the change of material resistance to store data, has the advantages of high storage density and low power consumption, and is very suitable for the application of integrated computing and storage of low power consumption and large-scale neural network inference, but its durability is relatively weak. It is more suitable for inference tasks of large-scale networks.
[0050] MRAM (Magnetoresistive Random Access Memory) uses the spin effect of magnetic materials to store information, has very high write durability and stability, and is suitable for application scenarios with frequent write and high reliability requirements, such as cache and edge computing, but its storage density is low and the write power consumption is high, and it is more suitable for the training process with frequent updates.
[0051] Based on the characteristics of the above various memristors, for the matrix vector multiplication calculation involved in each layer of the neural network model, a memristor array (such as the two-dimensional memristor array shown in FIG. 4) composed of corresponding memristors can be used to perform the matrix vector multiplication operation in the corresponding network layer.
[0052] For example, as shown in FIG. 2, the structure diagram of a binary deep separable convolutional neural network (DS-CNN) for speech keyword recognition, the neural network structure is divided into one convolutional layer, one deep separable convolutional layer (composed of one deep convolutional layer and one point convolutional layer), one maximum pooling layer and one fully connected layer, and the output target keyword recognition probability is normalized to obtain the recognition result. Among them, the convolution calculation (i.e. matrix vector multiplication operation) in each convolutional layer in the forward propagation process is performed by the corresponding calculation in the RRAM array unit. In which, the matrix vector multiplication operation can be realized by setting an RRAM array subunit for each convolutional layer, or the RRAM array unit can be divided into regions according to the needs, and each region is used to perform the matrix vector multiplication calculation of a corresponding convolutional layer. Each RRAM array region is allocated with an RRAM of the same dimension as the matrix to be processed. For the convolution calculation of the fully connected layer, since it involves the update of the weight in the training process, the same dimension of the MRAM array unit can be used for the convolution calculation.
[0053] The corresponding data transmission unit can be composed of an analog-to-digital converter, a digital-to-analog converter, an analog switch, an array connection base and the like, and is responsible for the overwriting control of each memristor in each memristor array unit. The weights of the convolution kernel used in the convolution layer and the fully connected layer can be correspondingly mapped to each memristor in the memristor array unit. The mapping here means that the data processing unit realizes the setting of the weights by changing the resistance state of the memristor through the data transmission unit. For each memristor, its corresponding weight is either 1 or 0, which can be controlled by different resistance values, for example, a low resistance state represents a weight of 1 and a high resistance state represents a weight of 0. When writing, the corresponding level is written through the corresponding writing path of the memristor, thereby realizing the setting of the weights.
[0054] According to the matrix structure of the memristor array, the principle of realizing matrix vector multiplication is that a voltage is applied to each memristor in the memristor array. Due to the different resistance states of each memristor, the conductance of each memristor is different, and the total current obtained on each row is different. The output row current is the corresponding weighted sum.
[0055] As can be seen from the above, the data computing system utilizes the in-memory computing feature of the memristor, adopts different memristor arrays as the computing mechanism of the matrix vector multiplication of each layer of the neural network model according to the structural characteristics of the neural network model, effectively allocates the weights of the neural network to the respective suitable in-memory computing array, realizes in-memory computing, significantly reduces the loss caused by data transmission, improves the computing efficiency and data processing capacity, and meets the demand for model training and operation.
[0056] In a specific embodiment, a magnetic random memory array unit and a resistive random memory array unit can be used. The resistive random memory array unit is used to perform matrix vector multiplication calculation on the matrix data of the convolution layer sent by the data processing unit according to the weight parameters of the convolution layer; and the magnetic random memory array unit is used to perform matrix vector multiplication calculation on the matrix data of the fully connected layer sent by the data processing unit according to the weight parameters of the fully connected layer.
[0057] The resistive random memory array unit includes a plurality of resistive random memory array sub-units, each of which corresponds to processing the matrix vector multiplication calculation of one convolution layer.
[0058] As a specific application of the above data computing system, referring to FIG. 3, a speech keyword recognition system constituted by the data computing system is shown, in which the data processing unit is an FPGA, the data transmission unit is a peripheral circuit, the memristor array unit adopts a magnetic random memory array unit and a resistive random memory array unit, and the recognition model adopts the convolutional neural network shown in FIG. 2.
[0059] In specific implementation, first, the network structure is built and the network weight is preliminarily trained on the host computer, and then the structure parameters and the weight parameters of each layer are transmitted to the BRAM (Block RAM, a type of memory in FPGA) in the FPGA.
[0060] Then, the weight mapping is performed. In the weight mapping stage, the FPGA maps the convolution layer weight to the resistive memory array unit and maps the fully connected layer weight to the magnetic random memory array unit through the peripheral circuit. The mapping process is completed by outputting the corresponding level inversion RRAM / MRAM array device resistance value through the peripheral circuit. The low resistance state is mapped to the weight value "1", and the high resistance state is mapped to the weight value "0".
[0061] In order to reduce the influence of hardware non-ideal factors on the accuracy of speech recognition, hardware collaborative training is performed on the fully connected layer in the MRAM array, and the parameters of the fully connected layer in the MRAM array are updated according to the hardware training results. After the hardware weight update is completed, the peripheral circuit collects real-time speech input, and the system realizes the real-time speech keyword recognition function. All hardware operations and array read-write processes are realized by the FPGA PS end and the PL end software and hardware collaborative design.
[0062] The MFCC (Mel Frequency Cepstral Coefficients) feature matrix used in training and actual application is obtained from the processing flow shown in FIG. 5: the MFCC feature extraction operation is realized through the FPGA PL end, and the specific process includes pre-emphasis, framing and windowing, fast Fourier transform, square energy spectrum, digital mel cepstrum filter bank filtering, logarithmic operation, discrete cosine transform, and binary operation. A specific length of speech input can be converted into a binary MFCC feature matrix. The feature extraction result is transmitted to the FPGA BRAM storage unit through the bus protocol, and the PS end calls the output. The final output is a binary 30x10 two-dimensional MFCC feature matrix, wherein 30 is the frame number after the input speech data is framed, and 10 is the 10-dimensional data reserved after 40-dimensional MFCC feature extraction. The output feature matrix is used as the neural network inference input, transmitted to the FPGA PS end through the AXI bus, and then stored in the FPGA.
[0063] Referring to FIG. 2, the binary DS-CNN network structure used has a small number of network weights, which reduces the requirement for the storage density of the MRAM device array.
[0064] After the host computer controls the FPGA to map the network weights obtained from the initial training, it performs hardware-based collaborative training on the neural network. Specifically, the FPGA performs MFCC feature extraction on the training set data to obtain a feature matrix, controls the peripheral circuit to input the convolutional layer RRAM array, reads the intermediate results, calculates the activation function, and transmits them layer by layer. Finally, after outputting from the fully connected layer MRAM array, it calculates the backpropagation weight update and updates the MRAM array weights. The above operation is repeated until training is complete. Specifically, for input data "1", the peripheral circuit inputs a high level to the corresponding path of the memristor array; for input data "0", the peripheral circuit inputs a low level to the corresponding path of the memristor array.
[0065] In the hardware training of the fully connected layer, the FPGA calculates the backpropagation gradient based on the hardware weights and inference results to update the weights of the fully connected layer. During the update of the binary network weights, if an explicit binary weight changes, the peripheral circuit performs a single write / reset operation on the devices in the target MRAM array. This hardware co-training method effectively reduces the impact of hardware non-ideals on the accuracy of the ideal network, while avoiding frequent erase / write operations on devices such as RRAM during the inference process and poor training performance. Since the weights in the RRAM array do not participate in hardware updates, the repeated write process does not affect the actual inference performance of the system. In practical applications, by flexibly selecting memristor arrays for weight mapping and function allocation according to different hardware requirements of the network layers, a better balance can be achieved between the accuracy, power consumption, latency, and other performance indicators of the hardware network.
[0066] After hardware co-training is completed, the system can perform full real-time speech keyword recognition. First, the microphone component in the peripheral circuit collects external audio input, which is then processed by other components and input into the FPGA. The FPGA performs MFCC feature extraction on the speech data, inputs it into the RRAM array according to the network structure for convolution operation, reads the convolution result, calculates the activation function, and continues to input it into the MRAM array until inference is completed, finally obtaining the real-time speech keyword recognition result.
[0067] Based on the same design concept, and referring to Figure 7, an embodiment of this application also provides a model deployment method, applied in the data computing system described in the above embodiments, including:
[0068] 701. Obtain the weight parameters of each layer in the neural network model.
[0069] 702. Based on the correspondence between each network layer and each type of memristor array unit, the control data processing unit maps the weight parameters of each network layer to the corresponding memristor array unit.
[0070] Specifically, the host computer can input the network weights obtained from the initial training into the FPGA for storage. Then, the FPGA controls the external circuitry to map the weights of the convolutional layers to the corresponding resistive random access memory (RRAM) array cells, and the weights of the fully connected layers to the magnetic random access memory (MRMemory) array cells. To ensure the accuracy of the weight values, a step-by-step writing method can be used. For example, the data processing unit can gradually increase the resistance level of the corresponding RRAM in the RRAM array cell until the resistance value of the corresponding RRAM matches the target resistance value. During the gradual increase, the resistance value in the RRAM is read to determine whether the corresponding resistance state has been reached.
[0071] In some specific embodiments, when training a neural network model, the data processing unit can be controlled to read the first matrix-vector multiplication calculation result data from the resistive random access memory array unit, and perform activation processing on the first matrix-vector multiplication calculation result data based on the activation function to obtain activation result data.
[0072] The control data processing unit inputs the activation result data into the resistive random access memory array unit to perform matrix-vector multiplication calculation for the next convolutional layer. The next convolutional layer is the first convolutional layer among two adjacent convolutional layers. The first matrix-vector multiplication calculation result data is the calculation result data of the target convolutional layer read from the resistive random access memory array unit. The target convolutional layer is the second convolutional layer among two adjacent convolutional layers. The second convolutional layer performs matrix-vector multiplication calculation before the first convolutional layer.
[0073] For example, referring to the forward propagation stage of the convolutional neural network model shown in Figure 2, which consists of three convolutional layers, during computation, the data processing unit first writes the feature matrix into the first resistive random access memory (RRAM) array sub-unit corresponding to the convolutional layer for computation. Then, the data processing unit reads the corresponding computation result data and calculates the first activation result data according to the activation function. This first activation result data is then written into the second RRAM array sub-unit corresponding to the deep convolutional layer for computation. The data processing unit then reads the corresponding computation result data and calculates the second activation result data according to the activation function. This second activation result data is then written into the RRAM array sub-unit corresponding to the point convolutional layer for computation, and so on.
[0074] During training of the fully connected layer, the control data processing unit reads the second matrix-vector multiplication calculation result data from the magnetic random access memory array unit. Then, based on the second matrix-vector multiplication calculation result data, the weight parameters of the fully connected layer are updated, and the control data processing unit maps the updated weight parameters to the magnetic random access memory array unit. The specific implementation process can be found in the embodiment of the data calculation system described above, and will not be repeated here.
[0075] For comparison, referring to Figure 6, the hardware co-training method based on memristor devices proposed in this application is compared with the simulation results of an ideal neural network model deployed on defective hardware. The left side shows a comparison of the training results of convolutional layers, and the right side shows a comparison of the training results of fully connected layers. It can be seen that as the number of hardware defects increases, it leads to a loss in network hardware mapping, and the accuracy of the hardware network decreases. When the number of defects exceeds half the number of weights in a single layer, the accuracy loss becomes significant. Hardware co-training can train the network on actual hardware, reducing the impact of hardware defects on network performance, and shows good results in both convolutional and fully connected layers.
[0076] The above describes a model deployment method provided by the embodiments of this application. The following describes the apparatus for performing the above model deployment method.
[0077] Please refer to Figure 8, which is a schematic diagram of a model deployment device provided in an embodiment of this application. As shown in Figure 8, the model deployment device includes:
[0078] The weight parameter acquisition module 801 is used to acquire the weight parameters of each layer in the neural network model. And,
[0079] The weight parameter mapping module 802 is used to control the data processing unit to map the weight parameters of each layer of the network to the corresponding memristor array cells according to the correspondence between each layer of the network and each type of memristor array cell.
[0080] In one possible implementation, it further includes: a first model training module, used to control the data processing unit to read the first matrix-vector multiplication calculation result data from the resistive random access memory array unit when training the neural network model, and to perform activation processing on the first matrix-vector multiplication calculation result data based on the activation function to obtain activation result data;
[0081] The control data processing unit inputs the activation result data into the resistive random access memory array unit to perform matrix-vector multiplication calculation for the next convolutional layer. The next convolutional layer is the first convolutional layer among two adjacent convolutional layers. The first matrix-vector multiplication calculation result data is the calculation result data of the target convolutional layer read from the resistive random access memory array unit. The target convolutional layer is the second convolutional layer among two adjacent convolutional layers. The second convolutional layer performs matrix-vector multiplication calculation before the first convolutional layer.
[0082] In one possible implementation, it also includes: a second model training module for controlling the data processing unit to read the second matrix-vector multiplication calculation result data from the magnetic random access memory array unit;
[0083] The weight parameters of the fully connected layer are updated based on the results of the second matrix-vector multiplication calculation, and the data processing unit is controlled to map the updated weight parameters to the magnetic random access memory array unit.
[0084] In one possible implementation, the weight parameter mapping module 802, in controlling the data processing unit to map the weight parameters of the convolutional layer to the resistive random access memory array cells, includes:
[0085] The control data processing unit gradually increases the resistance level of the corresponding resistive variable memory in the resistive variable memory array unit until the resistance value of the corresponding resistive variable memory matches the target resistance value.
[0086] This application also provides an electronic device. Referring to FIG9, a schematic diagram of a structure suitable for implementing the electronic device in this application is shown. The electronic device in this application may include, but is not limited to, fixed terminals such as mobile phones, laptops, PDAs (personal digital assistants), PADs (tablet computers), desktop computers, etc. The electronic device shown in FIG9 is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.
[0087] As shown in Figure 9, the electronic device may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 into a random access memory (RAM) 903. When the electronic device is powered on, the RAM 903 also stores various programs and data required for the operation of the electronic device. The processing unit 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.
[0088] Typically, the following devices can be connected to I / O interface 905: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, memory cards, hard drives, etc.; and communication devices 909. Communication device 909 allows the electronic device to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 9 shows an electronic device with various devices, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.
[0089] This application also provides a computer program product including computer-readable instructions, which, when executed on an electronic device, cause the electronic device to implement any of the model deployment methods provided in this application.
[0090] This application also provides a computer-readable storage medium that carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement any of the model deployment methods provided in this application.
[0091] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.
[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0093] In the above embodiments, the implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.
[0094] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).
Claims
1. A data computing system, characterized in that, include: Data processing unit, data transmission unit, and at least two types of memristor array units; The at least two types of memristor array units are respectively connected through the data transmission unit and the data processing unit; The data processing unit is used to map the weight parameters used in each inference process of the neural network model to a corresponding memristor array unit; Each of the memristor array units is used to perform matrix-vector multiplication calculations on the matrix data sent by the data processing unit according to the weight parameters.
2. The data computing system according to claim 1, characterized in that, The at least two types of memristor array units include: a magnetic random access memory array unit and a resistive random access memory array unit. The resistive random access memory array unit is used to perform matrix-vector multiplication calculations on the matrix data of the convolutional layer sent by the data processing unit according to the weight parameters of the convolutional layer. The magnetic random access memory array unit is used to perform matrix-vector multiplication calculations on the matrix data of the fully connected layer sent by the data processing unit according to the weight parameters of the fully connected layer.
3. The data computing system according to claim 2, characterized in that, The resistive random access memory (RRAM) array unit includes multiple RRAM array sub-units, each of which is responsible for processing matrix-vector multiplication calculations for one convolutional layer.
4. A model deployment method, applied in the data computing system according to any one of claims 1 to 3, characterized in that, include: Obtain the weight parameters of each layer in the neural network model; Based on the correspondence between each network layer and each memristor array unit, the control data processing unit maps the weight parameters of each network layer to the corresponding memristor array unit.
5. The model deployment method according to claim 4, characterized in that, Also includes: When training the neural network model, the data processing unit is controlled to read the first matrix-vector multiplication calculation result data from the resistive random access memory array unit, and to perform activation processing on the first matrix-vector multiplication calculation result data based on the activation function to obtain activation result data; The data processing unit is controlled to input the activation result data into the resistive random access memory array unit to perform matrix-vector multiplication calculation for the next convolutional layer. The next convolutional layer is the first convolutional layer among two adjacent convolutional layers. The first matrix-vector multiplication calculation result data is the calculation result data of the target convolutional layer read from the resistive random access memory array unit. The target convolutional layer is the second convolutional layer among the two adjacent convolutional layers. The second convolutional layer performs matrix-vector multiplication calculation before the first convolutional layer.
6. The model deployment method according to claim 5, characterized in that, Also includes: The data processing unit is controlled to read the second matrix-vector multiplication calculation result data from the magnetic random access memory array unit; The weight parameters of the fully connected layer are updated based on the calculation result of the second matrix-vector multiplication, and the data processing unit is controlled to map the updated weight parameters into the magnetic random access memory array unit.
7. The model deployment method according to any one of claims 4 to 6, characterized in that, When the control data processing unit maps the weight parameters of the convolutional layer to the resistive random access memory array cells, it includes: The data processing unit is controlled to gradually increase the resistance level of the corresponding resistive variable memory in the resistive variable memory array unit until the resistance value of the corresponding resistive variable memory matches the target resistance value.
8. A model deployment device, characterized in that, include: The weight parameter acquisition module is used to obtain the weight parameters of each layer in the neural network model. as well as, The weight parameter mapping module is used to control the data processing unit to map the weight parameters of each layer of the network to the corresponding memristor array unit according to the correspondence between each layer of the network and each type of memristor array unit.
9. An electronic device, characterized in that, It includes at least one processor and a memory connected to the processor, wherein: The memory is used to store computer programs; The processor is used to execute the computer program to enable the electronic device to implement the model deployment method as described in any one of claims 4 to 7.
10. A computer storage medium, characterized in that, The storage medium carries one or more computer programs that, when executed by an electronic device, enable the electronic device to implement the model deployment method as described in any one of claims 4 to 7.