Register file, read / write path allocation method, processor, chip, and electronic device

Abstract

The embodiments of the present disclosure belong to the technical field of chips. Provided are a register file, a read / write path allocation method, a processor, a chip, and an electronic device. The register file comprises: a register array, a connection network, and read / write ports, wherein the connection network comprises a first selection layer and second selection layers. The first selection layer is provided with a set of column multiplexers and a set of row multiplexers, wherein the set of column multiplexers includes a plurality of column multiplexers, each of which is configured to select a register from a column in the register array; and the set of row multiplexers includes a plurality of row multiplexers, each of which is configured to select a register from a row in the register array. The second selection layers are configured to select target registers from registers already selected by the first selection layer, so as to establish data read / write paths between the read / write ports and the target registers. The embodiments of the present disclosure can reduce the area of the connection network and reduce the probability of read-read and write-write conflicts.

Description

Register file, read / write path allocation method, processor, chip and electronic device Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a register file, a read / write path allocation method, a processor, a chip, and an electronic device. Background Technology

[0002] The register file is an important component of the processor architecture, typically consisting of multiple registers arranged in a matrix. Its primary function is to store data for the processor's computational units to read or write.

[0003] With the continuous development of processor technology, in order to improve processing performance, multiple computing units are usually set up in the processor to execute different computing tasks in parallel. Considering the limited processor space, and based on the design concept of sharing storage resources, the computing units in the processor usually share the same register file. That is, during task execution, each computing unit will simultaneously perform data reading or writing operations on the registers in the same register file through its corresponding read / write port.

[0004] To achieve the above functionality and avoid read / write conflicts, related technologies employ multiple data selectors to fully connect the read / write ports to the registers in the register file. That is, each read / write port is connected to every register in the register file. Refer to Figure 1, which is a schematic diagram of a register file structure provided by related technologies. Figure 1 exemplarily illustrates a scenario with two read ports and a register array consisting of 4×4 = 16 registers. As can be seen from Figure 1, for the above scenario, each read port requires five 4-to-1 data selectors (hereinafter referred to as mux4 for ease of description), which is equivalent to requiring 15 2-to-1 data selectors (hereinafter referred to as mux2 for ease of description). Two read ports would require a total of 30 mux2s. The coordinates of the lower left register in the register array are marked as (0,0), the upper right register as (3,3), and so on, to obtain the coordinates of the remaining registers in the register array. Observing Figure 1, we can see that if read port 0 wants to read data from the (2,2) position register, then for the four mux4s connected to the register array in Figure 1, only the gray mux4 is occupied, while the other three mux4s can be multiplexed by read port 1. Based on the above analysis, in some related technologies, the register file shown in Figure 1 can be structurally improved, as shown in Figure 2. In Figure 2, read port 0 and read port 1 share the four mux4s connected to the register array. In this case, if the register position to be read by read port 1 is not located in the second column, there will be no concurrent read conflict; however, if the register position to be read by read port 1 is located in the second column, a concurrent read conflict will occur.

[0005] All of the above solutions result in a huge network area for the register file connections. Statistics show that the network area will account for 80-90% of the total area of ​​the register file. This is detrimental to processor performance improvement and also hinders cost reduction. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide a register file, a read / write path allocation method, a processor, a chip, and an electronic device to at least solve or alleviate the above-mentioned problems.

[0007] According to a first aspect of the present disclosure, a register file is provided, including: a register array, a connection network, and a plurality of read / write ports;

[0008] The register array includes multiple registers arranged in an array.

[0009] The connection network includes: a first selection layer and a second selection layer;

[0010] The first selection layer includes a set of column data selectors and a set of row data selectors; the set of column data selectors contains multiple column data selectors, one of which is used to select a register from a column in the register array; the set of row data selectors contains multiple row data selectors, one of which is used to select a register from a row in the register array.

[0011] There are multiple second selection layers, and each second selection layer corresponds to one read / write port; the second selection layer is used to select a target register from the registers already selected by the first selection layer, so as to establish a data read / write path between the corresponding read / write port and the target register.

[0012] According to a second aspect of the present disclosure, a read / write path allocation method is provided, applied to the register file described in the first aspect above, the method comprising:

[0013] Determine the coordinates of the register to be allocated within the register array; the register to be allocated is the register that the target read / write port will access.

[0014] Count the number of first allocated registers that have the same first-direction coordinate value as the register to be allocated along the first direction;

[0015] If the number of the first allocated registers in the same direction is less than the number of the first direction data selector sets set in the register file, then the register to be allocated is assigned to the first data selector in the target first direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the first data selector; the target first direction data selector set is a first direction data selector set that is not occupied by other read / write ports, and the first data selector is the data selector in the target first direction data selector set that corresponds to the register to be allocated;

[0016] Wherein, the first direction is either a column direction or a row direction; if the first direction is a column direction, the first direction data selector set is a column data selector set; if the first direction is a row direction, the first direction data selector set is a row data selector set.

[0017] According to a third aspect of the present disclosure, a processor is provided, including: a computing unit, and the register file described in the first aspect above;

[0018] The register file is used to store computational data;

[0019] The computing unit is used to execute computing tasks, and during the task execution, it performs computing data read and write operations on the registers in the register file through the read and write ports in the register file.

[0020] According to a fourth aspect of the present disclosure, a chip is provided, comprising: the processor described in the third aspect above.

[0021] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising: the processor described in the third aspect above, or the chip described in the fourth aspect above.

[0022] According to the register file provided in this embodiment, the connection network is divided into two selection layers. The first selection layer selects any register from the register array, and the second selection layer selects the target register based on the selection result of the first selection layer. This establishes a data read / write path between the read / write port corresponding to the second selection layer and the target register. In this embodiment, during parallel data transmission based on multiple read / write ports, each read / write port shares the aforementioned first selection layer. Therefore, this embodiment can effectively reduce the number of selectors in the register file, thereby reducing the area of ​​the connection network and lowering the cost of the register file.

[0023] Furthermore, in the register file provided in this embodiment, the first selection layer simultaneously sets two sets of data selectors in both row and column directions, thereby providing each register in the register array with two optional paths to connect to the read / write port: it can connect to the read / write port through the column data selector in the column data selector set, or it can connect to the read / write port through the row data selector in the row data selector set. Therefore, the possibility of different read / write ports performing data read / write operations from different registers simultaneously through the same data selector can be reduced, which also reduces the probability of simultaneous read / write conflicts in the register file. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0025] Figure 1 is a schematic diagram of a register file structure provided by related technologies;

[0026] Figure 2 is a schematic diagram of another register file structure provided by related technologies;

[0027] Figure 3 is a schematic diagram of the structural framework of a register file according to an embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of a specific structure of a register file according to Embodiment 1 of this disclosure;

[0029] Figure 5 is a schematic diagram of read / write conflicts in the register file shown in Figure 4;

[0030] Figure 6 is a schematic diagram of another specific structure of a register file provided according to Embodiment 1 of this disclosure;

[0031] Figure 7 is a schematic diagram of read / write conflicts in the register file shown in Figure 6;

[0032] Figure 8 is a schematic diagram of another specific structure of a register file according to Embodiment 1 of this disclosure;

[0033] Figure 9 is a schematic diagram of the read / write path allocation process;

[0034] Figure 10 is a flowchart of a read / write path allocation method according to an embodiment of the present disclosure;

[0035] Figure 11 is a schematic diagram of a scenario of the read / write path allocation method according to an embodiment of the present disclosure;

[0036] Figure 12 is a flowchart of the read / write path allocation method according to an embodiment of the present disclosure in a specific scenario;

[0037] Figure 13 is a schematic diagram of the row coordinate value matrix in an embodiment of this disclosure. Detailed Implementation

[0038] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0039] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0040] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0041] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0042] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0043] Example 1

[0044] Referring to Figure 3, Figure 3 is a schematic diagram of the structural framework of a register file according to an embodiment of this disclosure. The register file 300 includes: a register array 302, a connection network 304, and multiple read / write ports 306;

[0045] Register array 302 contains multiple registers arranged in an array;

[0046] The connection network 304 includes: a first selection layer 3042 and a second selection layer 3044;

[0047] The first selection layer 3042 is provided with a column data selector set and a row data selector set; the column data selector set contains multiple column data selectors, and one column data selector is used to select a register from a column in the register array 302; the row data selector set contains multiple row data selectors, and one row data selector is used to select a register from a row in the register array 302.

[0048] There are multiple second selection layers 3044, and one second selection layer 3044 corresponds to one read / write port 306. The second selection layer 3044 is used to select the target register from the registers already selected by the first selection layer 3042, so as to establish a data read / write path between the corresponding read / write port 306 and the target register.

[0049] Specifically, the register file 300 provided in this embodiment divides the connection network 304 into two selection layers, wherein the first selection layer 3042 is used to select any register from the register array 302. Specifically, by setting a set of column data selectors in the column direction and a set of row data selectors in the row direction, each register in the register array 302 can have two optional paths: it can be connected to the second selection layer 3044 through the column data selectors in the column data selector set. Since the second selection layer 3044 is one-to-one with and connected to the read / write port 306, by setting the set of column data selectors in the column direction, a data read / write path of "register - column data selector in the first selection layer 3042 - second selection layer 3044 - read / write port 306" can be finally established; or, it can be connected to the second selection layer 3044 through the row data selectors in the row data selector set, thereby establishing a data read / write path of "register - row data selector in the first selection layer 3042 - second selection layer 3044 - read / write port 306".

[0050] In this embodiment, the second selection layer 3044 is configured corresponding to the read / write ports 306. That is, the number of second selection layers 3044 corresponds to the number of read / write ports 306, connecting the first selection layer 3042 to the read / write ports 306 via the corresponding second selection layer 3044. In this embodiment, the specific structure of the second selection layer 3044 is not limited and can be customized according to the size of the register array 302 and other practical considerations. For example, assuming the first selection layer 3042 contains N data selectors, the second selection layer 3044 can be configured as any data selector or set of data selectors capable of performing an N-to-1 selection function. For example, an N-to-1 data selector can be used as the second selection layer 3044, or a multi-select 1 data selector can be set for the set of column data selectors in the first selection layer 3042. Similarly, a multi-select 1 data selector can be set for the set of row data selectors in the first selection layer 3042. Then, a 2-to-1 data selector can be set to select data from the above two multi-select 1 data selectors, and so on.

[0051] Referring to Figure 4, which is a schematic diagram of a specific structure of a register file according to Embodiment 1 of this disclosure, the register file provided in Embodiment 1 of this disclosure will be explained in detail below with reference to Figure 4:

[0052] Figure 4 illustrates an example of a register array containing 4×4 registers; a set of column data selectors X, consisting of 4 mux4 column data selectors, is arranged along the column direction, wherein one column data selector is used to select a register from a column. Specifically, the 0th column data selector in the set of column data selectors X in Figure 4 is used to select a register from the 0th column, the 1st column data selector is used to select a register from the 1st column, ..., and the 3rd column data selector is used to select a register from the 3rd column; similarly, a set of row data selectors Y, consisting of 4 mux4 row data selectors, is also arranged along the row direction.

[0053] Figure 4 also illustrates the specific structure of the second selection layer. A single second selection layer includes two mux4s and one mux2. The two mux4s are used to select data selectors from the column data selector set and the row data selector set, respectively. The mux2 is used to select again from the data selectors selected by the two mux4s, thereby determining the target register. For example, the second selection layer corresponding to read / write port 0 consists of a data selector 0Y and a data selector 0X in the form of mux4, and a data selector XY0 in the form of mux2. The data selector 0Y is used to select from the row data selector set, the data selector 0X is used to select from the column data selector set, and the data selector XY0 is used to select again from 0Y and 0X.

[0054] Referring to Figure 5, which is a schematic diagram of read-write conflicts in the register file shown in Figure 4, the following explanation, in conjunction with Figure 5, clarifies the potential read-write conflicts in the register file shown in Figure 4:

[0055] Suppose the current register file has 6 read / write ports: port 0, port 1, port 2, port 3, port 4, and port 5. The registers to be accessed by these 6 read / write ports are, in order: row 2, column 1; row 2, column 2; row 2, column 3; row 1, column 1; row 1, column 2; and row 1, column 3. As shown in the figure, for the register in row 2, column 1 that the 0th read / write port wants to access, it can be assigned to the first column data selector corresponding to that register in column data selector set X; for the register in row 2, column 2 that the 1st read / write port wants to access, to avoid read / write conflicts, it can be assigned to the corresponding row data selector in row data selector set Y; for the register in row 2, column 3 that the 2nd read / write port wants to access, to avoid read / write conflicts, it can be assigned to the corresponding data selector in column data selector set X; for the register in row 1, column 1 that the 3rd read / write port wants to access, to avoid read / write conflicts, it can be assigned to the corresponding row data selector in row data selector set Y; for the register in row 1, column 2 that the 4th read / write port wants to access, to avoid read / write conflicts, it can be assigned to the corresponding data selector in column data selector set X. When processing the register in the 1st row and 3rd column that the 5th read / write port wants to access, a read / write conflict will occur because both the corresponding row data selector in the row selector set and the corresponding column data selector in the column selector set are occupied by other registers or other read / write ports. Therefore, no matter which allocation method is selected from either the column data selector set X or the row data selector set Y, a read / write conflict will occur.

[0056] Based on the above analysis of Figure 5, it can be seen that for the register file provided in this embodiment, when the number of column data selector sets and the number of row data selector sets set in the first selection layer 3042 are both 1, a maximum of 5 read / write ports can be implemented without conflict during the same read / write process.

[0057] Furthermore, simple statistics show that for a register file with 5 read / write ports, if the structure shown in Figure 1 is used, as mentioned above, 15 mux2s are required for each read / write port, resulting in 75 mux2s for all 5 read / write ports. However, if the structure provided in this embodiment is used, the first selection layer is configured with 8 mux4s, where each mux4 requires 2+1=3 mux2s to function, meaning the first selection layer is configured with 8×3=24 mux2s; a single second selection layer is configured with one mux8, where each mux8 requires 4+2+1=7 mux2s to function, meaning a single second selection layer is configured with 7 mux2s. Since there are 5 read / write ports, configuring 5 second selection layers, i.e., a total of 5×7=35 mux2s, is sufficient. In summary, using the structure provided in this embodiment, only 35+24=59 mux2s are needed. Therefore, for a register file containing 5 read / write ports, compared to the structure shown in Figure 1, the structure of this embodiment can save 75-59=16 mux2s.

[0058] According to the register file provided in this embodiment, the connection network is divided into two selection layers. The first selection layer selects any register from the register array, and the second selection layer selects the target register based on the selection result of the first selection layer. This establishes a data read / write path between the read / write port corresponding to the second selection layer and the target register. In this embodiment, during parallel data transmission based on multiple read / write ports, each read / write port shares the aforementioned first selection layer. Therefore, this embodiment can effectively reduce the number of selectors in the register file, thereby reducing the area of ​​the connection network and lowering the cost of the register file.

[0059] Furthermore, in the register file provided in this embodiment, the first selection layer simultaneously sets two sets of data selectors in both row and column directions, thereby providing each register in the register array with two optional paths to connect to the read / write port: it can connect to the read / write port through the column data selector in the column data selector set, or it can connect to the read / write port through the row data selector in the row data selector set. Therefore, the possibility of different read / write ports performing data read / write operations from different registers simultaneously through the same data selector can be reduced, which also reduces the probability of simultaneous read / write conflicts in the register file.

[0060] Optionally, in some embodiments, when the number of read / write ports is greater than 5, the number of column data selector sets in the first selection layer is set to multiple, and the number of row data selector sets is equal to the number of column data selector sets.

[0061] As indicated in the analysis based on Figure 5 above, when the number of read / write ports exceeds five, read / write conflicts will occur if the number of column data selector sets and row data selector sets in the first selection layer are set to one. To reduce the probability of conflicts, in the above embodiments of this disclosure, the number of column data selector sets and row data selector sets in the first selection layer are set to multiple. That is, if one column data selector set and one row data selector set are considered as a set of data selectors, then in the above embodiments of this disclosure, multiple sets of data selector sets are set in the first selection layer. Since a set of data selectors can provide two optional paths to each register in the register array, the optional paths to each register will increase exponentially when the number of data selector sets increases. This effectively reduces the probability of multiple read / write ports sending simultaneous read / write conflicts.

[0062] Referring to Figure 6, which is a schematic diagram of another specific structure of a register file according to Embodiment 1 of this disclosure, the internal structure of a register file containing multiple sets of data selectors is explained below with reference to Figure 6:

[0063] Figure 6 illustrates an exemplary register array containing 8×8 registers. The first selection layer contains two sets of data selectors: two sets of column data selectors and two sets of row data selectors. Specifically, each set of column data selectors is used to select a register from the corresponding column in the register array, and similarly, each set of row data selectors is used to select a register from the corresponding row in the register array.

[0064] Compared to the case with only one set of data selectors, since the total number of data selectors in the first selection layer increases from 16 to 32, the function to be implemented in the second selection layer should be changed from 16-to-1 to 32-to-1. Furthermore, since there is a one-to-one correspondence between the second selection layer and the read / write ports, the number of data selectors with 32-to-1 functionality should be set for each read / write port.

[0065] See Figure 7, which is a schematic diagram of read / write conflicts in the register file shown in Figure 6.

[0066] The following explanation, in conjunction with Figure 7, details the potential read / write conflicts that may occur in the register file shown in Figure 6:

[0067] Assume the current register file has 19 read / write ports. The registers to be accessed by these 19 read / write ports are, in order: row 6, column 1; row 6, column 2; row 6, column 3; row 6, column 4; row 6, column 5; row 5, column 1; row 5, column 2; row 5, column 3; row 5, column 4; row 5, column 1; row 4, column 2; row 4, column 3; row 4, column 5; row 3, column 1; row 3, column 2; row 3, column 3; and row 3, column 4. As shown in Figure 7, the register in row 6, column 1 is assigned to the corresponding column data selector in column data selector set X0; the register in row 6, column 2 is assigned to the corresponding column data selector in column data selector set X1; the register in row 6, column 3 is assigned to the corresponding row data selector in row data selector set Y0; the register in row 6, column 4 is assigned to the corresponding row data selector in row data selector set Y1; the register in row 6, column 5 is assigned to the corresponding column data selector in column data selector set X0; the register in row 5, column 1 is assigned to the corresponding row data selector in row data selector set Y1; the register in row 5, column 2 is assigned to the corresponding column data selector in column data selector set X0; the register in row 5, column 3 is assigned to the corresponding column data selector in column data selector set X1; and the register in row 5, column 4 is assigned to the corresponding row data selector in row data selector set Y0. The following functions are used to assign the register in row 5, column 5 to the corresponding column data selector in column data selector set X1, assign the register in row 4, column 1 to the corresponding row data selector in row data selector set Y0, assign the register in row 4, column 2 to the corresponding row data selector in row data selector set Y1, assign the register in row 4, column 3 to the corresponding column data selector in column data selector set X0, assign the register in row 4, column 4 to the corresponding column data selector in column data selector set X1, assign the register in row 3, column 1 to the corresponding column data selector in column data selector set X1, assign the register in row 3, column 2 to the corresponding row data selector in row data selector set Y0, assign the register in row 3, column 3 to the corresponding row data selector in row data selector set Y1, and assign the register in row 3, column 4 to the corresponding column data selector in column data selector set X0. At this point, only one register remains: the register in row 4 and column 5. Since both the corresponding row data selectors in row selector sets Y0 and Y1 and the corresponding column data selectors in column selector sets X0 and X1 are occupied by other registers or other read / write ports, a read / write conflict will occur no matter how the register in row 4 and column 5 is allocated.

[0068] Based on the above analysis of Figure 7, it can be seen that for the register file provided in this embodiment, when the number of column data selector sets and the number of row data selector sets set in the first selection layer 3042 are both 2, a maximum of 18 read / write ports can be implemented without conflict during the same read / write process.

[0069] Furthermore, simple statistics show that for a register file containing 18 read / write ports, if the structure shown in Figure 1 is adopted, 63 mux2s need to be configured for each read / write port. Therefore, 18 read / write ports would require 18 × 63 = 1134 mux2s. If the structure provided in this embodiment is adopted, the first selection layer is configured with two sets of data selectors. Each set of data selectors includes a column data selector set and a row data selector set. The number of data selectors in the row data selector set and the column data selector set is equal, both being 8. Therefore, the first selection layer is configured with a total of 2×2×8 mux8. Since 1 mux8 requires 7 mux2 to implement the function, the first selection layer is configured with a total of 2×2×8×7=224 mux2. The second selection layer is configured with a total of 18 mux32. Since 1 mux32 requires 16+8+4+2+1=31 mux2 to implement the function, the second selection layer is configured with a total of 18×31==558 mux2. In summary, if the structure provided in this embodiment is adopted, a total of 224+558=782 mux2 can be configured. Therefore, for a register file containing 18 read / write ports, the structure of this embodiment can save 1134-782=352 mux2s compared to the structure shown in Figure 1.

[0070] Furthermore, as shown in Figures 5 and 7, regardless of the number of data selector sets configured in the first selection layer, for a given register in the register array, if the row or column data selector corresponding to that register is occupied by other registers, further allocation to that register will result in a read / write conflict. Therefore, to further reduce the probability of read / write conflicts, optionally, in some embodiments, when the number of read / write ports is greater than (2^n)... 2 When the number of read / write ports is greater than 2^n, the number of column data selectors in the first selection layer is set to be greater than n; where n is a natural number greater than 1. Correspondingly, when the number of read / write ports is greater than (2^n)... 2 When +n, the number of row data selectors in the first selection layer is also set to be greater than n; where n is a natural number greater than 1.

[0071] The data relationships between the number of column data selector sets and the number of read / write ports, and between the number of row data selector sets and the number of read / write ports, are derived from the internal structure of the register file provided in this embodiment and the characteristics of the data selector itself. Therefore, setting the number of column data selector sets and the number of row data selector sets based on these data relationships can effectively reduce the probability of read / write conflicts.

[0072] In the above embodiments, the register file provided by this disclosure is mainly explained through the read port, while the overall logic of the write port is similar to that of the read port. Referring to Figure 8, Figure 8 is a schematic diagram of another specific structure of a register file provided according to Embodiment 1 of this disclosure. Figure 8 is a schematic diagram of the internal structure of the register file when the specific type of the port is a write port. Analysis of Figure 8 shows that for a register file containing 5 write ports and a register array size of 4×4, if the structure corresponding to Figure 1 is adopted, for each register, 4 write ports require 2+1=3 mux2s, so 5 write ports require one more mux2, that is, 5 write ports require a total of 3+1=4 mux2s. For a register file containing a 4×4 register array, a total of 4×4×4=64 mux2s are required. However, if the structure provided in this embodiment is adopted, each register in the first selection layer needs to receive data in either the row direction or the column direction, so the first selection layer is configured with a total of 16 mux2s; the second selection layer needs to be configured with 8 mux5s, that is, 8 × 4 = 32 mux2s. In summary, using the structure provided in this embodiment, only 32 + 16 = 48 mux2s are needed. Therefore, for a register file containing 5 read / write ports, compared with the structure corresponding to Figure 1, the structure of this embodiment can save 16 mux2s.

[0073] Refer to Figure 9, which is a schematic diagram of the read / write path allocation process. Figure 9 uses a 3×3 register array with 5 read / write ports as an example to explain the specific situations where different allocation methods may lead to conflicts:

[0074] Assume the registers to be accessed by the 5 read / write ports are, in order: row 2, column 1; row 1, column 1; row 1, column 2; row 0, column 1; and row 0, column 2.

[0075] As shown in the read / write path allocation method on the left side of Figure 9, the register in row 2, column 1 is assigned to the row data selector corresponding to that register in row selector set Y; the register in row 1, column 1 is assigned to the column data selector corresponding to that register in column selector set X; the register in row 1, column 2 is assigned to the row data selector corresponding to that register in row selector set Y; the register in row 0, column 1 can be assigned to the row data selector corresponding to that register in row selector set Y; and the register in row 0, column 2 is assigned to the column data selector corresponding to that register in column selector set X. As can be seen from the left side of Figure 9, this read / write path allocation method can avoid conflicts.

[0076] If we follow the read / write path allocation method shown on the right side of Figure 9, the register in row 2, column 1 is allocated to the column data selector corresponding to that register in column selector set X; the register in row 1, column 1 is allocated to the row data selector corresponding to that register in row selector set Y; the register in row 1, column 2 is allocated to the column data selector corresponding to that register in column selector set X; and the register in row 0, column 1 can be allocated to the row data selector corresponding to that register in row selector set Y. However, for the register in row 0, column 2, since both the corresponding row data selector in row selector set Y and the corresponding column data selector in column selector set X are already occupied by other registers, a read / write conflict will occur regardless of the allocation method used for the register in row 0, column 2.

[0077] By comparing the two different read / write path allocation methods in Figure 9, it can be seen that the register file provided in this embodiment of the present disclosure can effectively reduce the probability of simultaneous read / write conflicts by providing multiple optional paths to each register. However, providing multiple optional connection paths does not necessarily mean that conflicts will not occur. When the connection path is not selected properly, conflicts may still occur. Therefore, whether a conflict occurs also depends on the specific read / write path allocation method, that is, on which data selector in the first selection layer the register is assigned to.

[0078] Example 2

[0079] Figure 10 shows a flowchart of a read / write path allocation method according to an embodiment of this disclosure. This read / write path allocation method can be executed by the register file 300 in the above embodiments. It should be noted that the specific structure of the register file 300 has been described in detail in the register file embodiment section with reference to the structural diagram. For details, please refer to the description in the aforementioned register file embodiment, and it will not be repeated here. The following mainly explains the read / write path allocation method applied to the register file 300.

[0080] As shown in Figure 10, the read / write path allocation method may include the following steps:

[0081] Step 1002: Determine the coordinates of the register to be allocated in the register array; the register to be allocated is the register that the target read / write port will access.

[0082] Specifically, the read / write ports in the register file can be connected to external computing units. When an external computing unit needs to read or write data to a register in the register array—that is, when an external computing unit needs to access a register in the register array—it can send a data read / write request or access request to the register file through the read / write port. This request may contain the identification information of the register to be accessed. After receiving the request, the register file can decode the request and determine the coordinates of the register to be accessed in the register array based on the identification information contained in the request. Since the register to be accessed has not yet been assigned to a specific data selector, it can be called an unassigned register.

[0083] After determining the register that the target read / write port will access, this step can determine the register's position in the register array. Furthermore, the position can be represented using coordinate values. For example, coordinate values ​​in a first perpendicular direction and a second perpendicular direction can be used to represent the register's specific position in the register array. For instance, the first and second directions can correspond to the row and column directions, respectively.

[0084] Step 1004: Count the number of first allocated registers in the same direction that have the same first coordinate value as the register to be allocated along the first direction.

[0085] Here, the first direction is either the column direction or the row direction; the first allocated register in the same direction refers to the register in the allocated registers whose allocated data selector set has the same direction as the first direction.

[0086] Specifically, compared to registers to be allocated, allocated registers can be registers in the register array that have already been assigned to a specific data selector.

[0087] Regarding the allocated directional registers, when the first direction is the column direction, the first allocated directional register refers to the register allocated to the column data selector in the column data selector set; when the first direction is the row direction, the first allocated directional register refers to the register allocated to the row data selector in the row data selector set.

[0088] When the first direction is the column direction, count the number of first allocated registers in the same direction that have the same column coordinate value as the register to be allocated. That is, count the number of registers in the same column as the register to be allocated that have been allocated to the column data selector in the column data selector set. When the first direction is the row direction, count the number of first allocated registers in the same direction that have the same row coordinate value as the register to be allocated. That is, count the number of registers in the same row as the register to be allocated that have been allocated to the row data selector in the row data selector set.

[0089] Step 1006: If the number of first allocated registers in the same direction is less than the number of first direction data selectors set in the register file, then the register to be allocated is allocated to the first data selector in the target first direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the first data selector.

[0090] The target first direction data selector set is a first direction data selector set that is not occupied by other read / write ports, and the first data selector is the data selector in the target first direction data selector set that corresponds to the register to be allocated; if the first direction is the column direction, the first direction data selector set is the column data selector set; if the first direction is the row direction, the first direction data selector set is the row data selector set.

[0091] Specifically, if the number of allocated registers in the same direction in the column containing the register to be allocated is less than the number of column data selector sets, it indicates that there is at least one unoccupied column data selector set at the current time. Therefore, the register to be allocated can be assigned to the column data selector corresponding to the register in the unoccupied column data selector set to avoid simultaneous read / write conflicts. Conversely, if the number of allocated registers in the same direction in the row containing the register to be allocated is less than the number of row data selector sets (the number of row data selectors is the same as the number of column data selectors), it indicates that there is at least one unoccupied row data selector set at the current time. Therefore, the register to be allocated can be assigned to the row data selector corresponding to the register in the unoccupied row data selector set to avoid simultaneous read / write conflicts.

[0092] For example, when the first selection layer of the register file contains a set of data selectors, namely, a set of row data selectors and a set of column data selectors, if the first direction coordinate value of the register to be allocated along the first direction is different from the first direction coordinate values ​​of other allocated registers in the same direction, then the register to be allocated is assigned to the target data selector corresponding to the register in the first direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the target data selector. In other words, if there is no allocated register in the same direction as the register to be allocated, it indicates that the column data selector set is not occupied at the current time. Therefore, the register to be allocated can be assigned to the target data selector corresponding to the register in the column data selector set to avoid simultaneous read / write conflicts. Correspondingly, if there is no allocated register in the same direction as the register to be allocated, it means that the current row data selector set is not occupied. Therefore, the register to be allocated can be assigned to the target data selector corresponding to the register in the row data selector set to avoid simultaneous read and write conflicts.

[0093] Alternatively, in some embodiments, the read / write path allocation method may further include:

[0094] If the number of first allocated registers in the same direction is greater than or equal to the number of first direction data selectors, then count the number of second allocated registers in the same direction that have the same second coordinate value as the register to be allocated along the second direction.

[0095] If the number of second allocated registers in the same direction is less than the number of second direction data selectors set in the register file, the register to be allocated is assigned to the second data selector in the target second direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the second data selector.

[0096] The target second-direction data selector set is a set of second-direction data selectors that are not occupied by other read / write ports. The second data selector is the data selector in the target second-direction data selector set that corresponds to the register to be allocated. The second direction is either the row direction or the column direction. If the second direction is the row direction, the second-direction data selector set is the row data selector set. If the second direction is the column direction, the second-direction data selector set is the column data selector set.

[0097] The read / write path allocation method provided in this disclosure counts the number of allocated registers in the same row or column as the register to be allocated. Based on the relationship between the number of allocated registers in the same direction and the number of row or column data selector sets in the register file, it infers whether there are currently any unoccupied row or column data selector sets. If such sets exist, the register to be allocated is assigned to one of them. A data read / write path is then established between the register to be allocated and the target read / write port using the target selector in the unoccupied set. This disclosure effectively reduces the probability of conflicts when multiple read / write ports in the register file are simultaneously performing data read / write operations.

[0098] Optionally, in some embodiments, the read / write path allocation method may further include:

[0099] An allocation conflict is determined when the number of first allocated in-direction registers is greater than or equal to the number of first direction data selector sets set in the register file, and the number of second allocated in-direction registers is also greater than or equal to the number of second direction data selector sets set in the register file;

[0100] For the next register to be allocated, return to the step of determining the coordinates of the register to be allocated in the register array, until all registers to be allocated have been allocated.

[0101] Specifically, for some processors, read-write conflict handling logic can be pre-defined. When a simultaneous read / write conflict occurs in the register file, an allocation conflict is identified. The processor can then execute the corresponding processing operation according to the pre-defined read-write conflict handling logic to avoid the conflict. In this embodiment, the specific content of the read-write conflict handling logic is not limited and can be customized according to actual conditions. For example, registers located in other positions in the register array can be reallocated to the read / write ports as registers to be accessed, and then the read-write path allocation process can be executed through this embodiment. Alternatively, the read-write path allocation process can be executed through this embodiment after other read / write ports have completed their read / write operations, and so on.

[0102] In the embodiments described above, for scenarios with read / write conflict handling logic, if a simultaneous read / write conflict will occur after the register to be allocated is allocated using a data selector, the allocation process is stopped. Instead, the allocation conflict is identified, triggering the execution of the conflict handling logic. This conflict handling logic then avoids simultaneous read / write conflicts. This approach is a simplified conflict handling scheme, offering the advantages of a simpler processing procedure and higher processing efficiency.

[0103] Referring to Figure 11, which is a schematic diagram of a scenario of the read / write path allocation method according to an embodiment of this disclosure, the specific read / write path allocation process is as follows: the register file receives a data read request sent from an external source, which may contain identification information of the register to be accessed; after receiving the request, the register file decodes the request and determines the coordinates of the register to be accessed in the register array based on the identification information contained in the request; then, the read / write path allocation method provided by this disclosure can be executed; during the execution of the method, if a suitable data selector can be allocated to the register to be accessed without conflict, a data read / write path is determined based on the allocated data selector, and the data in the register to be accessed is read to the outside of the register file according to the data read / write path; conversely, if a suitable data selector cannot be allocated to the register to be accessed without conflict, the allocation process can be stopped, and an allocation conflict can be determined.

[0104] Optionally, in some embodiments, step 1004 above may further include:

[0105] The number of first allocated registers in the same direction along the first direction that have the same first direction coordinate value as the register to be allocated is counted; and the number of the remaining first unallocated registers in the first direction that have the same first direction coordinate value as the register to be allocated is counted.

[0106] Summing the number of the first allocated registers in the same direction and the number of the first remaining unallocated registers yields the summation result for the first direction.

[0107] The number of second allocated registers in the same direction along the second direction that have the same second-direction coordinate value as the register to be allocated is counted; and the number of second remaining unallocated registers in the second direction that have the same second-direction coordinate value as the register to be allocated is counted.

[0108] Summing the number of the second allocated registers in the same direction and the number of the remaining unallocated registers yields the summation result for the second direction.

[0109] Correspondingly, step 1006 above can be: if the summation result corresponding to the first direction is less than the number of the first direction data selectors set in the register file, then the register to be allocated is allocated to the first data selector, that is: the register to be allocated is allocated to the data selector corresponding to the register to be allocated in the unoccupied first direction data selector set, so as to establish a data read and write path between the register to be allocated and the target read and write port through the first data selector;

[0110] If the summation result corresponding to the second direction is less than the number of second-direction data selectors set in the register file, then the register to be allocated will be assigned to the second data selector. That is, the register to be allocated will be assigned to the data selector corresponding to the register to be allocated in the unoccupied second-direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the second data selector.

[0111] Furthermore, when the summation result corresponding to the first direction, that is, the total number of the first remaining unallocated registers and the first allocated registers in the same direction that have the same first direction coordinate value as the register to be allocated along the first direction, is greater than or equal to the number of the first direction data selector sets set in the register file, and the summation result corresponding to the second direction, that is, the total number of the second remaining unallocated registers and the second allocated registers in the same direction that have the same second direction coordinate value as the register to be allocated along the second direction, is also greater than or equal to the number of the second direction data selector sets set in the register file, it is determined whether there is a target allocated register in the same row or column as the register to be allocated;

[0112] If a target allocated register exists in the same row or column, and this target allocated register in the same row or column is allocated to a row data selector in the first row data selector set, then the register to be allocated is allocated to a target column data selector in the target column data selector set; or, the register to be allocated is allocated to a row data selector corresponding to the register to be allocated in the target second row data selector set. Wherein, the target column data selector set is a set of column data selectors not occupied by other read / write ports; the target column data selector is a column data selector corresponding to the register to be allocated in the target column data selector set; and the target second row data selector set is a set of row data selectors different from the first row data selector set and not occupied by other read / write ports.

[0113] If a target allocated register exists in the same row or column, and that target allocated register is assigned to a column data selector in the first column data selector set, then the register to be allocated is assigned to a target row data selector in the target row data selector set, or the register to be allocated is assigned to the data selector corresponding to the register to be allocated in the target second column data selector set; wherein, the target row data selector set is a set of row data selectors not occupied by other read / write ports; the target row data selector is the row data selector corresponding to the register to be allocated in the target row data selector set; the target second column data selector set is a set of column data selectors different from the first column data selector set and not occupied by other read / write ports;

[0114] If no target register is already allocated in the same row or column, it can be allocated freely.

[0115] Specifically, in the above embodiments of this disclosure, when the total number of first other registers to be allocated and first allocated registers having the same first-direction coordinate value as the register to be allocated along the first direction is greater than or equal to the number of first-direction data selector sets set in the register file, and the total number of second other registers to be allocated and second allocated registers having the same second-direction coordinate value as the register to be allocated along the second direction is also greater than or equal to the number of second-direction data selector sets set in the register file, then the allocation of data selectors for allocated registers in the same row or column as the register to be allocated is referenced. Specifically, the principle is to maintain a different allocation method from that of allocated registers in the same row or column. The allocation method is as follows: if an allocated register in the same row or column is allocated to a row data selector in the first row data selector set, then the register to be allocated is allocated to the data selector corresponding to the register to be allocated in the column data selector set, or the register to be allocated is allocated to the data selector corresponding to the register to be allocated in the second row data selector set; conversely, if an allocated register in the same row or column is allocated to a first column data selector in the column data selector set, then the register to be allocated is allocated to the data selector corresponding to the register to be allocated in the row data selector set, or the register to be allocated is allocated to the data selector corresponding to the register to be allocated in the second column data selector set.

[0116] For example, when the first selection layer of the register file contains a set of data selectors, that is, a set of row data selectors and a set of column data selectors, if there are other registers to be allocated and allocated registers in the same column as the register to be allocated, and there are also other registers to be allocated and allocated registers in the same row as the register to be allocated, then the allocation of the register to be allocated is performed with reference to the allocation method of the allocated registers in the same row or column as the register to be allocated. Specifically, if the allocated registers in the same row or column are allocated to the row data selectors in the set of row data selectors, then the register to be allocated is allocated to the column data selector in the set of column data selectors corresponding to the register to be allocated; conversely, if the allocated registers in the same row or column are allocated to the column data selectors in the set of column data selectors, then the register to be allocated is allocated to the row data selector in the set of row data selectors corresponding to the register to be allocated.

[0117] The above allocation principle ensures that within the first selection layer, registers in the same row or column are assigned to data selectors from different directional dimensions. Therefore, it can effectively avoid conflicts when multiple read / write ports in the register file are performing data read / write operations simultaneously.

[0118] Referring to Figure 12, which is a flowchart of the read / write path allocation method of this disclosure embodiment in a specific scenario, Figure 12 illustrates a scenario involving five read port register files. The read / write path allocation method provided by this disclosure embodiment will be briefly described below with reference to Figure 12:

[0119] The first step is to compare the row and column coordinate values ​​of the registers to be accessed by each read / write port pairwise. Specifically, a row coordinate value matrix can be constructed, where each element in the matrix indicates whether the row coordinate values ​​of the registers to be accessed by two different read / write ports are equal. For example, if they are equal, the value is 1; otherwise, it is 0. Refer to Figure 13, which is a schematic diagram of the row coordinate value matrix in an embodiment of this disclosure. In Figure 13, A, B, C, D, and E represent the row coordinate values ​​of the registers to be accessed by each read / write port, respectively. Correspondingly, a column coordinate value matrix can also be constructed: each element in the column coordinate value matrix indicates whether the column coordinate values ​​of the registers to be accessed by two different read / write ports are equal. For example, if they are equal, the value is 1; otherwise, it is 0.

[0120] The second step is to allocate the read / write ports sequentially, that is, to assign the registers to be accessed by each read / write port to the appropriate data selectors in the first selection layer. Specifically:

[0121] If the row coordinate value of a register to be accessed at a certain read / write port is not equal to the row coordinate values ​​of other registers to be accessed, then the register to be accessed at that read / write port is assigned to the row data selector corresponding to the register in the row data selector set of the first selection layer. As shown in Figure 12, referring to the row coordinate value matrix, when the vector formed by the row elements of the register to be accessed in the row coordinate value matrix is ​​a one-hot vector (a one-hot vector is a vector in which only one element is 1 and the rest are 0), that is, when only one element in the row elements of the register to be accessed is 1 (equal to itself), then the register to be accessed is assigned to the row data selector corresponding to the register in the row data selector set of the first selection layer.

[0122] If the column coordinate value of a register to be accessed at a certain read / write port is not equal to the column coordinate values ​​of other registers to be accessed, then the register to be accessed at that read / write port is assigned to the column data selector corresponding to the register in the column data selector set of the first selection layer. Alternatively, a column coordinate value matrix can be used as a reference. If the vector formed by the elements of the column containing the column coordinate value of the register to be accessed is a one-hot vector (i.e., only one element in the column containing the column coordinate value of the register to be accessed has a value of 1), then the register to be accessed is assigned to the column data selector corresponding to the register in the column data selector set of the first selection layer.

[0123] If, for a register to be accessed on a certain read / write port, there are other registers to be accessed with the same column coordinate value as the register, and there are other registers to be accessed with the same row coordinate value as the register, then the allocation of the data selectors of the allocated registers in the same row or column as the register is referenced: if the allocated register in the same row or column is allocated to the row data selector in the row data selector set, then the register is allocated to the corresponding column data selector in the column data selector set; otherwise, if the allocated register in the same row or column is allocated to the column data selector in the column data selector set, then the register is allocated to the corresponding row data selector in the row data selector set. Alternatively, the row coordinate matrix and column coordinate matrix can be referenced. If, in the row coordinate matrix, the vector formed by the elements of the row containing the row coordinate of the register to be accessed is a non-one-hot vector (i.e., more than one element in the row containing the row coordinate of the register to be accessed has a value of 1), and in the column coordinate matrix, the vector formed by the elements of the column containing the column containing the column coordinate of the register to be accessed is also a non-one-hot vector (i.e., more than one element in the column containing the column coordinate of the register to be accessed has a value of 1), then the allocation of the data selectors of the allocated registers in the same row or column as the register to be accessed can be referenced: if the allocated register in the same row or column is allocated to a row data selector in the row data selector set, then the register to be allocated to the corresponding column data selector in the column data selector set; conversely, if the allocated register in the same row or column is allocated to a column data selector in the column data selector set, then the register to be allocated to the corresponding row data selector in the row data selector set.

[0124] Optionally, in some embodiments, after determining the coordinates of the register to be allocated in the register array, the method may further include:

[0125] Based on the coordinates of the register to be allocated in the register array, determine whether there is an overlapping allocated register with the same location as the register to be allocated; where the overlapping allocated register is a register that has completed read / write path allocation and is not currently accessed by other read / write ports;

[0126] If it exists, then determine the read / write path of the register to be allocated within the first selection layer according to the read / write path of the overlapping allocated registers within the first selection layer;

[0127] Based on the correspondence between the target read / write port and the second selection layer, the read / write path of the register to be allocated within the target second selection layer is determined from multiple second selection layers. The target second selection layer is the second selection layer corresponding to the register to be allocated among multiple second selection layers.

[0128] Based on the read / write path of the register to be allocated within the first selection layer, and the read / write path of the register to be allocated within the target second selection layer, a read / write path is established between the register to be allocated and the target read / write port.

[0129] Specifically, after determining the location coordinates of the register to be allocated corresponding to the target read / write port, it is possible to first determine whether there are other read / write ports. The register corresponding to the other read / write port is the aforementioned register to be allocated. In other words, it is possible to first determine whether other ports have accessed this register to be allocated. If other ports have previously accessed this register to be allocated and these other ports are no longer accessing this register to be allocated (this register to be allocated is not currently being accessed by other read / write ports), then the path allocation operation can be performed by referring to the read / write path determined when the other ports accessed this register to be allocated.

[0130] For the connection network in the register file, different read / write ports share only the first selection layer, while the second selection layer is independent; that is, different read / write ports correspond to different second selection layers. Therefore, for different read / write ports accessing the same register, the final read / write paths are also different. Based on the above, the specific reference method for the read / write path in this embodiment is not to directly use the read / write path determined when other ports access this register to be allocated as the current read / write path, but rather: to determine the read / write path of the register to be allocated within the first selection layer by overlapping the read / write paths of the allocated registers; and simultaneously, according to the correspondence between the target read / write port and the second selection layer, to determine the read / write path of the register to be allocated within the target second selection layer from multiple second selection layers, wherein the target second selection layer is the second selection layer corresponding to the register to be allocated among multiple second selection layers. Thus, by combining the read / write path of the register to be allocated within the first selection layer and the read / write path of the register to be allocated within the target second selection layer, a complete read / write path between the register to be allocated and the target read / write port can be established.

[0131] Since the read / write paths determined when other ports access this register to be allocated did not result in concurrent read or write conflicts, this path allocation operation will also not result in concurrent read or write conflicts if the read / write paths determined when other ports access this register to be allocated are used as a reference.

[0132] In the embodiments disclosed above, existing data selector allocation schemes are fully referenced, which can quickly and efficiently obtain data read and write paths that will not cause conflicts without performing complex process steps.

[0133] This disclosure also provides a processor, including: a computing unit, and a register file as described in the above embodiments;

[0134] The register file is used to store computation data; the computation unit is used to execute computation tasks and, during task execution, performs computation data read and write operations on the registers in the register file through the read and write ports in the register file.

[0135] This disclosure also provides a chip, including the processor described in the above embodiments.

[0136] This disclosure also provides an electronic device, including: the processor in the above embodiments, or the chip in the above embodiments.

[0137] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0138] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0139] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0140] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A register file, comprising: Register array, network connectivity, and multiple read / write ports; The register array includes multiple registers arranged in an array. The connection network includes: a first selection layer and a second selection layer; The first selection layer includes a set of column data selectors and a set of row data selectors; the set of column data selectors contains multiple column data selectors, one of which is used to select a register from a column in the register array; the set of row data selectors contains multiple row data selectors, one of which is used to select a register from a row in the register array. There are multiple second selection layers, and each second selection layer corresponds to one read / write port; the second selection layer is used to select a target register from the registers already selected by the first selection layer, so as to establish a data read / write path between the corresponding read / write port and the target register.

2. The register file according to claim 1, wherein, When the number of read / write ports is greater than 5, the number of column data selector sets in the first selection layer is set to multiple, and the number of row data selector sets is equal to the number of column data selector sets.

3. The register file according to claim 2, wherein, When the number of read / write ports is greater than (2n) 2 When +n, the number of column data selector sets in the first selection layer is set to be greater than n; where n is a natural number greater than 1.

4. A read / write path allocation method, applied to the register file according to any one of claims 1-3, the method comprising: Determine the coordinates of the register to be allocated within the register array; The register to be allocated is the register that the target read / write port will access; Count the number of first allocated registers that have the same first-direction coordinate value as the register to be allocated along the first direction; If the number of the first allocated registers in the same direction is less than the number of the first direction data selector sets set in the register file, then the register to be allocated is assigned to the first data selector in the target first direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the first data selector; the target first direction data selector set is a first direction data selector set that is not occupied by other read / write ports, and the first data selector is the data selector in the target first direction data selector set that corresponds to the register to be allocated; Wherein, the first direction is either a column direction or a row direction; if the first direction is a column direction, the first direction data selector set is a column data selector set; if the first direction is a row direction, the first direction data selector set is a row data selector set.

5. The method according to claim 4, wherein, The method further includes: If the number of the first allocated registers in the same direction is greater than or equal to the number of the first direction data selector set, then count the number of the second allocated registers in the same direction that have the same second direction coordinate value as the register to be allocated along the second direction; the first direction is perpendicular to the second direction; If the number of the second allocated registers in the same direction is less than the number of the second direction data selector sets set in the register file, then the register to be allocated is allocated to the second data selector in the target second direction data selector set, so as to establish a data read / write path between the register to be allocated and the target read / write port through the second data selector; the target second direction data selector set is a set of second direction data selectors not occupied by other read / write ports, and the second data selector is the data selector in the target second direction data selector set corresponding to the register to be allocated; Wherein, the second direction is either a row direction or a column direction; if the second direction is a row direction, the second direction data selector set is a row data selector set; if the second direction is a column direction, the second direction data selector set is a column data selector set.

6. The method according to claim 5, wherein, After counting the number of first allocated registers in the same direction that have the same first-direction coordinate value as the register to be allocated along the first direction, the method further includes: The number of the first remaining unallocated registers that have the same first direction coordinate value as the register to be allocated along the first direction is counted, and the number of the first allocated registers in the same direction and the number of the first remaining unallocated registers are summed to obtain the summation result corresponding to the first direction; If the summation result corresponding to the first direction is less than the number of first direction data selectors set in the register file, then the register to be allocated is assigned to the first data selector so as to establish a data read / write path between the register to be allocated and the target read / write port through the first data selector. After counting the number of second allocated registers in the same direction that have the same second-direction coordinate value as the register to be allocated, the method further includes: The number of the second remaining unallocated registers that have the same second-direction coordinate value as the register to be allocated is counted along the second direction, and the number of the second allocated registers in the same direction and the number of the second remaining unallocated registers are summed to obtain the summation result corresponding to the second direction; If the summation result corresponding to the second direction is less than the number of second direction data selectors set in the register file, then the register to be allocated is assigned to the second data selector so as to establish a data read / write path between the register to be allocated and the target read / write port through the second data selector.

7. The method according to claim 6, wherein, The method further includes: When the summation result corresponding to the first direction is greater than or equal to the number of first direction data selectors set in the register file, and the summation result corresponding to the second direction is also greater than or equal to the number of second direction data selectors set in the register file, it is determined whether there is a target allocated register in the same row or column as the register to be allocated; If the target allocated register exists, and the target allocated register is allocated to a row data selector in the first row data selector set, then the register to be allocated is allocated to a target column data selector in the target column data selector set; or, the register to be allocated is allocated to a row data selector corresponding to the register to be allocated in the target second row data selector set; the target column data selector set is a set of column data selectors not occupied by other read / write ports; the target column data selector is a column data selector corresponding to the register to be allocated in the target column data selector set; the target second row data selector set is a set of row data selectors different from the first row data selector set and not occupied by other read / write ports. If the target allocated register exists and the target allocated register is allocated to a column data selector in the first column data selector set, then the register to be allocated is allocated to a target row data selector in the target row data selector set; or, the register to be allocated is allocated to a column data selector corresponding to the register to be allocated in the target second column data selector set; the target row data selector set is a set of row data selectors not occupied by other read / write ports; the target row data selector is the row data selector corresponding to the register to be allocated in the target row data selector set; the target second column data selector set is a set of column data selectors different from the first column data selector set and not occupied by other read / write ports.

8. The method according to claim 5, wherein, The method further includes: An allocation conflict is determined when the number of the first allocated in-direction registers is greater than or equal to the number of the first direction data selector sets set in the register file, and the number of the second allocated in-direction registers is also greater than or equal to the number of the second direction data selector sets set in the register file. For the next register to be allocated, return to the step of determining the coordinates of the register to be allocated in the register array, until the data read / write paths for each register to be allocated have been allocated.

9. The method according to any one of claims 4-8, wherein, After determining the coordinates of the register to be allocated in the register array, the method further includes: Based on the coordinates of the register to be allocated in the register array, it is determined whether there is an overlapping allocated register with the same location as the register to be allocated; the overlapping allocated register is a register that has completed read / write path allocation and is not currently accessed by other read / write ports; If it exists, then the read / write path of the register to be allocated within the first selection layer is determined according to the read / write path of the overlapping allocated register within the first selection layer; According to the correspondence between the target read / write port and the second selection layer, the read / write path of the register to be allocated within the target second selection layer is determined from multiple second selection layers, wherein the target second selection layer is the second selection layer corresponding to the register to be allocated among multiple second selection layers; Based on the read / write path of the register to be allocated within the first selection layer, and the read / write path of the register to be allocated within the target second selection layer, a read / write path is established between the register to be allocated and the target read / write port.

10. A processor, comprising: A computing unit, and a register file as described in any one of claims 1-3; The register file is used to store computational data; The computing unit is used to execute computing tasks, and during the task execution process, it performs computing data read and write operations on the registers in the register file through the read and write ports in the register file.

11. A chip, comprising: The processor as described in claim 10.

12. An electronic device, comprising: The processor as claimed in claim 10, or the chip as claimed in claim 11.

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