Display apparatus

Abstract

Provided in the present application is a display apparatus. The technical solution executed by the display apparatus comprises: I: within a blanking period of a drive cycle for each image frame, controlling by means of a control signal a fifteenth transistor to turn on, so as to write a high-level voltage into a node K_i; and II: providing a twenty-sixth transistor between a fourteenth transistor and the node K_i, and making the critical switching voltage at a node between the fourteenth transistor and the twenty-sixth transistor be 3-5 volts lower than the critical switching voltage of the node K_i. The present application can effectively improve the stability of the operation of a gate drive circuit in a high-temperature and high-humidity environment.

Description

Display device Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] In the field of display panel technology, CMOS (Complementary Metal-Oxide-Semiconductor) GOA (Gate-driver On Array) technology can achieve frequency division and segmentation functions. However, under dual 85°C (85°C, 85% humidity) reliability verification (RA) environments, the threshold voltage (Vth) of the IGZO transistors in the display panel experiences large-area drift, causing the circuit's operational stability to be compromised. This situation severely affects the operational stability of the gate driver circuit under dual 85°C conditions. Invention Overview

[0003] The purpose of embodiments of this application is to provide a display device designed to improve the operational stability of CMOS GOA circuits in a dual 85 environment.

[0004] This application provides a display device, including: a display panel, the display panel including a gate driving circuit and a plurality of pixels, the gate driving circuit including a multi-level cascaded gate driving sub-circuit, the i-th level gate driving sub-circuit in the multi-level gate driving sub-circuit including at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module and a second gate driving signal frequency division control module, the shift register module being electrically connected to the self-stabilizing module, the first gate driving signal frequency division control module and the second gate driving signal frequency division control module being electrically connected to both the shift register module and the self-stabilizing module; the self-stabilizing module including at least: a first transistor, the gate of the first transistor being electrically connected to node K_i, the node K_i being a node of the connection line between the shift register module and the first gate driving signal frequency division control module and / or the second gate driving signal frequency division control module, one of the source and drain of the first transistor being electrically connected to a first low-level signal input terminal, the other of the source and drain of the first transistor being electrically connected to node P_i, the node P_i being a node of the i-th level gate driving sub-circuit. A node in the connection line between a gate drive signal frequency division control module and a second gate drive signal frequency division control module; a third transistor, the gate of which is electrically connected to node K_i, one of the source and drain of which is electrically connected to a first high-level signal input terminal, and the other of the source and drain of which is electrically connected to node P_i; a fourteenth transistor, the gate of which is electrically connected to node P_i, and one of the source and drain of which is electrically connected to a second low-level signal input terminal. The source and drain of the fourteenth transistor are electrically connected to the node K_i; and the fifteenth transistor has its gate electrically connected to the control signal input terminal, one of its source and drain being electrically connected to the first high-level signal input terminal, and the other of its source and drain being electrically connected to the node K_i; wherein the signal at the control signal input terminal is used to control the fifteenth transistor to write a high-level voltage to the node K_i during the blanking period of the driving cycle of each frame.

[0005] This application also provides a display device, characterized in that it includes: a display panel, the display panel including a gate driving circuit and a plurality of pixels, the gate driving circuit including multiple cascaded gate driving sub-circuits, the i-th stage gate driving sub-circuit in the multiple stages of the gate driving sub-circuit including at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module and a second gate driving signal frequency division control module, the shift register module being electrically connected to the self-stabilizing module, and both the first gate driving signal frequency division control module and the second gate driving signal frequency division control module being connected to the shift register module. The module and the self-stabilizing module are electrically connected; the self-stabilizing module includes at least: a first transistor, one of the source and drain of the first transistor is electrically connected to a first low-level signal input terminal, the gate of the first transistor is electrically connected to node K_i, the node K_i is a node of the connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, and the other of the source and drain of the first transistor is electrically connected to node P_i, the node P_i is a connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module. The nodes of the connection lines between the drive signal frequency division control modules; a third transistor, the gate of which is electrically connected to the node K_i, one of the source and drain of which is electrically connected to the first high-level signal input terminal, and the other of the source and drain of which is electrically connected to the node P_i; a fourteenth transistor, the gate of which is electrically connected to the node P_i, and one of the source and drain of which is electrically connected to the second low-level signal input terminal; and a twenty-sixth transistor, the gate of which is connected to the fourth clock signal input terminal. The source of the 26th transistor is electrically connected to the other of the source and drain of the 14th transistor, and the drain of the 26th transistor is electrically connected to the node K_i; the shift register module includes at least: a second transistor, the gate of the second transistor is electrically connected to the first clock signal input terminal, one of the source and drain of the second transistor is electrically connected to the first high-level signal input terminal, and the other of the source and drain of the second transistor is electrically connected to the node K_i; wherein, the signal at the fourth clock signal input terminal is inverted compared to the signal at the first clock signal input terminal. Beneficial effects

[0006] The display device provided in this application improves the operational stability of the gate drive circuit under high temperature and high humidity environments through the following two technical solutions:

[0007] The first technical solution involves controlling the fifteenth transistor to conduct during the blanking period of each frame's drive cycle, thereby writing a high-level voltage from the first high-level signal input to node K_i. Since the first and third transistors form an inverter, when the level of node K_i is pulled high, the inverter pulls the level of node P_i low. Thus, by periodically adjusting the levels of nodes K_i and P_i during the blanking period, even if the threshold voltage of the semiconductor transistors drifts, it ensures that the level of node P_i can normally transition from high to low, thereby preventing the fourteenth transistor from abnormally conducting and affecting the normal change of the level of node K_i.

[0008] The second technical solution involves adding a twenty-sixth transistor between the source and drain of the fourteenth transistor and node K_i, and using a fourth clock signal input that is inverted by the signal at the first clock signal input to control the conduction and cutoff of the twenty-sixth transistor. Since the critical transition voltage of the node between the source and drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3-5 volts lower than the critical transition voltage of node K_i, even if the threshold voltage of the semiconductor transistor drifts, the voltage between the source and drain of the fourteenth transistor will decrease by 3-5 volts. This reduces the conduction current of the fourteenth transistor and prevents abnormal conduction of the fourteenth transistor from affecting the normal level change of node K_i.

[0009] Both of the above technical solutions can effectively solve the problem that the levels of nodes K_i and P_i cannot change normally due to the threshold voltage drift of semiconductor transistors in high temperature and high humidity environments, thereby improving the working stability of the gate drive circuit in high temperature and high humidity environments. Attached Figure Description

[0010] Figure 1 is a schematic diagram of the display device provided in this application.

[0011] Figure 2 is a circuit diagram of a gate driver sub-circuit in the display device provided in this application.

[0012] Figure 3 is another circuit diagram of the gate driving sub-circuit in the display device provided in this application.

[0013] Figure 4 is a schematic diagram of the performance of the gate driver sub-circuit of a conventional display device when the threshold voltages of the first and third transistors drift.

[0014] Figure 5 is a schematic diagram of the performance of the gate driver sub-circuit shown in Figure 3 when the threshold voltages of the first and third transistors drift.

[0015] Figure 6 shows the waveforms of various signals when the threshold voltage of the first transistor in the gate driver circuit of a conventional display device drifts by 6 volts.

[0016] Figure 7 shows the waveforms of each signal in the gate driver sub-circuit shown in Figure 3 when the threshold voltage of the first transistor drifts by 6 volts. Embodiments of the present invention

[0017] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0018] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0019] The embodiments of this application can be combined with each other.

[0020] This application relates to the field of display technology, specifically to a technical solution for improving display abnormalities in display devices under high temperature and high humidity environments. This technology is mainly applied to the gate driving circuit of a display device, aiming to improve the stability and reliability of the gate driving circuit under specific harsh environments, ensuring the normal operation of the display device.

[0021] As shown in Figure 1, the display device provided in the embodiments of this application includes a display panel. The display panel includes a gate driving circuit and a plurality of pixels PX. The gate driving circuit includes multiple cascaded gate driving sub-circuits.

[0022] The display panel includes a display area and a non-display area. The display area has multiple pixels (PX) arranged in an array, and the non-display area is located around the periphery of the display area. The display panel also includes multiple scan lines (SCAN), multiple data lines (DATA), multiple light emission control signal lines (EM), a light emission controller, and a gate drive circuit. The multiple scan lines (SCAN) and multiple light emission control signal lines (EM) extend along a first direction and are arranged along a second direction, while the multiple data lines (DATA) extend along the second direction and are arranged along the first direction, with the first direction perpendicular to the second direction. The gate drive circuit is located in the non-display area and is electrically connected to the multiple scan lines (SCAN). The source drive circuit is electrically connected to the multiple data lines (DATA) via a flexible circuit board. The timing controller is electrically connected to the gate drive circuit and the source drive circuit.

[0023] The display panel includes an organic light-emitting diode (OLED) array substrate and an encapsulation layer. The OLED array substrate includes a substrate, a buffer layer disposed on the substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed within an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes a scan line (SCAN) and a gate electrode. The second metal layer includes a data line (DATA), a source electrode, and a drain electrode. The encapsulation layer is hermetically connected to the OLED array substrate.

[0024] Each pixel (PX) includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes at least two transistors and a storage capacitor. One transistor acts as a switching transistor, with its gate electrically connected to the corresponding scan line (SCAN) and its source electrically connected to the corresponding data line (DATA). The other transistor acts as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to a first power supply voltage line, and its drain electrically connected to the anode of the light-emitting device. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to either the source or drain of the driving transistor. The cathode of the light-emitting device is electrically connected to a second power supply voltage line.

[0025] The gate driving circuit includes multiple cascaded gate driving sub-circuits, each electrically connected to a scan line (SCAN). Under the control of the timing controller, the gate driving sub-circuits sequentially output scan signals, scanning each row of pixels (PX) in the display area line by line. The source driving circuit, also under the control of the timing controller, generates and outputs data signals based on the image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source driving circuit. The power management chip provides operating voltages to various parts of the display device, including providing a second power supply voltage to the cathode of the light-emitting device, a first power supply voltage to the first power supply line, and a gate driving voltage to the gate driving circuit.

[0026] The display device of this application includes a display panel, which includes a gate driving circuit and a plurality of pixels PX. The gate driving circuit includes multi-stage cascaded gate driving sub-circuits, the circuit structure of each stage of which is shown in Figure 2. To address the problems encountered by the gate driving circuit in high-temperature and high-humidity environments, this application proposes two embodiments to improve the stability of nodes K_i and P_i under the positive bias temperature stress of IGZO transistors, thereby enhancing the stability of the gate driving circuit in high-temperature and high-humidity environments.

[0027] The embodiments of this application are based on the gate driver sub-circuit shown in FIG2. The i-th stage gate driver sub-circuit in the multi-stage gate driver sub-circuit includes multiple transistors and capacitors.

[0028] Specifically, the i-th stage gate driver sub-circuit includes a first transistor T1_i, a third transistor T3_i, a fourteenth transistor T14_i, and a fifteenth transistor T15_i.

[0029] The gate of the first transistor T1_i is electrically connected to node K_i. One of the source and drain of the first transistor T1_i is electrically connected to the first low-level signal input terminal PVGL, and the other of the source and drain of the first transistor T1_i is electrically connected to node P_i. The gate of the third transistor T3_i is electrically connected to node K_i. One of the source and drain of the third transistor T3_i is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain of the third transistor T3_i is electrically connected to node P_i. The gate of the fourteenth transistor T14_i is electrically connected to node P_i. The source and drain of the fourteenth transistor T14_i are electrically connected to node K_i. One of the transistors is electrically connected to the second low-level signal input terminal NVGL, and the other of the source and drain of the fourteenth transistor T14_i is electrically connected to node K_i; the gate of the fifteenth transistor T15_i is electrically connected to the control signal input terminal Ctrl, one of the source and drain of the fifteenth transistor T15_i is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain of the fifteenth transistor T15_i is electrically connected to node K_i; wherein, the signal of the control signal input terminal Ctrl is used to control the fifteenth transistor T15_i to write a high-level voltage to node K_i during the blanking period of the driving cycle of each frame.

[0030] The Ctrl signal at the control signal input terminal is low during the blanking period of each frame's drive cycle and high during the non-blanking period of each frame's drive cycle.

[0031] The duration of the low level signal at the Ctrl input terminal is less than or equal to the duration of the blanking period.

[0032] The i-th stage gate driver sub-circuit also includes the second transistor T2_i, the fourth transistor T4_i, the fifth transistor T5_i, the sixth transistor T6_i, the seventh transistor T7_i, the eighth transistor T8_i, the ninth transistor T9_i, the tenth transistor T10_i, the eleventh transistor T11_i, the twelfth transistor T12_i, the thirteenth transistor T13_i, the sixteenth transistor T16_i, the seventeenth transistor T17_i, the eighteenth transistor T18_i, the nineteenth transistor T19_i, the twentieth transistor T20_i, the twenty-first transistor T21_i, the twenty-second transistor T22_i, the twenty-third transistor T23_i, the twenty-fourth transistor T24_i, and the twenty-fifth transistor T25_i.

[0033] Among them, the first transistor T1_i, the fourth transistor T4_i, the tenth transistor T10_i, the thirteenth transistor T13_i, the fourteenth transistor T14_i, the seventeenth transistor T17_i, and the twenty-first transistor T21_i are N-type dual-gate transistors (the two gates of each transistor are electrically connected), and these transistors can be, for example, IGZO transistors; the second transistor T2_i, the third transistor T3_i, the fifth transistor T5_i, the sixth transistor T6_i, the seventh transistor T7_i, the eighth transistor T8_i, the ninth transistor T9_i, the eleventh transistor T11_i, the twelfth transistor T12_i, the fifteenth transistor T15_i, the sixteenth transistor T16_i, the eighteenth transistor T18_i, the nineteenth transistor T19_i, the twentieth transistor T20_i, the twenty-second transistor T22_i, the twenty-third transistor T23_i, the twenty-fourth transistor T24_i, and the twenty-fifth transistor T25_i are P-type single-gate transistors, and these transistors can be, for example, LTPS transistors.

[0034] The gate of the second transistor T2_i is electrically connected to the first clock signal input terminal XCK1, and one of its source and drain is electrically connected to node O_i (one of the source and drain of the second transistor is electrically connected to the first high-level signal input terminal PVGH through the twelfth transistor, and electrically connected to the second low-level signal input terminal NVGL through the thirteenth transistor T13_i), and the other of its source and drain is electrically connected to node K_i; the gate of the fourth transistor T4_i is electrically connected to the first clock signal input terminal XCK1, and one of its source and drain is electrically connected to node K_i, and the other of its source and drain is electrically connected to the other of its source and drain of the fifth transistor T5_i; the gate of the fifth transistor T5_i is connected to node P_i. The first transistor T5_i is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain of the fifth transistor T5_i is electrically connected to the other of the source and drain of the fourth transistor T4_i. The gate of the sixth transistor T6_i is electrically connected to node Q1_i, one of its source and drain is electrically connected to the second clock signal CK1, and the other of its source and drain is electrically connected to the first gate drive signal output terminal Pout1_i. The gate of the seventh transistor T7_i is electrically connected to node P_i, one of its source and drain is electrically connected to the first high-level signal input terminal PVGH, and the other of its source and drain is electrically connected to the first gate drive signal output terminal Pout1_i. The eighth transistor T8_i... The gate of transistor i is electrically connected to node P_i-2 in the (i-2)th stage gate driver sub-circuit (node ​​P_i-2 in the (i-2)th stage gate driver sub-circuit corresponds to node P_i in the i-th stage gate driver sub-circuit in terms of position, connection relationship, and function). One of its source and drain is electrically connected to node M_i, and the other of its source and drain is electrically connected to node Q1_i. The gate of the ninth transistor T9_i is electrically connected to node W_i. One of its source and drain is electrically connected to the second high-level signal input terminal NVGH, and the other of its source and drain is electrically connected to the second gate drive signal output terminal Nout_i. The gate of the tenth transistor T10_i is electrically connected to node K_i, and one of its source and drain is electrically connected to the second low-level signal input terminal Nout_i. The input terminal NVGL is electrically connected, and the other of the source and drain terminals is electrically connected to the second gate drive signal output terminal Nout_i; the source and drain terminals of the eleventh transistor T11_i are electrically connected to node K_i, and the other of the source and drain terminals are electrically connected to node W_i; the gate of the twelfth transistor T12_i is electrically connected to the start signal input terminal STV / node P_i-1 in the (i-1)th stage gate drive sub-circuit (node ​​P_i-1 in the (i-1)th stage gate drive sub-circuit corresponds to node P_i in the i-th stage gate drive sub-circuit in terms of position, connection relationship, and function), one of the source and drain terminals is electrically connected to the first high-level signal input terminal PVGH, and the other of the source and drain terminals is electrically connected to node O_i;The gate of the thirteenth transistor T13_i is electrically connected to the start signal input terminal STV, one of its source and drain is electrically connected to the second low-level signal input terminal NVGL, and the other of its source and drain is electrically connected to node O_i; the gate of the sixteenth transistor T16_i is electrically connected to node P_i, one of its source and drain is electrically connected to the first partition allocation control signal input terminal NLF, and the other of its source and drain is electrically connected to the gate of the eleventh transistor T11_i; the gate of the seventeenth transistor T17_i is electrically connected to the first clock signal input terminal XCK1, and one of its source and drain is electrically connected to node W_i. The gate of the eighteenth transistor T18_i is electrically connected to node P_i, one of its source and drain is electrically connected to the first high-level signal input terminal PVGH, and the other of its source and drain is electrically connected to the other of the source and drain of the seventeenth transistor T17_i; one of the source and drain of the nineteenth transistor T19_i is electrically connected to node K_i, and the other of its source and drain is electrically connected to node M_i; the gate of the twentieth transistor T20_i is electrically connected to node P_i, one of its source and drain is electrically connected to the second partition allocation control signal input terminal PLF, and the other of its source and drain is electrically connected to the nineteenth transistor. The gate of transistor T19_i is electrically connected; the gate of the twenty-first transistor T21_i is electrically connected to the first clock signal input terminal XCK1, and one of its source and drain is electrically connected to node M_i; the gate of the twenty-second transistor T22_i is electrically connected to node P_i, one of its source and drain is electrically connected to the first high-level signal input terminal PVGH, and the other of its source and drain is electrically connected to the other of the source and drain of the twenty-first transistor T21_i; the gate of the twenty-third transistor T23_i is electrically connected to node P_i-2 in the (i-2)th stage gate driver sub-circuit, and one of its source and drain is electrically connected to node M_i. Electrically connected, with the other of the source and drain terminals electrically connected to node Q2_i; the gate of the twenty-fourth transistor T24_i is electrically connected to node Q2_i, one of its source and drain terminals is electrically connected to the third clock signal CK2, and the other of its source and drain terminals is electrically connected to the third gate drive signal output terminal Pout2_i (stage transmission signal output terminal); the gate of the twenty-fifth transistor T25_i is electrically connected to node P_i, one of its source and drain terminals is electrically connected to the first high-level signal input terminal PVGH, and the other of its source and drain terminals is electrically connected to the third gate drive signal output terminal Pout2_i (stage transmission signal output terminal).

[0035] In addition, the i-th stage gate driver sub-circuit also includes four capacitors. One plate of the first capacitor C1 is electrically connected to node Q1_i, and the other plate is electrically connected to the first gate drive signal output terminal Pout1_i. One plate of the second capacitor C2 is electrically connected to node W_i, and the other plate is electrically connected to the gate of the eleventh transistor T11_i. One plate of the third capacitor C3 is electrically connected to node M_i, and the other plate is electrically connected to the gate of the nineteenth transistor T19_i. One plate of the fourth capacitor C4 is electrically connected to node Q2_i, and the other plate is electrically connected to the third gate drive signal output terminal Pout2_i (stage transmission signal output terminal).

[0036] The second transistor T2_i, the twelfth transistor T12_i, and the thirteenth transistor T13_i constitute a shift register module 201. The first transistor T1_i, the third transistor T3_i, the fourth transistor T4_i, the fifth transistor T5_i, the fourteenth transistor T14_i, and the fifteenth transistor T15_i constitute a self-stabilizing module 202. The eleventh transistor T11_i, the sixteenth transistor T16_i, the seventeenth transistor T17_i, the eighteenth transistor T18_i, and the second capacitor C2_i constitute a first gate drive signal frequency division control module 203. The ninth transistor T9_i and the tenth transistor T10_i constitute a first gate drive signal frequency division control module 203. The dynamic signal output module 204, the nineteenth transistor T19_i, the twentieth transistor T20_i, the twenty-first transistor T21_i, the twenty-second transistor T22_i, and the third capacitor C3_i constitute the second gate drive signal frequency division control module 205, the sixth transistor T6_i, the seventh transistor T7_i, the eighth transistor T8_i, and the first capacitor C1_i constitute the second gate drive signal output module 206, and the twenty-third transistor T23_i, the twenty-fourth transistor T24_i, the twenty-fifth transistor T25_i, and the fourth capacitor C4_i constitute the third gate drive signal output module (stage transmission signal output module) 207.

[0037] The shift register module 201 is electrically connected to the self-stabilizing module 202. The first gate drive signal frequency division control module 203 and the second gate drive signal frequency division control module 205 are both electrically connected to the shift register module 201 and the self-stabilizing module 202. The first gate drive signal output module 204 is electrically connected to the self-stabilizing module 202 and the first gate drive signal frequency division control module 203. The second gate drive signal output module 206 and the third gate drive signal output module 207 are both electrically connected to the second gate drive signal frequency division control module 205 and the self-stabilizing module 202.

[0038] Analysis revealed that the gate drive circuit malfunctions under high temperature and high humidity conditions because node K_i cannot be pulled up and node P_i cannot be pulled down. Node K_i is the node connecting the shift register module to the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module, and node P_i is the node connecting the first gate drive signal frequency division control module and the second gate drive signal frequency division control module. To address this, this embodiment proposes a periodic reset of node K_i. Specifically, using the signal from the control signal input terminal Ctrl, the voltage of the first high-level signal input terminal PVGH of node K_i is written through the fifteenth transistor T15_i during the blanking period of each frame's drive cycle. The voltage of the first high-level signal input terminal PVGH is a relatively high voltage value, specifically between 10 volts and 20 volts, for example, 10 volts, 12 volts, 14 volts, 16 volts, 18 volts, or 20 volts. The voltage of the first high-level signal input terminal PVGH is selected to effectively change the potential of node K_i and influence the potential of node P_i through the inverter action of the first transistor T1_i and the third transistor T3_i. The voltage of the first high-level signal input terminal PVGH needs to be high enough to overcome the resistive losses in the circuit and the voltage drop of other components, ensuring that the potential of node K_i can be reliably pulled up.

[0039] The blanking period needs to be long enough so that the fifteenth transistor T15_i has sufficient time to write the voltage of the first high-level signal input terminal PVGH to node K_i and complete the subsequent process of influencing the potential of node P_i through the inverters of the first transistor T1_i and the third transistor T3_i. However, it cannot be too long, lest it affect the display phase time and cause a decrease in the frame rate of the displayed image. The blanking period accounts for 10%-30% of the driving cycle of one frame.

[0040] When the fifteenth transistor T15_i is turned on during the blanking period, the voltage of the first high-level signal input terminal PVGH is transmitted to node K_i through the fifteenth transistor T15_i, causing the potential of node K_i to rise. This high voltage is then converted into the signal of the first low-level signal input terminal PVGL by the inverter composed of the first transistor T1_i and the third transistor T3_i. The inverter composed of the first transistor T1_i and the third transistor T3_i utilizes the characteristics of the N-type transistor first transistor T1_i and the P-type transistor third transistor T3_i. When node K_i is high, the first transistor T1_i is turned on and the third transistor T3_i is turned off, causing the potential of node P_i to be pulled down, thereby achieving the purpose of changing the pull-down of node P_i and the pull-up of node K_i. Through such periodic reset operation, the potential of node K_i is adjusted during the blanking period of each frame's drive cycle, improving the working state of nodes K_i and P_i, and enhancing the stability of the gate drive circuit in high temperature and high humidity environments.

[0041] Based on the above embodiments, as an improvement, the signal at the control signal input terminal Ctrl is optimized, specifically including: adjusting the signal frequency, amplitude, or duty cycle to adapt to different display panel requirements and operating environments. For example, increasing the frequency of the control signal makes the periodic reset of node K_i more frequent, thereby more accurately adjusting the potentials of nodes K_i and P_i, further improving circuit stability; adjusting the signal amplitude according to different power supply conditions and circuit component characteristics to ensure that when writing the voltage at the first high-level signal input terminal PVGH, the node potential can be effectively changed without causing excessive electrical stress to other components; optimizing the duty cycle according to the specific duration requirements of the display phase and blanking phase in a frame to achieve optimal circuit performance.

[0042] As an improvement, for applications requiring low power consumption, a transistor with a small on-resistance (e.g., less than 1 kΩ) can be selected as the fifteenth transistor T15_i, or a transistor with an on-resistance smaller than that of other transistors (e.g., any one of the first transistor T1_i to the fourteenth transistor T14_i, the sixteenth transistor T16_i to the twenty-sixth transistor T26_i) can be selected as the fifteenth transistor T15_i. This reduces energy loss when transmitting the voltage of the first high-level signal input terminal PVGH, and also allows for faster potential adjustment of node K_i.

[0043] The above embodiment addresses the problem of node K_i being unable to be pulled up and node P_i being unable to be pulled down by periodically resetting node K_i, directly improving the operating state of nodes K_i and P_i. Specifically, the periodic reset operation involves using the signal at the control signal input terminal Ctrl to write the voltage of the first high-level signal input terminal PVGH to node K_i during the blanking period via the fifteenth transistor T15_i. This, in turn, uses the inverter effect of the first transistor T1_i and the third transistor T3_i to change the pull-down of node P_i and the pull-up of node K_i, thus improving the stability of the gate drive circuit under high temperature and high humidity environments.

[0044] In the embodiments of this application, based on the circuit shown in FIG2, a twenty-sixth transistor T26_i is added between node K_i and the drain of the fourteenth transistor T14_i. The twenty-sixth transistor T26_i is an N-type dual-gate transistor, and the twenty-sixth transistor T26_i can be, for example, an IGZO transistor, as shown in FIG3.

[0045] Specifically, the i-th stage gate driver sub-circuit also includes a twenty-sixth transistor T26_i. The gate of the twenty-sixth transistor T26_i is electrically connected to the fourth clock signal input terminal XCK2, the source of the twenty-sixth transistor T26_i is electrically connected to the other of the source and drain of the fourteenth transistor T14_i, and the drain of the twenty-sixth transistor T26_i is electrically connected to node K_i; wherein, the signal at the fourth clock signal input terminal XCK2 is inverted compared to the signal at the first clock signal input terminal XCK1.

[0046] The inverter formed by the first transistor T1_i and the third transistor T3_i is used to invert the level signal of node K_i and output it to node P_i.

[0047] The critical switching voltage of node X_i between the source and drain of the fourteenth transistor T14_i and the source of the twenty-sixth transistor T26_i is 3-5 volts lower than the critical switching voltage of node K_i.

[0048] The rising edge of the signal at the fourth clock signal input terminal XCK2 is time-aligned with the falling edge of the signal at the first clock signal input terminal XCK1. The duty cycle of the signal at the fourth clock signal input terminal XCK2 is the same as the duty cycle of the signal at the first clock signal input terminal XCK1 (including absolutely the same and approximately the same, where approximately the same means a difference of no more than 10%).

[0049] The drain of the fourteenth transistor T14_i is no longer directly electrically connected to node K_i, but is instead electrically connected through the twenty-sixth transistor T26_i. The twenty-sixth transistor T26_i is controlled by the signal from the fourth clock signal input terminal XCK2, which is inverted compared to the signal from the first clock signal input terminal XCK1. Specifically, the gate of the twenty-sixth transistor T26_i is electrically connected to the fourth clock signal input terminal XCK2, its source is electrically connected to the drain of the fourteenth transistor T14_i, and its drain is electrically connected to node K_i. The twenty-sixth transistor T26_i is an N-type dual-gate transistor.

[0050] The threshold voltage of the 26th transistor T26_i is set such that the critical switching voltage of node X_i is 3-5 volts lower than that of node K_i. This can limit the drain current of the 14th transistor T14_i in advance when the threshold voltage drifts.

[0051] Since the first transistor T1_i and the third transistor T3_i form an inverter, the input of this inverter is electrically connected to node K_i, and the output is electrically connected to node P_i. In high-temperature and high-humidity environments, when the threshold voltage of the first transistor T1_i drifts, it will affect the normal operation of the inverter. Specifically, when node K_i is high, the first transistor T1_i should be turned on to pull node P_i low. However, if the threshold voltage of the first transistor T1_i drifts too much, it will prevent the first transistor T1_i from turning on properly, thus failing to pull node P_i low.

[0052] With the addition of the 26th transistor T26_i, the critical transition voltage of node X_i between the source of the 26th transistor T26_i and the drain of the 14th transistor T14_i is 3-5 volts lower than the critical transition voltage of node K_i. This causes the voltage of node X_i to reach the critical value earlier when the threshold voltage of the first transistor T1_i drifts. When the voltage of node X_i reaches the critical value, it limits the drain current of the 14th transistor T14_i, thereby reducing the pull-down effect of the 14th transistor T14_i on node K_i. Thus, even if the threshold voltage of the first transistor T1_i drifts significantly, node K_i can still maintain a higher level, ensuring that the first transistor T1_i can conduct normally, thereby guaranteeing the normal operation of the inverter.

[0053] Therefore, by adding a 26th transistor T26_i, when the threshold voltage of the first transistor T1_i drifts, the level of node K_i can be maintained by controlling the drain current of the 14th transistor T14_i, thereby improving the tolerance of the first transistor T1_i to threshold voltage drift.

[0054] The signal at the fourth clock signal input terminal XCK2 is out of phase with the signal at the first clock signal input terminal XCK1. This means that the turn-on / turn-off timing of the 26th transistor T26_i is complementary to that of the transistors controlled by the signal at the first clock signal input terminal XCK1 (such as the second transistor T2_i and the fourth transistor T4_i). This ensures that during critical time periods (such as during the reset of node K_i), the 26th transistor T26_i cuts off the drain path of the 14th transistor T14_i, avoiding current competition. Specifically, when the signal at the fourth clock signal input terminal XCK2 is high, the 26th transistor T26_i is turned on, and a path is formed between the drain of the 14th transistor T14_i and node K_i. However, the threshold voltage characteristic of the 26th transistor T26_i affects the equivalent resistance of this path. The critical switching voltage of node X_i is 3-5 volts lower than that of node K_i. This means that when the threshold voltage drifts, the voltage of node X_i reaches the critical value earlier, thus limiting the drain current of the 14th transistor T14_i in advance. Because the voltage at node X_i is pulled down by the 26th transistor T26_i (the conduction of T26_i introduces a voltage divider effect between nodes K_i and T14_i), the drain voltage of the 14th transistor T14_i decreases (the potential (V_X) at node X_i is lower than that at node K_i), resulting in a 3-5 volt reduction in the source-drain voltage difference of the 14th transistor T14_i. This reduction in the source-drain voltage difference directly leads to a decrease in the pull-down current of the 14th transistor T14_i, thereby avoiding the problem of node K_i being unable to be pulled high, significantly improving the threshold voltage tolerance of the circuit, and enhancing the stability of the circuit in high-temperature and high-humidity environments.

[0055] Threshold voltage is a crucial parameter of a transistor, determining when it turns on or off. Critical transition voltage, on the other hand, refers to the threshold voltage at a specific node in a circuit that triggers a change in the operating state of at least one transistor when that node voltage reaches a preset threshold. The critical transition voltage of a node is typically determined based on the threshold voltage of the transistors connected to that node. For example, in this application, when the voltage at node X_i reaches a certain threshold voltage related to the threshold voltage of the 26th transistor T26_i, it causes a change in the operating state of the 14th transistor T14_i, thereby affecting the current and voltage distribution of the entire circuit. The critical transition voltage is generated during the high-low level switching of the inverter; gate drive circuit failure is caused by the inability to successfully complete the high-low level switching.

[0056] The signal at the fourth clock signal input terminal XCK2 is used to control the 26th transistor T26_i, and is inversely phase with the signal at the first clock signal input terminal XCK1. Since the turn-on / off timing of the 26th transistor T26_i is complementary to the turn-on / off timing of the transistor controlled by the signal at the first clock signal input terminal XCK1, during node K_i reset, when the signal at the first clock signal input terminal XCK1 is in a certain state causing other related transistors to be in a specific operating state, the signal at the fourth clock signal input terminal XCK2 causes the 26th transistor T26_i to be in the opposite state, cutting off the drain path of the 14th transistor T14_i, preventing unwanted current flow during this period, and avoiding the impact of current competition on circuit stability. This complementary signal control method ensures stable operation of the circuit under complex operating conditions, especially under threshold voltage drift, maintaining normal circuit operation by controlling the turn-on and turn-off of the 26th transistor T26_i.

[0057] The embodiments of this application add a twenty-sixth transistor T26_i between node K_i and the drain of the fourteenth transistor T14_i, and utilize the signal control of the fourth clock signal input terminal XCK2 to reduce the pull-down current of the fourteenth transistor T14_i, thereby solving the problem that node K_i cannot be pulled high and enhancing the stability of the circuit during threshold voltage drift. The coordinated operation of the twenty-sixth transistor T26_i and the signal of the fourth clock signal input terminal XCK2 makes the critical switching voltage of node X_i 3-5 volts lower than that of node K_i, thereby reducing the source-drain voltage difference and pull-down current of the fourteenth transistor T14_i, improving the stability of the gate drive circuit in high temperature and high humidity environments, and improving the stability of nodes K_i and P_i under positive bias temperature stress of semiconductor materials.

[0058] By comparing the waveforms of the prior art gate driver sub-circuit shown in Figure 4 and the gate driver sub-circuit of Embodiment 2 of this application shown in Figure 5, it can be seen that:

[0059] In the prior art, the gate drive circuit operates normally when the threshold voltage of the first transistor T1_i drifts by 0.5V and the threshold voltage of the third transistor T3_i drifts from 0V to 4V. However, when the threshold voltage of the first transistor T1_i drifts by 0.5V and the threshold voltage of the third transistor T3_i (the channel width of the third transistor T3 is 12 micrometers) drifts by more than 4V, for example, from 4V to 7V, the gate drive sub-circuit fails. In particular, during the time period t3 after t2, the level of node P_i cannot transition from high to low, causing the level of the gate drive signal output terminal Nout_i to fluctuate between medium and high levels, failing to remain stably at a low level. This indicates that the gate drive sub-circuit of the prior art has poor operational stability under high temperature and high humidity environments.

[0060] In Embodiment 2 of this application, by adding a 26th transistor T26 between the source and drain of the 14th transistor T14 and node K, and making the critical switching voltage of the node between the source and drain of the 14th transistor T14 and the source of the 26th transistor T26 3-5 volts lower than the critical switching voltage of node K, the gate drive circuit still operates normally under the same conditions, i.e., when the threshold voltage of the first transistor T1_i drifts by 0.5V and the threshold voltage of the third transistor T3_i (the channel width of the third transistor T3 is 12 micrometers) drifts from 0V to 7V. In particular, during the time period t3 after t2, the level of node P_i can be stably maintained at a low level, and the level of the gate drive signal output terminal Nout_i can also be stably maintained at a low level. This indicates that the gate drive sub-circuit of Embodiment 2 of this application significantly improves the working stability in high temperature and high humidity environments.

[0061] By comparing the waveforms of the prior art gate driver sub-circuit shown in Figure 6 and the gate driver sub-circuit of Embodiment 2 of this application shown in Figure 7, it can be seen that:

[0062] In the prior art, due to the threshold voltage drift of transistors (e.g., the first transistor T1_i and the third transistor T3_i), node P_i cannot transition from a high level to a low level during the time period t3 after t2, causing transistor T14_i to remain on and generating a continuous pull-down current. Because transistor T14_i remains on, the level of node K_i fluctuates between medium and low levels, failing to maintain a stable high level. Simultaneously, because the level of node K_i cannot be stably maintained at a high level, the level of the gate drive signal output terminal Nout_i decreases to some extent when node K_i is at a medium level, affecting the output stability of the gate drive signal.

[0063] In Embodiment 2 of this application, a twenty-sixth transistor T26_i is added between the source and drain of the fourteenth transistor T14_i and node K_i. The turn-on and turn-off of the twenty-sixth transistor T26_i are controlled by a signal from the fourth clock signal input terminal XCK2, which is inverted by the signal from the first clock signal input terminal XCK1. This ensures that the critical transition voltage of the node between the source and drain of the fourteenth transistor T14_i and the source of the twenty-sixth transistor T26_i is 3-5 volts lower than the critical transition voltage of node K_i. Thus, even if the threshold voltage of the transistors (e.g., the first transistor T1_i and the third transistor T3_i) drifts, node K_i remains stably high during the time period t3 after t2. This allows node P_i to remain stably low, and the gate drive signal output terminal Nout_i to also remain stably low, effectively improving the operational stability of the gate drive circuit in high-temperature and high-humidity environments.

[0064] In the embodiments of this application, by periodically resetting and / or adding a twenty-sixth transistor T26_i, the stability of nodes K_i and P_i under the positive bias temperature stress of the semiconductor material is effectively improved, thereby enhancing the stability of the gate drive circuit in high-temperature and high-humidity environments. This enables the display device to operate normally in harsh environments with high temperature and high humidity, reducing display abnormalities caused by circuit instability and improving display quality and reliability.

[0065] And / or, through the coordination of the signal at the fourth clock signal input terminal XCK2 with the twenty-sixth transistor T26_i, the threshold voltage tolerance of the first transistor T1_i is improved by more than 3 volts, enhancing the circuit's tolerance to threshold voltage drift. This means that even when the threshold voltage of the semiconductor material drifts within a large range, the circuit can still maintain normal operation, reducing the risk of circuit failure caused by changes in material properties.

[0066] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, comprising: The display panel includes a gate driving circuit and multiple pixels. The gate driving circuit includes multiple cascaded gate driving sub-circuits. The i-th stage gate driving sub-circuit in the multiple gate driving sub-circuits includes at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module, and a second gate driving signal frequency division control module. The shift register module is electrically connected to the self-stabilizing module. The first gate driving signal frequency division control module and the second gate driving signal frequency division control module are both electrically connected to the shift register module and the self-stabilizing module. The self-stabilizing module includes at least: The first transistor has its gate electrically connected to node K_i, where node K_i is a node in the connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module. One of the source and drain of the first transistor is electrically connected to a first low-level signal input terminal, and the other of the source and drain of the first transistor is electrically connected to node P_i, where node P_i is a node in the connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module. The third transistor has its gate electrically connected to the node K_i, one of its source and drain electrically connected to the first high-level signal input terminal, and the other of its source and drain electrically connected to the node P_i. A fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to node P_i, one of the source and drain of the fourteenth transistor is electrically connected to a second low-level signal input terminal, and the other of the source and drain of the fourteenth transistor is electrically connected to node K_i; and The fifteenth transistor has its gate electrically connected to the control signal input terminal, one of its source and drain terminals electrically connected to the first high-level signal input terminal, and the other of its source and drain terminals electrically connected to the node K_i. The signal at the control signal input terminal is used to control the fifteenth transistor to write a high-level voltage to the node K_i during the blanking period of the driving cycle of each frame.

2. The display device according to claim 1, wherein, The control signal is at a low level during the blanking period of the driving cycle of each frame and at a high level during the non-blanking period of the driving cycle of each frame.

3. The display device according to claim 1, wherein, The duration of the low level of the control signal is less than or equal to the duration of the blanking period.

4. The display device according to claim 1, wherein, The proportion of the blanking period to the driving cycle of a frame is 10%-30%.

5. The display device according to claim 1, wherein, The on-resistance of the fifteenth transistor is less than the on-resistance of any one of the first transistor, the third transistor, and the fourteenth transistor.

6. The display device according to claim 1, wherein, The first transistor is an N-type dual-gate transistor, the third transistor is a P-type single-gate transistor, the fourteenth transistor is an N-type dual-gate transistor, and the fifteenth transistor is a P-type single-gate transistor.

7. The display device according to claim 1, wherein, The i-th stage gate driver sub-circuit further includes a first gate drive signal output module, a second gate drive signal output module, and a third gate drive signal output module. The first gate drive signal output module is electrically connected to the self-stabilizing module and the first gate drive signal frequency division control module. The second gate drive signal output module and the third gate drive signal output module are both electrically connected to the second gate drive signal frequency division control module and the self-stabilizing module.

8. A display device, comprising: The display panel includes a gate driving circuit and multiple pixels. The gate driving circuit includes multiple cascaded gate driving sub-circuits. The i-th stage gate driving sub-circuit in the multiple gate driving sub-circuits includes at least a shift register module, a self-stabilizing module, a first gate driving signal frequency division control module, and a second gate driving signal frequency division control module. The shift register module is electrically connected to the self-stabilizing module. The first gate driving signal frequency division control module and the second gate driving signal frequency division control module are both electrically connected to the shift register module and the self-stabilizing module. The self-stabilizing module includes at least: A first transistor, wherein one of its source and drain is electrically connected to a first low-level signal input terminal, and the gate of the first transistor is electrically connected to node K_i, wherein node K_i is a node of the connection line between the shift register module and the first gate drive signal frequency division control module and / or the second gate drive signal frequency division control module; the other of its source and drain is electrically connected to node P_i, wherein node P_i is a node of the connection line between the first gate drive signal frequency division control module and the second gate drive signal frequency division control module. The third transistor has its gate electrically connected to the node K_i, one of its source and drain electrically connected to the first high-level signal input terminal, and the other of its source and drain electrically connected to the node P_i. The fourteenth transistor, wherein the gate of the fourteenth transistor is electrically connected to the node P_i, and one of the source and drain of the fourteenth transistor is electrically connected to the second low-level signal input terminal; and The gate of the 26th transistor is electrically connected to the fourth clock signal input terminal, the source of the 26th transistor is electrically connected to the other of the source and drain of the 14th transistor, and the drain of the 26th transistor is electrically connected to the node K_i. The shift register module includes at least: The second transistor has its gate electrically connected to the first clock signal input terminal, one of the source and drain of the second transistor electrically connected to the first high-level signal input terminal, and the other of the source and drain of the second transistor electrically connected to the node K_i. The signal at the fourth clock signal input terminal is out of phase with the signal at the first clock signal input terminal.

9. The display device according to claim 8, wherein, The first transistor, the fourteenth transistor, and the twenty-sixth transistor are all N-type transistors.

10. The display device according to claim 8, wherein, The first transistor, the fourteenth transistor, and the twenty-sixth transistor are all dual-gate transistors.

11. The display device according to claim 8, wherein, The i-th stage gate driver sub-circuit further includes: The third transistor has its gate electrically connected to the node K_i, one of its source and drain electrically connected to the first high-level signal input terminal, and the other of its source and drain electrically connected to the node P_i.

12. The display device according to claim 11, wherein, The inverter formed by the first transistor and the third transistor is used to invert the level signal of node K_i and output it to node P_i.

13. The display device according to claim 8, wherein, The critical switching voltage of the node between the source or drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3-5 volts lower than the critical switching voltage of node K_i.

14. The display device according to claim 8, wherein, The rising edge of the signal at the fourth clock signal input terminal is time-aligned with the falling edge of the signal at the first clock signal input terminal.

15. The display device according to claim 8, wherein, The duty cycle of the signal at the fourth clock signal input terminal is the same as the duty cycle of the signal at the first clock signal input terminal.

16. The display device according to claim 8, wherein, The first transistor, the fourteenth transistor, and the twenty-sixth transistor are IGZO transistors, and the second transistor and the third transistor are LTPS transistors.

17. The display device according to claim 8, wherein, The i-th stage gate driver sub-circuit further includes: A first gate drive signal output module is electrically connected to the self-stabilizing module and the first gate drive signal frequency division control module. A second gate drive signal output module, which is electrically connected to the second gate drive signal frequency division control module and the self-stabilizing module; and The third gate drive signal output module is electrically connected to the second gate drive signal frequency division control module and the self-stabilizing module.

18. The display device according to claim 8, wherein, The critical switching voltage of the node between the source or drain of the fourteenth transistor and the source of the twenty-sixth transistor is 3-5 volts lower than the critical switching voltage of node K_i.

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