Method for manufacturing ultra-deep photodiode CMOS image sensor

Abstract

Disclosed in the present invention is a method for manufacturing an ultra-deep photodiode CMOS image sensor. Two instances of N-type ion implantation are performed on the front surface and back surface of a P-type epitaxial layer by means of silicon wafer bonding and backside thinning, such that an ultra-deep photodiode having a depth exceeding 4 um can be formed, wherein light in a near-infrared band can be absorbed by the ultra-deep photodiode to generate photon-generated carriers, thus improving the quantum conversion efficiency of a CMOS image sensor. In addition, an ultra-deep isolation area is formed by means of performing two instances of P-type ion implantation on the front surface and back surface of the P-type epitaxial layer, and thus the crosstalk effect of the photodiode can be effectively alleviated.

Description

Manufacturing method of ultra-deep photodiode CMOS image sensor Technical Field

[0001] This invention relates to CMOS image sensor (CIS) manufacturing technology, and particularly to a method for manufacturing an ultra-deep photodiode CMOS image sensor. Background Technology

[0002] A CMOS image sensor (CIS) consists of pixel unit circuits and CMOS circuitry. The pixel unit circuits are located in the pixel area, while the CMOS circuitry, consisting of logic circuitry, is located in the logic area. Compared to CCD image sensors, CMOS image sensors, due to their use of standard CMOS manufacturing processes, offer better integrability. They can be integrated with other analog-to-digital converters and control circuits on the same chip, making them more adaptable to future developments. Based on the number of transistors in the pixel unit circuits of existing CMOS image sensors, they are mainly classified into 3T and 4T structures.

[0003] Figure 1 shows the equivalent circuit diagram of a typical 3T CMOS image sensor pixel unit circuit, which includes a photodiode (PD) D1 and a CMOS pixel readout circuit. The CMOS pixel readout circuit is a 3T pixel circuit, including a reset transistor M1, a source follower transistor (SF) M2, and a select transistor (SG) M3, all of which are NMOS transistors. The N-type region of the photodiode D1 is connected to the source of the reset transistor M1. The gate of the reset transistor M1 is connected to a reset signal Reset, which is a potential pulse. When the reset signal Reset is high, the reset transistor M1 conducts and absorbs electrons from the photodiode D1 into the power supply Vdd of the readout circuit to achieve a reset. When light shines on the photodiode D1, photogenerated electrons are generated, increasing its potential. The signal is then amplified and output as an electrical signal. The gate of the select transistor M3 is connected to a horizontal selection signal Rs, used to select the amplified electrical signal as the output signal Vout.

[0004] Figure 2 shows the equivalent circuit diagram of a typical pixel unit circuit of a 4T CMOS image sensor. The difference between the structure shown in Figure 1 and the structure shown in Figure 2 is the addition of a transfer transistor, or transmission transistor M4. The source region of the transfer transistor M4 is the N-type region connected to the photodiode D1, and the drain region of the transfer transistor M4 is a floating diffusion (FD) region. The gate of the transfer transistor M4 is connected to the transmission control signal Tx. After the photodiode D1 generates photoelectrons, they are transferred to the floating diffusion region through the transfer transistor M4, and then connected to the gate of the source follower (SF) transistor M2 through the floating diffusion region to amplify the signal.

[0005] Due to limitations in ion implantation depth and concentration, the photodiodes of traditional CIS devices, as shown in Figure 3, have a shallow depth (less than 3 μm), while the absorption length of near-infrared light (wavelength > 700 nm) is much greater than 3 μm. When light passes through the photodiode, photogenerated carriers recombine or diffuse and cannot be collected, resulting in extremely low quantum absorption efficiency of the photodiode for near-infrared light and easy crosstalk. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a method for manufacturing an ultra-deep photodiode CMOS image sensor, which can form an ultra-deep photodiode with a depth of more than 4 μm, improve the quantum conversion efficiency of the CMOS image sensor, and effectively reduce the crosstalk effect of the photodiode.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an ultra-deep photodiode image sensor, which includes the following steps:

[0008] S1. A P-type epitaxial layer 101 is grown on a P-type silicon substrate 100;

[0009] S2. By photolithography and ion implantation, N-type ions are implanted from the front side of the P-type epitaxial layer 101 into the P-type epitaxial layer 101 to form a plurality of first-segment N-type doped regions;

[0010] S3. P-type ions are implanted from the front side of the P-type epitaxial layer 101 using photolithography and ion implantation methods, and a first P-type isolation region is formed between each of the first N-type doped regions.

[0011] S4. P-type ions are implanted on the front surface of the P-type epitaxial layer 101 by photolithography and ion implantation to form a front surface P-type doped region 102.

[0012] S5. A layer of front-side bonded silicon oxide 103 is deposited on the front side of the P-type epitaxial layer 101 using chemical vapor deposition.

[0013] S6. After flipping the silicon wafer, it is bonded to the front-side carrier 104 through the front-side bonding silicon oxide 103;

[0014] S7. The silicon wafer is thinned by a back-side thinning process, thereby reducing the thickness of the remaining P-type epitaxial layer 101;

[0015] S8. Corresponding to multiple first-segment N-type doped regions, N-type ions are implanted from the back side of the P-type epitaxial layer into the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first-segment N-type doped regions to form multiple ultra-deep N-type doped regions with uniform concentration and the same depth as the remaining P-type epitaxial layer 101.

[0016] Corresponding to the first P-type isolation region, P-type ions are implanted from the back side of the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first P-type isolation region to form an ultra-deep P-type isolation region with uniform concentration and the same depth as the remaining P-type epitaxial layer 101.

[0017] S9. By photolithography and ion implantation, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a back surface P-type doped region 105. The back surface P-type doped region 105 and the ultra-deep N-type doped region form an ultra-deep photodiode.

[0018] S10. Proceed with subsequent processes.

[0019] Preferably, step S10 includes:

[0020] S101. A CMOS device consisting of a MOS transport transistor and a logic region required for a CIS device is formed by photolithography and ion implantation.

[0021] Connecting the polysilicon process and the contact hole process to complete the front-end process;

[0022] S102. Connect to the subsequent process and complete the subsequent metal routing of the CIS device.

[0023] Preferably, in step S10, the following steps are performed after step S102:

[0024] S103. Deposit a back-side bonding oxide layer 106 on the top of the back side of the silicon wafer;

[0025] S104. After flipping the silicon wafer, it is bonded to the back substrate 107 through the back bonding oxide layer 106;

[0026] S105. Using the front-side bonded silicon oxide 103 as the thinning termination point, the silicon wafer is thinned through a front-side thinning process;

[0027] S106. Remove the front-bonded silicon oxide 103;

[0028] S107. Complete the BSI process for CIS devices;

[0029] S108. Complete the microlens process.

[0030] Preferably, in step S2, the cross-section of the first N-type doped region is circular, and multiple first N-type doped regions are uniformly distributed in a rectangular region.

[0031] Preferably, in step S2, the cross-section of the first N-type doped region is square, and multiple first N-type doped regions are uniformly distributed in a rectangular region.

[0032] Preferably, in step S1, the thickness of the grown P-type epitaxial layer 101 is 6-8 μm;

[0033] In step S2, the implantation depth of the first N-type doped region is 2–3 μm;

[0034] In step S3, the injection depth of the first P-type isolation region is 2-3 μm;

[0035] In step S4, the implantation depth of the front surface P-type doped region 102 is 50-150 nm, and the P doping concentration of the front surface P-type doped region 102 is greater than the P doping concentration of the P-type epitaxial layer 101.

[0036] In step S7, the thickness of the remaining P-type epitaxial layer 101 is reduced to 5-6 μm;

[0037] In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region.

[0038] P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region.

[0039] In step S9, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a P-type doped region 105 on the back surface, with an implantation depth of 0.2 to 0.3 μm.

[0040] Preferably, in step S1, the P-doping concentration of the P-type epitaxial layer 101 is 8E14 to 1E15;

[0041] In step S2, the N-doping concentration of the first N-type doped region is approximately 1E17 to 2E17;

[0042] In step S3, the P-doping concentration of the first P-type isolation region is approximately 1E17 to 2E17;

[0043] In step S4, the P doping concentration of the front surface P-type doped region 102 is 1E15 to 5E15.

[0044] In step S7, the thickness of the remaining P-type epitaxial layer 101 is reduced to 5-6 μm;

[0045] In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region.

[0046] P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region.

[0047] In step S9, the doping concentration of the P-type doped region 105 on the back surface is 1E17 to 2E17.

[0048] Preferably, in step S5, the thickness of the front-side bonded silicon oxide 103 is 1.5 μm to 2.5 μm.

[0049] Preferably, the front-end process includes at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, and furnace tube deposition;

[0050] The back-end process includes at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, and furnace tube deposition.

[0051] Preferably, in step S103, a back bonding oxide layer 106 with a thickness of 1.5 to 2.5 μm is deposited on the top of the back side of the silicon wafer using a chemical vapor deposition method.

[0052] In steps S7 and S105, the thinning method is grinding, wet etching, chemical mechanical polishing or TMAH wet etching.

[0053] In step S106, the front-side bonded silicon oxide 103 is removed by dry etching, wet etching or chemical mechanical polishing.

[0054] The manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention, through silicon wafer bonding and back-side thinning, performs two N-type ion implantations on the front and back sides of the P-type epitaxial layer, which can form an ultra-deep photodiode with a depth of more than 4 μm. Near-infrared light can be absorbed by the ultra-deep photodiode to generate photogenerated carriers, thereby improving the quantum conversion efficiency of the CMOS image sensor; and by performing two P-type ion implantations on the front and back sides of the P-type epitaxial layer to form an ultra-deep isolation region, the crosstalk effect of the photodiode can be effectively reduced. Attached Figure Description

[0055] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 is an equivalent circuit diagram of the pixel unit circuit of a typical 3T CMOS image sensor;

[0057] Figure 2 is an equivalent circuit diagram of the pixel unit circuit of a typical 4T CMOS image sensor;

[0058] Figure 3 is a schematic cross-sectional view of a conventional depth photodiode of a CIS device manufactured using traditional methods.

[0059] Figure 4 is a schematic cross-sectional view of the growth of a P-type epitaxial layer in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0060] Figure 5 is a schematic cross-sectional view of the first N-type doped region formed in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0061] Figure 6 is a schematic diagram of the formation of the first N-type doped region with a circular cross-section in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention;

[0062] Figure 7 is a schematic diagram of the formation of the first N-type doped region with a square cross-section in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention;

[0063] Figure 8 is a schematic cross-sectional view of the formation of the first P-type isolation region in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0064] Figure 9 is a schematic diagram of the first N-type doped region in a circular cross-section after forming the first P-type isolation region in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0065] Figure 10 is a schematic diagram of the first N-type doped region with a square cross-section after forming the first P-type isolation region in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0066] Figure 11 is a schematic cross-sectional view of the formation of the front surface P-type doped region in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0067] Figure 12 is a schematic cross-sectional view of the front-side bonded silicon oxide deposition in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0068] Figure 13 is a schematic cross-sectional view of the bonding between the front-side bonded silicon oxide and the front-side substrate in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0069] Figure 14 is a schematic cross-sectional view of the back side of a silicon wafer thinning method according to an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0070] Figure 15 is a schematic cross-sectional view of the formation of an ultra-deep P-type isolation region in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0071] Figure 16 is a schematic cross-sectional view of the front-end process of an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0072] Figure 17 is a schematic cross-sectional view of the back-side bonding oxide layer in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0073] Figure 18 is a schematic cross-sectional view of the bonding between the back-side bonded oxide layer and the back-side substrate in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0074] Figure 19 is a schematic cross-sectional view of the removal of front-side bonded silicon oxide in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0075] Figure 20 is a schematic cross-sectional view of the microlens process completed in an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention.

[0076] Figure 21 is a schematic cross-sectional view of the ultra-deep photodiode of the CIS device manufactured according to an embodiment of the manufacturing method of the ultra-deep photodiode CMOS image sensor of the present invention. Detailed Implementation

[0077] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "front," and "back" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0079] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. Example 1

[0080] A method for manufacturing an ultra-deep photodiode CMOS image sensor includes the following steps:

[0081] S1. A P-type epitaxial layer 101 is grown on a P-type silicon substrate (P Sub) 100, as shown in Figure 4;

[0082] S2. By photolithography and ion implantation, N-type ions are implanted from the front side of the P-type epitaxial layer 101 into the P-type epitaxial layer 101 to form multiple first-segment N-type doped regions, as shown in Figure 5.

[0083] S3. P-type ions are implanted from the front side of the P-type epitaxial layer 101 using photolithography and ion implantation, forming a first P-type isolation region between each of the first N-type doped regions, as shown in Figure 8.

[0084] S4. P-type ions are implanted on the front surface of the P-type epitaxial layer 101 by photolithography and ion implantation to form a front surface P-type doped region 102, as shown in Figure 11.

[0085] S5. A layer of front-side bonded silicon oxide 103 is deposited on the front side of the P-type epitaxial layer 101 using chemical vapor deposition, as shown in Figure 12;

[0086] S6. After flipping the silicon wafer, it is bonded to the front-side carrier wafer 104 through the front-side bonding silicon oxide 103, as shown in Figure 13;

[0087] S7. The silicon wafer is thinned by a back-side thinning process, so that the thickness of the remaining P-type epitaxial layer 101 is reduced, as shown in Figure 14;

[0088] S8. Corresponding to multiple first-segment N-type doped regions, N-type ions are implanted from the back side of the P-type epitaxial layer into the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first-segment N-type doped regions to form multiple ultra-deep N-type doped regions with uniform concentration and the same depth as the remaining P-type epitaxial layer 101.

[0089] Corresponding to the first P-type isolation region, P-type ions are implanted from the back side of the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first P-type isolation region to form an ultra-deep P-type isolation region with uniform concentration and the same depth as the remaining P-type epitaxial layer 101, as shown in Figure 15.

[0090] S9. By photolithography and ion implantation, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a back surface P-type doped region 105. The back surface P-type doped region 105 and the ultra-deep N-type doped region form an ultra-deep photodiode.

[0091] S10. Proceed with subsequent processes.

[0092] The fabrication method of the ultra-deep photodiode CMOS image sensor in Example 1 involves silicon wafer bonding and back-side thinning. Two N-type ion implantations are performed on the front and back sides of the P-type epitaxial layer, forming an ultra-deep photodiode with a depth exceeding 4 μm, as shown in Figure 21. Near-infrared light can be absorbed by the ultra-deep photodiode to generate photogenerated carriers, improving the quantum conversion efficiency of the CMOS image sensor. Furthermore, by performing two P-type ion implantations on the front and back sides of the P-type epitaxial layer to form an ultra-deep isolation region, the crosstalk effect of the photodiode can be effectively reduced. Example 2

[0093] The manufacturing method of the ultra-deep photodiode CMOS image sensor based on Embodiment 1 includes step S10 as follows:

[0094] S101. A CMOS device consisting of a MOS transport transistor and a logic region required for a CIS device is formed by photolithography and ion implantation.

[0095] Connecting the polysilicon process and the contact hole process (Poly to CT loop), the front-end process is completed (specific processes include at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, furnace tube deposition, etc.), as shown in Figure 16;

[0096] S102. Connect the back-end processes (specific processes include at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, furnace tube deposition, etc.) to complete the back-end metal routing of the CIS device.

[0097] Preferably, in step S10, the following steps are performed after step S102:

[0098] S103. Deposit a back bonding oxide layer 106 on the top of the back side of the silicon wafer, as shown in Figure 17;

[0099] S104. After flipping the silicon wafer, it is bonded to the back carrier wafer 107 through the back bonding oxide layer 106, as shown in FIG18;

[0100] S105. Using the front-side bonded silicon oxide 103 as the thinning termination point, the silicon wafer is thinned through a front-side thinning process;

[0101] S106. Remove the front-side bonded silicon oxide 103, as shown in Figure 19;

[0102] S107. Complete the BSI (back-illuminated) process for CIS devices. The BSI (back-illuminated) process includes BDTI (back-side deep trench isolation), BSST, BVIA, BMET, BMG, BPADO and other process steps.

[0103] S108. Complete the microlens process, as shown in Figure 20. Example 3

[0104] In the manufacturing method of the ultra-deep photodiode CMOS image sensor based on Embodiment 1 or 2, the thickness of the grown P-type epitaxial layer 101 in step S1 is 6-8 μm.

[0105] In step S2, the implantation depth of the first N-type doped region is 2–3 μm;

[0106] In step S3, the injection depth of the first P-type isolation region is 2-3 μm;

[0107] In step S4, the implantation depth of the front surface P-type doped region 102 is 50-150 nm, and the P doping concentration of the front surface P-type doped region 102 is greater than the P doping concentration of the P-type epitaxial layer 101.

[0108] In step S7, the thickness of the remaining P-type epitaxial layer 101 is reduced to 5-6 μm;

[0109] In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region.

[0110] P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region.

[0111] In step S9, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a P-type doped region 105 on the back surface, with an implantation depth of 0.2 to 0.3 μm.

[0112] Preferably, in step S1, the P-doping concentration of the P-type epitaxial layer 101 is 8E14 to 1E15;

[0113] In step S2, the N-doping concentration of the first N-type doped region is approximately 1E17 to 2E17;

[0114] In step S3, the P-doping concentration of the first P-type isolation region is approximately 1E17 to 2E17;

[0115] In step S4, the P doping concentration of the front surface P-type doped region 102 is 1E15 to 5E15.

[0116] In step S7, the thickness of the remaining P-type epitaxial layer 101 is reduced to 5-6 μm;

[0117] In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region.

[0118] P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region.

[0119] In step S9, the doping concentration of the P-type doped region 105 on the back surface is 1E17 to 2E17.

[0120] Preferably, in step S5, the thickness of the front-side bonded silicon oxide 103 is 1.5 μm to 2.5 μm.

[0121] Preferably, in step S103, a back bonding oxide layer 106 with a thickness of 1.5 to 2.5 μm (about 2 μm) is deposited on the top of the back side of the silicon wafer using a chemical vapor deposition method.

[0122] Preferably, in steps S7 and S105, the thinning method is grinding, wet etching, chemical mechanical polishing, or TMAH (tetramethylammonium hydroxide) wet etching.

[0123] Preferably, in step S106, the front-side bonded silicon oxide 103 is removed by a process such as dry etching, wet etching, or chemical mechanical polishing. Example 4

[0124] In the manufacturing method of the ultra-deep photodiode CMOS image sensor based on Embodiment 1 or 2, in step S2, the cross-section of the first N-type doped region is circular, and multiple first N-type doped regions are uniformly distributed in a rectangular area, as shown in Figure 6.

[0125] In step S4, a first P-type isolation region is formed between each of the first N-type doped regions, as shown in Figure 9. Example 5

[0126] The manufacturing method of the ultra-deep photodiode CMOS image sensor based on Embodiment 1 or 2 has a square cross-section for the first N-type doped region, and multiple first N-type doped regions are uniformly distributed in a rectangular area, as shown in Figure 7.

[0127] In step S4, a first P-type isolation region is formed between each of the first N-type doped regions, as shown in Figure 10.

[0128] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for manufacturing an ultra-deep photodiode CMOS image sensor, characterized in that, Includes the following steps: S1. A P-type epitaxial layer (101) is grown on a P-type silicon substrate (100); S2. By means of photolithography and ion implantation, N-type ions are implanted from the front side of the P-type epitaxial layer (101) into the P-type epitaxial layer (101) to form a plurality of first-segment N-type doped regions; S3. P-type ions are implanted from the front of the P-type epitaxial layer (101) using photolithography and ion implantation methods, and a first P-type isolation region is formed between each of the first N-type doped regions. S4. P-type ions are implanted on the front surface of the P-type epitaxial layer (101) by photolithography and ion implantation to form a front surface P-type doped region (102). S5. A layer of front-bonded silicon oxide (103) is deposited on the front side of the P-type epitaxial layer (101) using chemical vapor deposition. S6. After flipping the silicon wafer, it is bonded to the front-side carrier (104) through the front-side bonded silicon oxide (103); S7. The silicon wafer is thinned by a back-side thinning process, thereby reducing the thickness of the remaining P-type epitaxial layer (101); S8. Corresponding to multiple first-segment N-type doped regions, N-type ions are implanted from the back side of the P-type epitaxial layer into the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first-segment N-type doped regions to form multiple ultra-deep N-type doped regions with uniform concentration and the same depth as the remaining P-type epitaxial layer (101). Corresponding to the first P-type isolation region, P-type ions are implanted from the back side of the P-type epitaxial layer through photolithography and ion implantation processes, overlapping and connecting with the first P-type isolation region to form an ultra-deep P-type isolation region with uniform concentration and the same depth as the remaining P-type epitaxial layer (101). S9. By means of photolithography and ion implantation, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a back surface P-type doped region (105). The back surface P-type doped region (105) and the ultra-deep N-type doped region form an ultra-deep photodiode. S10. Proceed with subsequent processes.

2. The manufacturing method of the ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, Step S10 includes: S101. A CMOS device consisting of a MOS transport transistor and a logic region required for a CIS device is formed by photolithography and ion implantation. Connecting the polysilicon process and the contact hole process to complete the front-end process; S102. Connect to the subsequent process and complete the subsequent metal routing of the CIS device.

3. The manufacturing method of the ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, In step S10, the following steps are performed after step S102: S103. Deposit a back-side bonding oxide layer on the top of the back side of the silicon wafer (106). S104. After flipping the silicon wafer, it is bonded to the back substrate (107) through the back bonding oxide layer (106); S105. Using the front-side bonded silicon oxide (103) as the thinning termination point, the silicon wafer is thinned through a front-side thinning process; S106. Remove the front-side bonded silicon oxide (103); S107. Complete the BSI process for CIS devices; S108. Complete the microlens process.

4. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, In step S2, the cross-section of the first N-type doped region is circular, and multiple first N-type doped regions are uniformly distributed in a rectangular area.

5. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, In step S2, the cross-section of the first N-type doped region is square, and multiple first N-type doped regions are evenly distributed in a rectangular area.

6. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, In step S1, the thickness of the grown P-type epitaxial layer (101) is 6-8 μm; In step S2, the implantation depth of the first N-type doped region is 2–3 μm; In step S3, the injection depth of the first P-type isolation region is 2-3 μm; In step S4, the implantation depth of the front surface P-type doped region (102) is 50-150 nm, and the P doping concentration of the front surface P-type doped region (102) is greater than the P doping concentration of the P-type epitaxial layer (101). In step S7, the thickness of the remaining P-type epitaxial layer (101) is reduced to 5-6 μm; In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region. P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region. In step S9, P-type ions are implanted on the back side of the P-type epitaxial layer in the pixel area to form a P-type doped region (105) on the back surface, with an implantation depth of 0.2 to 0.3 μm.

7. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 6, characterized in that, In step S1, the P-doping concentration of the P-type epitaxial layer (101) is 8E14 to 1E15; In step S2, the N-doping concentration of the first N-type doped region is approximately 1E17 to 2E17; In step S3, the P-doping concentration of the first P-type isolation region is approximately 1E17 to 2E17; In step S4, the P doping concentration of the front surface P-type doped region (102) is 1E15 to 5E15; In step S7, the thickness of the remaining P-type epitaxial layer (101) is reduced to 5-6 μm; In step S8, N-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, and the doping concentration is the same as that of the first N-type doped region. P-type ions are implanted into the P-type epitaxial layer from the back side of the P-type epitaxial layer to a depth of 2.5–3 μm, with the doping concentration being the same as that of the first P-type isolation region. In step S9, the doping concentration of the P-type doped region (105) on the back surface is 1E17 to 2E17.

8. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 1, characterized in that, In step S5, the thickness of the front-side bonded silicon oxide (103) is 1.5um to 2.5um.

9. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 2, characterized in that, The front-end process includes at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, and furnace tube deposition. The back-end process includes at least one of photolithography, dry etching, wet etching, physical vapor deposition, chemical vapor deposition, and furnace tube deposition.

10. The method for manufacturing an ultra-deep photodiode CMOS image sensor according to claim 3, characterized in that, In step S103, a back bonding oxide layer with a thickness of 1.5 to 2.5 μm is deposited on the top of the back side of the silicon wafer using chemical vapor deposition (106). In steps S7 and S105, the thinning method is grinding, wet etching, chemical mechanical polishing or TMAH wet etching. In step S106, the front-side bonded silicon oxide (103) is removed by dry etching, wet etching or chemical mechanical polishing.

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