Field effect transistor, chip, and electronic device

Abstract

The present application relates to the technical field of semiconductors. Disclosed are a field effect transistor, a chip and an electronic device. The field effect transistor comprises a substrate, a first metal electrode, a second metal electrode, a third metal electrode, and a gate electrode stacked on the substrate, wherein the substrate comprises a drift region, and a source region and a drain region that are located in the drift region. The source region is coupled to the first metal electrode; the drain region is coupled to the second metal electrode; the source region comprises a plurality of source sub-regions arranged at intervals in the extension direction of the source region, and a portion of the drift region between any two adjacent source sub-regions is electrically connected to the third metal electrode, so as to form a Schottky diode, thereby improving reverse recovery characteristics. The substrate further comprises a plurality of first doped regions located in the drift region, wherein the conductivity type of doping elements in each first doped region is different from the conductivity type of doping elements in the drift region, and each first doped region is located, in the extension direction of the source region, between a source sub-region and a portion of the drift region electrically connected to the third metal electrode, so as to alleviate off-state leakage.

Description

Field-effect transistors, chips and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510295009.8, filed on March 12, 2025, entitled "Field-Effect Transistor, Chip and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a field-effect transistor, a chip, and an electronic device. Background Technology

[0003] With the development of science and technology, semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs, or "MOS transistors") are being used more and more widely.

[0004] The substrate of a MOSFET can include multiple drift regions and multiple body regions arranged alternately along the length of the MOSFET. A PN junction is formed between the drift regions and the body regions, thus the body diode of the MOSFET is a PN junction diode. When the PN junction diode is in the forward conduction state, holes in the P region diffuse into the N region, and electrons in the N region diffuse into the P region, resulting in the accumulation of electrons in the P region and holes in the N region. When the PN junction diode is in the reverse blocking state, both the electrons stored in the P region and the holes stored in the N region need to be recovered in the reverse direction; that is, the electrons stored in the P region need to return to the N region, and the holes stored in the N region need to return to the P region. Therefore, the reverse recovery charge (Qrr) of the PN junction diode is relatively large, and the reverse recovery characteristic is poor, meaning that the transition time from the forward conduction state to the reverse blocking state of the PN junction diode is long.

[0005] Therefore, reverse recovery characteristics can be improved by constructing a Schottky diode within the MOSFET. Specifically, the drift region of the MOSFET has an overall comb-like structure with extended drift regions that extend into the body region and are electrically connected to the metal electrode, thus constructing a Schottky diode. Schottky diodes have very little reverse recovery charge, which can improve reverse recovery characteristics. However, due to limitations in the molding process, the area of ​​the extended drift region is difficult to make small enough, resulting in more carriers migrating from the extended drift region to the metal electrode when the Schottky diode is reverse biased, forming a large leakage current, ultimately leading to a large off-state leakage current. Currently, MOSFETs can only deplete the N-type extended drift region through the P-type body region, which has limited depletion capability and is not conducive to improving the off-state leakage current problem. Summary of the Invention

[0006] Some embodiments of this application provide a field-effect transistor, chip, and electronic device that can improve reverse recovery characteristics and off-state leakage current problems.

[0007] In a first aspect, embodiments of this application provide a field-effect transistor (FET), which includes a substrate, a first metal electrode, a second metal electrode, a third metal electrode, and a gate. The gate is stacked on the substrate, which includes a source region, a drain region, and a drift region. The source and drain regions are located within the drift region. The source region is coupled to the first metal electrode, and the drain region is coupled to the second metal electrode. The source region includes multiple sub-source regions, which are spaced apart along the direction extending from the source region itself. A portion of the drift region between any two adjacent sub-source regions is electrically connected to the third metal electrode. The substrate also includes multiple first doped regions located within the drift region. The type of dopant element in each first doped region is different from the type of dopant element in the drift region. Each first doped region is located between a portion of the drift region electrically connected to the third metal electrode and a sub-source region along the direction extending from the source region itself.

[0008] The aforementioned field-effect transistor, on the one hand, forms a Schottky diode by creating a Schottky contact between a portion of the drift region between any two adjacent sub-source regions and the third metal electrode. Schottky diodes are unipolar devices with minimal reverse recovery charge, effectively improving the reverse recovery characteristics of the field-effect transistor. On the other hand, the first doped region can deplete the portion of the drift region between any two adjacent sub-source regions, further enhancing the depletion capability and effectively improving off-state leakage current. Furthermore, the portion of the drift region between any two adjacent sub-source regions is exposed to the outside through the gap between two adjacent first doped regions. Therefore, by controlling the size of the gap between the two first doped regions, the area of ​​the portion of the drift region between any two adjacent sub-source regions can be effectively controlled, allowing it to be set as small as possible, further improving off-state leakage current.

[0009] In some possible implementations of the first aspect described above, each sub-source region includes a first portion and a second portion, which are spaced apart along a direction perpendicular to the direction in which the source region extends. The substrate also includes a plurality of second doped regions located within a drift region. The type of dopant element in each second doped region is the same as the type of dopant element in the first doped region, and each second doped region is located between the first portion and the second portion of a sub-source region.

[0010] The aforementioned second doped region helps suppress the latch-up effect of the field-effect transistor. Furthermore, by placing the second doped region between the first and second portions of the sub-source region, the layout space of the field-effect transistor can be effectively saved, which helps to achieve the miniaturization design of the field-effect transistor.

[0011] In some possible implementations of the first aspect described above, each second doped region is connected to an adjacent first doped region. In this way, the second doped region can also deplete a portion of the drift region between any two adjacent sub-source regions, thereby further enhancing the depletion effect on that portion of the drift region and helping to improve off-state leakage current.

[0012] In some possible implementations of the first aspect mentioned above, the first doped region is a heavily doped region to enhance the depletion capability of the first doped region for the partial drift region between any two adjacent sub-source regions, thereby further improving the off-state leakage current.

[0013] In some possible implementations of the first aspect described above, the substrate further includes a plurality of first body regions located within the drift region, each sub-source region located within each first body region, and each first body region located between two adjacent drift regions electrically connected to the third metal electrode in the direction extending from the source region itself.

[0014] In the aforementioned field-effect transistor, both the first doped region and the first body region can deplete a portion of the drift region between any two adjacent sub-source regions, thereby further improving the off-state leakage problem.

[0015] In some possible implementations of the first aspect described above, the field-effect transistor includes a fourth metal electrode. The substrate also includes a plurality of third doped regions located within a drift region and between two adjacent drain regions. The type of dopant element in each third doped region is the same as the type of dopant element in the first doped region. The plurality of third doped regions are spaced apart along the direction extending from the drain region itself, and a portion of the drift region between any two adjacent third doped regions is electrically connected to the fourth metal electrode.

[0016] The aforementioned field-effect transistor, on the one hand, can effectively improve its reverse recovery characteristics by electrically connecting a portion of the drift region between any two adjacent third doped regions to a fourth metal electrode to construct a second Schottky diode. On the other hand, the third doped region can deplete a portion of the drift region between any two adjacent third doped regions, thereby further enhancing the depletion capability of the drift region between any two adjacent third doped regions, and thus effectively improving off-state leakage current. Furthermore, since the portion of the drift region used to form the second Schottky diode is exposed to the outside through the gap between two adjacent third doped regions, the area size of the portion of the drift region used to form the second Schottky diode can be effectively controlled by controlling the size of the gap between two adjacent third doped regions. This allows the portion of the drift region used to form the second Schottky diode to be set as small as possible, which helps to further improve off-state leakage current.

[0017] In some possible implementations of the first aspect described above, the substrate further includes a plurality of second body regions located within the drift region, each third doped region located within each second body region, and each second body region located between two adjacent portions of the drift region electrically connected to the fourth metal electrode in the direction extending along the drain region itself.

[0018] In the aforementioned field-effect transistor, both the third doped region and the second body region can deplete a portion of the drift region between any two adjacent third doped regions, thereby further improving the off-state leakage problem.

[0019] Secondly, embodiments of this application provide a field-effect transistor (FET), which includes a substrate, a first metal electrode, a second metal electrode, a third metal electrode, and a gate. The gate is stacked on the substrate, which includes a source region, a drain region, and a drift region. The source and drain regions are located within the drift region. The source region is coupled to the first metal electrode, and the drain region is coupled to the second metal electrode. The substrate also includes multiple doped regions located within the drift region and between two adjacent drain regions. The type of dopant element in each doped region differs from the type of dopant element in the drift region. The multiple doped regions are arranged at intervals along the direction extending from the drain region itself, and a portion of the drift region between any two adjacent doped regions is electrically connected to the third metal electrode.

[0020] In some possible implementations of the second aspect mentioned above, the doped region is a heavily doped region.

[0021] In some possible implementations of the second aspect described above, the substrate further includes a plurality of body regions located within the drift region, each doped region located within the body region, and each body region located between two adjacent portions of the drift region electrically connected to the third metal electrode in the direction extending along the drain region itself.

[0022] Thirdly, embodiments of this application provide a chip, the chip including the field-effect transistors of the first aspect, any possible implementation of the first aspect, the second aspect, and any possible implementation of the second aspect.

[0023] Fourthly, embodiments of this application provide an electronic device, which includes a circuit board and the chip provided in the third aspect above, the chip being disposed on the circuit board.

[0024] It should be understood that the beneficial effects of the second to fourth aspects mentioned above can be referred to the beneficial effects of the first aspect mentioned above, and the beneficial effects of the possible implementations of the second aspect mentioned above can be referred to the beneficial effects of the possible implementations of the first aspect mentioned above, which will not be elaborated here. Attached Figure Description

[0025] Figure 1 shows an exemplary block diagram of the power supply in an embodiment of this application;

[0026] Figure 2 shows an exemplary circuit diagram of the step-down circuit in an embodiment of this application;

[0027] Figure 3A shows a schematic diagram of the planar structure of the integrated layout of MOSFETs in some technical solutions;

[0028] Figure 3B shows a schematic cross-sectional view of the MOSFET in some technical solutions, as shown in section AA of Figure 3A.

[0029] Figure 3C shows a schematic diagram of the planar structure of a single cell in a MOS transistor in some technical solutions, based on Figure 3A.

[0030] Figure 4A shows a schematic diagram of the planar structure of a MOS transistor in some other technical solutions;

[0031] Figure 4B shows a schematic cross-sectional view of the MOSFET in the BB section of Figure 4A in some other technical solutions;

[0032] Figure 4C shows a schematic cross-sectional view of the MOSFET in the CC section of Figure 4A in some other technical solutions;

[0033] Figure 4D shows a schematic diagram of the planar structure of a single cell in a MOS transistor in some other technical solutions, based on Figure 4A.

[0034] Figure 5A shows a schematic diagram of the planar structure of the MOS transistor in an embodiment of this application;

[0035] Figure 5B shows a schematic cross-sectional view of the MOS transistor in the EE section of Figure 5A in an embodiment of this application;

[0036] Figure 6A shows a planar structural schematic diagram of the first source structure in the MOS transistor according to Figures 5A and 5B in an embodiment of this application.

[0037] Figure 6B shows a schematic cross-sectional view of the first source structure in the MOS transistor in the embodiment of this application, as shown in the FF section of Figure 6A.

[0038] Figure 6C shows a schematic cross-sectional view of the first source structure in the MOS transistor in an embodiment of this application, as shown in the HH section of Figure 6A.

[0039] Figure 6D shows a schematic cross-sectional view of the first source structure in the MOS transistor in an embodiment of this application, as shown in section II of Figure 6A.

[0040] Figure 6E shows a schematic cross-sectional view of the first source structure in the MOS transistor in an embodiment of this application, as shown in the JJ section of Figure 6A.

[0041] Figure 7A shows a second schematic diagram of the planar structure of the MOS transistor in an embodiment of this application;

[0042] Figure 7B shows a schematic cross-sectional view of the MOS transistor in the KK section of Figure 7A in an embodiment of this application;

[0043] Figure 8A shows a schematic planar structure of the second source structure in the MOS transistor according to Figures 7A and 7B in an embodiment of this application.

[0044] Figure 8B shows a schematic cross-sectional view of the second source structure in the MOS transistor in the embodiment of this application, as shown in the LL section of Figure 8A.

[0045] Figure 8C shows a schematic cross-sectional view of the second source structure in the MOS transistor in the embodiment of this application, as shown in the MM section of Figure 8A.

[0046] Figure 8D shows a schematic cross-sectional view of the second source structure in the MOS transistor in the embodiment of this application, as shown in the OO section of Figure 8A.

[0047] Figure 9A shows a schematic diagram of the planar structure of the MOS transistor in an embodiment of this application;

[0048] Figure 9B shows a schematic cross-sectional view of the MOS transistor in the RR section of Figure 9A in an embodiment of this application;

[0049] Figure 10A shows a schematic diagram of the planar structure of the MOS transistor in an embodiment of this application;

[0050] Figure 10B shows a schematic cross-sectional view of the MOS transistor in the TT section of Figure 10A in an embodiment of this application;

[0051] Figure 10C shows a schematic cross-sectional view of the MOS transistor in the UU section of Figure 10A in an embodiment of this application;

[0052] Figure 11 shows a schematic diagram of the planar structure of the MOS transistor in an embodiment of this application. Detailed Implementation

[0053] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0054] This application provides a MOSFET, also known as a "field-effect transistor," which will be used as an example for description purposes. The MOSFET provided in this application is a laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor, which can be integrated into a chip, and the chip can be used in electronic devices. It is understood that the electronic device provided in this application can be any of the following: a primary power supply, a secondary power supply, a tertiary power supply, a mobile phone, a tablet computer, a laptop computer, a wearable device, a netbook, an ultra-mobile personal computer (UMPC), a personal digital assistant (PDA), or any other electronic device with a MOSFET. For ease of description, this solution will be described below using a tertiary power supply as an example.

[0055] Figure 1 shows an exemplary block diagram of the power supply 1000 in an embodiment of this application. Referring to Figure 1, the power supply 1000 may include a power input module 1, a control module 2, a power module 3, and a power output module 4. The power input module 1 is used to receive an input voltage signal. The control module 2 is used to control the power module 3 to convert the input voltage signal into a voltage signal required by the load 2000. The power output module 4 is used to process the converted voltage signal, for example, by filtering, and provide the processed voltage signal to the load 2000 to supply power to the load 2000 and meet the power requirements of the load 2000.

[0056] For example, in some implementations, the load 2000 can be an artificial intelligence (AI) chip. When the load 2000 is an AI chip, the power input module 1 can receive a 12V DC voltage signal from the secondary power supply and perform preliminary processing on the voltage signal, such as filtering. Then, the control module 2 can control the power module 3 to step down the 12V DC voltage signal to reduce it to the 1V voltage signal required by the AI ​​chip. Finally, the power output module 4 processes the converted DC voltage signal, such as filtering, local voltage regulation, and impedance matching, and provides the processed voltage signal to the AI ​​chip. In addition, when the load of the AI ​​chip changes abruptly, for example, from idle to full load calculation, the control module 2 can also adjust the switching frequency or duty cycle in the power module 3 to ensure the stability of the output voltage.

[0057] For example, in some other implementations, the load 2000 can also be an RF power amplifier. When the load 2000 is an RF power amplifier, the power input module 1 can receive a 12V DC voltage signal from the secondary power supply and perform preliminary processing on the voltage signal, such as filtering. Then, the control module 2 can control the power module 3 to boost the 12V DC voltage signal to the 28V voltage signal required by the RF power amplifier. Finally, the power output module 4 processes the converted DC voltage signal, such as filtering, local voltage regulation, impedance matching, etc., and provides the processed voltage signal to the RF power amplifier.

[0058] For example, in some implementations, the load 2000 can also be a central processing unit (CPU). When the load 2000 is a CPU, the power input module 1 can receive a 220V AC voltage signal and perform preliminary processing on the voltage signal, such as filtering. Then, the control module 2 can control the power module 3 to convert the 220V AC voltage to a 220V DC voltage and perform step-down processing on the 220V DC voltage to reduce it to the 3.3V DC voltage signal required by the CPU. Finally, the power output module 4 processes the converted DC voltage signal, such as filtering, local voltage regulation, impedance matching, etc., and provides the processed voltage signal to the CPU.

[0059] It should be noted that the above only illustrates a partial implementation of the load 2000 and the corresponding operating mode of the power supply 1000, and does not constitute a limitation on this application. In other embodiments, the load 2000 may be, for example, a graphics processing unit (GPU), a microcontroller unit (MCU), or a system-on-chip (SoC), etc., and this application does not impose specific limitations on it. Furthermore, depending on the type of load 2000, the power supply 1000 may have different operating modes, such as DC / AC conversion, boost / buck conversion, etc., and this application does not impose specific limitations on it.

[0060] In the aforementioned power supply 1000, each circuit of the power module 3 may include a MOSFET to achieve different functions. The MOSFET can be mounted on a circuit board; for example, the MOSFET and MOSFET driver can be integrated on the same circuit board (referred to as "driver MOS (drMOS)"). The MOSFET driver provides voltage to the MOSFET to drive it to operate.

[0061] The following section uses the step-down circuit (or "BUCK circuit") in power module 3 to illustrate the exemplary operation of the MOSFET.

[0062] Figure 2 shows an exemplary circuit diagram of the buck circuit 30 in an embodiment of this application. Referring to Figure 2, the buck circuit 30 is used to implement direct current (DC-DC) step-down conversion to meet the power supply requirements of the load.

[0063] Specifically, the step-down circuit 30 may include multiple capacitors, multiple MOSFETs, and at least one inductor. The multiple capacitors include a first capacitor C1 and a second capacitor C2. The multiple MOSFETs include a first MOSFET Q1 and a second MOSFET Q2. The at least one inductor is inductor L1. The first capacitor C1, the first MOSFET Q1, the inductor L1, and the second capacitor C2 are connected sequentially to form a closed loop. One end of the second MOSFET Q2 is connected between the first capacitor C1 and the second capacitor C2, and the other end of the second MOSFET is connected between the first MOSFET and the inductor L1. The load Rload is connected in parallel with the second capacitor C2.

[0064] In this circuit, the first capacitor C1 is the input capacitor, used for filtering to stabilize the input voltage. The second capacitor C2 is the output capacitor, used for energy storage and filtering. The first MOSFET Q1 and the second MOSFET Q2 are used to periodically turn on and off to control the energy storage and release of the second capacitor C2 and the inductor L1, thereby regulating the output voltage.

[0065] For example, when the first MOSFET Q1 is turned on and the second MOSFET Q2 is turned off, i Q1 Increase, i Q2 When the voltage at terminal SW is 0, the voltage at terminal SW is the input voltage VIN. The input voltage VIN charges inductor L1, thereby increasing the current in inductor L1. The current in inductor L1 forms a loop along the dashed path, thus supplying power to the load Rload. At the same time, the input voltage VIN also charges the second capacitor C2.

[0066] When the first MOSFET Q1 is off and the second MOSFET Q2 is on, i Q1 i is 0 Q2 The current in inductor L1 decreases. Since the current in inductor L1 cannot change abruptly, the current in inductor L1 forms a loop along the dotted line path. At this time, the current in inductor L1 decreases linearly, and the stored energy is released through inductor L1 and the second capacitor C2 to supply power to the load Rload.

[0067] By controlling the on and off states of the first MOSFET Q1 and the second MOSFET Q2, the storage and release of energy in the inductor L1 and the second capacitor C2 can be controlled, thereby making the output voltage VOUT adjustable and less than the input voltage VIN, ultimately achieving the step-down function.

[0068] It should be noted that in the embodiment shown in Figure 2 above, the application of the MOSFET in the buck circuit 30 is only used as an example for illustrative purposes, and it is not limited to the MOSFET provided in this application embodiment being used only in the buck circuit 30 shown in Figure 2 above. In other embodiments of this application, the MOSFET can also be used in scenarios such as boost circuits, inverters, power amplifiers, or RF switches. For example, a boost circuit may include one or more MOSFETs, which can serve as core switching devices, controlling the storage and release of energy through periodic on and off cycles, thereby achieving voltage boosting. That is, the actual application scenarios, placement locations, and quantities of the MOSFETs provided in this application embodiment can be adjusted according to actual design requirements, and this application embodiment does not impose specific limitations on this.

[0069] The following describes several exemplary structures of MOSFETs with reference to the accompanying drawings. It is understood that the MOSFET structures mentioned below can be applied to the first MOSFET Q1 and the second MOSFET Q2 in the embodiment shown in Figure 2, and will not be elaborated further below.

[0070] Figure 3A shows a planar structural diagram of the integrated layout of MOSFET Q in some technical solutions. Figure 3B shows a cross-sectional structural diagram of MOSFET Q in some technical solutions along section AA in Figure 3A. Figure 3C shows a planar structural diagram of a single cell in MOSFET Q in some technical solutions, based on Figure 3A. Referring to Figures 3A to 3C, MOSFET Q is a laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor, hereinafter referred to as "LDMOS transistor" for ease of description. Based on the type of charge carriers, LDMOS transistors can be divided into N-type LDMOS transistors and P-type LDMOS transistors. LDMOS transistors using electrons as charge carriers can be called N-type LDMOS transistors, and those using holes as charge carriers can be called P-type LDMOS transistors. For ease of description, the following description uses MOSFET Q as an N-type LDMOS transistor as an example.

[0071] It should be noted that in the figures below, the X direction can be the length direction of the MOSFET Q, the Y direction can be the width direction of the MOSFET Q, and the Z direction can be the thickness direction of the MOSFET Q. In some implementations, the X direction can be the channel length direction of the MOSFET Q, the Y direction can be the channel width direction of the MOSFET Q, and the Z direction can be the channel depth direction of the MOSFET Q. The X, Y, and Z directions intersect each other; for example, in this application, the X, Y, and Z directions are mutually perpendicular.

[0072] Referring again to Figures 3A to 3C, the MOS transistor Q may include a substrate 100, multiple metal electrodes, and multiple gate electrodes G. The multiple metal electrodes may include, for example, metal electrode 610 and metal electrode 620. The substrate 100 is a semiconductor substrate used to support the metal electrodes 610, metal electrode 620, and multiple gate electrodes G.

[0073] The substrate 100 may include multiple drift regions 200, multiple body regions 300, multiple source regions 400, and multiple drain regions 500. The multiple drift regions 200 and multiple body regions 300 are arranged alternately along the X-direction, thus the body regions 300 and drift regions 200 are offset along the Z-direction. Each of the multiple body regions 300 corresponds one-to-one with the multiple source regions 400, with each source region 400 located within its corresponding body region 300; thus, the source regions 400 and drift regions 200 are also offset along the Z-direction. Each of the multiple drain regions 500 corresponds one-to-one with the multiple drift regions 200, with each drain region 500 located within its corresponding drift region 200.

[0074] Each drift region 200 is at least partially located between a source region 400 and a drain region 500. The element doping concentration of the drift regions 200 is low to improve the high voltage withstand capability of the MOSFET Q. In this embodiment, the drift region 200 can be an N-type drift region (or "Ndrift"). The N-type drift region can be obtained by doping the substrate 100 with a low concentration of N-type elements. For example, the doping concentration of the drift region 200 can be 1×10⁻⁶. 14 cm -3 -1×10 16 cm -3 For example, 1×10 14 cm -3 1×10 15 cm -3 Or 1×10 16 cm -3 wait.

[0075] Body region 300 can also be referred to as a "well region". Body region 300 provides an isolation region to isolate the source S and the gate G. In this embodiment, body region 300 is a P-type body region, which can also be referred to as a "P body". A P-type body region can be obtained by doping the substrate 100 with P-type elements. The doping concentration of body region 300 is higher than that of drift region 200. For example, the doping concentration of body region 300 can be greater than 1 × 10⁻⁶. 16 cm -3 For example, 1×10 17 cm -3 1×10 18 cm -3 wait.

[0076] Each source region 400 is a strip-shaped structure extending along the Y direction. Each source region 400 can be coupled to one of the multiple metal electrodes 610 to construct the source S of a MOS transistor Q, thereby enabling the transmission of electrical signals. In this embodiment, the source region 400 can be an N-type heavily doped region (or "SN"), thus forming an ohmic contact between the source region 400 and the metal electrode 610. An ohmic contact is a type of contact formed between a metal and a semiconductor, characterized by the absence of a significant potential barrier between the metal and semiconductor at the contact interface, allowing electrons to freely pass through the contact surface between the metal and semiconductor. The N-type heavily doped region can be obtained by doping the P-type body region 300 with a high concentration of N-type elements. The doping concentration of the source region 400 is higher than that of the drift region 200 and the body region 300; for example, the doping concentration of the source region 400 can be 1 × 10⁻⁶. 18 cm -3 1×10 19 cm -3 Or 1×10 20 cm -3 wait.

[0077] In some embodiments, the number of metal electrodes 610 corresponding to each source region 400 can be one or more, for example, two, three, or four. Multiple metal electrodes 610 can be arranged at intervals along the Y direction to couple to different segments of each source region 400. In some embodiments, the metal electrodes 610 can be holes filled with metal, or holes with a metal layer on the hole walls; this application is not limited in this regard. In some embodiments, the metal material of the metal electrodes 610 can be titanium, tungsten, molybdenum, gold, silver, aluminum, or nickel, etc.; this application is not limited in this regard.

[0078] Each drain region 500 is a strip-shaped structure extending along the Y direction. Each drain region 500 can be coupled to one of the multiple metal electrodes 620 to form the drain D of a MOS transistor Q, thereby enabling the transmission of electrical signals. In this embodiment, the drain region 500 can be an N-type heavily doped region (or "SN"), thus forming an ohmic contact with the metal electrode 620. The N-type heavily doped region can be obtained by doping the N-type drift region 200 with a high concentration of N-type elements. The element doping concentration of the drain region 500 is higher than that of the drift region 200 and the body region 300; for example, the doping concentration of the drain region 500 can be 1 × 10⁻⁶. 18 cm -3 1×10 19 cm -3 Or 1×10 20 cm -3 wait.

[0079] It is understood that the structure and layout of the metal electrode 620 are essentially the same as those of the metal electrode 610. Therefore, the description of the metal electrode 610 can be referred to, and will not be repeated here.

[0080] Each gate G is a strip-shaped structure extending along the Y direction. Each gate G is located between each adjacent source S and each drain D. The gate G is used to control the current flow between the source S and the drain D in response to voltage changes. In some embodiments, the gate G can be made of metal or polysilicon (or "poly").

[0081] In the aforementioned MOS transistor Q, electrons inverted from the gate G can accumulate between the source region 400 and the drain region 500. When a voltage is applied to the gate G to a preset threshold, the electrons inverted from the gate G can conduct the source region 400 and the drain region 500, thereby achieving the conduction of the source S and the drain D.

[0082] It is understood that in the MOS transistor Q of the embodiments shown in Figures 3A to 3C above, the source region 400, drain region 500, and gate G are all strip-shaped structures extending along the Y direction, the source regions 400 are spaced apart along the X direction, the drain regions 500 are located between two adjacent source regions 400, and the gate G is located between the source S and the drain D. However, this application is not limited to this. In some other embodiments, each gate G and each source region 400 are concentric ring structures, and a ring-shaped source region 400 is disposed outside a ring-shaped gate G, and a drain D is located at the center of the ring structure. This layout can be called a "grid structure". In some implementations, the ring structure can be, for example, a regular octagonal ring structure, a circular ring structure, or other ring structures. For ease of description, the structure of the MOS transistor Q based on the embodiments shown in Figures 3A to 3C above will be described exemplarily below.

[0083] In the MOS transistor Q of the embodiments shown in Figures 3A to 3C above, each source region 400 and the corresponding metal electrode 610 constitute a source S, and the semiconductor portion corresponding to the source S together constitute a source structure, wherein the semiconductor portion may include, for example, a body region 300.

[0084] It is worth noting that a PN junction is formed between the P-type body region 300 and the N-type drift region 200 in the source structure of MOSFET Q, thus the body diode of MOSFET Q is a PN junction diode. The body diode is also called a "parasitic diode" or "internal diode." PN junction diodes are bipolar devices. When a PN junction diode changes from forward conduction to reverse conduction, electrons in the P-region and holes in the N-region need to be reverse-recovered, resulting in poor reverse recovery characteristics of the PN junction diode.

[0085] Therefore, in some technical solutions, reverse recovery characteristics are improved by forming a Schottky contact in the source structure of the MOSFET Q, or in other words, by constructing a Schottky diode in the source structure of the MOSFET Q. The Schottky contact is another type of contact formed between a metal and a semiconductor, where the doping concentration of the semiconductor used to form the Schottky contact is lower than that of the semiconductor used to form the ohmic contact. A characteristic of the Schottky contact is that the energy band of the semiconductor at the contact interface bends, forming a Schottky barrier. The presence of the Schottky barrier results in a relatively large interface resistance and makes the Schottky contact unidirectionally conductive; that is, current can flow relatively easily from the metal to the semiconductor, but there is a significant obstacle when current flows from the semiconductor to the metal. A Schottky diode is a diode constructed from a Schottky contact formed by a semiconductor and a metal. Schottky diodes are unipolar devices with low reverse recovery charge and excellent reverse recovery characteristics.

[0086] Specifically, Figure 4A shows a planar structural schematic diagram of the MOS transistor Q in some other technical solutions, Figure 4B shows a cross-sectional structural schematic diagram of the MOS transistor Q in the BB section of Figure 4A in some other technical solutions, Figure 4C shows a cross-sectional structural schematic diagram of the MOS transistor Q in the CC section of Figure 4A in some other technical solutions, and Figure 4D shows a planar structural schematic diagram of a single cell in the MOS transistor Q in some other technical solutions based on Figure 4A.

[0087] Referring to Figures 4A to 4D, the relative positions of the drift region 200, body region 300, and source region 400 of the MOSFET Q are essentially the same as those shown in Figures 3A and 3B. That is, the drift region 200 and body region 300 are arranged alternately along the X-direction, and the drift region 200 is also arranged alternately with the source region 400 along the X-direction. Alternatively, the drift region 200 and body region 300 are offset along the Z-direction, and the drift region 200 is also offset from the source region 400 along the Z-direction.

[0088] The drift region 200 of the MOSFET Q includes a main drift region 201a and an extended drift region 202a connected together. The main drift region 201a is generally rectangular and located on one side of the body region 300 along the X direction. The extended drift region 202a is generally finger-shaped and extends towards the body region 300 along the X direction. Alternatively, the drift region 200 of the MOSFET Q is generally comb-shaped, and the extended drift region 202a is a comb-like structure with teeth.

[0089] The extended drift region 202a is electrically connected to one of the multiple metal electrodes 630. Because the elemental doping concentration of the extended drift region 202a is low, a Schottky contact can be formed between the extended drift region 202a and the metal electrode 630, thus forming a Schottky diode. A Schottky diode is a unipolar device with very little reverse recovery charge, thereby improving its reverse recovery characteristics.

[0090] However, due to limitations in the molding process, the area of ​​the extended drift region 202a cannot be set small enough. This results in a larger Schottky contact area between the extended drift region 202a and the metal electrode 630, leading to more carriers migrating from the extended drift region 202a to the metal electrode 630 under reverse bias, forming a larger leakage current and ultimately resulting in a larger off-state leakage current. In the aforementioned MOSFET Q, depletion can only be achieved through the N-type extended drift region 202a in the Schottky contact between the P-type body region 300 and the MOSFET. This limited depletion capability is detrimental to improving the off-state leakage current problem.

[0091] To address the aforementioned problems, this application provides a MOSFET. Compared to the MOSFETs described above, the MOSFET provided in this application has a source region located within a drift region. The source region includes multiple sub-source regions spaced apart along its own extending direction. A portion of the drift region between any two adjacent sub-source regions is electrically connected to a metal electrode to construct a Schottky diode, thereby significantly improving reverse recovery characteristics. Furthermore, the substrate also includes multiple doped regions located within the drift region. Each doped region is situated between a Schottky diode and a sub-source region. The type of dopant element in the doped region differs from that in the drift region, allowing the doped region to deplete the drift region, further enhancing its depletion capability and effectively improving off-state leakage current and operating efficiency. Simultaneously, since the portion of the drift region used to construct the Schottky diode is exposed to the outside through the gap between adjacent doped regions, the area of ​​the portion used to construct the Schottky diode in the drift region can be effectively controlled by controlling the size of the gap between adjacent doped regions. This allows the area of ​​this portion to be set as small as possible, further improving off-state leakage current.

[0092] The following is a detailed description with reference to the accompanying drawings.

[0093] Figure 5A shows a planar structural schematic diagram of MOS transistor Q in an embodiment of this application. Figure 5B shows a cross-sectional structural schematic diagram of MOS transistor Q in the EE section of Figure 5A in an embodiment of this application. Figure 6A shows a planar structural schematic diagram of the first source structure Sa in MOS transistor Q in an embodiment of this application, based on Figures 5A and 5B. Figure 6B shows a cross-sectional structural schematic diagram of the first source structure Sa in MOS transistor Q in an embodiment of this application, in the FF section of Figure 6A. Figure 6C shows a cross-sectional structural schematic diagram of the first source structure Sa in MOS transistor Q in an embodiment of this application, in the HH section of Figure 6A. Figure 6D shows a cross-sectional structural schematic diagram of the first source structure Sa in MOS transistor Q in an embodiment of this application, in the II section of Figure 6A. Figure 6E shows a cross-sectional structural schematic diagram of the first source structure Sa in MOS transistor Q in an embodiment of this application, in the JJ section of Figure 6A.

[0094] Referring to Figures 5A and 5B, and in conjunction with Figures 6A to 6E, the MOS transistor Q can be an LDMOS transistor. In this embodiment, the MOS transistor Q may include a substrate 100, a plurality of metal electrodes, and a gate G. The plurality of metal electrodes may include, for example, a metal electrode 610 (as an example of a first metal electrode), a metal electrode 620 (as an example of a second metal electrode), and a metal electrode 630 (as an example of a third metal electrode). The substrate 100 is a semiconductor substrate used to support the metal electrodes 610, 620, 630, and the gate G.

[0095] The substrate 100 may include a drift region 200, a source region 400, and a drain region 500. Exemplarily, there may be one or more source regions 400 and drain regions 500; for ease of description, multiple source regions 400 and multiple drain regions 500 will be used below. All multiple source regions 400 and multiple drain regions 500 are located within the same drift region 200. Each source region 400 may be coupled to one of a plurality of metal electrodes 610 to form a source S. Each drain region 500 may be coupled to one of a plurality of metal electrodes 620 to form a drain D. A gate G is stacked on the substrate 100. The functions of the drift region 200, the multiple source regions 400, the multiple drain regions 500, and the gate G can be referred to the relevant descriptions in the embodiments shown in Figures 3A to 3C above, and will not be repeated here.

[0096] In the embodiments shown in Figures 5A to 6E, the source region 400, drain region 500, and gate G are all strip-shaped structures extending along the Y direction. The source regions 400 are spaced apart along the X direction, the drain regions 500 are located between adjacent source regions 400, and the gate G is located between the source S and the drain D. However, this application is not limited to these embodiments. In other embodiments, each gate G and each source region 400 in the MOS transistor Q is a concentric ring structure, with one ring-shaped source region 400 surrounding one ring-shaped gate G, and one drain D located at the center of the ring structure. This layout can be called a "grid structure." In some implementations, the ring structure can be, for example, a regular octagonal ring structure, a circular ring structure, or other ring structures. For ease of description, the structure of the MOS transistor Q based on the embodiments shown in Figures 5A to 6E will be described exemplarily below.

[0097] Referring again to Figures 5A to 6E, each source region 400 and its corresponding metal electrode 610 constitute a source S, and the semiconductor portion corresponding to that source S together constitute a first source structure Sa. The semiconductor portion may include a portion of the drift region 200. In this application, by rationally designing the layout of the first source structure Sa of the MOSFET Q, the reverse recovery characteristics and off-state leakage current problem can be effectively improved.

[0098] Specifically, taking one of the first source structures Sa as an example, the source region 400 includes a plurality of sub-source regions spaced apart along its own extending direction, such as two, three, or four. For example, in the embodiments shown in Figures 5A to 6E, each source region 400 may include two sub-source regions: sub-source region 410 and sub-source region 420. Sub-source regions 410 and 420 are spaced apart along the Y direction.

[0099] A portion of the drift region 200 between any two adjacent sub-source regions is electrically connected to one of the multiple metal electrodes 630 to form a first Schottky diode. For example, in the embodiments shown in Figures 5A to 6E, the drift region 200 may include a segment 201 located between sub-source regions 410 and 420 and electrically connected to the metal electrode 630. Since the element doping concentration of segment 201 is low, a Schottky contact can be formed between segment 201 and the metal electrode 630, thereby forming a first Schottky diode and improving reverse recovery characteristics. It can be understood that in this embodiment, in the same source structure, for example, the first source structure Sa, the number of metal electrodes 630 can be the same as the number of segments in the drift region 200 used to form the first Schottky diode, and they correspond one-to-one. Each segment in the drift region 200 used to form the first Schottky diode can be electrically connected to the corresponding metal electrode 630 to form a first Schottky diode. Alternatively, in other embodiments, in the same source structure, for example, the first source structure Sa, the number of metal electrodes 630 may also be one. One metal electrode 630 is electrically connected to all segments in the drift region 200 used to form the first Schottky diode, thereby forming multiple first Schottky diodes. That is, different segments of the drift region 200 are electrically connected to the same metal electrode 630. This application does not limit this.

[0100] The substrate 100 also includes a plurality of doped regions 710 (as an example of a first doped region), which are located within the drift region 200. The type of doped element in each doped region 710 is different from the type of doped element in the drift region 200. Along the Y direction, each doped region 710 is located between a first Schottky diode and a sub-source region, or in other words, each doped region 710 is located between a portion of the drift region electrically connected to the metal electrode 630 and a sub-source region. For example, in the embodiments shown in Figures 5A to 6E, each source region 400 may correspond to two doped regions 710, one of which is located between the sub-source region 410 and the first Schottky diode formed by the segment 201 and the metal electrode 630, and the other doped region 710 is located between the sub-source region 420 and the first Schottky diode formed by the segment 201 and the metal electrode 630. Alternatively, one doped region 710 can be described as being located between the source region 410 and segment 201, and the other doped region 710 is located between the source region 420 and segment 201. Thus, segment 201 is exposed to the outside environment through the gap 1 between the two doped regions 710, facilitating electrical connection between segment 201 and the metal electrode 630. Both doped regions 710 can be doped with P-type elements, therefore, both doped regions 710 can be P-type doped regions.

[0101] The aforementioned MOSFET Q, on the one hand, forms a Schottky diode by creating a Schottky contact between segment 201 of the drift region 200 and the metal electrode 630. Schottky diodes are unipolar devices with minimal reverse recovery charge, effectively improving the reverse recovery characteristics of MOSFET Q. On the other hand, the doped region 710 can deplete segment 201 of the drift region 200, further enhancing its depletion capability and thus effectively improving off-state leakage current. Furthermore, segment 201 is exposed to the outside environment through the gap Gap1 between the two doped regions 710. Therefore, by controlling the size of the gap Gap1, the area of ​​segment 201 can be effectively controlled, allowing it to be set as small as possible, further improving off-state leakage current.

[0102] Furthermore, the doped region 710 also helps suppress the latch-up effect of the MOSFET Q. The latch-up effect is a parasitic effect unique to complementary metal-oxide-semiconductor (CMOS) processes, which can lead to circuit failure and even chip burnout. Specifically, the latch-up effect is generated by the npnp structure consisting of the source region of the N-type MOSFET, the P-type substrate, the N-type body region, and the source region of the P-type MOSFET. When one of the transistors is forward biased, positive feedback is formed, resulting in latch-up. In this application, by placing the doped region 710 near the sub-source regions 410 and 420, the conduction of the npnp structure can be avoided, thereby suppressing the latch-up effect and improving the operating performance of the MOSFET Q.

[0103] Referring again to Figures 5A to 6E, in some embodiments of this application, the MOS transistor Q may further include multiple body regions 310 (as an example of a first body region). The multiple body regions 310 are located within the drift region 200 and correspond one-to-one with multiple sub-source regions. Each sub-source region is located within its corresponding body region 310, and along the direction extending from the source region 400 itself, each body region 310 is located between two adjacent first Schottky diodes. Alternatively, along the direction extending from the source region 400 itself, each first Schottky diode is located between two adjacent body regions 310. Or, it can be understood that along the direction extending from the source region 400 itself, body regions 310 and first Schottky diodes are alternately arranged. Furthermore, it can be understood that along the direction extending from the source region 400 itself, each body region 310 is located between two adjacent portions of the drift region 200 electrically connected to the metal electrode 630; or, along the direction extending from the source region 400 itself, each portion of the drift region 200 electrically connected to the metal electrode 630 is located between two adjacent body regions 310. For example, in the embodiments shown in Figures 6A to 6E, each source region 400 may correspond to two body regions 310. Along the Y direction, the two body regions 310 are arranged at intervals. The first Schottky diode formed by the segment 201 and the metal electrode 630 is located between the two body regions 310. In other words, the segment 201 is located between the two body regions 310, the sub-source region 410 is located in one of the body regions 310, and the sub-source region 420 is located in the other body region 310.

[0104] In the aforementioned MOS transistor Q, both the doped region 710 and the body region 310 can deplete segment 201 of the drift region 200 to further improve the off-state leakage problem.

[0105] For ease of description, the layout design of the sub-source region 410 and sub-source region 420 in the embodiments shown in Figures 5A to 6E will be further described below using the examples of sub-source region 410 and sub-source region 420 in each source region 400.

[0106] Referring again to Figures 6A to 6E, in some embodiments of this application, the sub-source region 410 can be coupled to one of the metal electrodes to achieve signal transmission. For example, in the examples shown in Figures 6A to 6E, the sub-source region 410 can be coupled to the metal electrode 610. Since the sub-source region 410 is a heavily doped region, an ohmic contact can be formed between the sub-source region 410 and the metal electrode 610.

[0107] Referring again to Figures 6A to 6E, in some embodiments of this application, the sub-source region 410 may include a first portion 411 and a second portion 412, which are spaced apart along the X direction.

[0108] The substrate 100 also includes a doped region 720 (as an example of a second doped region), located within the drift region 200 and between the first portion 411 and the second portion 412. The doped region 720 is connected to the doped region 710, thus forming a T-shaped structure. The type of dopant element in the doped region 720 is different from the type of dopant element in the drift region 200, or in other words, the type of dopant element in the doped region 720 is the same as the type of dopant element in the doped region 710. For example, in this embodiment, the doped region 720 is doped with a P-type element, thus the doped region 720 is a P-type doped region.

[0109] Thus, the doped region 720 can also deplete segment 201 of the drift region 200, thereby further enhancing the depletion effect on segment 201 of the drift region 200 and helping to improve off-state leakage current. Secondly, the doped region 720 also helps to suppress the latch-up effect of the MOSFET Q. Finally, by placing the doped region 720 between the first portion 411 and the second portion 412 of the sub-source region 410, layout space in the Y direction can be effectively saved, which helps to realize the miniaturization design of the MOSFET Q.

[0110] In other embodiments of this application, doped region 720 and doped region 710 may not be connected, and this application does not impose specific restrictions on this.

[0111] It can be understood that the electrical connection relationship and structural form of the source region 420 are essentially the same as those of the source region 410.

[0112] Specifically, in some embodiments of this application, the sub-source region 420 can also be electrically connected to the source electrode S through one of a plurality of metal electrodes. For example, in the embodiments shown in Figures 6A to 6E, the sub-source region 420 is coupled to the metal electrode 640 to achieve signal transmission. It can be understood that in the embodiments shown in Figures 6A to 6E, an ohmic contact is formed between the sub-source region 410 and the metal electrode 620, an ohmic contact is formed between the sub-source region 420 and the metal electrode 640, and a Schottky contact is formed between the segment 201 of the drift region 200 and the metal electrode 630. Thus, the ohmic contact and the Schottky contact are alternately arranged along the Y direction.

[0113] In some embodiments of this application, the sub-source region 420 may also include a first portion 421 and a second portion 422 spaced apart along the X direction. A doped region connected to the doped region 710 may be provided between the first portion 421 and the second portion 422, thereby jointly forming a T-shaped structure. The type of doped element in this doped region is different from the type of doped element in the drift region 200. For example, in the embodiments shown in Figures 6A to 6E, there are two doped regions 720. One doped region 720 is located between the first portion 411 and the second portion 412 of the sub-source region 410 and is connected to one of the doped regions 710, thereby jointly forming a T-shaped structure. The other doped region 720 is located between the first portion 421 and the second portion 422 of the sub-source region 420 and is connected to the other doped region 710, thereby jointly forming a T-shaped structure.

[0114] As previously described, in the embodiments shown in Figures 5A to 6E, each source region 400 and its corresponding metal electrode 610 constitute a source S, and the semiconductor portion corresponding to that source S can together constitute a first source structure Sa. Since the first source structure Sa includes the source region 400, it can serve as the current path for the MOS transistor Q during normal operation. Thus, all source structures in the cell array of the MOS transistor Q can be the first source structure Sa.

[0115] By way of example, continuing to refer to Figures 5A and 5B, the MOS transistor Q may include three first source structures Sa. The source regions 400 and two drain regions 500 of the three first source structures Sa are alternately arranged along the X direction. Each source region 400 is coupled to a metal electrode 610 to form a source S, thus the MOS transistor Q may include three sources S. Each drain region 500 is coupled to a metal electrode 620 to form a drain D, thus the MOS transistor Q may include two drains D. The three sources S and two drains D are alternately arranged along the X direction, and a gate G is provided between an adjacent source S and a drain D.

[0116] In some implementations, the sources S of the three first source structures Sa can transmit the same signal. Alternatively, in other alternative implementations, the sources S of the three first source structures Sa can transmit different signals, and this application does not impose any specific restrictions on this.

[0117] It is understood that the two drains D can transmit the same signal or different signals. Similarly, the four gates G can transmit the same signal or different signals respectively, and this application does not impose specific limitations on this.

[0118] In addition, the specific structure and function of the first source structure Sa can be referred to the relevant descriptions in the embodiments shown in Figures 6A to 6E above, and will not be repeated here. The specific structure, function and formation method of the drain region 500, drain D, and gate G can all be referred to the relevant descriptions in the schemes shown in Figures 3A to 3C above, and will not be repeated here.

[0119] In the first source structure Sa shown in Figures 5A to 6E, a first Schottky diode is constructed by electrically connecting a portion of the drift region 200 between any two adjacent sub-source regions to the metal electrode 630. However, this application is not limited to this. In some other embodiments, the source structure may not include a source region. A second Schottky diode is constructed by electrically connecting a portion of the drift region 200 between any two adjacent doped regions to the metal electrode. Therefore, this source structure does not serve as a current path for the MOS transistor Q during normal operation, but is only used to improve reverse recovery characteristics. Thus, a portion of the source structure in the cell array of the MOS transistor Q can be a second source structure Sb. That is, the second source structure Sb needs to be used in combination with other source structures that can operate normally, such as the first source structure Sa in the embodiments shown in Figures 6A to 6E. The structure of the second source structure Sb and the combination of the second source structure Sb and the first source structure Sa will be described exemplarily below with reference to the accompanying drawings.

[0120] Specifically, Figure 7A shows a second planar structural schematic diagram of the MOS transistor Q in an embodiment of this application, and Figure 7B shows a cross-sectional structural schematic diagram of the MOS transistor Q in the embodiment of this application along the KK section in Figure 7A. Figure 8A shows a planar structural schematic diagram of the second source structure Sb in the MOS transistor Q in an embodiment of this application, based on Figures 7A and 7B. Figure 8B shows a cross-sectional structural schematic diagram of the second source structure Sb in the MOS transistor Q in an embodiment of this application along the LL section in Figure 8A. Figure 8C shows a cross-sectional structural schematic diagram of the second source structure Sb in the MOS transistor Q in an embodiment of this application along the MM section in Figure 8A. Figure 8D shows a cross-sectional structural schematic diagram of the second source structure Sb in the MOS transistor Q in an embodiment of this application along the OO section in Figure 8A.

[0121] Referring to Figures 7A and 7B, and in conjunction with Figures 8A to 8D, the multiple drain regions 500 of the MOSFET Q may include adjacent first drain region 510 and second drain region 520.

[0122] The substrate 100 may further include a plurality of doped regions 730 (as an example of a third doped region), which are located within the drift region 200 and between two adjacent drain regions, such as a first drain region 510 and a second drain region 520. The type of dopant element in each doped region 730 is the same as that in the doped region 710. For example, in this embodiment, each doped region 730 may be doped with a P-type element, thus all doped regions 730 are P-type doped regions. The plurality of doped regions 730 are spaced apart along the direction extending from the drain region 500 itself, and a portion of the drift region 200 between any two adjacent doped regions 730 is electrically connected to one of the plurality of metal electrodes 650 (as an example of a fourth metal electrode) to form a second Schottky diode.

[0123] For example, in the embodiments shown in Figures 7A to 8D, four doped regions 730 are arranged at intervals along the Y direction, and the drift region 200 further includes segments 202, 203, and 204. Segment 202 is located between the first and second doped regions 730 and is electrically connected to the first metal electrode 650 to form a first second Schottky diode; segment 203 is located between the second and third doped regions 730 and is electrically connected to the second metal electrode 650 therein to form a second second Schottky diode; segment 204 is located between the third and fourth doped regions 730 and is electrically connected to the third metal electrode 650 therein to form a third second Schottky diode.

[0124] In the embodiments shown in Figures 7A to 8D above, the doped region 730, the partial drift region 200, and the metal electrode 650 can collectively constitute the second source structure Sb. In the second source structure Sb, on the one hand, by electrically connecting the partial drift region 200 between any two adjacent doped regions 730 to the metal electrode 650 to construct a second Schottky diode, the reverse recovery characteristics of the MOSFET Q can be effectively improved. On the other hand, the doped region 730 can deplete the partial drift region 200 between any two adjacent doped regions 730, thereby further enhancing the depletion capability of the partial drift region 200 between any two adjacent doped regions 730, and thus effectively improving the off-state leakage current. Furthermore, since the portion of the drift region 200 used to form the second Schottky diode is exposed to the outside through the gap 2 between two adjacent doped regions 730, the area of ​​the portion of the drift region 200 used to form the second Schottky diode can be effectively controlled by controlling the size of the gap 2 between the two adjacent doped regions 730. This allows the portion of the drift region 200 used to form the second Schottky diode to be set as small as possible, which helps to further improve the off-state leakage current. The portion of the drift region 200 used to form the second Schottky diode may include segments 202, 203, and 204.

[0125] Referring again to Figures 8A to 8D, in some embodiments of this application, the MOS transistor Q may further include multiple body regions 320 (as an example of a second body region). The multiple body regions 320 are located within the drift region 200. Each of the multiple body regions 320 corresponds one-to-one with a multiple doped region 730, with each doped region 730 located within its corresponding body region 320. Furthermore, along the direction extending from the drain region 500 itself, each body region 320 is located between two adjacent second Schottky diodes. Alternatively, along the direction extending from the drain region 500 itself, each second Schottky diode is located between two adjacent body regions 320. Or, it can also be understood that along the direction extending from the drain region 500 itself, the body regions 320 and the second Schottky diodes are alternately arranged. Alternatively, it can be understood that, along the direction extending from the drain region 500 itself, each body region 320 is located between two adjacent drift regions 200 electrically connected to the metal electrode 650; or, along the direction extending from the drain region 500 itself, each drift region 200 electrically connected to the metal electrode 650 is located between two adjacent body regions 320. For example, in the embodiments shown in Figures 8A to 8D, along the Y direction, four body regions 320 are alternately arranged with three second Schottky diodes, wherein a segment 202 of the drift region 200 is located between the first body region 320 and the second body region 320, a segment 203 of the drift region 200 is located between the second body region 320 and the third body region 320, and a segment 204 of the drift region 200 is located between the third body region 320 and the fourth body region 320.

[0126] In the aforementioned MOSFET Q, both the doped region 730 and the body region 320 can deplete the portion of the drift region 200 used to form the second Schottky diode, thereby further improving the off-state leakage current. The portion of the drift region 200 used to form the second Schottky diode may include segments 202, 203, and 204.

[0127] Since the second source structure Sb in the embodiments shown in Figures 7A to 8D does not include a source, the second source structure Sb is not used as a current path when the MOSFET Q is operating normally; it is only used to improve reverse recovery characteristics and off-state leakage current. The second source structure Sb needs to be used in combination with other source structures that can operate normally, such as the first source structure Sa in the embodiments shown in Figures 5A to 6E, as illustrated below.

[0128] In some feasible solutions, the first source structure Sa and the second source structure Sb can be two physically independent source structures. That is, the source S of the first source structure Sa and the second source structure Sb are two physically independent sources. The first source structure Sa can serve as the current path for the MOSFET Q during normal operation, while the second source structure Sb cannot. Both the first source structure Sa and the second source structure Sb can improve reverse recovery characteristics and off-state leakage current.

[0129] For example, continuing to refer to Figures 8A to 8D, the MOS transistor Q may include three source structures: two first source structures Sa and one second source structure Sb. Along the X direction, the two first source structures Sa are arranged at intervals, a first drain region 510 and a second drain region 520 are located between the two first source structures Sa, and the second source structure Sb is located between the first drain region 510 and the second drain region 520.

[0130] It is understandable that in the aforementioned MOSFET Q, the two first source structures Sa can serve as current paths during normal operation, while the second source structure Sb does not. Furthermore, both the first source structure Sa and the second source structure Sb can improve reverse recovery characteristics and off-state leakage current.

[0131] In some implementations, the source S of the two first source structures Sa and the source S of the second source structure Sb can transmit the same signal. Alternatively, in other alternative implementations, the source S of the two first source structures Sa and the source S of the second source structure Sb can transmit different signals, and this application does not impose specific limitations on this.

[0132] It is understood that the two drains D can transmit the same signal or different signals. Similarly, the four gates G can transmit the same signal or different signals respectively, and this application does not impose specific limitations on this.

[0133] In addition, the specific structure and function of the first source structure Sa can be referred to the relevant descriptions in the embodiments shown in Figures 6A to 6E above, and will not be repeated here. The specific structure and function of the second source structure Sb can be referred to the relevant descriptions in the embodiments shown in Figures 8A to 8D above, and will not be repeated here.

[0134] It should be noted that Figures 7A and 7B only schematically illustrate partial layouts of the first source structure Sa and the second source structure Sb, and do not constitute a limitation on this application. For example, in some other embodiments, the MOS transistor Q may also include two second source structures Sb and one first source structure Sa, with the two second source structures Sb located on opposite sides of a first source structure Sa along the X direction.

[0135] In other feasible schemes, the first source structure Sa and the second source structure Sb can also be different parts of the same source structure. This can also be understood as the source S of the first source structure Sa and the second source structure Sb being different parts of the same source.

[0136] For example, Figure 9A shows a planar structural schematic diagram of the MOS transistor Q in an embodiment of this application, and Figure 9B shows a cross-sectional structural schematic diagram of the MOS transistor Q in the RR section of Figure 9A in an embodiment of this application. Referring to Figures 9A and 9B, the first source structure Sa and the second source structure Sb can be arranged along the Y direction, and the first source structure Sa and the second source structure Sb share the same source S.

[0137] Based on the MOS transistor Q in the embodiments shown in Figures 5A to 9B, in some embodiments of this application, the doped region 710 can be a heavily doped region to enhance the depletion capability of the doped region 710 on segment 201 of the drift region 200, thereby further improving the off-state leakage current. The doping concentration of the heavily doped region can, for example, be greater than or equal to 1 × 10⁻⁶. 18 cm -3 For example, 1×10 18 cm -3 1×10 19 cm -3 Or 1×10 20 cm -3 wait.

[0138] Taking the doped region 710 as a heavily P-type doped region as an example, in some implementations, the heavily P-type doped region can be obtained by doping the substrate 100 of the MOS transistor Q with a high concentration of P-type elements. In other implementations, a low concentration of P-type elements can be doped into the substrate 100 of the transistor Q through a lightly doped source / drain (LDD) formation step in a bipolar-CMOS-DMOS (BCD) process. Then, a high concentration of P-type elements is doped into the substrate 100 of the MOS transistor Q, ultimately resulting in a heavily P-type doped region with a higher doping concentration, thereby further improving the depletion capability of the doped region 710 for the first segment 201. The doping concentration of the lightly doped source / drain formation process can, for example, be 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 For example, 1×10 16 cm -3 1×10 17 cm -3 Or 1×10 18 cm -3 wait.

[0139] It is understood that the structural forms of doped regions 720 and 730 are essentially the same as those of doped region 710. Therefore, you can refer to the relevant description of doped region 710, which will not be repeated here.

[0140] This application also provides a MOSFET Q, which may include the second source structure Sb in the embodiments shown in Figures 8A to 8D, but does not include the first source structure Sa in the embodiments shown in Figures 5A to 6E. The second source structure Sb can be used in combination with other source structures that can operate normally. The second source structure Sb cannot serve as a current path for the MOSFET Q during normal operation; it is only used to improve reverse recovery characteristics and off-state leakage current. Other source structures that can operate normally can serve as current paths for the MOSFET Q during normal operation, but are not used to improve reverse recovery characteristics and off-state leakage current.

[0141] Specifically, Figure 10A shows a planar structural schematic diagram of MOS transistor Q in an embodiment of this application, Figure 10B shows a cross-sectional structural schematic diagram of MOS transistor Q in the TT section of Figure 10A in an embodiment of this application, and Figure 10C shows a cross-sectional structural schematic diagram of MOS transistor Q in the UU section of Figure 10A in an embodiment of this application.

[0142] Referring to Figures 10A to 10C, the MOS transistor Q can be an LDMOS transistor. In this embodiment, the MOS transistor Q may include a substrate 100, multiple metal electrodes, and a gate G. The multiple metal electrodes may include, for example, a metal electrode 610 (as an example of a first metal electrode), a metal electrode 620 (as an example of a second metal electrode), and a metal electrode 650 (as an example of a third metal electrode). The substrate 100 is a semiconductor substrate used to support the metal electrodes 610, 620, 650, and the gate G.

[0143] The substrate 100 may include a drift region 200, a source region 400, and a drain region 500. Exemplarily, there may be one or more source regions 400 and drain regions 500; for ease of description, multiple source regions 400 and multiple drain regions 500 are described below. All multiple source regions 400 and multiple drain regions 500 are located within the same drift region 200. Each source region 400 may be coupled to one of a plurality of metal electrodes 610 to form a source S. Each drain region 500 may be coupled to one of a plurality of metal electrodes 620 to form a drain D. A gate G is stacked on the substrate 100.

[0144] In the embodiments shown in Figures 10A to 10C, the source region 400, drain region 500, and gate G are all strip-shaped structures extending along the Y direction. The source regions 400 are spaced apart along the X direction, the drain regions 500 are located between adjacent source regions 400, and the gate G is located between the source S and the drain D. However, this application is not limited to these embodiments. In other embodiments, each gate G and each source region 400 in the MOS transistor Q is a concentric ring structure, and a ring-shaped source region 400 is disposed outside a ring-shaped gate G. A drain D is located at the center of the ring structure. This layout can be called a "grid structure." In some implementations, the ring structure can be, for example, a regular octagonal ring structure, a circular ring structure, or other ring structures. For ease of description, the structure of the MOS transistor Q based on the embodiments shown in Figures 10A to 10C will be described exemplarily below.

[0145] Referring to Figures 10A through 10C, to improve reverse recovery characteristics and off-state leakage current, the multiple drain regions 500 of the MOSFET Q may include adjacent first drain region 510 and second drain region 520.

[0146] The substrate 100 may further include a plurality of doped regions 730 located within the drift region 200 and between two adjacent drain regions, wherein the two adjacent drain regions may be, for example, a first drain region 510 and a second drain region 520. The type of dopant element in each doped region 730 is different from the type of dopant element in the drift region 200. For example, in this embodiment, each doped region 730 may be doped with a P-type element, so that all doped regions 730 are P-type doped regions. The plurality of doped regions 730 are arranged at intervals along the direction extending from the drain region 500 itself, and a portion of the drift region 200 between any two adjacent doped regions 730 is electrically connected to one of the plurality of metal electrodes 650 to form a Schottky diode.

[0147] For example, in the embodiments shown in Figures 10A to 10C, four doped regions 730 are arranged at intervals along the Y direction, and the drift region 200 includes segments 202, 203, and 204. Segment 202 is located between the first and second doped regions 730 and is electrically connected to the first metal electrode 650 to form a first Schottky diode; segment 203 is located between the second and third doped regions 730 and is electrically connected to the second metal electrode 650 therein to form a second Schottky diode; segment 204 is located between the third and fourth doped regions 730 and is electrically connected to the third metal electrode 650 therein to form a third Schottky diode.

[0148] In the embodiments shown in Figures 10A to 10C above, the doped region 730, the partial drift region 200, and the metal electrode 650 can collectively constitute the second source structure Sb. In the second source structure Sb, on one hand, by electrically connecting the partial drift region 200 between any two adjacent doped regions 730 to the metal electrode 650 to construct a Schottky diode, the reverse recovery characteristics of the MOSFET Q can be effectively improved. On the other hand, the doped region 730 can deplete the portion of the drift region 200 used to form the Schottky diode, thereby further enhancing the depletion capability of the portion of the drift region 200 used to form the Schottky diode, and thus effectively improving the off-state leakage current. Furthermore, since the portion of the drift region 200 used to form the Schottky diode is exposed to the outside through the gap between two adjacent doped regions 730, the area of ​​the portion of the drift region 200 used to form the Schottky diode can be effectively controlled by controlling the size of the gap between two adjacent doped regions 730. This allows the portion of the drift region 200 used to form the Schottky diode to be set as small as possible, which helps to further improve the off-state leakage current. The portion of the drift region 200 used to form the Schottky diode may include segments 202, 203, and 204.

[0149] Each source region 400 and its corresponding metal electrode 610 form a source S, and the semiconductor portion corresponding to the source S can together constitute a third source structure Sc. Since the third source structure Sc includes the source region 400 but excludes the Schottky diode and the doped region near the Schottky diode, the third source structure Sc can serve as the current path for the MOSFET Q during normal operation and is not used to improve reverse recovery characteristics or off-state leakage current.

[0150] It is understood that the structure, variations, and beneficial effects of the second source structure Sb in the embodiments shown in Figures 10A to 10C are substantially the same as those in the embodiments shown in Figures 7A to 8D. For example, the structure and beneficial effects of the doped region 730 in the second source structure Sb shown in Figures 10A to 10C are substantially the same as those in the second source structure Sb shown in Figures 7A to 8D. Furthermore, the second source structure Sb shown in Figures 10A to 10C may also include a body region, for example, a body region 320, to further improve off-state leakage current. The structure and layout of the body region 320 in the second source structure Sb shown in Figures 10A to 10C are substantially the same as those in the second source structure Sb shown in Figures 7A to 8D. Therefore, the description of the second source structure Sb in the embodiments shown in Figures 7A to 8D can be referred to, and will not be repeated here.

[0151] Referring again to Figures 10A to 10C, in some embodiments of this application, each source region 400 in the third source structure Sc may include a plurality of sub-source regions 410 spaced apart along the Y direction, and a doped region 740 is provided between any two adjacent sub-source regions 410. The type of dopant element in the doped region 740 is the same as the type of dopant element in the doped region 730, thereby, the doped region 740 helps to suppress the latch-up effect of the MOS transistor Q.

[0152] In some embodiments of this application, the number of third source structures Sc can be multiple. For example, in the embodiments shown in Figures 10A and 10B, the number of third source structures Sc is two, and the two third source structures Sc are respectively disposed on opposite sides of the second source structure Sb along the X direction. However, this application is not limited to this. In other embodiments of this application, the two second source structures Sb may be respectively disposed on opposite sides of a third source structure Sc along the X direction.

[0153] It should be noted that the embodiments shown in Figures 5A, 5B, 7A, 7B, 9A to 10C are only illustrated with the example of a MOS transistor Q comprising three source structures, two drain regions, and four gates, and do not constitute a limitation of this application. In other embodiments, the MOS transistor Q may also include more or fewer source structures, for example, two, four, or five, and correspondingly, the number of drain regions and gates may also be more or fewer, for example, one, two, three, four, or five, etc. This application does not impose any limitations on this, as long as it ensures that the MOS transistor Q can function normally.

[0154] It should also be noted that the gate G, source S, and drain D of the MOS transistor Q in the embodiments shown in Figures 5A, 5B, 7A, 7B, 9A to 10C are all elongated structures, but this application is not limited to this. In some other embodiments, the gate G, source S, and drain D of the MOS transistor Q can also be ring-shaped structures, thereby forming a ring-shaped mesh structure MOS transistor Q. The following description uses the ring-shaped mesh structure MOS transistor Q including the first source structure Sa in the embodiments shown in Figures 5A to 6E as an example.

[0155] Figure 11 shows a schematic diagram of the planar structure of the MOS transistor Q in an embodiment of this application. Referring to Figure 11, each gate G and each source region 400 in the MOS transistor Q is a concentric ring structure, and the source region 400 of one ring structure is disposed outside the gate G of another ring structure. A drain D is located at the center of the ring structure. For example, in the embodiment shown in Figure 11, the ring structure is a regular octagonal ring structure, then the drain D can be located at the intersection of the diagonals of the regular octagon. In some other examples, the ring structure can also be a circular ring structure, then the drain D can be located at the center of the circle.

[0156] Each source region 400 and the corresponding metal electrode 610 constitute a source S, and the semiconductor portion corresponding to the source S together constitute a first source structure Sa. The first source structure Sa is a ring structure. The specific structure and function of the ring structure first source structure Sa are substantially the same as the specific structure and function of the strip-shaped second source structure Sb in the embodiments shown in Figures 5A to 6E. Therefore, the relevant descriptions of the embodiments shown in Figures 5A to 6E can be referred to, and will not be repeated here.

[0157] It is understood that the first source structure Sa of the ring structure can be replaced by the second source structure Sb of the ring structure. The specific structure and function of the second source structure Sb of the ring structure are substantially the same as the specific structure and function of the strip-shaped second source structure Sb in the embodiments shown in Figures 7A to 8D above. Therefore, the relevant descriptions of the embodiments shown in Figures 7A to 8D above can be referred to, and will not be repeated here.

[0158] This application also provides a chip that integrates a field-effect transistor. The field-effect transistor can be any of the MOS transistors Q shown in the embodiments of Figures 5A to 11 above. Its specific structure and function can be referred to the relevant descriptions in the embodiments shown in Figures 5A to 11 above, and will not be repeated here.

[0159] This application also provides an electronic device, which includes a circuit board and a chip. The chip can be disposed on the circuit board, and the chip integrates a field-effect transistor. The field-effect transistor can be any type of MOS transistor Q shown in the embodiments of Figures 5A to 11 above. Its specific structure and function can be referred to the relevant descriptions in the embodiments shown in Figures 5A to 11 above, and will not be repeated here.

[0160] The specific embodiments described above illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Although the description of this application is presented in conjunction with some embodiments, this does not mean that the features of this application are limited to this embodiment. On the contrary, the purpose of describing the application in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of this application. This application may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of this application, some specific details have been omitted in the description. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0161] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "outer", "inner", "circumferential", "radial", "axial", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0162] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "set," "install," "connect," and "fit" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0163] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A field-effect transistor, characterized in that, The system includes a substrate, a first metal electrode, a second metal electrode, a third metal electrode, and a gate electrode. The gate electrode is stacked on the substrate. The substrate includes a source region, a drain region, and a drift region. The source region and the drain region are located within the drift region. The source region is coupled to the first metal electrode, and the drain region is coupled to the second metal electrode. The source region includes multiple sub-source regions, which are arranged at intervals along the direction of the source region itself. The portion of the drift region between any two adjacent sub-source regions is electrically connected to the third metal electrode. The substrate further includes a plurality of first doped regions located within the drift region. The type of doped element in each first doped region is different from the type of doped element in the drift region. Each first doped region is located between a portion of the drift region electrically connected to the third metal electrode and a sub-source region, extending along the direction of the source region itself.

2. The field-effect transistor according to claim 1, characterized in that, Each of the sub-source regions includes a first part and a second part, which are spaced apart along a direction perpendicular to the direction in which the source region extends itself. The substrate further includes a plurality of second doped regions located within the drift region. The type of doped element in each second doped region is the same as the type of doped element in the first doped region. Each second doped region is located between a first portion and a second portion of a sub-source region.

3. The field-effect transistor according to claim 2, characterized in that, Each of the second doped regions is connected to the adjacent first doped region.

4. The field-effect transistor according to claim 1, characterized in that, The first doped region is a heavily doped region.

5. The field-effect transistor according to claim 1, characterized in that, The substrate further includes a plurality of first body regions located within the drift region, each of the sub-source regions being located within each of the first body regions, and each of the first body regions being located between two adjacent portions of the drift region electrically connected to the third metal electrode, extending along the direction of the source region itself.

6. The field-effect transistor according to claim 1, characterized in that, The field-effect transistor includes a fourth metal electrode; The substrate further includes a plurality of third doped regions located within the drift region and between two adjacent drain regions, wherein the type of dopant element in each third doped region is the same as the type of dopant element in the first doped region; The plurality of third doped regions are arranged at intervals along the direction of the drain region, and the portion of the drift region between any two adjacent third doped regions is electrically connected to the fourth metal electrode.

7. The field-effect transistor according to claim 6, characterized in that, The substrate further includes a plurality of second body regions located within the drift region, each of the third doped regions being located within each of the second body regions, and each of the second body regions being located between two adjacent portions of the drift region electrically connected to the fourth metal electrode, extending along the direction of the drain region itself.

8. A field-effect transistor, characterized in that, The system includes a substrate, a first metal electrode, a second metal electrode, a third metal electrode, and a gate electrode. The gate electrode is stacked on the substrate. The substrate includes a source region, a drain region, and a drift region. The source region and the drain region are located within the drift region. The source region is coupled to the first metal electrode, and the drain region is coupled to the second metal electrode. The substrate further includes multiple doped regions located within the drift region and between two adjacent drain regions. The type of dopant element in the doped regions is different from the type of dopant element in the drift region. The plurality of doped regions are arranged at intervals along the direction in which the drain region extends itself, and the portion of the drift region between any two adjacent doped regions is electrically connected to the third metal electrode.

9. The field-effect transistor according to claim 8, characterized in that, The doped region is a heavily doped region.

10. The field-effect transistor according to claim 8, characterized in that, The substrate further includes a plurality of body regions located within the drift region, each of the doped regions being located within the body region, and each of the body regions being located between two adjacent portions of the drift region electrically connected to the third metal electrode, extending along the direction of the drain region itself.

11. A chip, characterized in that, The chip includes a field-effect transistor according to any one of claims 1 to 10.

12. An electronic device, characterized in that, It includes a circuit board and the chip of claim 11, the chip being disposed on the circuit board.

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