Processor system, chip, and electronic device

Abstract

Provided in the present application are a processor system, a chip, and an electronic device. The processor system comprises a processor module and a cache processing subsystem. The processor module comprises a processor and is configured to implement operation and control functions of the processor. The cache processing subsystem is configured to implement a cache coherency function, and comprises a bridge module and a CCI module, wherein the bridge module is configured to implement data transmission between the processor and external devices, and the CCI module is optionally integrated into the cache processing subsystem on the basis of the manner in which the processor handles cache coherency.

Description

Processor systems, chips and electronic devices

[0001] Cross-referencing

[0002] This application claims priority to Chinese Patent Application No. 202510301788.8, filed on March 14, 2025, entitled “Processor System, Chip and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of chip technology, and in particular to a processor system, chip, and electronic device. Background Technology

[0004] In chip design, processor systems can be integrated into chips in certain scenarios. For example, a processor system can be integrated into a System-on-Chip (SoC) chip. A processor system typically contains one or more processors, each of which may include one or more cores. External devices can access and interact with the processors via the system bus. In related technologies, to ensure the correctness of the data obtained during data interaction between the processor and external devices, the processor needs to guarantee cache coherency. However, different processors handle cache coherency differently. When integrating processor systems, the same integration method may work for processor A but not for processor B, leading to integration complexity and poor adaptability. Summary of the Invention

[0005] This application provides a processor system, a chip, and an electronic device.

[0006] In a first aspect, a processor system is provided, comprising: a processor module including a processor for implementing the processor's computation and control functions; and a cache processing subsystem connected to the processor module for implementing cache coherency functions; wherein the cache processing subsystem includes a bridging module and a CCI module, the bridging module for implementing data transmission between the processor and external devices, and the CCI module optionally integrated into the cache processing subsystem according to the processor's cache coherency processing method.

[0007] In a second aspect, a chip is provided, comprising the processor system described in the first aspect.

[0008] Thirdly, an electronic device is provided, including the chip as described in the second aspect. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 is a schematic diagram of the structure of a processor system according to an embodiment of this application;

[0011] Figure 2 is a schematic diagram of an embodiment of this application in which the CCI module is not integrated into the processor system;

[0012] Figure 3 is a schematic diagram of the structure of integrating a CCI module in a processor system according to an embodiment of this application;

[0013] Figure 4 is a schematic diagram of a processor system, DDR module, PCIe module and external devices according to an embodiment of this application;

[0014] Figure 5 is a flowchart illustrating an embodiment of the processor system integration method of this application. Detailed Implementation

[0015] In chip design, processor systems can be integrated into a chip to realize its computational and control functions. With the increasing diversity of applications, chip design places higher demands on processor performance. For example, the shift from single-cluster to multi-cluster architectures, and the increase in the number of clusters and cores, not only requires more complex integration but also places higher demands on maintaining cache coherency during the interaction between external and internal data. However, processors from different manufacturers implement cache coherency differently. For instance, some processors achieve cache coherency through I / O Coherency Ports (IOCP), while others require additional Cache Coherent Interconnects (CCI). Thus, when integrating processor systems, the same integration method may not be applicable to processors from different manufacturers, resulting in high integration complexity and poor adaptability.

[0016] This application provides a processor system, chip, and electronic device that allows CCI to be optionally set in the cache processing subsystem of the processor system. When the processor needs to use CCI to achieve cache coherency, CCI is enabled, that is, CCI is integrated into the cache processing subsystem. When the processor does not need to use CCI to achieve cache coherency, CCI is disabled, that is, CCI is not integrated into the cache processing subsystem. This provides a universal processor system integration solution that can adapt to the integration of processors with different cache coherency processing methods, improve integration flexibility, reduce complexity, and also improve system stability and maintainability.

[0017] It should be noted that the technical solutions provided in the embodiments of this application can be applied to integrated circuits and chip integration in various technical fields (such as automotive electronics, consumer electronics or communication chips). For example, they can be applied to SOC chip integration, and more specifically, they can be applied to SOC chip integration based on Reduced Instruction Set Computing-Version (RISC-V). No specific limitations are made here.

[0018] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in this application will be clearly and completely described below with reference to the accompanying drawings of one or more embodiments. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this application.

[0019] The terms "first," "second," etc., used in this application and the claims are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that this application can be implemented in orders other than those illustrated or described herein. Furthermore, in this application and the claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0020] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0021] Figure 1 is a schematic diagram of the structure of a processor system 10 according to an embodiment of this application. The processor system 10 shown in Figure 1 includes a processor module 11 and a cache processing subsystem 12. The processor module 11 includes a processor for implementing the processor's computation and control functions. The cache processing subsystem 12 is connected to the processor module 11 and is used to implement cache coherency functions. The cache processing subsystem 12 includes a bridging module 121 and a CCI module 122. The bridging module 121 is used to implement data transmission between the processor and external devices; that is, external devices can access the processor through the bridging module 121. The CCI module 122 is an optional module and can be optionally integrated into the cache processing subsystem 12 depending on the processor's cache coherency handling method. This optional integration can mean connecting or not connecting the CCI module 122 to the cache processing subsystem 12, or enabling or disabling the CCI module 122 within the cache processing subsystem 12.

[0022] In this way, since the CCI module is added as an option in the cache processing subsystem of the processor system, and the integration of the CCI module or not is selected according to the processor's cache coherency handling method, it can be adapted to the integration of processors with different cache coherency handling methods, thereby improving integration flexibility, reducing complexity, and improving system stability and maintainability.

[0023] It should be noted that in some possible implementations, the bridging module may not be integrated into the cache processing subsystem, but rather integrated into the processor system as a separate module. Regardless of the integration method, the functionality of the bridging module, the processor module, and the cache processing subsystem will not be affected. This application embodiment uses the integration of the bridging module into the cache processing subsystem as an example for illustration.

[0024] In some implementations, the processor handles cache coherency in a first manner, which includes achieving cache coherency through IOCP. In this case, since cache coherency can be achieved through IOCP, the CCI module can be omitted; that is, the CCI module can be excluded from the cache processing subsystem.

[0025] In some implementations, the processor handles cache coherency in a second manner, which includes achieving cache coherency through CCI. In this case, since cache coherency needs to be achieved through CCI, a CCI module is required; that is, the CCI module needs to be integrated into the cache processing subsystem.

[0026] It should be noted that most processors in related technologies achieve cache coherence through the first or second method described above. Therefore, by optionally integrating the CCI module into the cache processing subsystem, it can be adapted to the integration of most processors. Optionally, if a processor achieves cache coherence through other methods, the module implementing cache coherence for that processor can be optionally integrated into the cache processing subsystem. This module is integrated into the cache processing subsystem when it is needed to achieve cache coherence, and not integrated when it is not needed. This application's embodiments use a processor that achieves cache coherence through the first or second method described above as an example for illustration.

[0027] In some implementations, the bridging module in the cache processing subsystem can connect to external devices, Double Data Rate (DDR) modules, and peripheral component interconnect express (PCIe) modules. The DDR module stores data. The PCIe module allows external devices to access the processor or DDR module. This way, external devices can access data through two paths: one is through the bridging module to directly access the DDR module without going through the processor, and the other is through the PCIe module to access the processor, achieving cache coherency. The PCIe module may include interfaces such as PCIe and / or Universal Serial Bus (USB).

[0028] In some implementations, where the CCI module is not integrated into the cache processing subsystem, the processor achieves cache coherency through its internal IOCP. In this case, the bridge module can connect to the processor's IOCP in addition to external devices, DDR modules, and PCIe modules. When external devices access data, they can access the processor through the PCIe module, bridge module, and IOCP; alternatively, they can access the DDR module through the PCIe module and bridge module without going through the processor.

[0029] Please refer to Figure 2. In Figure 2, the processor uses IOCP to achieve cache coherency. The CCI module may not be integrated into the cache processing subsystem (the connection line between the CCI module and the bridge module in Figure 2 is a dashed line). The bridge module in the cache processing subsystem connects to external devices, the DDR module, and the PCIe module, as well as to the IOCP in the processor. When an external device needs to interact with the processor and also interact with other modules (such as the DDR module) without going through the processor, a new matrix bridge (i.e., the bridge module shown in Figure 2) needs to be added between the processor module and the PCIe module. Simultaneously, the bridge module can be configured through the processor's internal IOCP to determine whether the external device interacts with the processor. Thus, when an external device accesses data, it can access the processor sequentially through the PCIe or USB interface in the PCIe module, the bridge module, and the IOCP module; or it can access the DDR module sequentially through the PCIe or USB interface in the PCIe module and the bridge module.

[0030] In some implementations, when the CCI module is integrated into the cache processing subsystem, the CCI module can connect to external devices, DDR modules, and PCIe modules, and connect to the processor module via a bridge module. When accessing data, external devices can access the processor through the PCIe module, CCI module, and bridge module, or they can access the DDR module through the PCIe module and bridge module.

[0031] Please refer to Figure 3. In Figure 3, the processor uses a CCI architecture to achieve cache coherency. The CCI module needs to be integrated into the cache processing subsystem (the connection line between the CCI module and the bridge module in Figure 3 is a solid line). The CCI module itself has the function of a matrix bridge, which can realize access between multiple masters and slaves. However, since different processors have different integration of different modules or components such as interrupts and debugging, a corresponding bridge module is still needed to complete the integration between the processor and the CCI module. In Figure 3, the CCI module is connected to external devices, DDR modules, and PCIe modules, and is connected to the processor module through the bridge module. The bridge module is connected to external devices, DDR modules, and PCIe modules. When external devices access data, they can access the processor sequentially through the PCIe or USB interface in the PCIe module (not shown in Figure 3), the CCI module, and the bridge module; or they can access the DDR module sequentially through the PCIe or USB interface in the PCIe module and the bridge module.

[0032] In some implementations, the processor module may include one or more processors, and each processor may include one or more cores. That is, the integration scheme provided in this application embodiment can be applied to processor systems with any number of processors and / or any number of cores.

[0033] In some implementations, the processor in the processor module can be a processor based on the RISC-V instruction set architecture (which can be referred to as a RISC-V processor). That is, the integration scheme provided in the embodiments of this application can be applied to RISC-V-based processor systems.

[0034] In some implementations, in addition to a processor, the processor module may also include at least one of the following: an interrupt handling submodule; a debug submodule; and a cross-clock domain submodule.

[0035] It should be noted that in practical applications, the interrupt handling submodule and the debug submodule may be integrated into the processor. Therefore, the above-mentioned inclusion of at least one of the following can specifically be including the interrupt handling submodule, the debug submodule, and the cross-clock domain submodule (corresponding to the case where the interrupt handling submodule and the debug submodule are not integrated into the processor), or including the cross-clock domain submodule but excluding the interrupt handling submodule and the debug submodule (corresponding to the case where the interrupt handling submodule and the debug submodule are integrated into the processor).

[0036] It should also be noted that in some possible implementations, in addition to the interrupt handling submodule, debug submodule and cross-clock domain submodule mentioned above, the processor module may also include other submodules that can perform processing functions, which will not be listed here.

[0037] In some implementations, the processor system can be a master-slave architecture, or a multi-master-multi-slave architecture. That is, the integration solutions provided in this application can be applied to scenarios where the processor system has a master-slave architecture or a multi-master-multi-slave architecture. In these scenarios, the integration solutions provided in this application can be adapted to the integration of different processors.

[0038] Optionally, in some implementations, in addition to the processor module and cache processing subsystem, the processor system may also include a read-only memory (ROM) module and a clock / reset module. The ROM module is connected to the processor module and stores processor-related instructions, such as control instructions related to processor startup or operation. The clock / reset module is connected to the processor module and provides the clock and reset control signals required by the processor. This ensures the normal operation of the processor system.

[0039] Figure 4 is a schematic diagram of a processor system, DDR module, PCIe module, and external devices according to an embodiment of this application. The processor system in Figure 4 includes a clock reset module, a processor module, a ROM module, and a cache processing subsystem. The cache processing subsystem includes a bridge module and a CCI module, with the CCI module optionally integrated into the cache processing subsystem. The bridge module in the cache processing subsystem is connected to the DDR module, the PCIe module, and the external devices (i.e., external devices 1 to external devices N shown in Figure 4). Specifically: The clock reset module provides the clock and reset signals required by the processor.

[0040] Processor module: This includes a processor (such as a RISC-V processor) used to implement CPU operations and control, such as encryption, floating-point operations, and multi-stage pipelined instruction fetching. The number of processors can be one or more, and each processor can include one or more cores. Optionally, the processor module can also integrate interrupt handling submodules, debug submodules, and cross-clock domain submodules.

[0041] The Cache Processing Subsystem handles cache coherency and includes a bridging module and a CCI module. The bridging module facilitates data transfer between the processor and external devices. The CCI module is optionally integrated into the Cache Processing Subsystem, depending on the processor's cache coherency handling method. For example, if the processor implements cache coherency through IOCP, the CCI module may not be integrated; otherwise, it is integrated.

[0042] ROM module: Used to store processor-related instructions, such as instructions related to processor startup.

[0043] DDR module: Used to store interactive data.

[0044] PCIe modules, including PCIe and / or USB interfaces, comply with the PCIe protocol and are used for external device access.

[0045] Based on the architecture shown in Figure 4, data consistency between the processor and different peripherals can be maintained, while bus access efficiency can be improved, enabling a universal solution for integrating different processor chips. In processor integration based on the RISC-V open-source instruction set architecture, regardless of the expansion or change of processor configuration selection, the processor system integration can be dynamically adjusted. For different chips and scenarios, only the actual situation needs to be selected, making modifications more flexible, maintainingability stronger, and increasing system stability.

[0046] Figure 5 is a flowchart illustrating a method for integrating a processor system according to an embodiment of this application. This method can be used by integrated circuit and chip designers to integrate the processor system provided in this embodiment. As shown in Figure 5, the integration of the processor system may include the following steps.

[0047] Step 1: Configure the processor module.

[0048] The processor module is the core of the chip, responsible for various functions such as value fetching, execution, control, floating-point arithmetic, and encryption. It also supports interrupt handling and Joint Test Action Group (JTAG) debugging. Processors based on the RISC-V instruction set architecture can selectively add different extended instruction sets on top of the basic instruction set.

[0049] When configuring a processor module, it is necessary to determine the processor's operating clock frequency and reset control signal, the number of external devices, cache coherence structure, low-power control, and other related information. In addition, configuring the processor module also requires configuring various information such as the number of cores, cache levels and size, whether error checking and correcting (ECC) is included, vector length and width, Memory Management Unit (MMU) address width, Translation Lookaside Buffer (TLB) entries, the number of supported interrupts, and the latency of the processor accessing the shared cache. Furthermore, it is essential to understand the parameters such as the bus protocols supported by the processor.

[0050] In this embodiment, the core configuration of the processor module is to determine whether it maintains cache consistency based on the IOCP structure or by using an external CCI structure, thereby deciding whether to select a CCI module and thus selecting the corresponding cache processing subsystem.

[0051] Step 2: Based on the configured clock frequency, reset signal and other information, complete the integration of the clock reset module.

[0052] Step 3: Select the appropriate ROM size based on the configuration information.

[0053] Step 4: Complete the integration of the processor module.

[0054] Step 5: Based on the cache structure type, select either the IOCP structure or the CCI structure, and integrate the CCI module into the cache processing subsystem. For example, if the processor achieves cache coherency through IOCP, the CCI module is not integrated into the cache processing subsystem. If the processor achieves cache coherency through CCI, the CCI module is integrated into the cache processing subsystem.

[0055] Step 6: Based on the number of master and slave devices, complete the integration of the bridging module in the cache processing subsystem.

[0056] Step 7: The above steps complete the integration of the processor system. Subsequently, the processor system can be integrated with external devices such as PCIe and DDR into the chip to achieve more complex functions.

[0057] The processor system provided in this embodiment includes a processor module and a cache processing subsystem. The processor module includes a processor, and the cache processing subsystem includes a bridging module and a CCI module. The bridging module is used to implement data transmission between the processor and external devices. The CCI module is optionally integrated into the cache processing subsystem depending on the processor's cache coherency handling method. Thus, by adding a CCI module as an option to the cache processing subsystem of the processor system, and by selecting whether to integrate the CCI module or not based on the processor's cache coherency handling method, the system can adapt to the integration of processors with different cache coherency handling methods. This improves integration flexibility, reduces complexity, and also enhances system stability and maintainability.

[0058] This application also provides a chip that includes the processor system provided in this application. In some embodiments, this chip can be a System-on-a-Chip (SoC), specifically a RISC-V based SoC. The processor in the SoC can be a RISC-V processor. RISC-V based SoCs not only perform basic instruction calculations and control, but also play a crucial role in trusted encryption through extensions such as vector K. Furthermore, their customizability and scalability ensure lower power consumption and performance in scenarios with the same functionality, demonstrating significant advantages in SoC chip design.

[0059] This application also provides an electronic device, which includes the chip provided in this application.

[0060] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

[0061] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0062] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0063] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0064] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

Claims

1. A processor system, comprising: A processor module, including a processor, for implementing the processor's computational and control functions; The cache processing subsystem is connected to the processor module and is used to implement cache consistency functionality. The cache processing subsystem includes a bridging module and a CCI module. The bridging module is used to realize data transmission between the processor and external devices. The CCI module can be optionally integrated into the cache processing subsystem depending on the processor's cache consistency processing method.

2. In the processor system as described in claim 1, when the processor handles cache coherency in a first manner, the CCI module is not integrated into the cache processing subsystem, and the first manner includes achieving cache coherency through IOCP.

3. In the processor system as described in claim 1, when the processor handles cache coherency in a second manner, the CCI module is integrated into the cache processing subsystem, and the second manner includes achieving cache coherency through CCI.

4. The processor system according to any one of claims 1 to 3, wherein the bridging module is connected to the external device, the DDR module and the PCIe module, the DDR module is used to store data, and the PCIe module is used by the external device to access the processor or the DDR module.

5. In the processor system of claim 4, if the CCI module is not integrated into the cache processing subsystem, the bridging module is also connected to the IOCP in the processor, and the external device accesses the processor through the PCIe module, the bridging module and the IOCP, or the external device accesses the DDR module through the PCIe module and the bridging module.

6. In the processor system of claim 4, when the CCI module is integrated into the cache processing subsystem, the CCI module is connected to the external device, the DDR module and the PCIe module, and is connected to the processor module through the bridging module. The external device accesses the processor through the PCIe module, the CCI module and the bridging module, or the external device accesses the DDR module through the PCIe module and the bridging module.

7. The processor system as described in claim 1, wherein the processor system is a master-slave architecture or a multi-master-multi-slave architecture.

8. The processor system of claim 1, comprising at least one of the following: The number of processors is one or more, and each processor includes one or more cores; The processor includes a processor based on the RISC-V instruction set architecture; The processor module further includes at least one of the following: an interrupt handling submodule, a debug submodule, and a cross-clock domain submodule.

9. The processor system of claim 1, further comprising: The ROM module, connected to the processor module, is used to store the processor's related instructions; A clock reset module, connected to the processor module, is used to provide the clock and reset control signals required by the processor.

10. A chip comprising the processor system according to any one of claims 1 to 9.

11. An electronic device comprising the chip of claim 10.

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