Structure of trench-gate power mosfet, and method for manufacturing trench-gate power mosfet

Abstract

Disclosed in the present application are a structure of a trench-gate power MOSFET and a method for manufacturing a trench-gate power MOSFET. The structure comprises: a second epitaxial layer; a strip-shaped P-pillar, the lengthwise direction of which is parallel to the projection direction, on the surface of an epitaxial material, of a crystal orientation with the most obvious channel effect; a trench gate, which comprises a trench, wherein the trench is parallel to the lengthwise direction of the strip-shaped P-pillar or is perpendicular to the lengthwise direction of the strip-shaped P-pillar, the trench is filled with a filler to form the trench gate, and when the lengthwise direction of the trench is parallel to the lengthwise direction of the strip-shaped P-pillar, the trench is located directly above the strip-shaped P-pillar, and the width of the trench is consistent with the width of the strip-shaped P-pillar, and when the lengthwise direction of the trench is perpendicular to the lengthwise direction of the strip-shaped P-pillar, the width of the trench is unrelated to the width of the strip-shaped P-pillar; and a surface source region. The present application has the advantages of reducing manufacturing steps and simplifying the processing technology.

Description

A structure and manufacturing method of a trench gate power MOSFET Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a structure of a trench gate power MOSFET and a method for manufacturing a trench gate power MOSFET. Background Technology

[0002] Silicon carbide (SiC) MOSFET devices are widely used in high-voltage power electronic equipment due to their high voltage withstand capability, low loss, and high efficiency. Currently, SiC power devices are mainly positioned for applications with power outputs between 1kW and 500kW and operating frequencies between 10kHz and 100MHz, particularly in applications with high energy efficiency and space requirements, such as electric vehicle on-board chargers and drive systems, charging piles, photovoltaic micro-inverters, and electric vehicles. The use of SiC MOSFETs to replace silicon IGBTs is an inevitable trend in the development of electric drive systems. Most electric vehicles launched in recent years have adopted electric drive and control systems based on SiC power devices.

[0003] Silicon carbide (SiC) MOSFET devices are mainly divided into planar gate MOSFETs and trench gate MOSFETs. Planar gate MOSFETs have a simpler fabrication process and higher maturity, making them the primary structure for mass-produced SiC MOSFETs. However, with increasing demands for device performance and cost, the larger cell size and higher JFET region resistance of planar gate SiC MOSFETs limit further optimization. In contrast, trench gate SiC MOSFETs, by introducing a trench structure, change the direction of channel current flow, eliminating the performance and cell size limitations of the JFET region, and thus possess greater development potential. The latest generation of trench gate SiC MOSFETs has shown significant performance improvements.

[0004] Furthermore, with the continuous maturation of SiC device technology and fabrication processes, combining trench gate structures and the charge balance concept (superjunction) to form trench-gate SiC MOSFETs with superjunction structures will be the ultimate goal of SiC MOSFET device development. Currently, the mainstream superjunction implementation schemes in SiC devices include: 1) deep trench etching combined with Al ion implantation on the trench sidewalls; 2) deep trench etching combined with P-type epitaxial backfilling; 3) high-energy Al ion implantation combined with multiple epitaxial growth, etc. All of the above schemes suffer from increased fabrication difficulty and low mass production feasibility. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this application provides a structure of a trench gate power MOSFET, a trench gate power MOSFET chip, and a method for manufacturing a trench gate power MOSFET.

[0006] First, this application provides a structure for a trench gate power MOSFET, including a substrate, a first epitaxial layer, a P-body region, and further comprising:

[0007] The second epitaxial layer, wherein the P-body region is located on the upper part of the surface layer of the second epitaxial layer;

[0008] A strip-shaped P-pillar, the length direction of which is parallel to the projection direction of the crystal orientation in which the channel effect is most obvious on the surface of the epitaxial material, and the depth of which penetrates the P-body region and the second epitaxial layer to reach the first epitaxial layer;

[0009] A trench grid includes a trench that is parallel to or perpendicular to the length direction of the strip-shaped P-pillar. The depth of the trench penetrates the P-body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench grid.

[0010] The surface source region is located on the surface of the P-body region and further includes a surface N++ region and a surface P++ region, which are spaced apart and whose length direction is perpendicular to the length direction of the trench.

[0011] In the above structure, the second epitaxial layer is formed on the upper half of the first epitaxial layer by ion implantation. The ion implantation method includes at least one high-energy ion implantation or channel implantation, and the channel implantation direction is the direction in which the channel effect of the epitaxial material is most obvious.

[0012] In the above structure, when the length direction of the groove is parallel to the length direction of the strip P column, the groove is located directly above the strip P column and its width is the same as the width of the strip P column. Below the surface P++ region, there is also a P connector with the same width as it. One end of the P connector is electrically connected to the surface P++ region and the other end is electrically connected to the strip P column.

[0013] In the above structure, when the length direction of the groove is perpendicular to the length direction of the strip P column, the width of the strip P column is the same as the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P column.

[0014] In the above structure, the orthographic projection of the second epitaxial layer onto the first epitaxial layer completely covers the first epitaxial layer, or only covers the region designated as the active region of the chip.

[0015] In the above structure, the P-connector is formed by at least one high-energy injection.

[0016] In the above structure, a P-type doped bottom protection zone is also formed at the bottom of the trench gate. The bottom protection zone is formed after the trench is etched and before the trench is filled.

[0017] Secondly, this application also provides a trench gate power MOSFET chip having the structure of a trench gate power MOSFET as described above.

[0018] Finally, this application also provides a method for manufacturing a trench gate power MOSFET, for manufacturing the above-mentioned trench gate power MOSFET chip, comprising the following steps:

[0019] To form a second epitaxial layer, N-type ions are implanted into the first epitaxial layer containing N-type SiC epitaxial material once or multiple times by ion implantation, thereby forming a uniformly doped second epitaxial layer.

[0020] To form a strip-shaped P-pillar, P-type ions are implanted into the second epitaxial layer once or multiple times. The implantation direction is the direction in which the channel effect of the epitaxial material is most obvious, and the implantation depth penetrates the second epitaxial layer to reach the first epitaxial layer, thereby forming the strip-shaped P-pillar.

[0021] A P-body region is formed by repeatedly implanting P-type ions into the surface of the second epitaxial layer, thereby forming the P-body region in the upper part of the second epitaxial layer.

[0022] Source surface implantation involves injecting high-concentration P-type ions and high-concentration N-type ions at intervals above the P-body region to form strip-shaped surface N++ regions and surface P++ regions that appear at intervals. The length directions of the surface N++ regions and surface P++ regions are perpendicular or parallel to the length direction of the strip-shaped P-pillars.

[0023] Etch gate trenches in a direction parallel or perpendicular to the length direction of the strip-shaped P pillar, and etch to a depth that penetrates the surface N++ region, the surface P++ region, and the P-body region to reach the second epitaxial layer.

[0024] A trench grid is fabricated by filling the trenches with a filler material to obtain the trench grid.

[0025] In the above manufacturing method, the ion implantation method includes at least one high-energy ion implantation or channel implantation, wherein the direction of the channel implantation is the direction in which the channel effect of the epitaxial material is most obvious.

[0026] In the above manufacturing method, when the length direction of the groove is parallel to the length direction of the strip P-post, the groove is located directly above the strip P-post and its width is the same as the width of the strip P-post. Below the surface P++ region, there is also a P-connector with the same width as it. One end of the P-connector is electrically connected to the surface P++ region and the other end is electrically connected to the strip P-post.

[0027] In the above manufacturing method, when the length direction of the groove is perpendicular to the length direction of the strip P-post, the width of the strip P-post is the same as the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P-post.

[0028] In the above manufacturing method, the orthographic projection of the second epitaxial layer onto the first epitaxial layer completely covers the first epitaxial layer, or only covers the region designated as the active region of the chip.

[0029] The manufacturing method described above also includes etching the gate trench and then performing ion implantation on the bottom surface of the trench to form a trench bottom protection zone.

[0030] Compared with existing technologies, this application simultaneously improves both the device structure and the manufacturing method. Structurally, this application proposes that the strip P-pillar structure does not need to be located at the bottom of the trench parallel to the trench direction, and can even intersect the trench direction at 90°, thus allowing the strip P-pillar design and trench design to be independent. In other words, the width of the strip P-pillar and the width of the trench can be designed independently according to their respective design requirements, maximizing the potential of the superjunction structure and the trench gate structure.

[0031] Methodologically, this application breaks away from the existing "bottom-planting" approach and proposes a process method of implanting first and then etching. This method makes the P-pillar structure design independent of trench design and etching processes. Furthermore, when ion implantation is performed at the bottom of the trench, the implanted ions inevitably end up on the sidewalls of the trench. However, by adopting the implantation-first-then-etching process method, the problems affecting the doping concentration in the bulk region and the device threshold voltage can be completely solved, thereby optimizing device design and improving device performance. Attached Figure Description

[0032] Figure 1 shows a schematic diagram of the basic materials for fabricating trench gate power SiC MOSFETs according to some embodiments of this application;

[0033] Figure 2a shows a schematic diagram of a second epitaxial layer for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0034] Figure 2b shows a schematic diagram of another second epitaxial layer structure for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0035] Figure 3 shows a schematic diagram of the structure of a strip P-pillar for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0036] Figure 4 shows a schematic diagram of the P-body region for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0037] Figure 5 shows a schematic diagram of the structure of the P-connector for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0038] Figure 6 shows a schematic diagram of the surface source region for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0039] Figure 7 shows a schematic diagram of the trench structure for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0040] Figure 8a shows a schematic diagram of the structure of the trench bottom protection zone for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0041] Figure 8b shows a schematic cross-section of the structure shown in Figure 8a according to some embodiments of this application;

[0042] Figure 9 illustrates a schematic diagram of the inner wall deposition for fabricating a trench gate power SiC MOSFET according to some embodiments of this application;

[0043] Figure 10 illustrates a schematic diagram of variations in the filling deposition for fabricating trench gate power SiC MOSFETs according to some embodiments of this application;

[0044] Figure 11 shows a schematic diagram of the trench structure for fabricating a trench gate power SiC MOSFET according to some other embodiments of this application;

[0045] Figure 12 shows a schematic diagram of another strip P-pillar structure for fabricating a trench gate power SiC MOSFET according to some other embodiments of this application;

[0046] Figure 13 shows a schematic diagram of the surface source region and strip P-pillar of another trench gate power SiC MOSFET according to some other embodiments of the present application;

[0047] Figure 14 shows a schematic diagram of the trench and trench bottom protection zone for fabricating another trench gate power SiC MOSFET according to some other embodiments of this application;

[0048] Figure 15 shows a flowchart of a method for fabricating a trench gate power SiC MOSFET device according to some embodiments of this application. Detailed Implementation

[0049] Various exemplary embodiments, features, and aspects of this application will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0050] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise explicitly specified, "multiple" means two or more.

[0052] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0053] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0054] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist.

[0055] In addition, the term "at least one" in this document means any combination of at least two of any one or more of a plurality of elements, such as including at least one of A, B, and C, and may mean including any one or more elements selected from the set consisting of A, B, and C.

[0056] Furthermore, to better illustrate this application, numerous specific details are provided in the following detailed description. Those skilled in the art should understand that this application can be implemented without certain specific details. In some instances, methods, means, components, and circuits well-known to those skilled in the art have not been described in detail in order to highlight the main points of this application.

[0057] The following section will first describe a method for manufacturing a trench gate power MOSFET, using Figures 1-10 and 15, and the structural changes of the trench gate power MOSFET after each manufacturing step.

[0058] As shown in Figure 1, the epitaxial material to be processed includes a SiC substrate 1 and a first epitaxial layer 2. The first epitaxial layer 2 is a lightly doped epitaxial layer formed on the SiC substrate 1 by an epitaxial growth process. In this embodiment, the doping type of the first epitaxial layer 2 is N-type ion doping.

[0059] Step S1: Forming the second epitaxial layer. In some embodiments, N-type ions, such as phosphorus (P) ions, can be implanted once or multiple times into the N-type SiC epitaxial material having the first epitaxial layer 2, thereby forming a uniformly doped second epitaxial layer 3 in the upper half of the first epitaxial layer 2. The thickness of the second epitaxial layer 3 is greater than that of the first epitaxial layer 2. The implantation method can be high-energy ion implantation or channel implantation (or tunnel implantation). The N-type ion concentration in the second epitaxial layer 3 is greater than that in the first epitaxial layer 2. Typically, as shown in Figure 2a, the orthogonal projection of the second epitaxial layer 3 onto the first epitaxial layer 2 completely covers the first epitaxial layer 2. Another preferred embodiment is shown in Figure 2b, where the orthogonal projection of the second epitaxial layer 3 onto the first epitaxial layer 2 may only cover a portion of the active region of the chip. In some embodiments, the depth of the second epitaxial layer 3 may be much greater than the implantation depth achievable by conventional ion implantation; therefore, a channel implantation method can be used, i.e., the implantation direction is the direction in which the channel effect of the epitaxial material is most pronounced. This direction is typically parallel to a specific crystal orientation of the epitaxial material. The depth of the second epitaxial layer formed by this method can be 2-5 micrometers, with a doping concentration of 3E16 to 2E17. In a preferred embodiment, after channel implantation, the thickness of the second epitaxial layer 3 is 3-4 micrometers, with a doping concentration of 6E16 to 8E16. The thickness of the second epitaxial layer 3 can also be understood as the implantation depth during channel implantation, and its effect is to increase the ion concentration in the upper half of the first epitaxial layer 2. Specifically, the doping depth of the second epitaxial layer 3 is determined by the highest energy selected during channel implantation, the doping distribution is uniform, and the doping concentration is determined by the implantation dose.

[0060] Step S2: Forming strip-shaped P-pillars 6. The length direction of the strip-shaped P-pillars 6 is parallel to the projection direction of the crystal orientation where the channel effect is most pronounced on the surface of the second epitaxial layer 3. The strip-shaped P-pillars 6 can be formed by implanting P-type ions into the second epitaxial layer 3 once or more. The P-type ions can be aluminum (Al) ions or boron (B) ions, and the implantation direction is the direction where the channel effect is most pronounced. The depth of the strip-shaped P-pillars 6 can approach or even exceed the thickness of the second epitaxial layer 3, penetrating into the first epitaxial layer 2. Figure 3 shows an example of strip-shaped P-pillars 6 penetrating into the first epitaxial layer 2. The depth of the strip-shaped P-pillars 6 formed by this method can be 2-5 micrometers, with a doping concentration of 5E16 to 3E17. In a preferred embodiment, after channel implantation, the thickness of the strip-shaped P-pillars 6 is 3-4 micrometers, with a doping concentration of 1E17 to 2E17.

[0061] Step S3: Forming the P-body region. As shown in Figure 4, a P-body region 4 is also formed inside the second epitaxial layer 3. The P-body region 4 can be formed by ion implantation and is located in the upper middle part of the second epitaxial layer 3. The impurities doped in the P-body region 4 are P-type dopants, such as aluminum (Al) ions, with a specific doping concentration of approximately 1E17-5E17 and an implantation depth of 0.2-1.0 micrometers.

[0062] After step S3, there are two different unit cell structures. One structure has elongated trenches parallel to and above the strip-shaped P-pillars 6, with the trench width matching the width of the strip-shaped P-pillars 6. The other structure has elongated trenches perpendicular to and orthogonal to the strip-shaped P-pillars 6, with their widths independent of each other. Both structures require additional trench bottom implantation to suppress electric field concentration at the trench bottom corners. Furthermore, the highly doped P-type and N-type source regions on the epitaxial surface are always arranged perpendicularly to and orthogonal to the trench direction.

[0063] The following steps S4a-S5a illustrate the first structure, namely the scheme where the trench is parallel to the P-pillar. Schematic diagrams of the relevant structural variations can be found in Figures 5-8b.

[0064] Step S4a, source surface implantation. The goal of this step is to implant high-concentration P-type ions and high-concentration N-type ions at intervals on the surface portion of the second epitaxial layer 3 above the P-body region 4, thereby forming strip-shaped surface N++ regions 5a and surface P++ regions 5b that appear at intervals and intersect perpendicularly to the strip-shaped P-pillars 6, as shown in Figure 6. Both of these regions are heavily doped.

[0065] Specifically, including:

[0066] 1) As shown in Figure 5, high-energy ion implantation is performed at the location where the surface P++ region 5b will be formed to create a P-connector 11. The concentration of the P-connector 11 is generally significantly higher than that of the P-body region 4, and comparable to the concentration of the P-type protected area at the bottom of the trench to be fabricated later. Furthermore, the implantation depth of the P-connector 11 is greater than the depth of the trench to be processed. After the trench etching is completed, the P-connector 11 maintains electrical connection with the P-type protected area at the bottom of the trench. The relationship between the depth of the P-connector 11 and the trench depth can be illustrated in Figure 8b. Figure 8b is a cross-sectional view at the location indicated by the green arrow in Figure 8a. As shown, the depth of the P-connector 11 needs to be greater than that of the trench 7 to connect with the protected area 8 at the bottom of the trench, so that the strip-shaped P-pillar 6 can achieve a reliable connection between the source and ground.

[0067] 2) Following Figure 5, ion implantation continues in the top region of the P-connector 11 to form a surface P++ region 5b with a doping concentration of P++ (meaning a higher concentration than that of the P-connector 11), as shown in Figure 6. Further, N-type ions are implanted in the surface source region 5, excluding the surface P++ region 5b, to form a surface N++ region 5a with a concentration of N++ (meaning a concentration comparable to that of the surface P++ region 5b). The depth of the surface P++ region 5b can be slightly greater than that of the surface N++ region 5a, meaning that the depth of the surface P++ region 5b can penetrate the surface source region 5 and reach the P-body region 4.

[0068] After performing step S4a above, the structure shown in Figure 6 is obtained. On the upper surface of the epitaxial material, blue regions with a concentration of P++ and red regions with a concentration of N++ alternately appear, forming surface N++ region 5a and surface P++ region 5b. The high-concentration N-type ion implantation depth reaches the P-body region 4. The length direction of surface N++ region 5a and surface P++ region 5b is perpendicular to the length direction of strip P pillar 6.

[0069] Step S5a: Etch gate trenches. The length direction of the gate trenches is perpendicular to the length directions of the surface N++ region 5a and the surface P++ region 5b. The etching depth penetrates the surface N++ region 5a and the surface P++ region 5b, as well as the P-body region 4, to reach the second epitaxial layer 3, but is shallower than the depth of the P-connector 11. That is, based on the structure shown in Figure 6, the length direction of the trench 7 is parallel to the length direction of the strip P-pillar 6, the trench 7 is located directly above the strip P-pillar 6, and its width is the same as the width of the strip P-pillar 6, as shown in Figure 7.

[0070] Furthermore, in this embodiment, P-type ions are injected again at the bottom of the trench 7 to form a trench bottom protection zone 8, thereby alleviating the problem of electric field concentration at the corner of the trench bottom (see Figures 8a and 8b). The ion concentration in the trench bottom protection zone 8 is higher than that in the strip P-pillar 6, and it is electrically connected to the strip P-pillar 6.

[0071] After etching groove 7, the device structure shown in Figure 8a is obtained. If a cross-section is taken at the location indicated by the green arrow in Figure 8a, the cross-sectional view shown in Figure 8b will be obtained. Comparing Figures 8a and 8b, it can be clearly seen that the P-connector 11 intersects with the strip-shaped P-pillar 6 in the second epitaxial layer 3.

[0072] Step S6: Fabricate the trench gate. As shown in Figures 9-10, GOX (Gate Oxide) is deposited on the inner wall of trench 7 to form an inner wall GOX deposition 9, as shown in Figure 9. Then, filler is added to trench 7 to form a POLY filler deposition 10 that fills trench 7. Polysilicon etch-back is then performed in local areas using photolithography to obtain the trench gate cell structure, as shown in Figure 10.

[0073] At this point, the manufacturing method of a trench gate power MOSFET is complete. Subsequent processes can include interlayer dielectric (ILD) deposition and etching, surface metal interconnection, passivation layer deposition and etching, backside thinning and laser annealing, etc.

[0074] In this embodiment, the trench injection method is used to manufacture the second epitaxial layer 3 and the strip P-pillars 6, which can achieve a deeper injection depth. When the strip P-pillars 6 are placed directly below the trench, the width of the strip P-pillars 6 is limited by the width of the trench 7. During the manufacturing process, the same mask can be used to manufacture the trench and the P-pillars, thereby reducing the mask fabrication and cleaning steps.

[0075] In another embodiment, the groove 7 can also be etched before manufacturing the strip-shaped P-pillar 6. Specifically, this includes the following steps:

[0076] The second epitaxial layer 3 is formed, and the specific formation method is the same as step S1, which will not be described in detail here.

[0077] The P-body region 4 and the surface source region 5 (including the surface N++ region 5a and the surface P++ region 5b) are formed by ion implantation. For details, please refer to steps S3 and S4a.

[0078] The P-connector 11 is formed by high-energy ion implantation, as detailed in step S4a.

[0079] Trench etching is a method of etching to form trenches. The length direction of the trench is parallel to the projection direction of the crystal orientation on the surface of the epitaxial material where the channel effect is most obvious, thereby forming the trench 7 shown in Figure 11.

[0080] P-type ion implantation is performed at the bottom of trench 7 along the crystal orientation where the epitaxial material channel effect is most pronounced, thereby forming strip-shaped P pillars 6 below the trench, as shown in Figure 12.

[0081] The above method can yield a structure with the same process steps as shown in Figures 1-7, and subsequent processing can continue as shown in Figures 8a-10. The difference between these two routes lies in whether trench etching is performed first and then P-pillar implantation is performed at the bottom, or P-pillar implantation is performed first and then trench etching.

[0082] Steps S4b-S5b illustrate the second structure, namely, the scheme where the trench is perpendicular to the P-pillar. In general, compared to the first structure, in the second structure, the P-shaped trench bottom protection zone 8 at the bottom of the trench is connected to the surface P++ region 5b via the strip-shaped P-pillar 6, thus directly electrically connecting to the source electrode, eliminating the need to fabricate the P-connector 11. The related structural changes can be understood by referring to Figures 1-4, 9-10, and 13-14.

[0083] Step S4b, source surface implantation. High-concentration P-type and N-type ions are implanted at intervals on the surface source region 5, thereby forming strip-shaped surface N++ regions 5a and surface P++ regions 5b that are parallel to the strip-shaped P pillars 6 and appear at intervals, as shown in Figure 13. The implanted region of P-type ions coincides with or is slightly larger than the width of the strip-shaped P pillars 6; that is, the width of the surface P++ region 5b is the same as the width of the strip-shaped P pillars 6.

[0084] Step S5b, as shown in Figure 14, involves etching the gate trench. Based on the surface N++ region 5a and surface P++ region 5b formed in step S4b, the length direction of the gate trench is perpendicular to the length directions of the surface N++ region 5a and surface P++ region 5b. The etching depth penetrates the surface N++ region 5a and surface P++ region 5b, as well as the P-body region 4, to reach the second epitaxial layer 3. In this embodiment, the length direction of the trench 7 is perpendicular to the length direction of the strip-shaped P-pillar 6, and its width is independent of the strip-shaped P-pillar 6. The trench width and the P-pillar width can be designed independently to better leverage the performance advantages of this structure.

[0085] Similar to step S5a, P-type ions are also injected again into the bottom of the trench 7 to form a trench bottom protection zone 8, which is used to suppress the phenomenon of electric field intensity concentration at the corner of the trench bottom.

[0086] Step S6: Fabricate the trench gate. This step has been described in detail above and will not be repeated here.

[0087] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A structure of a trench-gate power MOSFET, characterized by, Including a substrate, a first epitaxial layer, a P-body region, and also: The second epitaxial layer, wherein the P-body region is located in the upper middle part of the second epitaxial layer; The strip-shaped P-pillar has a length direction parallel to the projection direction of the crystal orientation where the channel effect is most obvious on the surface of the epitaxial material, and the depth of the strip-shaped P-pillar penetrates the P-body region and approaches or exceeds the second epitaxial layer. A trench grid includes a trench that is parallel to or perpendicular to the length direction of the strip-shaped P-pillar. The depth of the trench penetrates the P-body region to reach the second epitaxial layer, and a filler is filled into the trench to manufacture the trench grid. The surface source region is located on the surface of the P-body region and further includes a surface N++ region and a surface P++ region, which are spaced apart and whose length direction is perpendicular to the length direction of the trench.

2. The trench-gated power MOSFET structure of claim 1, wherein, The second epitaxial layer is formed on the upper half of the first epitaxial layer by ion implantation. The ion implantation method includes at least one high-energy ion implantation or channel implantation, wherein the channel implantation direction is the direction in which the channel effect of the epitaxial material is most obvious.

3. The trench-gated power MOSFET structure of claim 1, wherein, When the length direction of the groove is parallel to the length direction of the strip P-post, the groove is located directly above the strip P-post and its width is the same as the width of the strip P-post. Below the surface P++ region, there is also a P-connector with the same width as it. One end of the P-connector is electrically connected to the surface P++ region and the other end is electrically connected to the strip P-post.

4. The trench gate power MOSFET structure of claim 1, wherein, When the length direction of the groove is perpendicular to the length direction of the strip P-post, the width of the strip P-post is the same as the width of the surface P++ region, and the surface P++ region is electrically connected to the strip P-post.

5. The trench gate power MOSFET structure of claim 2, wherein, The orthographic projection of the second epitaxial layer onto the first epitaxial layer completely covers the first epitaxial layer, or only covers the region designated as the active area of ​​the chip.

6. The trench gate power MOSFET structure of claim 3, wherein, The P-connector is formed by at least one high-energy injection.

7. The trench gate power MOSFET structure of claim 1, wherein, The bottom of the trench gate also has a P-type doped trench bottom protection zone, which is formed after the trench is etched out and before the trench is filled.

8. A trench-gated power MOSFET chip, characterized by, It has the structure of a trench gate power MOSFET as described in any one of claims 1-7.

9. A method of manufacturing a trench gate power MOSFET chip, characterized by, The method for manufacturing the trench gate power MOSFET chip as described in claim 8 includes the following steps: To form a second epitaxial layer, N-type ions are implanted into the first epitaxial layer containing N-type SiC epitaxial material once or multiple times by ion implantation, thereby forming a uniformly doped second epitaxial layer. To form a strip-shaped P-pillar, P-type ions are implanted into the second epitaxial layer once or multiple times. The implantation direction is the direction in which the channel effect of the epitaxial material is most obvious, and the implantation depth penetrates the second epitaxial layer to reach the first epitaxial layer, thereby forming the strip-shaped P-pillar. A P-body region is formed by repeatedly implanting P-type ions into the surface of the second epitaxial layer, thereby forming the P-body region in the upper part of the second epitaxial layer. source surface implant, implanting high-concentration P-type ions and high-concentration N-type ions above the P body region to form surface N++ regions and surface P++ regions in the form of spaced-apart strips, the length direction of the surface N++ regions and the surface P++ regions being perpendicular or parallel to the length direction of the strip-shaped P pillars; gate trench etching, etching a trench in a direction parallel or perpendicular to the length direction of the strip-shaped P pillars, the etching depth being such that the surface N++ regions and the surface P++ regions and the P body region are penetrated to reach the second epitaxial layer; trench gate fabrication, filling the trench with a filler to obtain the trench gate.

10. The production method according to claim 9, wherein The ion implantation method includes at least one high-energy ion implantation or channel implantation, the direction of the channel implantation being the direction in which the channel effect of the epitaxial material is most obvious.

11. The production method according to claim 9, wherein When the length direction of the trench is parallel to the length direction of the strip-shaped P pillars, the trench is located directly above the strip-shaped P pillars and has a width consistent with that of the strip-shaped P pillars, and the surface P++ region further includes a P connector having a width consistent with that of the surface P++ region, one end of the P connector being in electrical communication with the surface P++ region and the other end being in electrical communication with the strip-shaped P pillars.

12. The production method according to claim 9, wherein When the length direction of the trench is perpendicular to the length direction of the strip-shaped P pillars, the width of the strip-shaped P pillars is consistent with that of the surface P++ region, and the surface P++ region is in electrical communication with the strip-shaped P pillars.

13. The production method according to claim 9, wherein The second epitaxial layer has a normal projection on the first epitaxial layer that completely covers the first epitaxial layer or only covers a region that is predetermined as an active region of a chip.

14. The production method according to claim 9, wherein Further comprising, after the gate trench etching, performing ion implantation on the bottom surface of the trench to form a trench bottom protection region.

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