Chip and electronic device

Abstract

Provided are a chip and an electronic device, which relate to the technical field of chips. The chip has a first region and a second region. The chip comprises a plurality of cores and a plurality of power supply circuits, wherein each power supply circuit comprises a power stage circuit and a control stage circuit connected to the power stage circuit. A plurality of processor cores are respectively connected to the plurality of power supply circuits on a one-to-one basis; and the plurality of processor cores are all disposed in the first region. The control stage circuits of the plurality of power supply circuits are all located in the second region, and the power stage circuits of the plurality of power supply circuits are all disposed in the first region; and the power stage circuit of each power supply circuit is disposed around the corresponding processor core while leaving an opening.

Description

Chips and electronic devices Technical Field

[0001] This application relates to the field of chip technology, and more particularly to a chip and an electronic device. Background Technology

[0002] A multi-core architecture is a computer architecture that integrates multiple processor cores onto a single chip. Each core can execute instructions independently, significantly improving computing performance, parallel processing capabilities, and energy efficiency. In current multi-core architectures, multiple cores share the same power supply circuit, and each core operates at the same voltage. As the load on a core increases, the required operating voltage also increases. When the load on each core differs, to meet the operating voltage requirement of the core with the highest load (maximum operating voltage), each core operates at its maximum voltage. This results in lower-load cores still operating at their maximum voltage, wasting power and increasing the overall power consumption of the multi-core architecture.

[0003] To reduce power consumption, heterogeneous power supply technology has become a research hotspot in recent years. This technology integrates on-chip power supply circuitry for each core, allowing for the setting of appropriate operating voltages based on each core's operating state, thus significantly reducing power consumption. However, the layout of the power supply circuitry in heterogeneous power supply technology can lead to high current-resistance voltage drop (IR drop) and can also disrupt inter-core communication, thereby affecting core performance. Summary of the Invention

[0004] This application provides a chip and electronic device that, by adjusting the layout of the power supply circuit, can balance IR drop and inter-core communication to improve core performance.

[0005] This application provides a chip having a first region and a second region. The chip includes multiple processor cores (hereinafter referred to as cores) and multiple power supply circuits. Each power supply circuit includes a power stage circuit and a control stage circuit connected to the power stage circuit. The multiple processor cores are connected one-to-one with the multiple power supply circuits. All processor cores are located in the first region. The control stage circuits in the multiple power supply circuits are located in the second region. The power stage circuits of the multiple power supply circuits are all located in the first region, with each power stage circuit surrounding its corresponding processor core and having an opening.

[0006] Because the power stage circuitry has openings, communication paths between cores can be reserved in the opening areas, ensuring interconnection and communication between different cores and meeting the communication requirements of multi-core architectures. On the other hand, the power stage circuitry is positioned around the core, providing a power path along most of the area surrounding the core (i.e., outside the openings), thus minimizing IR drop. In other words, it balances IR drop and inter-core communication, thereby improving core performance.

[0007] In some possible implementations, the power stage circuitry and the corresponding processor core reside in the same circuit layout. This ensures a small distance between the power stage circuitry and the core, thereby reducing chip area overhead. Furthermore, the power stage circuitry and the corresponding processor core can be fabricated using a digital process based on standard cells, saving design time and manpower while maintaining performance, resulting in a low-cost advantage.

[0008] In some possible implementations, the distance between the processor core and the corresponding power stage circuitry in the first region is less than 10 μm. That is, there is a very small gap between the processor core and the power stage circuitry, thereby reducing the power supply footprint.

[0009] In some possible implementations, the control stage circuit includes a reference circuit and an error amplifier circuit connected to the reference circuit, with the error amplifier circuit also connected to the power stage circuit. The error amplifier circuit controls the power stage circuit based on the reference voltage provided by the reference circuit and the output voltage provided by the power stage circuit. Multiple control stage circuits share the same reference circuit. By having multiple control stage circuits share the same reference circuit, circuit design can be simplified and the power supply footprint reduced.

[0010] In some possible implementations, different processor cores are connected through open areas. That is, communication channels are formed between different cores in these open areas, thus enabling interconnection and communication between multiple cores.

[0011] In some possible implementations, the power stage circuit is connected to the control stage circuit via two ends forming an opening. This allows the control stage circuit to adjust the output of the power stage circuit based on a negative feedback mechanism formed at the output of the power stage circuit.

[0012] In some possible implementations, the control stage circuit and the power stage circuit are connected via two control lines, with signal transmission rates on these lines less than 10MHz. In other words, the control stage circuit and the power stage circuit are connected via two low-speed control lines. Using low-speed control lines has the advantage of strong anti-interference capability, effectively resisting noise coupled through the physical parasitic capacitance AC (alternating current) of high-speed communication lines between cores.

[0013] In some possible implementations, openings in multiple power stage circuits are positioned in adjacent areas of multiple processor cores. That is, multiple openings are positioned towards the central area of ​​multiple cores, allowing the corresponding cores to be connected via shorter communication lines, thereby improving core performance.

[0014] In some possible implementations, the aforementioned multiple processor cores are heterogeneous cores. In this case, the multiple processor cores can be various different types of computing cores integrated on the same processor chip, each core optimized for a specific task. This setup can improve the overall performance and energy efficiency of the processor, especially when handling diverse workloads.

[0015] In some possible implementations, the openings in the aforementioned power stage circuits are arranged adjacent to each other. In this case, the openings of the multiple power stage circuits are located in a neighboring (or intermediate) region between multiple cores. This allows the corresponding multiple cores to be connected through the openings with shorter communication lines, thereby improving core performance.

[0016] In some possible implementations, the power supply circuit includes a low dropout regulator (LDO), which has advantages such as low dropout characteristics, low noise output, and fast response.

[0017] In some possible implementations, the low-dropout regulator includes an input voltage terminal and an output voltage terminal; the control stage circuit includes a reference circuit and an error amplifier circuit; and the power stage circuit includes a power transistor. The input terminal of the reference circuit is connected to the input voltage terminal, the output terminal of the reference circuit is connected to the first input terminal of the error amplifier circuit, and the second input terminal of the error amplifier circuit is connected to the output voltage terminal; the power supply terminal of the error amplifier circuit is connected to the input voltage terminal; the output terminal of the error amplifier circuit is connected to the gate of the power transistor; the first stage of the power transistor is connected to the input voltage terminal, and the second stage of the power transistor is connected to the output voltage terminal; one of the first and second stages is the source, and the other is the drain.

[0018] In some possible implementations, the power supply circuit includes a BUCK circuit, which, as a step-down switching power supply, has advantages such as high efficiency, strong step-down capability, small size, and fast dynamic response.

[0019] In some possible implementations, the power supply circuit includes a switched capacitor converter (SC), which has advantages such as high efficiency, small size, and flexible design.

[0020] This application also provides an electronic device, which further includes a circuit board and a chip as provided in any of the aforementioned possible implementations, and the circuit board is connected to the chip. Attached Figure Description

[0021] Figure 1 is a circuit layout diagram of a chip provided in the related art;

[0022] Figure 2 shows a circuit layout diagram of another chip provided in the related art;

[0023] Figure 3 shows a circuit layout diagram of another chip provided in the related art;

[0024] Figure 4 is a schematic diagram of the circuit structure in a chip provided in an embodiment of this application;

[0025] Figure 5 is a schematic diagram of a power supply circuit provided in an embodiment of this application;

[0026] Figure 6 is a circuit diagram of a power supply circuit provided in an embodiment of this application;

[0027] Figure 7 is a circuit layout diagram of a chip provided in an embodiment of this application;

[0028] Figure 8 is a circuit layout diagram of a chip provided in an embodiment of this application;

[0029] Figure 9 is a partial circuit layout diagram of a chip provided in an embodiment of this application;

[0030] Figure 10 is a schematic diagram of a power supply circuit provided in an embodiment of this application;

[0031] Figure 11 is a schematic diagram of a power supply circuit provided in an embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for distinguishing purposes only and should not be construed as indicating or implying relative importance or order. "At least one" means one or more, and "more" means two or more. "Connected," "linked," etc., should be interpreted broadly, for example, as an electrical connection or a mechanical connection; a fixed connection or a detachable connection or an integral connection; a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. "Upper," "lower," "left," "right," etc., are used only with respect to the orientation of components in the drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0034] This application provides an electronic device that employs a multi-core architecture chip. By adjusting the layout of the power supply circuit, the chip can balance IR drop and inter-core communication, thereby improving core performance.

[0035] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product with a chip, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronics, etc.

[0036] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, storage devices, radar, base stations, and other communication equipment.

[0037] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the chip, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0038] The following describes in detail the chip provided in the embodiments of this application, in conjunction with relevant technologies.

[0039] Figure 1 is a circuit layout diagram of a chip provided in the related art.

[0040] Referring to Figure 1, in some chips, the power supply circuit 10 is distributed around the core 20. In this arrangement, since the power supply circuit 10 is a ring structure, the power supply circuit 10 supplies power through multiple paths around the core 20, which has the advantage of small IR drop. However, the power supply circuit 10 will block the interconnection communication between multiple cores, so it is not suitable for multi-core architectures.

[0041] Figure 2 shows a circuit layout diagram of another chip provided in the related art.

[0042] Referring to Figure 2, in some chips, the power supply circuits 10 are distributed on the top and bottom sides of the core 20, while the left and right sides do not have power supply circuits 10. In this arrangement, multiple cores can interconnect and communicate through the sides (left and right sides) where no power supply circuits are provided. However, this area cannot provide a power supply path, especially for relatively large cores. Limited wiring resources will generate more IR drop, thereby limiting core performance (such as frequency).

[0043] Figure 3 shows a circuit layout diagram of another chip provided in the related art.

[0044] Referring to Figure 3, in some chips, multiple power supply circuits 10 are evenly distributed inside the core 20. In this arrangement, the multiple power supply circuits 10 will interrupt the communication lines inside the core 20, thereby limiting the core performance (such as frequency).

[0045] Based on this, this application provides a novel chip that can accommodate both IR drop and inter-core communication. Referring to Figure 4, the chip includes multiple power supply circuits 100 and multiple cores 200 (also referred to as processor cores), with each power supply circuit 100 connected to a corresponding core 200. Figure 4 is only an illustration using four power supply circuits 100 and four cores 200 as an example, but it is not limited to this.

[0046] This application does not restrict the configuration of multiple power supply circuits 100; in practice, they can be configured as needed.

[0047] As illustrated, in some possible implementations, the multiple power supply circuits 100 can be one or more of various power supply circuits such as LDO (low dropout regulator), BUCK circuit, and switched capacitor converter (SC). The following embodiments mainly use LDOs as an example to illustrate the multiple power supply circuits 100.

[0048] This application does not restrict the type of multiple core 200s; in practice, the configuration can be set as needed.

[0049] As illustrated, in some possible implementations, the aforementioned multiple cores 200 can be one or more logical units such as CPU (central processing unit), GPU (graphics processing unit), NPU (neural processing unit), SOC (system on chip), accelerator, etc.

[0050] Furthermore, the aforementioned multiple cores 200 can be cores of the same type or cores of different types, and this application does not impose any restrictions on this.

[0051] For example, in some possible implementations, the aforementioned multiple cores 200 can be heterogeneous cores. In this case, the multiple cores 200 can be various different types of computing cores integrated on the same processor chip, each core optimized for a specific task. This setup can improve the overall performance and energy efficiency of the processor, especially when handling diverse workloads.

[0052] For example, in some possible implementations, the multiple cores 200 mentioned above can be homogeneous cores. In this case, the multiple cores 200 can be cores of the same type, such as all being CPUs.

[0053] Based on this, referring to Figure 5, the power supply circuit 100 includes a control stage circuit 101 and a power stage circuit 102, which are connected to each other. Multiple power supply circuits 100 are respectively connected to multiple cores 200 one-to-one through the power stage circuits 102. In this case, the power supply circuit 100 can supply power to the corresponding core 200 through the power stage circuits 102.

[0054] As illustrated in Figure 5, the power stage circuit 102 is responsible for converting the input voltage into an output voltage. The power stage circuit may include a power transistor T (such as a PMOS transistor), which controls the output voltage by adjusting its on-state. The performance of the power stage circuit directly affects the output voltage stability and load regulation capability of the power supply circuit. Of course, depending on actual needs, the power stage circuit 102 may include other functional modules.

[0055] Referring to Figure 5, the control stage circuit 101 includes a reference circuit a1 and an error amplifier a2. The reference circuit a1 provides a stable reference voltage and current, while the error amplifier a2 compares the reference voltage with the output voltage to generate an error signal to adjust the output of the power stage circuit. Through a negative feedback mechanism, the error amplifier a2 ensures that the output voltage remains near the set value. Of course, the control stage circuit 101 may also include other auxiliary circuits depending on actual needs.

[0056] Schematic, referring to Figure 6, in some LDOs, the control stage circuit 101 includes an input voltage terminal Vin, an output voltage terminal Vout, a reference circuit a1, and an error amplifier circuit a2. The power stage circuit 102 includes a power transistor T, which can be one or more, such as two or four. The input terminal of the reference circuit a1 is connected to the input voltage terminal Vin, the output terminal of the reference circuit a1 is connected to the first input terminal of the error amplifier circuit a2, and the second input terminal of the error amplifier circuit a2 is connected to the output voltage terminal Vout. The power supply terminal of the error amplifier circuit a2 is connected to the input voltage terminal Vin, providing a power supply voltage to the error amplifier circuit a2 through the input voltage terminal Vin. The output terminal of the error amplifier circuit a2 is connected to the gate of the power transistor T, the source (or drain) of the power transistor T is connected to the input voltage terminal Vin, and the drain (or source) of the power transistor T is connected to the output voltage terminal Vout.

[0057] In this case, the output terminal of the reference circuit a1 inputs a reference voltage to the first input terminal of the error amplifier circuit a2. The error amplifier circuit a2 compares the reference voltage input at the first input terminal with the output voltage terminal Vout at the second input terminal and generates an error signal to adjust the power transistor T. Through the negative feedback mechanism, it ensures that the voltage at the output voltage terminal Vout is kept near the set voltage value.

[0058] The following describes the actual layout of the multiple cores 200 and the corresponding multiple power supply circuits 100.

[0059] Schematic, referring to Figure 7, the chip may include a first region A1 and a second region A2, which are different layout and wiring regions within the chip. Multiple cores 200 are located in the first region A1, and the power stage circuits 102 of the multiple power supply circuits 100 are also located in the first region A1, with each power stage circuit 102 arranged around its corresponding core 200 and having an opening b. The control stage circuits 101 of the multiple power supply circuits 100 are all located in the second region A2. That is, the power stage circuits 102 adopt a distributed layout, while the control stage circuits 101 adopt a lumped layout.

[0060] Because the power stage circuit 102 adopts a ring-shaped structure with an opening b, communication paths between cores 200 can be reserved in the opening b region. This ensures that different cores 200 can communicate with each other through the opening b region, thus meeting the communication requirements of multi-core architectures. On the other hand, the power stage circuit 102 can provide a power supply path along most of the area surrounding the core 200, which can accommodate a smaller IR drop. That is, it can balance IR drop and inter-core communication, thereby improving core performance (such as frequency).

[0061] This application does not impose any restrictions on the position, size, or orientation of the opening b; in practice, it can be set according to the requirements.

[0062] As illustrated in Figure 8, in some possible implementations, in the first region A1, the openings b in the multiple power stage circuits 102 are respectively arranged in the adjacent region between the multiple cores 200. That is, the multiple openings b are arranged towards the middle region of the multiple cores 200. In this way, the corresponding multiple cores 200 can be connected to each other through the openings b with a shorter communication line, thereby improving core performance.

[0063] As illustrated in Figure 8, with the four cores 200 arranged in a matrix, the opening b in the upper left power stage circuit 102 is located at the lower right of the core 200, the opening b in the upper right power stage circuit 102 is located at the lower left of the core 200, the opening b in the lower left power stage circuit 102 is located at the upper right of the core 200, and the opening b in the lower right power stage circuit 102 is located at the upper left of the core 200. In other words, the openings b in the multiple power stage circuits 102 are positioned towards the central area between the multiple cores 200. This ensures a shorter communication path when the four cores 200 are interconnected through the openings b.

[0064] Furthermore, in existing chip layout design, the power supply circuit 100 and the core 200 are located in different layout circuits and distributed in different areas of the chip. The core 200 adopts a digital design flow based on standard cells, while the power supply circuit 100 adopts an analog circuit design flow. The analog back-end is designed manually, which requires a lot of time and manpower and is costly.

[0065] In contrast, in the chip provided in this application, the power stage circuit 102 and the core 200 can be designed in the same layout circuit (first layout circuit), while the control stage circuit 101 of the multiple power supply circuits 100 is set in a separate layout circuit (second layout circuit). In this case, the power stage circuit 102 and the core 200 can be fabricated based on standard cells through a digital process, which can save design time and manpower while ensuring performance, and has the advantage of low cost.

[0066] In this application, the multiple control-level circuits 101 located in the second region A2 are distributed in a lumped manner and set separately in another layout circuit (the second layout circuit). In this way, the power supply area occupied can be reduced, and the design complexity can be avoided by having the analog circuits in the second region A2 and the digital circuits in the first region A1 located in the same layout circuit, which would increase the design complexity.

[0067] It should be understood that during the design process, circuits within the same layout must adhere to the design rules of the manufacturing process and undergo verification through methods such as Design Rule Check (DRC) and Layout vs. Schematic (LVS) to ensure correctness. Furthermore, circuits within the same layout can maintain a minimum distance of one or more DRCs to save chip area.

[0068] Therefore, in this application, when the power stage circuit 102 and the core 200 are located in the same circuit layout, there is a very small gap between the power stage circuit 102 and the core 200. Illustrated, in some possible implementations, the distance between the power stage circuit 102 and the core 200 can be less than 10 μm, such as around 1 μm.

[0069] This application does not impose any restrictions on the specific location of the second area A2; in practice, it can be set as needed.

[0070] As illustrated in Figures 7 and 8, in some possible implementations, the second region A2 can be set outside the first region A1. In this way, the control level circuit 101 located in the second region A2 will not block the communication between cores, thereby better meeting the communication needs between cores and reducing design complexity.

[0071] In addition, for the multiple control-level circuits 101 in the second region A2, the multiple control-level circuits 101 can be independently set control circuits, or some circuit modules can be reused, thereby simplifying the circuit and saving chip area.

[0072] Schematic, referring to Figure 9, multiple control stage circuits (101a, 101b, 101c, 101d) can share the same reference circuit a1, each employing an independent error amplifier circuit a2. In this case, multiple independent error amplifier circuits a2 are connected to the same reference circuit a1. In this way, the multiple error amplifier circuits a2 can compare the reference voltage and current provided by the same reference circuit a1 and generate error signals to adjust the output of the power stage circuit 102 respectively, thereby meeting the power supply requirements of multiple cores.

[0073] By setting up multiple control-level circuits (101a, 101b, 101c, 101d) to share the same reference circuit a1, the circuit design can be simplified and the power supply area can be reduced.

[0074] Furthermore, this application does not impose any restrictions on the connection method between the power stage circuit 102 and the control stage circuit 101; in practice, it can be configured as needed.

[0075] Schematic, in some possible implementations, referring to Figure 7, the power stage circuit 102 can be connected to the control stage circuit 101 at its two ends forming the opening b; in this way, the control stage circuit 101 can adjust the output of the power stage circuit 102 by forming a negative feedback mechanism based on the output of the power stage circuit 102.

[0076] Based on this, referring to Figure 7, the control stage circuit 101 and the power stage circuit 102 can be connected via two low-speed control lines. Specifically, the control stage circuit 101 is connected to the power stage circuit 102 at both ends of opening b via two low-speed control lines, ensuring the required power supply voltage and current for the multi-core system. Using low-speed control lines offers the advantage of strong anti-interference capability, effectively resisting noise coupled through the physical parasitic capacitance AC (alternating current) of high-speed communication lines between cores.

[0077] As illustrated, the signal transmission rate on the two low-speed control lines mentioned above can be below 10MHz, but is not limited to this.

[0078] Furthermore, actual simulations have verified that, compared to the layout shown in Figure 3, the layout proposed in this application does not damage the internal wiring of the core and does not interrupt communication between cores, resulting in a core frequency gain of over 1.7%, i.e., a core performance gain of over 1.7%. Compared to multiple cores sharing a single power supply circuit, the energy consumption gain of the layout proposed in this application is over 3mAh.

[0079] The following is a brief explanation of other configurations for the power supply unit 100.

[0080] Schematic, referring to Figure 10, in some possible implementations, the power supply unit 100 employs a BUCK circuit, which includes a control stage circuit 101, a power stage circuit 102, a power stage auxiliary circuit 103, a first voltage input terminal, a second voltage input terminal, a first voltage output terminal, and a second voltage output terminal. The control stage circuit 101 includes a pulse width modulation (PWM) circuit. The power stage circuit 102 includes power transistors T, which can be one or more, such as two or four. The power stage auxiliary circuit 103 includes an inductor L (which can be one or more) and a capacitor C (which can be one or more). The gate of the power transistor T is connected to the PWM circuit, and the source (or drain) of the power transistor T is connected to the first input voltage terminal, and the drain (or source) is connected to the first output voltage terminal. The second voltage output terminal is connected to the second voltage input terminal. The inductor L and capacitor C are connected in parallel between the first and second voltage output terminals. The core 200 is connected between the first voltage output terminal and the second voltage output terminal, and power is supplied to the core 200 through the first voltage output terminal and the second voltage output terminal.

[0081] In this case, the pulse width modulation circuit (PWM) obtains a control signal (pulse width modulation signal) based on the voltage (Vout) between the second input voltage terminal and the first output voltage terminal, and adjusts the power transistor T to ensure that the voltage between the second input voltage terminal and the first output voltage terminal is kept near the set voltage value to meet the stable power supply of the core 200.

[0082] In addition, the distribution of the power stage auxiliary circuit 103 can be set according to actual needs. The power stage auxiliary circuit 103 can be set in the first region A1, the second region A2, or other regions. This application does not limit this. In practice, it can be laid out as needed.

[0083] The following is a brief explanation of the SC circuit configuration used in the power supply unit 100.

[0084] Schematic, referring to Figure 11, in some possible implementations, the power supply unit 100 employs an SC circuit, which includes a control stage circuit 101, a power stage circuit 102, a first voltage input terminal, a second voltage input terminal, a first voltage output terminal, and a second voltage output terminal. The control stage circuit 101 includes a level shifter circuit LS. The power stage circuit 102 includes a first power transistor T1, a second power transistor T2, and a capacitor C. There can be one or more first power transistors T1; there can be one or more second power transistors T2; and there can be one or more capacitors C. The gates of the first power transistor T1 and the second power transistor T2 are connected to the level shifter circuit LS. The source (or drain) of the first power transistor T1 is connected to the first voltage input terminal, and the drain (or source) of the first power transistor T1 is connected to the first node N1. The source (or drain) of the second power transistor T2 is connected to the first node N1, and the drain (or source) of the second power transistor T2 is connected to the first voltage output terminal. One end of capacitor C is connected to the first node N1, and the other end of capacitor C is connected to the second node N2. The second voltage input terminal is connected to the second node N2, and the second voltage output terminal is also connected to the second node N2. Core 200 is connected between the first and second voltage output terminals, and power is supplied to core 200 through both terminals.

[0085] In this case, the level conversion circuit LS obtains a control signal based on the voltage (Vout) between the second input voltage terminal and the first output voltage terminal to adjust the first power transistor T1 and the second power transistor T2, ensuring that the voltage between the second input voltage terminal and the first output voltage terminal is kept near the set voltage value to meet the stable power supply of the core 200.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, The chip has a first region and a second region; The chip includes multiple processor cores and multiple power supply circuits. Each power supply circuit includes a control level circuit and a power level circuit electrically connected to the control level circuit. The multiple processor cores are respectively connected to the power level circuits of the multiple power supply circuits in a one-to-one correspondence. The plurality of cores are located in the first region, and the control level circuits of the plurality of power supply circuits are all located in the second region; The power stage circuits of the plurality of power supply circuits are all disposed in the first region, and the power stage circuits of each power supply circuit are disposed around the corresponding processor core and have openings.

2. The chip according to claim 1, characterized in that, The power stage circuit and the corresponding processor core are located in the same circuit layout.

3. The chip according to claim 1 or 2, characterized in that, The distance between the processor core and the corresponding power stage circuit is less than 10 μm.

4. The chip according to any one of claims 1-3, characterized in that, The control stage circuit includes a reference circuit and an error amplifier circuit connected to the reference circuit, and the error amplifier circuit is connected to the power stage circuit; the error amplifier circuit is used to control the power stage circuit according to the reference voltage provided by the reference circuit and the output voltage provided by the power stage circuit. The multiple control-level circuits share the same reference circuit.

5. The chip according to any one of claims 1-4, characterized in that, Different processor cores are connected through the area of ​​the opening.

6. The chip according to any one of claims 1-5, characterized in that, The power stage circuit is connected to the control stage circuit through the two ends that form the opening.

7. The chip according to claim 6, characterized in that, The control stage circuit and the power stage circuit are connected by two control lines, and the signal transmission rate on the two control lines is less than 10MHz.

8. The chip according to any one of claims 1-7, characterized in that, The openings in the multiple power stage circuits are respectively disposed in the adjacent regions of the multiple processor cores.

9. The chip according to any one of claims 1-8, characterized in that, The multiple processor cores are heterogeneous cores.

10. The chip according to any one of claims 1-9, characterized in that, The power supply circuit includes a low-dropout regulator (LDO).

11. The chip according to any one of claims 1-10, characterized in that, The low-dropout regulator includes an input voltage terminal and an output voltage terminal; the control stage circuit includes a reference circuit and an error amplifier circuit; the power stage circuit includes a power transistor. The input terminal of the reference circuit is connected to the input voltage terminal, the output terminal of the reference circuit is connected to the first input terminal of the error amplifier circuit, and the second input terminal of the error amplifier circuit is connected to the output voltage terminal; the power supply terminal of the error amplifier circuit is connected to the input voltage terminal; the output terminal of the error amplifier circuit is connected to the gate of the power transistor, the first stage of the power transistor is connected to the input voltage terminal, and the second stage of the power transistor is connected to the output voltage terminal. In the first stage and the second stage, one is the source and the other is the drain.

12. The chip according to any one of claims 1-9, characterized in that, The power supply circuit includes a BUCK circuit.

13. The chip according to any one of claims 1-9, characterized in that, The power supply circuit includes a switched capacitor circuit SC.

14. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-13, wherein the circuit board is connected to the chip.

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