Display substrate and display device

Abstract

Provided in the present disclosure are a display substrate and a display device. The display substrate comprises a base substrate, and a second level signal line and a gate drive circuit that are arranged on the base substrate. The gate drive circuit comprises a plurality of cascaded shift register units. Each shift register unit comprises output transistors, wherein the output transistors are coupled to a gate drive signal output end of the shift register unit. The second level signal line extends in a first direction. Orthographic projections of the output transistors on the base substrate are located on a first side of the orthographic projection of the second level signal line on the base substrate, and orthographic projections of transistor structures other than the output transistors in each shift register unit on the base substrate are located on a second side of the orthographic projection of the second level signal line on the base substrate.

Description

Display substrate and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510277446.7, filed in China on March 10, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0004] With the continuous development of display technology, display products are showing a trend towards high integration and low cost. A crucial technology used in display products is the mass production of GOA (Gate Driver on Array) technology. GOA technology integrates the gate driver circuit onto the array substrate of the display panel, thus eliminating the need for the gate driver integrated circuit, reducing product costs in terms of both materials and manufacturing processes. This gate driver circuit integrated onto the array substrate using GOA technology is also called a GOA circuit or shift register circuit, where each shift register circuit within the gate driver circuit is also called a shift register unit.

[0005] However, when applying shift register units to display products, there is a problem that the internal nodes of the shift register unit are easily affected by coupling, resulting in unstable output of the shift register unit. Summary of the Invention

[0006] The purpose of this disclosure is to provide a display substrate and a display device.

[0007] To achieve the above objectives, this disclosure provides the following technical solution:

[0008] A first aspect of this disclosure provides a display substrate, including a substrate and a second level signal line and a gate driving circuit disposed on the substrate; the gate driving circuit includes a plurality of cascaded shift register units, each shift register unit including an output transistor, the output transistor being coupled to the gate driving signal output terminal of the shift register unit;

[0009] The second level signal line extends along the first direction, and the orthographic projection of the output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate. The orthographic projection of the other transistor structures in the shift register unit, excluding the output transistor, on the substrate is located on the second side of the orthographic projection of the second level signal line on the substrate. The first side and the second side are opposite to each other along the second direction, and the second direction intersects with the first direction.

[0010] Optionally, the display substrate further includes a first level signal line; the shift register unit further includes a first output node and a first output transistor; the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first level signal line, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal of the shift register unit; the orthographic projection of the first output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

[0011] Optionally, the shift register unit further includes: a first coupling node and a second capacitor; the first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node;

[0012] The orthographic projection of the second plate of the second capacitor onto the substrate is located on the second side of the orthographic projection of the second level signal line onto the substrate, and is adjacent to the orthographic projection of the second level signal line onto the substrate.

[0013] Optionally, the orthographic projection of the second level signal line on the substrate of the display substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the first output transistor on the substrate.

[0014] The shift register unit further includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second electrode plate of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

[0015] Optionally, the shift register unit further includes: a second output node and a second output transistor; the gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal of the shift register unit; the orthographic projection of the second output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

[0016] Optionally, the shift register unit further includes a third capacitor, the first plate of which is coupled to the gate of the second output transistor, and the second plate of which is coupled to the second level signal line; the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the second level signal line on the substrate at least partially overlap.

[0017] Optionally, the shift register unit further includes a seventh control transistor, the gate of which is coupled to a first output node in the shift register unit, the first terminal of which is coupled to the second level signal line, and the second terminal of which is coupled to a second output node in the shift register unit.

[0018] At least a portion of the orthographic projection of the active layer of the seventh control transistor onto the substrate is located on the second side of the orthographic projection of the second level signal line onto the substrate.

[0019] Optionally, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive two rows of sub-pixel rows;

[0020] The orthographic projection of the second plate of the second capacitor in the shift register unit onto the substrate and the orthographic projection of the active layer of the seventh control transistor onto the substrate are aligned along the first direction.

[0021] Optionally, the gate of the seventh control transistor and the gate of the first output transistor in the shift register unit are formed as a single structure.

[0022] Optionally, the shift register unit further includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to a first clock signal input terminal, the first terminal of the fifth control transistor is coupled to the second level signal line, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to a second input node, and the second terminal of the sixth control transistor is coupled to a first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer, which extends along the second direction; the orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the integral active layer on the substrate; and / or,

[0023] The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to a first level signal line, and the second terminal of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to a second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second coupling node. Point coupling; the gate of the fourth control transistor is coupled to the first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to the second output node; the orthographic projections of the second electrode plate of the second capacitor, the active layer of the fourth control transistor, the active layer of the second control transistor, and the active layer of the third control transistor on the substrate are arranged sequentially along the first direction; the orthographic projection of the active layer of the second control transistor on the substrate is located between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the second level signal line on the substrate.

[0024] Optionally, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive one row of sub-pixel rows;

[0025] At least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the active layer of the seventh control transistor onto the substrate and the orthographic projection of the second level signal line onto the substrate.

[0026] Optionally, the gate of the seventh control transistor and the gate of the eighth control transistor are formed as an integral structure.

[0027] Optionally, the shift register unit further includes a fourth control transistor, a fifth control transistor, and a sixth control transistor; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first electrode of the fourth control transistor is coupled to a second input node, and the second electrode of the fourth control transistor is coupled to a second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first electrode of the fifth control transistor is coupled to a second level signal line, and the second electrode of the fifth control transistor is coupled to the first electrode of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second electrode of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer extending along the first direction; at least a portion of the orthographic projection of the active layer of the fourth control transistor onto the substrate is located between the orthographic projection of the second electrode of the second capacitor onto the substrate and the orthographic projection of the integral active layer onto the substrate; at least a portion of the active layer of the seventh control transistor is located between the integral active layer and the active layer of the fourth control transistor; and / or,

[0028] The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to a first level signal line, and the second electrode of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to a second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layers of the first control transistor and the active layers of the eighth control transistor; the active layers of the first control transistor and the active layers of the third control transistor are arranged along the first direction, and at least a portion of the active layer of the second control transistor is located between the active layers of the first control transistor and the active layers of the third control transistor; the active layers of the first control transistor, the active layers of the second control transistor, and the active layers of the third control transistor are sequentially coupled to form a single structure.

[0029] Optionally, the first level signal line and the second level signal line in the display substrate are arranged along the second direction; the orthographic projection of the other transistor structures in the shift register unit, excluding the output transistor, on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate.

[0030] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0031] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0032] Figure 1 is a schematic cross-sectional view of the film layer of the display substrate provided in the embodiment of this disclosure;

[0033] Figure 2 is a circuit schematic diagram of the shift register unit provided in an embodiment of this disclosure;

[0034] Figure 3 is a timing diagram of the shift register unit provided in an embodiment of this disclosure;

[0035] Figure 4 is a signal waveform diagram of node N3 provided in an embodiment of this disclosure;

[0036] Figure 5 is a schematic diagram of the layout of the active layer in a shift register unit provided in an embodiment of this disclosure;

[0037] Figure 6 is a schematic diagram of the layout of the first gate metal layer in a shift register unit provided in an embodiment of the present disclosure;

[0038] Figure 7 is a schematic diagram of the layout of the second gate metal layer in a shift register unit provided in an embodiment of this disclosure;

[0039] Figure 8 is a schematic diagram of the layout of an active layer, a first gate metal layer, and a second gate metal layer in a shift register unit provided in an embodiment of this disclosure;

[0040] Figure 9 is a schematic diagram of the layout of the first source-drain metal layer in a shift register unit provided in an embodiment of this disclosure;

[0041] Figure 10 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 8;

[0042] Figure 11 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 8;

[0043] Figure 12 is a schematic diagram of the layout of the active layer in another shift register unit provided in an embodiment of this disclosure;

[0044] Figure 13 is a schematic diagram of the layout of the first gate metal layer in another shift register unit provided in an embodiment of this disclosure;

[0045] Figure 14 is a schematic diagram of the layout of the second gate metal layer in another shift register unit provided in an embodiment of this disclosure;

[0046] Figure 15 is a schematic diagram of the layout of an active layer, a first gate metal layer, and a second gate metal layer in another shift register unit provided in an embodiment of this disclosure.

[0047] Figure 16 is a schematic diagram of the layout of the first source-drain metal layer in another shift register unit provided in an embodiment of this disclosure;

[0048] Figure 17 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 15;

[0049] Figure 18 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 15;

[0050] Figure 19 is a schematic diagram of the layout of two shift register units provided in the embodiments of this disclosure. Detailed Implementation

[0051] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0052] Please refer to Figures 2, 5 to 18. This disclosure provides a display substrate, including a substrate and a second level signal line VGH' and a gate driving circuit disposed on the substrate. The gate driving circuit includes a plurality of cascaded shift register units 10. Each shift register unit 10 includes an output transistor (such as a first output transistor T10 and a second output transistor T9). The output transistor is coupled to the gate driving signal output terminal OUT of the shift register unit 10.

[0053] The second level signal line VGH' extends along a first direction. The orthographic projection of the output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line VGH' on the substrate. The orthographic projection of the other transistor structures in the shift register unit 10, excluding the output transistor, on the substrate is located on the second side of the orthographic projection of the second level signal line VGH' on the substrate. The first side and the second side are opposite to each other along a second direction, and the second direction intersects with the first direction.

[0054] For example, the display substrate further includes a first level signal line VGL'; the shift register unit 10 further includes a first output node N3 and a first output transistor T10; the gate 310 of the first output transistor T10 is coupled to the first output node N3, the first terminal of the first output transistor T10 is coupled to the first level signal line VGL', and the second terminal of the first output transistor T10 is coupled to the gate drive signal output terminal OUT of the shift register unit 10; the orthographic projection of the first output transistor T10 on the substrate is located on the first side of the orthographic projection of the second level signal line VGH' on the substrate.

[0055] For example, the shift register unit 10 further includes: a second output node N5 and a second output transistor T9; the gate 39 of the second output transistor T9 is coupled to the second output node N5, the first terminal of the second output transistor T9 is coupled to the second level signal line VGH', and the second terminal of the second output transistor T9 is coupled to the gate drive signal output terminal OUT of the shift register unit 10; the orthographic projection of the second output transistor T9 on the substrate is located on the first side of the orthographic projection of the second level signal line VGH' on the substrate.

[0056] For example, the active layer 210 of the first output transistor T10 and the active layer 29 of the second output transistor T9 are arranged along the first direction.

[0057] For example, the first level signal line VGL' is used to transmit a first level signal, and the second level signal line VGH' is used to transmit a second level signal; for example, the first level signal includes a low level signal, and the second level signal includes a high level signal, but is not limited to this.

[0058] It should be noted that Figure 1 illustrates the first level signal input terminal VGL and the second level signal input terminal VGH. The first level signal input terminal VGL is coupled to the first level signal line VGL', and the second level signal input terminal VGH is coupled to the second level signal line VGH'.

[0059] As shown in Figures 5 to 11 and Figures 13 to 18, exemplarily, the orthographic projection of the second level signal line VGH' on the substrate is located between the orthographic projection of the first level signal line VGL' on the substrate and the orthographic projection of the output transistor on the substrate. The shift register unit further includes an eleventh conductive connection portion 42, which is coupled to the first terminal of the first output transistor T10 and the first level signal line VGL', respectively. The orthographic projection of the eleventh conductive connection portion 42 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0060] As shown in Figures 5 to 11, exemplarily, the shift register unit further includes a first conductive connection portion 51, which is coupled to the first terminal of the input transistor T1 and a tenth conductive connection portion 41, respectively. The tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous stage shift register unit. The orthographic projection of the first conductive connection portion 51 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0061] As shown in Figures 13 to 18, exemplarily, the shift register unit further includes a twelfth conductive connection portion 61. This twelfth conductive connection portion 61 is coupled to the first terminal of the input transistor T1 and a tenth conductive connection portion 41, which is coupled to the gate drive signal output terminal of the previous-stage shift register unit. The orthographic projection of the twelfth conductive connection portion 61 on the substrate is located between the orthographic projections of the first level signal line VGL' and the second level signal line VGH' on the substrate.

[0062] As shown in Figures 5 to 11, for example, the distance between the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 onto the substrate and the orthographic projection of the tenth conductive connection 41 onto the substrate is greater than the distance between the orthographic projection of the active layer 29 of the second output transistor T9 onto the substrate and the orthographic projection of the tenth conductive connection 41 onto the substrate. This arrangement allows the plate of the third capacitor C3 to be moved away from the tenth conductive connection 41, thereby effectively reducing the coupling effect of the signal transmitted by the tenth conductive connection 41 on the third capacitor C3.

[0063] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, by setting the orthogonal projection of the output transistor on the substrate to be located on the first side of the orthogonal projection of the second level signal line VGH' on the substrate, and the orthogonal projection of the other transistor structures in the shift register unit 10, excluding the output transistor, on the substrate to be located on the second side of the orthogonal projection of the second level signal line VGH' on the substrate, the second level signal line VGH' can separate the output transistor from other transistor structures, thereby effectively reducing the coupling between the output node (such as the first output node N3 and the second output node N5) controlling the output transistor and other transistor structures, as well as the nodes coupled to other transistor structures, avoiding the output node being affected by coupling, and thus avoiding the output transistor being affected by coupling, thereby ensuring that the gate drive signal output terminal OUT can be output stably, effectively reducing the disturbance effect on the output waveform, and effectively improving the reliability of the shift register unit.

[0064] Therefore, the display substrate provided in this embodiment effectively improves the voltage stability of the internal nodes of the shift register unit 10, and at the same time improves the stability of the output signal of the shift register unit 10.

[0065] As shown in Figures 2, 5 to 18, in some embodiments, the shift register unit 10 further includes: a first coupling node N0 and a second capacitor C2; the first plate C21 of the second capacitor C2 is coupled to the first output node N3, and the second plate C22 of the second capacitor C2 is coupled to the first coupling node N0.

[0066] The orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate is located on the second side of the orthographic projection of the second level signal line VGH' onto the substrate, and is adjacent to the orthographic projection of the second level signal line VGH' onto the substrate.

[0067] For example, the orthographic projection of the second level signal line VGH' on the substrate of the display substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the substrate.

[0068] For example, the gate 310 of the first output transistor T10 and the first plate C21 of the second capacitor C2 are formed as an integral structure, and the orthographic projection of the integral structure on the substrate overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0069] The above configuration places the second capacitor C2 near the second level signal line VGH', effectively reducing the coupling effect of other AC signals on the second capacitor C2. Furthermore, this configuration allows the second level signal line VGH' to separate the second capacitor C2 from the first output transistor T10, reducing the coupling effect of other AC signals through the second capacitor C2 on the gate 310 potential of the first output transistor T10, and reducing the coupling capacitance of the gate 310 of the first output transistor T10. This effectively reduces the step formed during the pull-down of the potential of the first output node N3, enabling stable output of the gate drive signal OUT and effectively reducing the disturbance of the output waveform. Therefore, in the display substrate provided by the above embodiment, the voltage stability of the internal nodes (such as the first output node N3) of the shift register unit 10 is effectively improved, while the stability of the output signal of the shift register unit 10 is also improved.

[0070] More specifically, as shown in Figure 4, in the existing layout of the shift register unit 10, the waveform has a large step (such as L1) during the process of the first output node N3 being pulled low; in the layout of the shift register unit 10 of the display substrate provided in this embodiment, the step height of the waveform is greatly reduced (such as L2) during the process of the first output node N3 being pulled low.

[0071] As shown in Figures 2, 5 to 18, in some embodiments, the orthographic projection of the second level signal line VGH' on the substrate of the display substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 210 of the first output transistor T10 on the substrate.

[0072] The shift register unit 10 further includes an eighth control transistor T11; the gate 311 of the eighth control transistor T11 is coupled to the first output node N3, the first terminal of the eighth control transistor T11 is coupled to the first clock signal input terminal CKB, and the second terminal of the eighth control transistor T11 is coupled to the first coupling node N0; the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate are arranged along the first direction.

[0073] For example, the eighth control transistor T11 includes a dual-gate transistor structure, but is not limited to this.

[0074] For example, the active layer 211 of the eighth control transistor T11 extends along the first direction, which helps to reduce the layout space occupied by the eighth control transistor T11 as a whole along the second direction.

[0075] For example, along the first direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is adjacent to the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate; along the second direction, the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is adjacent to the orthographic projection of the second level signal line VGH' on the substrate.

[0076] For example, the gate 311 of the eighth control transistor T11, the gate 310 of the first output transistor T10, and the first plate C21 of the second capacitor C2 are formed into an integral structure.

[0077] The above arrangement allows the eighth control transistor T11, the second capacitor C2 and the first output transistor T10 to be arranged in a concentrated manner, which not only reduces the difficulty of connecting the three and ensures the reliability of the connection, but also helps to reduce the overall layout space occupied by the shift register unit 10, and helps to achieve a narrow bezel on the display substrate.

[0078] As shown in Figures 2, 5 to 18, in some embodiments, the shift register unit 10 further includes a third capacitor C3. The first plate C31 of the third capacitor C3 is coupled to the gate 39 of the second output transistor T9, and the second plate C32 of the third capacitor C3 is coupled to the second level signal line VGH'. The orthographic projection of the second plate C32 of the third capacitor C3 on the substrate and the orthographic projection of the second level signal line VGH' on the substrate at least partially overlap.

[0079] For example, the first plate C31 of the third capacitor C3 and the gate 39 of the second output transistor T9 are formed as an integral structure. The orthographic projection of the first plate C31 of the third capacitor C3 on the substrate at least partially overlaps with the orthographic projection of the second level signal line VGH' on the substrate.

[0080] For example, the display substrate further includes multiple rows of sub-pixel rows; when the shift register unit 10 is used to drive two rows of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along a first direction; when the shift register unit 10 is used to drive one row of sub-pixel rows, the second plate C32 of the third capacitor C3 extends along a second direction.

[0081] For example, the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate is located inside the orthographic projection of the first plate C31 of the third capacitor C3 onto the substrate.

[0082] The above-mentioned configuration of the second plate C32 of the third capacitor C3 on the substrate at least partially overlaps with the orthogonal projection of the second level signal line VGH' on the substrate, which better saves the overall layout space occupied by the shift register unit 10 and is conducive to the display substrate to achieve a narrow bezel.

[0083] As shown in Figures 2, 5 to 18, in some embodiments, the second level signal line VGH' extends along a first direction; the active layer 210 of the first output transistor T10 and the active layer 29 of the second output transistor T9 are arranged along the first direction; the orthographic projection of the second plate C32 of the third capacitor C3 on the substrate and the orthographic projection of the active layer 29 of the second output transistor T9 on the substrate are arranged along a second direction, and the second direction intersects the first direction.

[0084] For example, the orthographic projection of the second output transistor T9 onto the substrate is located on the first side of the orthographic projection of the second level signal line VGH' onto the substrate along the second direction. This arrangement allows the second level signal line VGH' to separate the first output transistor T10 and the second output transistor T9 from other functional structures (such as other transistors, capacitors, etc.), reducing interference from other functional structures to the first output transistor T10 and the second output transistor T9, and better ensuring the output stability of the first output transistor T10 and the second output transistor T9.

[0085] The above arrangement makes the third capacitor C3 adjacent to the second output transistor T9, which effectively reduces the difficulty of connecting the third capacitor C3 and the second output transistor T9 and ensures the reliability of the connection between the third capacitor C3 and the second output transistor T9.

[0086] As shown in Figures 2, 5 to 18, in some embodiments, the shift register unit 10 further includes a seventh control transistor T8. The gate 38 of the seventh control transistor T8 is coupled to the first output node N3 in the shift register unit 10. The first terminal of the seventh control transistor T8 is coupled to the second level signal line VGH'. The second terminal of the seventh control transistor T8 is coupled to the second output node N5 in the shift register unit 10.

[0087] At least a portion of the orthographic projection of the active layer 28 of the seventh control transistor T8 onto the substrate is located on the second side of the orthographic projection of the second level signal line VGH' onto the substrate.

[0088] For example, the active layer 28 of the seventh control transistor T8 extends along the second direction.

[0089] As shown in Figures 2, 5 to 11, in some embodiments, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit 10 is used to drive two rows of sub-pixel rows; the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 onto the substrate and the orthographic projection of the active layer 28 of the seventh control transistor T8 onto the substrate are arranged along the first direction.

[0090] For example, the gate 38 of the seventh control transistor T8 and the gate 310 of the first output transistor T10 in the shift register unit 10 are formed as an integral structure.

[0091] For example, the display area of ​​the display substrate includes multiple rows of subpixel rows, each row of subpixel rows including multiple subpixels arranged along a second direction. When the shift register unit 10 is used to drive two rows of subpixel rows, the shift register unit 10 can provide driving signals to the two rows of subpixel rows.

[0092] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, which is beneficial for the display substrate to achieve a narrow bezel.

[0093] As shown in Figures 2, 5 to 11, in some embodiments, the shift register unit 10 further includes an input transistor T1. The gate 31 of the input transistor T1 is coupled to the second clock signal input terminal CK. The first terminal of the input transistor T1 is coupled to the input signal terminal STV. The second terminal of the input transistor T1 is coupled to the first input node N1 of the shift register unit 10. At least a portion of the orthographic projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 211 of the input transistor T1 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate; and / or,

[0094] The shift register unit 10 further includes a transfer transistor T12, the gate 312 of which is coupled to a first level signal line VGL', the first terminal of which is coupled to a first input node N1, and the second terminal of which is coupled to a first output node N3; the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 onto the substrate and the orthographic projection of the active layer 212 of the transfer transistor T12 onto the substrate are arranged along the first direction; and / or,

[0095] The shift register unit 10 further includes a fifth control transistor T6 and a sixth control transistor T7; the gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal line VGH', and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; the gate 37 of the sixth control transistor T7 is coupled to the second input node N2, and the second terminal of the sixth control transistor T7 is coupled to the first input node N1; the active layer 26 of the fifth control transistor T6 is connected to the sixth control transistor. The active layer 27 of transistor T7 is formed as an integral active layer extending along the second direction; the orthographic projection of the active layer 211 of the eighth control transistor T11 on the substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the integral active layer on the substrate; the orthographic projection of the active layer 212 of the transmission transistor T12 on the substrate is located between the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate and the orthographic projection of the integral active layer on the substrate; and / or,

[0096] The shift register unit 10 further includes a second coupling node N4, a first control transistor T2, a second control transistor T3, a third control transistor T4, and a fourth control transistor T5; the gate 32 of the first control transistor T2 is coupled to the second coupling node N4, the first terminal of the first control transistor T2 is coupled to the first level signal line VGL', and the second terminal of the first control transistor T2 is coupled to the second input node N2; the gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal line VGH', and the second terminal of the second control transistor T3 is coupled to the second input node N2; the gate 34 of the third control transistor T4 is coupled to the first input node N1, the first terminal of the third control transistor T4 is coupled to the second level signal line VGH', and the second terminal of the third control transistor T5 ...3 of the second control transistor T Two coupling nodes N4 are coupled; the gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, the first terminal of the fourth control transistor T5 is coupled to the second input node N2, and the second terminal of the fourth control transistor T5 is coupled to the second output node N5; the orthographic projections of the second plate C22 of the second capacitor C2, the active layer 25 of the fourth control transistor T5, the active layer 23 of the second control transistor T3, and the active layer 24 of the third control transistor T4 on the substrate are arranged sequentially along the first direction; the orthographic projection of the active layer 23 of the second control transistor T3 on the substrate is located between the orthographic projection of the active layer 22 of the first control transistor T2 on the substrate and the orthographic projection of the second level signal line VGH' on the substrate; and / or,

[0097] The shift register unit 10 further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and the second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along the second direction.

[0098] For example, the active layer 21 of the input transistor T1 extends along the first direction, the active layer 212 of the transmission transistor T12 extends along the first direction, and the active layer 212 of the transmission transistor T12 is at least partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0099] For example, the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate, the orthographic projection of the active layer 211 of the eighth control transistor T11 onto the substrate, the active layer of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 forming an integral structure, the orthographic projection of the active layer 25 of the fourth control transistor T5 onto the substrate, the orthographic projection of the active layer 23 of the second control transistor T3 onto the substrate, and the orthographic projection of the active layer 24 of the third control transistor T4 onto the substrate are arranged sequentially along the first direction.

[0100] For example, the active layer 23 of the second control transistor T3 and the active layer 22 of the first control transistor T2 are formed as an integral structure extending along the second direction.

[0101] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, which is beneficial for the display substrate to achieve a narrow bezel.

[0102] As shown in Figures 5 to 11, the shift register unit further includes a first conductive connection portion 51, which is coupled to the first pole of the input transistor T1 and the tenth conductive connection portion 41, respectively. The tenth conductive connection portion 41 is coupled to the gate drive signal output terminal of the previous shift register unit.

[0103] The shift register unit further includes a second conductive connection portion 52, which is coupled to the first plate C21 of the second capacitor C2 and the second electrode of the transmission transistor T12.

[0104] The shift register unit further includes a third conductive connection part 53, which is coupled to the second plate C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11.

[0105] The shift register unit further includes a fourth conductive connection portion 54, which is coupled to the second terminal of the input transistor T1, the first terminal of the transmission transistor T12, the second terminal of the sixth control transistor T7, and the gate of the second control transistor T3, respectively.

[0106] The shift register unit further includes a fifth conductive connection portion 55, which is coupled to the first terminal of the eighth control transistor T11 and the gate of the fifth control transistor T6, respectively.

[0107] The shift register unit further includes a sixth conductive connection portion 56, which is coupled to the gate of the sixth control transistor T7, the first terminal of the fourth control transistor T5, the second terminal of the first control transistor T2, and the second terminal of the second control transistor T3, respectively.

[0108] The shift register unit further includes a seventh conductive connection portion 57, which is coupled to the second terminal of the fourth control transistor T5, the gate of the second output transistor T9, and the second terminal of the fourth control transistor T8, respectively.

[0109] The shift register unit further includes an eighth conductive connection portion 58, which is coupled to the second plate C21 of the first capacitor C1, the gate 32 of the first control transistor T2, and the second electrode of the third control transistor T4, respectively.

[0110] The shift register unit further includes an eleventh conductive connection part 42, which is coupled to the first pole of the first output transistor T10 and the first level signal line VGL'.

[0111] As shown in Figures 1, 12 to 18, in some embodiments, the display substrate further includes multiple rows of sub-pixel rows; the shift register unit 10 is used to drive one row of sub-pixel rows; at least a portion of the orthographic projection of the active layer 211 of the eighth control transistor T11 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 28 of the seventh control transistor T8 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate.

[0112] For example, the gate 38 of the seventh control transistor T8 and the gate 311 of the eighth control transistor T11 are formed as an integral structure.

[0113] For example, the display area of ​​the display substrate includes multiple rows of subpixel rows, each row of subpixel rows including multiple subpixels arranged along a second direction. When the shift register unit 10 is used to drive a row of subpixel rows, the shift register unit 10 can provide a driving signal to that row of subpixel rows.

[0114] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the first direction, and reduces the layout difficulty of the multi-level shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixel rows.

[0115] As shown in Figures 1 and 12 to 18, in some embodiments, the shift register unit 10 further includes an input transistor T1, the gate 31 of which is coupled to the second clock signal input terminal CK, the first terminal of which is coupled to the input signal terminal STV, and the second terminal of which is coupled to the first input node N1 of the shift register unit 10; at least a portion of the orthographic projection of the second plate C22 of the second capacitor C2 in the shift register unit 10 onto the substrate is located between the orthographic projection of the active layer 21 of the input transistor T1 onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate; and / or,

[0116] The shift register unit 10 further includes a transfer transistor T12, the gate 312 of which is coupled to a first level signal line VGL', the first electrode of which is coupled to a first input node N1, and the second electrode of which is coupled to a first output node N3; at least a portion of the orthographic projection of the active layer 212 of the transfer transistor T12 onto the substrate is located between the orthographic projection of the active layer 21 of the input transistor T1 onto the substrate and the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate; and / or,

[0117] The shift register unit 10 further includes a fourth control transistor T5, a fifth control transistor T6, and a sixth control transistor T7; the gate 35 of the fourth control transistor T5 is coupled to the first clock signal input terminal CKB, the first terminal of the fourth control transistor T5 is coupled to the second input node N2, and the second terminal of the fourth control transistor T5 is coupled to the second output node N5; the gate 36 of the fifth control transistor T6 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal line VGH', and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; the gate 37 of the sixth control transistor T7 is coupled to the first clock signal input terminal CKB, the first terminal of the fifth control transistor T6 is coupled to the second level signal line VGH', and the second terminal of the fifth control transistor T6 is coupled to the first terminal of the sixth control transistor T7; Two input nodes N2 are coupled together; the second electrode of the sixth control transistor T7 is coupled to the first input node N1; the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 are formed as an integral active layer, which extends along the first direction; at least a portion of the orthographic projection of the active layer 25 of the fourth control transistor T5 onto the substrate is located between the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate and the orthographic projection of the integral active layer onto the substrate; at least a portion of the active layer 28 of the seventh control transistor T8 is located between the integral active layer and the active layer 25 of the fourth control transistor T5; and / or,

[0118] The shift register unit 10 further includes a second coupling node N4, a first control transistor T2, a second control transistor T3, and a third control transistor T4; the gate 32 of the first control transistor T2 is coupled to the second coupling node N4, the first terminal of the first control transistor T2 is coupled to the first level signal line VGL', and the second terminal of the first control transistor T2 is coupled to the second input node N2; the gate 33 of the second control transistor T3 is coupled to the first input node N1, the first terminal of the second control transistor T3 is coupled to the second level signal line VGH', and the second terminal of the second control transistor T3 is coupled to the second input node N2; the gate 34 of the third control transistor T4 is coupled to the first input node N1, and the first terminal of the third control transistor T4 is coupled to the second input node N2. The two-level signal line VGH' is coupled, and the second terminal of the third control transistor T4 is coupled to the second coupling node N4; the active layer 28 of the seventh control transistor T8 is located between the active layer 22 of the first control transistor T2 and the active layer 211 of the eighth control transistor T11; the active layers 22 of the first control transistor T2 and the active layers 24 of the third control transistor T4 are arranged along the first direction, and at least a portion of the active layer 23 of the second control transistor T3 is located between the active layers 22 of the first control transistor T2 and the active layers 24 of the third control transistor T4; the active layers 22 of the first control transistor T2, the active layers 23 of the second control transistor T3, and the active layers 24 of the third control transistor T4 are sequentially coupled to form a single structure; and / or,

[0119] The shift register unit 10 further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the first clock signal input terminal CKB, and the second plate C12 of the first capacitor C1 is coupled to the second coupling node N4; the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C32 of the third capacitor C3 in the shift register unit 10 on the substrate are arranged along the second direction.

[0120] For example, the active layer 21 of the input transistor T1 extends along the second direction, and the active layer 212 of the transmission transistor T12 extends along the second direction. The active layer 212 of the transmission transistor T12 is partially offset from the active layer 21 of the input transistor T1 along the second direction.

[0121] For example, the second plate C22 of the second capacitor C2 includes a plate body and a plate protrusion. The plate body extends along the first direction, and the plate protrusion protrudes from the plate body along the second direction. The orthographic projection of the plate body on the substrate is located between the orthographic projection of the plate protrusion on the substrate and the orthographic projection of the second level signal line VGH' on the substrate.

[0122] For example, the orthographic projection of the active layer 212 of the transmission transistor T12 onto the substrate is offset from the orthographic projection of the electrode protrusion onto the substrate along the second direction.

[0123] For example, the active layer 26 of the fifth control transistor T6 and the active layer 27 of the sixth control transistor T7 form an integral structure, the active layer 28 of the seventh control transistor T8 and the active layer 25 of the fourth control transistor T5 are sequentially coupled to form an integral structure.

[0124] For example, the active layer 22 of the first control transistor T2 extends along the second direction, the active layer 24 of the third control transistor T4 extends along the second direction, and the active layer 23 of the second control transistor T3 extends along the first direction.

[0125] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the first direction, and reduces the layout difficulty of the multi-level shift register unit 10 when the shift register unit 10 is used to drive a row of sub-pixel rows.

[0126] As shown in Figures 12 to 18, the shift register unit further includes a twelfth conductive connection part 61, which is coupled to the first pole of the input transistor T1 and the tenth conductive connection part 41, respectively. The tenth conductive connection part 41 is coupled to the gate drive signal output terminal of the previous shift register unit.

[0127] The shift register unit also includes a thirteenth conductive connection part 62, which is coupled to the second electrode of the transmission transistor T12 and the first plate C21 of the second capacitor C2.

[0128] The shift register unit further includes a fourteenth conductive connection portion 63, which is coupled to the gate of the sixth control transistor T7 and the first electrode of the fourth control transistor T5, respectively.

[0129] The shift register unit also includes a fifteenth conductive connection part 64, which is coupled to the second plate C22 of the second capacitor C2 and the second electrode of the eighth control transistor T11.

[0130] The shift register unit further includes a sixteenth conductive connection portion 65, which is coupled to the second terminal of the input transistor T1, the first terminal of the transmission transistor T12, the gate of the second control transistor T3, and the gate of the third control transistor T4, respectively.

[0131] The shift register unit further includes a seventeenth conductive connection portion 66, which is coupled to the second electrode of the second control transistor T3 and the gate of the sixth control transistor T7, respectively.

[0132] The shift register unit further includes a nineteenth conductive connection part 68, which is coupled to the second plate C12 of the first capacitor C1, the second electrode of the third control transistor T4, and the gate of the first control transistor T2, respectively.

[0133] The shift register unit further includes a twentieth conductive connection portion 69, which is coupled to the second level signal line VGH', the first terminal of the third control transistor T4, the first terminal of the seventh control transistor T8, and the first terminal of the second control transistor T3, respectively.

[0134] The shift register unit further includes a twenty-first conductive connection portion 610, which is coupled to the first terminal of the eighth control transistor T11 and the gate of the fourth control transistor T5, respectively.

[0135] The shift register unit also includes a 22nd conductive connection part 611, which is coupled to the first plate C31 of the third capacitor C3 and the second plate of the seventh control transistor T8.

[0136] As shown in Figures 5 to 18, in some embodiments, the first level signal line VGL' and the second level signal line VGH' in the display substrate are arranged along the second direction; the orthographic projection of the other transistor structures in the shift register unit 10, excluding the output transistor, onto the substrate is located between the orthographic projection of the first level signal line VGL' onto the substrate and the orthographic projection of the second level signal line VGH' onto the substrate.

[0137] The above method enables the other transistor structures included in the shift register unit 10 to be centrally located between the first level signal line VGL' and the second level signal line VGH', so that the distribution density of CNT vias around each other transistor structure is uniform, avoiding the increase in regional characteristic differences caused by the effect of hydrogen removal on the layout area due to the uneven distribution of vias.

[0138] For example, the display substrate further includes a frame start signal line (e.g., ESTV, RSTV), a first clock signal line (e.g., ECB, RCB), and a second clock signal line (e.g., ECK, RCK); the frame start signal line, the first clock signal line, the second clock signal line, the first level signal line VGL', and the second level signal line VGH' are arranged sequentially along a second direction.

[0139] For example, in a cascaded plurality of shift register units 10, the first terminal of the first input transistor T1 in the first-stage shift register unit 10 is coupled to the frame start signal line, and the first terminal of the first input transistor T1 in the (n+1)th-stage shift register unit 10 is coupled to the gate drive signal output terminal OUT of the nth-stage shift register unit 10; n is an integer greater than or equal to 1.

[0140] For example, in one of the odd-level shift register units 10 and the even-level shift register unit 10, the first clock signal input terminal CKB is coupled to the first clock signal line, and the second clock signal input terminal CK is coupled to the second clock signal line; in the other of the odd-level shift register units 10 and the even-level shift register unit 10, the first clock signal input terminal CKB is coupled to the second clock signal line, and the second clock signal input terminal CK is coupled to the first clock signal line.

[0141] For example, as shown in Figure 19, the display substrate includes two types of shift register units 10. The first type of shift register unit 10 is used to drive two rows of pixel units simultaneously, specifically as EM GOA. The second type of shift register unit 10 is used to drive one row of pixel units simultaneously, specifically as Reset GOA. In actual layout, the Reset GOA can be placed between the EM GOA and the display area. It should be noted that the display area in Figure 19 is located on the far right.

[0142] For example, as shown in Figures 5 to 11 and Figures 13 to 19, the width of the first type of shift register unit along the first direction is greater than the width of the second type of shift register unit along the first direction, and the width of the first type of shift register unit along the second direction is less than the width of the second type of shift register unit along the second direction.

[0143] The width of the second plate C32 of the third capacitor C3 in the first type of shift register unit along the first direction is greater than the width of the second plate C32 of the third capacitor C3 in the second type of shift register unit along the first direction; the width of the second plate C32 of the third capacitor C3 in the first type of shift register unit along the second direction is less than the width of the second plate C32 of the third capacitor C3 in the second type of shift register unit along the second direction.

[0144] The width of the second plate C22 of the second capacitor C2 in the first type of shift register unit along the first direction is greater than the width of the second plate C22 of the second capacitor C2 in the second type of shift register unit along the first direction; the width of the second plate C22 of the second capacitor C2 in the first type of shift register unit along the second direction is less than the width of the second plate C22 of the second capacitor C2 in the second type of shift register unit along the second direction.

[0145] It is worth noting that the shift register unit 10 provided in the above embodiments is applicable to LTPS, LTPO, or all-oxide display products. The shift register unit 10 can be used for EM GOA (Emitting Light Control Shift Register Unit), Reset GOA (Reset Control Shift Register Unit), and Scan GOA (Gate Scan Drive Shift Register Unit).

[0146] It should be noted that the types of transistors included in the shift register unit 10 are diverse and are not limited to P-type transistors. For example, N-type transistors can also be used, but this is not the only option.

[0147] As shown in Figures 2 and 3, taking EM GOA as an example, the operation of the shift register unit 10 is as follows:

[0148] During phase P1, the input signal STV is at a low level, the second clock signal CK is at a high level, the first clock signal CKB is at a low level, the first reset transistor T10 is turned on, and the gate drive signal output OUT outputs the first level signal.

[0149] During the P2 phase, the input signal terminal STV is at a high level, the second clock signal input terminal CK is at a low level, the first clock signal input terminal CKB is at a high level, the input transistor T1 and the sixth control transistor T7 are turned on, and the gate drive signal output terminal OUT maintains the potential of the first level signal.

[0150] During P3 and P4 stages, the signal input at the input signal terminal STV is high, the second clock signal input at the second clock signal input terminal CK is high, the first clock signal input at the first clock signal input terminal CKB is low, the second output transistor T9 is turned on, and the gate drive signal output terminal OUT outputs the second level signal.

[0151] During the phase between P3 and P4, the signal input at the input signal terminal STV is at a high level, the second clock signal input at the second clock signal input terminal CK alternates between high and low levels, the first clock signal input at the first clock signal input terminal CKB alternates between high and low levels, and the gate drive signal output terminal OUT continuously outputs the second level signal.

[0152] During the P5 phase, the signal input at the input signal terminal STV is low, the second clock signal input at the second clock signal input terminal CK is low, the first clock signal input at the first clock signal input terminal CKB is high, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs the first level signal.

[0153] During the P6 phase, the signal input at the input signal terminal STV is low, the second clock signal input at the second clock signal input terminal CK is high, the first clock signal input at the first clock signal input terminal CKB is low, the first reset transistor T10 is turned on, and the gate drive signal output terminal OUT outputs the first level signal.

[0154] In the aforementioned shift register unit 10, the eighth control transistor T11 can control the electrical connection between the first coupling node N0 and the first clock signal input terminal CKB to be turned on or off, so that the potential of the first coupling node N0 can be the same as the potential of the clock signal input to the first clock signal input terminal CKB; at the same time, the second capacitor C2 can control the potential of the first output node N3 according to the potential of the first coupling node N0; thus, when the gate drive signal output terminal OUT is reset, the first coupling node can be controlled to have a suitable potential by controlling the input of a signal with a suitable potential to the first clock signal input terminal CKB, thereby controlling the potential of the first output node N3 to be pulled down quickly, eliminating the step formed during the process of the potential of the first output node N3 being pulled down, so that the gate drive signal output terminal OUT can be output stably, effectively reducing the disturbance of the output waveform.

[0155] As shown in Figure 1, exemplarily, the display substrate includes, sequentially stacked along a direction away from the substrate 70, a conductive layer BSM, a barrier layer Bar, a buffer layer BUF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc. The display substrate may also include a passivation layer PVX, but is not limited to this.

[0156] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0157] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0158] In the display substrate provided in the above embodiments, by setting the orthogonal projection of the output transistor on the substrate to be located on the first side of the orthogonal projection of the second level signal line VGH' on the substrate, and the orthogonal projection of the other transistor structures in the shift register unit 10 (excluding the output transistor) on the substrate to be located on the second side of the orthogonal projection of the second level signal line VGH' on the substrate, the second level signal line VGH' can separate the output transistor from other transistor structures. This effectively reduces the coupling between the output node controlling the output transistor (such as the first output node N3 and the second output node N5) and other transistor structures, as well as nodes coupled to other transistor structures. This avoids the output node being affected by coupling, thereby preventing the output transistor from being affected by coupling. This ensures that the gate drive signal output terminal OUT can be output stably, effectively reducing the disturbance to the output waveform and effectively improving the reliability of the shift register unit. Therefore, in the display substrate provided in the above embodiments, the voltage stability of the internal nodes of the shift register unit 10 is effectively improved, and the stability of the output signal of the shift register unit 10 is also improved.

[0159] The display device provided in this disclosure, when including the above-described display substrate, also has the above-described beneficial effects, which will not be repeated here.

[0160] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0161] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0162] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0163] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0164] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0165] It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "below" another element, the element may be located "directly" on or "below" the other element, or there may be intermediate elements. In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising a substrate and a second-level signal line and a gate driving circuit disposed on the substrate; the gate driving circuit includes a plurality of cascaded shift register units, each shift register unit including an output transistor, the output transistor being coupled to a gate driving signal output terminal of the shift register unit; The second level signal line extends along the first direction, and the orthographic projection of the output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate. The orthographic projection of the other transistor structures in the shift register unit, excluding the output transistor, on the substrate is located on the second side of the orthographic projection of the second level signal line on the substrate. The first side and the second side are opposite to each other along the second direction, and the second direction intersects with the first direction.

2. The display substrate according to claim 1, wherein, The display substrate further includes a first level signal line; the shift register unit further includes a first output node and a first output transistor; the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first level signal line, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal of the shift register unit; the orthographic projection of the first output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

3. The display substrate according to claim 2, wherein, The shift register unit further includes: a first coupling node and a second capacitor; the first plate of the second capacitor is coupled to the first output node, and the second plate of the second capacitor is coupled to the first coupling node; The orthographic projection of the second plate of the second capacitor onto the substrate is located on the second side of the orthographic projection of the second level signal line onto the substrate, and is adjacent to the orthographic projection of the second level signal line onto the substrate.

4. The display substrate according to claim 3, wherein, The orthographic projection of the second level signal line on the substrate of the display substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the first output transistor on the substrate. The shift register unit further includes an eighth control transistor; the gate of the eighth control transistor is coupled to the first output node, the first electrode of the eighth control transistor is coupled to the first clock signal input terminal, and the second electrode of the eighth control transistor is coupled to the first coupling node; the orthographic projection of the second electrode plate of the second capacitor on the substrate and the orthographic projection of the active layer of the eighth control transistor on the substrate are arranged along the first direction.

5. The display substrate according to claim 1, wherein, The shift register unit further includes: a second output node and a second output transistor; the gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal of the shift register unit; the orthographic projection of the second output transistor on the substrate is located on the first side of the orthographic projection of the second level signal line on the substrate.

6. The display substrate according to claim 5, wherein, The shift register unit further includes a third capacitor, the first plate of which is coupled to the gate of the second output transistor, and the second plate of which is coupled to the second level signal line; the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the second level signal line on the substrate at least partially overlap.

7. The display substrate according to any one of claims 1 to 6, wherein, The shift register unit further includes a seventh control transistor, the gate of which is coupled to a first output node in the shift register unit, the first terminal of which is coupled to a second level signal line, and the second terminal of which is coupled to a second output node in the shift register unit. At least a portion of the orthographic projection of the active layer of the seventh control transistor onto the substrate is located on the second side of the orthographic projection of the second level signal line onto the substrate.

8. The display substrate according to claim 7, wherein, The display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive two rows of sub-pixel rows; The orthographic projection of the second plate of the second capacitor in the shift register unit onto the substrate and the orthographic projection of the active layer of the seventh control transistor onto the substrate are aligned along the first direction.

9. The display substrate according to claim 8, wherein, The gate of the seventh control transistor and the gate of the first output transistor in the shift register unit are integrated into one structure.

10. The display substrate according to claim 8, wherein, The shift register unit further includes a fifth control transistor and a sixth control transistor; the gate of the fifth control transistor is coupled to a first clock signal input terminal, the first terminal of the fifth control transistor is coupled to a second level signal line, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to a second input node, and the second terminal of the sixth control transistor is coupled to a first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed into an integral active layer, which extends along the second direction; The orthographic projection of the active layer of the eighth control transistor on the substrate is located between the orthographic projection of the second plate of the second capacitor on the substrate and the orthographic projection of the active layer of the integrated structure on the substrate. And / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, a third control transistor, and a fourth control transistor; the gate of the first control transistor is coupled to the second coupling node, the first electrode of the first control transistor is coupled to a first level signal line, and the second electrode of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first electrode of the second control transistor is coupled to a second level signal line, and the second electrode of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first electrode of the third control transistor is coupled to the second level signal line, and the second electrode of the third control transistor is coupled to the second coupling node; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first electrode of the fourth control transistor is coupled to the second input node, and the second electrode of the fourth control transistor is coupled to a second output node; the orthographic projections of the second electrode plate of the second capacitor, the active layer of the fourth control transistor, the active layer of the second control transistor, and the active layer of the third control transistor on the substrate are arranged sequentially along the first direction; The orthographic projection of the active layer of the second control transistor on the substrate is located between the orthographic projection of the active layer of the first control transistor on the substrate and the orthographic projection of the second level signal line on the substrate.

11. The display substrate according to claim 7, wherein, The display substrate further includes multiple rows of sub-pixel rows; the shift register unit is used to drive one row of sub-pixel rows; At least a portion of the orthographic projection of the active layer of the eighth control transistor in the shift register unit onto the substrate is located between the orthographic projection of the active layer of the seventh control transistor onto the substrate and the orthographic projection of the second level signal line onto the substrate.

12. The display substrate according to claim 11, wherein, The gate of the seventh control transistor and the gate of the eighth control transistor are formed as a single structure.

13. The display substrate according to claim 11, wherein, The shift register unit further includes a fourth control transistor, a fifth control transistor, and a sixth control transistor; the gate of the fourth control transistor is coupled to a first clock signal input terminal, the first terminal of the fourth control transistor is coupled to a second input node, and the second terminal of the fourth control transistor is coupled to a second output node; the gate of the fifth control transistor is coupled to the first clock signal input terminal, the first terminal of the fifth control transistor is coupled to a second level signal line, and the second terminal of the fifth control transistor is coupled to the first terminal of the sixth control transistor; the gate of the sixth control transistor is coupled to the second input node, and the second terminal of the sixth control transistor is coupled to the first input node; the active layer of the fifth control transistor and the active layer of the sixth control transistor are formed as an integral active layer, which extends along the first direction; At least a portion of the orthographic projection of the active layer of the fourth control transistor onto the substrate is located between the orthographic projection of the second plate of the second capacitor onto the substrate and the orthographic projection of the active layer of the integral structure onto the substrate. At least a portion of the active layer of the seventh control transistor is located between the active layer of the integral structure and the active layer of the fourth control transistor. And / or, The shift register unit further includes a second coupling node, a first control transistor, a second control transistor, and a third control transistor; the gate of the first control transistor is coupled to the second coupling node, the first terminal of the first control transistor is coupled to a first level signal line, and the second terminal of the first control transistor is coupled to a second input node; the gate of the second control transistor is coupled to the first input node, the first terminal of the second control transistor is coupled to a second level signal line, and the second terminal of the second control transistor is coupled to the second input node; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second coupling node; the active layer of the seventh control transistor is located between the active layers of the first control transistor and the active layers of the eighth control transistor; The active layers of the first control transistor and the third control transistor are arranged along the first direction, and at least a portion of the active layer of the second control transistor is located between the active layers of the first control transistor and the third control transistor. The active layers of the first control transistor, the second control transistor, and the third control transistor are sequentially coupled to form a single structure.

14. The display substrate according to any one of claims 1 to 6, wherein, The first level signal line and the second level signal line in the display substrate are arranged along the second direction; the orthographic projection of the other transistor structures in the shift register unit, excluding the output transistor, on the substrate is located between the orthographic projection of the first level signal line on the substrate and the orthographic projection of the second level signal line on the substrate.

15. A display device comprising a display substrate as claimed in any one of claims 1 to 14.

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