Method for compensating for errors during the periodic operation of an electronic switching element

Abstract

The invention relates to a method for compensating for errors during the periodic operation of an electronic switching element, in particular a MOSFET, of a converter device, in particular a DC / DC converter device, for example a step-up converter, wherein power factor correction is carried out by means of the operation of the switching element.

Description

[0001] 202500226

[0002] 1

[0003] Description

[0004] Method for compensating for errors during the periodic operation of an electronic switching element

[0005] The invention relates to the field of power electronic converter devices, in particular power factor correction (PFC) stages in

[0006] Vehicle onboard chargers. More precisely, the invention relates to a method for compensating errors in the periodic operation of an electronic switching element - in particular a transistor, preferably a MOSFET - within a DC / DC converter device, for example a boost converter, in order to achieve highly precise current guidance and thus a low current harmonic.

[0007] Within the scope of this disclosure, the behavior of a MOSFET is explained as an example of an electronic switching element. The disclosure is applicable analogously to other electronic switching elements, in particular to any type of transistor.

[0008] Active PFC (boost) converters are used to ensure a power factor close to 1 and low Total Harmonic Distortion (THD) in accordance with EN 61000-3-2.

[0009] The load current is often measured cost-effectively via a shunt resistor using a digital current control loop (PWM control module). However, in practice, several time delays occur:

[0010] • parasitic gate driver delays (tGDon, tGDoff),

[0011] • Resonance-related delays when switching off the MOSFET (tRESoff), • Sampling latencies of the measurement chain.

[0012] These delays cause the load current value used in the control loop to deviate from the actual current waveform; consequently, the control quality decreases.

[0013] 2

[0014] and the THD increases. Known standard control systems either inadequately account for such delays or require high computing power.

[0015] It is therefore an object of the invention to provide an improved method. In particular, it is an object of the invention to provide a method that compensates for the aforementioned sources of error – especially the switching element turn-off delay – preferably without having to change the existing PWM control loop in its control design, and which is particularly feasible with limited computing resources in a microcontroller.

[0016] At the very least, the purpose of the invention is to create an alternative to the state of the art.

[0017] The invention solves the problem(s) according to claim 1. Preferred embodiments are the subject of the dependent claims.

[0018] The disclosed method for compensating for errors in the periodic operation of an electronic switching element, in particular a MOSFET, a converter device, in particular a

[0019] A DC / DC converter device, for example a boost converter, in which power factor correction is performed by means of the operation of the switching element, comprises the following steps:

[0020] - Determining a load current value, which in particular includes a value of the collector current, by the switching element, wherein the load current value is in particular representative of a specified or measured maximum value of the load current during a period;

[0021] - Providing an analytically calculated value and / or an empirically determined value, an empirically determined value in particular for load currents below a given threshold, for a

[0022] Switching element turn-off delay, especially at the end of the period, 202500226

[0023] 3

[0024] where the calculation is performed in particular on the basis of V_C (intermediate circuit voltage), V_in (input voltage), l_Lpeak (peak current value), z_0 (resonant impedance), depending on the load current through the switching element and / or depending on a switching delay caused by a control circuit of the switching element, in particular a gate driver circuit;

[0025] - Determining a switch-off time setpoint for a pulse by means of a

[0026] PWM control loop module;

[0027] - Performing a correction of the switch-off time setpoint using the value for the switching element switch-off delay, in particular where the correction by the PWM control loop module is disregarded, in particular the calculations of the PWM control loop module are carried out independently of the switching element switch-off delay.

[0028] The switching element turn-off delay can be determined analytically – e.g., using the parameters VC (intermediate circuit voltage), Vin (input voltage), ILpeak (peak current value), zO (resonant impedance) – and / or empirically. For low load currents below a threshold, an empirical value stored in a look-up table (LUT) is preferred.

[0029] Collector current can be understood as the time-dependent current that flows directly through the electronic switching element and thus constitutes the main energy-transferring current. In a MOSFET, the collector current corresponds to the drain-source current. The term is used in a transistor-neutral manner and allows for a uniform terminology across different switching element technologies.

[0030] The method according to claim 1 enables:

[0031] - Increased accuracy of current measurement.

[0032] - Reduction of THD and increase of the power factor (EN 61000-3-2). - Software enhancements only; no changes to the power hardware are required. 202500226

[0033] 4

[0034] - Low computational load, since, for example, a LUT with few support points can be used for current-dependent correction.

[0035] This combination of features offers the advantage that the greatest source of error—the current- and voltage-dependent turn-off delay of the MOSFET—is compensated for directly at its source, namely before the PWM signal is generated. This prevents the load current setpoint from being subsequently distorted, but rather corrects it directly in the microcontroller, ensuring that the downstream control loop remains stable. Technically, this results in more precise current control, a reduction in harmonics, and an increase in the power factor according to EN 61000-3-2. This software-based approach allows for retrofitting existing control units without requiring costly modifications to the power or measurement technology.

[0036] The method as disclosed may further comprise the following steps according to claim 2:

[0037] - Setting a target time for measuring the load current to determine the load current value during a period;

[0038] - Correction of the target date by at least one measure from the following group:

[0039] - Shifting the switching-on time of the switching element;

[0040] - Shifting the switching-off time of the switching element;

[0041] - Shift of the target time relative to the switch-on and / or switch-off time, especially depending on the switching element switch-off delay.

[0042] The method according to claim 2 offers the advantage that the target time for measuring the load current to determine the load current value is dynamically adapted to the changed switching kinematics, thereby simultaneously compensating for both switch-on and switch-off delays. This ensures that the current sampling is always performed at the point where the measured value corresponds to the actual value, regardless of variations in the conductor, components, or temperature.

[0043] 5

[0044] The mean value is used. This increases measurement accuracy and improves the system's control reserve.

[0045] The method disclosed according to claim 3 may further comprise measuring the load current by measuring the voltage drop across a shunt resistor in the load circuit of the switching element, in particular by means of a measuring arrangement comprising at least one assembly from the following group: analog-to-digital converter, signal conditioning arrangement, in particular signal conditioner, sample & hold arrangement, in particular sample-hold element.

[0046] The method according to claim 3 is advantageous because the load current measurement is realized by means of a shunt resistor and a downstream analog-to-digital chain.

[0047] This results in a cost-effective, easily calibrated, and high-bandwidth measurement system capable of capturing the entire current without an additional current transformer. Thanks to integrated signal conditioning and a sample-and-hold stage, noise is minimized and deterministic latency for digital evaluation is ensured, further increasing the reliability of the described correction methods.

[0048] The method disclosed according to claim 4 may comprise determining the value for the switching element turn-off delay based on one or more parameters from the group:

[0049] - Current setpoint,

[0050] - Input voltage,

[0051] - Output voltage,

[0052] - Switching element turn-on delay,

[0053] - Switching element turn-off delay, especially as a function of current and voltage,

[0054] - Turn-off delay induced by the gate driver;

[0055] representative value is determined. 202500226

[0056] 6

[0057] By adaptively determining the switch-off delay based on representative operating parameters according to claim 4, the method is robust against component and environmental variations. It is advantageous that the correction applies both at high load currents (analytical model) and in the partial load range (empirical model).

[0058] LUT values) work precisely. At the same time, the size of the look-up table can be reduced, since only a few reference points for the relevant parameters need to be stored, which minimizes memory requirements and processing time in the microcontroller.

[0059] In the method disclosed according to claim 5, a setpoint for the switching time can be corrected, in particular by means of a constant value, especially depending on the (type) characteristics of the switching element, in particular its parasitic capacitances.

[0060] The method according to claim 5 offers the advantage that the constant turn-on delay of the gate driver path is also systematically eliminated. Adding a fixed time compensation eliminates any remaining systematic offset, further increasing the mean accuracy of each current sample. Since the value can be set depending on the type, the algorithm causes no or only minimal additional computational overhead during real-time operation.

[0061] In the method disclosed according to claim 6, the determination of the switch-off time delay as a function of the load current can be carried out independently of the voltage in the load circuit of the switching element.

[0062] Advantageously, according to claim 6, the complexity of the model is reduced by determining the switch-off delay as a first approximation solely based on the current. Since the voltage dependence is low in many practical applications, complex voltage sensors or additional calculations can be dispensed with. This reduces the requirements for A / D channels and program memory, which is particularly important for cost- and resource-optimized microcontrollers, without affecting the overall accuracy of the method.

[0063] 7

[0064] Character description

[0065] The Revelation is exemplified in the following figures. These show:

[0066] - In Figure 1: Digitally controlled PFC boost converter

[0067] - In Figure 2: Current flow during the switch-on phase

[0068] - In Figure 3: Current flow during the switch-off phase

[0069] - In Figure 4: Functional circuit diagram of current detection

[0070] - In Figure 5: MOSFET with parasitic capacitances

[0071] - In Figure 6: Charging characteristic of a real MOSFET

[0072] - In Figure 7: MOSFET turn-on and turn-off delays

[0073] - In Figure 8: Equivalent circuit diagram of the resonant circuit

[0074] - Figure 9: Datasheet characteristics of the parasitic MOSFET capacitances - Figure 10: Resonance-related turn-off delay

[0075] - In Figure 11: Block diagram of the switch-off time correction

[0076] The overall efficiency of an electric vehicle is largely determined by the onboard charger (OBC). The OBC includes, among other things...

[0077] a) a Power Factor Correction stage (PFC boost converter) for

[0078] Mains-to-DC-circuit conversion and

[0079] b) a subsequent high-voltage DC / DC stage for current control.

[0080] According to EN 61000-3-2, every switched-mode power supply application above 75 W must exhibit a nearly sinusoidal mains current with low total harmonic distortion (THD). This is achieved using the active PFC boost topology.

[0081] In a cost-efficient design, the load current iL (in the sense of the load current value according to claim 1) is detected via a low-side shunt (R_shunt) and processed digitally in a PWM control loop module (see Figure 1).

[0082] During the off-phase (OFF phase) of the electronic switching element (MOSFET), iL(t) is ≤ 0 A; during the on-phase (ON phase), iL(t) exceeds the periodic mean value (see Figures 2 and 3). Within the scope of this disclosure, the behavior of the electronic switching element is described as an example.

[0083] 8

[0084] a MOSFET is explained. The disclosure is applicable analogously to other electronic switching elements, in particular to any type of transistor.

[0085] Typically, a sample correction algorithm extrapolates the mains input current from the current measurement during the switch-on phase.

[0086] For current-measurement-based control that minimizes total harmonic distortion (THD), it is crucial to precisely determine the turn-on and turn-off phases. The timing of the switching MOSFET is affected by parasitic effects.

[0087] Two approaches are being considered to improve the accuracy of current measurement:

[0088] Method 1: Correction of the PWM timings (switch-on and switch-off times)

[0089] Method 2: Correction of the measured current value

[0090] Method 1 requires the least computational effort on microcontrollers and is therefore the focus of this disclosure.

[0091] A correction method is proposed, particularly for the main sources of error. To achieve precise MOSFET turn-on / turn-off timing and thus accurate current measurement, the following is specifically addressed:

[0092] MOSFET turn-off delay is compensated in the microcontroller calculation chain (see Figure 4).

[0093] A field-effect transistor (especially a MOSFET) has three terminals: source, gate, and drain (see Figure 5). The capacitances for these terminals are: Input capacitance: Ciss = CGD + CGS

[0094] Output capacity: Coss = CDS + CGD

[0095] The capacitors are each isolated from each other by an oxide layer. Additionally, a freewheeling diode with a pn junction and associated 202500226 is connected in reverse bias.

[0096] 9

[0097] Space charge region integrated. This topology causes the occurrence of a parasitic "Miller capacitance", which is why the voltage rise during gate charging is delayed (see Figure 6).

[0098] The current setpoint specified by the microcontroller does not exactly match the actual drain-source current of the MOSFET; this is due to both a resonance-related effect and the switching delays of the switching element.

[0099] In Phase I (see Figure 6), the gate-source voltage VGS behaves like the charging curve of a capacitor and rises to the plateau voltage Vgp. Once the threshold voltage is reached, the transistor switches to the conducting state and the drain current ID begins. In Phase II, the increasing drain current causes a decrease in the drain-source voltage VDS.

[0100] Due to the negative slope of VDS, the transistor operates as an inverting voltage amplifier during this time interval; this causes the so-called Miller effect, in which the effective input capacitance Ce increases several times over. This relationship can be expressed using an absolute voltage gain factor Au:

[0101] Ce = (1 + |A |) ■ CGD

[0102] Phase II is referred to in the literature as the "Miller Plateau" (see Figure 6). The corresponding datasheets for the electronic components contain the relevant information.

[0103] Plateau voltage is usually denoted as Vgp. Once the Miller plateau is overcome, Phase III begins (see Figure 6): In this phase, the parasitic capacitances are fully charged to their final values, causing the MOSFET to reach its full conduction state at the end of Phase III.

[0104] The time delay between the switch-on time specified by the microcontroller and the actual complete switching of the switching element (switch-on delay tGDon ​​or switch-off delay tGDoff + tRESoff) has a significant influence on the current measurement accuracy. The real 202500226

[0105] 10

[0106] The values ​​of these switching delays can, in principle, be determined analytically. However, to reduce the computational effort in the microcontroller, a

[0107] A look-up table (LUT) is stored, from which interpolation is performed depending on current and voltage values.

[0108] Since the exact peak current ILpeak is a function of the (software-compensated) turn-off delay, it cannot be determined directly through purely analytical means. The times specified in the MOSFET datasheet merely reflect the idealized laboratory case. A more practical correction function can therefore be improved by combining analytical approaches with datasheet specifications and empirical measurement results.

[0109] Minimizing input data is advantageous for microcontroller environments. Key input variables (see Figures 7 and 8) include, among others: - current setpoint,

[0110] - Input and output voltage,

[0111] - Resonance-induced switch-off delay tRESoff as a function of current and voltage.

[0112] The switch-on delay (tGDon) can be considered essentially constant. Its magnitude is practically independent of current and voltage.

[0113] The resonance effect of the MOSFET is primarily caused by the parasitic output capacitance Coss. It occurs mainly during the turn-off process because the main inductance L, together with the output capacitance Coss, forms a series resonant circuit. This oscillation ends when the voltage across Coss has risen sufficiently for the freewheeling diode to conduct forward to the output. Until this point, the input current continues to rise; this results in the current value measured at the sampling point being too low, while the actual average current value is already higher, thus distorting the current measurement (see Figures 7 and 8).

[0114] Figure 8 schematically shows the series resonant circuit with: 202500226

[0115] 11

[0116] - L: Inductance of the charging coil

[0117] - Coss = CDS + CGD : Output capacitance

[0118] - Vc: Voltage across the parasitic capacitance Coss.

[0119] - Vin: Drain-source voltage of the MOSFET

[0120] - z_0= (L / C_oss ): Resonance impedance of the LC resonant circuit

[0121] - l_(L_Peak): Peak current at the time of shutdown

[0122] - 1_(1 ,2): Charging time of the capacitor Coss

[0123] The switch-off time delay tGDoff can be calculated analytically using the LC resonance effect:

[0124]

[0125] when the parasitic capacity is assumed to be constant.

[0126] In real circuits, ohmic resistances dampen the resonance response. Furthermore, neither the inductance of the main choke L nor the parasitic output capacitance Coss of the MOSFET is constant over the mains period. In particular, Coss varies significantly with the applied reverse voltage or drain-source voltage (see Figures 9 and 10).

[0127] In real circuits, ohmic resistances dampen the resonance response. Furthermore, neither the inductance of the main choke L nor the parasitic output capacitance Coss of the MOSFET is constant over the mains period. In particular, Coss varies significantly with the applied reverse voltage or drain-source voltage (see Figures 9 and 10).

[0128] Two process steps can be performed to adjust the microcontroller control signal:

[0129] Step 1: Shifting the PWM switch-off time: 202500226

[0130] 12

[0131] By selectively shifting the turn-off setpoint, both the resonance-induced turn-off delay tRESoff and the delay tGDoff caused by the gate driver can be compensated. The correction function is inserted immediately before the output to the microcontroller pin so that the changed duty cycle duration does not affect the higher-level control loop (see Figure 11).

[0132] Since the shutdown process is controlled at a higher software level, the calculation can be performed in standardized units. The new target shutdown time is determined according to the following relationship:

[0133]

[0134] This means

[0135] - Dset: duty cycle setpoint output by the PWM control loop module, - 1 RESoff: resonance-induced switch-off delay,

[0136] - 1 GDoff / 1 GDon: shutdown or shutdown caused by the gate driver.

[0137] Power-on delay,

[0138] - Dcorr: current- or voltage-dependent correction factor (for example, from a LUT).

[0139] Step 2: Shifting the ADC sampling trigger to the PWM turn-on phase. Placing the sampling in the middle of the turn-on duration allows for compensation of the nearly constant turn-on delay T_on. This can be implemented in three alternative ways:

[0140] 1) Shift of the rising edge of the PWM pulse,

[0141] 2) Shifting the falling edge of the PWM pulse or

[0142] 3) Directly moving the measurement trigger within the PWM pulse to the desired sampling position.

Claims

202500226 13 Patent claims 1. Method for compensating errors in the periodic operation of an electronic switching element, in particular a MOSFET, a converter device, in particular a DC / DC converter device, for example a boost converter, wherein a power factor correction is carried out by means of the operation of the switching element, comprising the steps: - Determining a load current value, which in particular includes a value of the collector current, by the switching element, wherein the load current value is in particular representative of a specified or measured maximum value of the load current during a period; - Providing an analytically calculated value and / or an empirically determined value, an empirically determined value in particular for load currents below a given threshold, for a Switching element turn-off delay, in particular at the end of the period, wherein the calculation is carried out in particular on the basis of V_C, V_in, l_Lpeak, z_0, depending on the load current through the switching element and / or depending on a switching delay caused by a control circuit of the switching element, in particular a gate driver circuit; - Determining a switch-off time setpoint for a pulse by means of a PWM control loop module; - Performing a correction of the switch-off time setpoint using the value for the switching element switch-off delay, in particular where the correction by the PWM control loop module is disregarded, in particular where the calculations of the PWM control loop module are independent of the switching element switch-off delay. 202500226 14 2. Method according to claim 1, comprising the steps - Setting a target time for measuring the load current to determine the load current value during a period; - Correction of the target date by at least one measure from the following group: - Shifting the switching-on time of the switching element; - Shifting the switching-off time of the switching element; - Shift of the target time relative to the switch-on and / or switch-off time, especially depending on the switching element switch-off delay.

3. Method according to the preceding claim, wherein the measurement of the load current is carried out by measuring the voltage drop across a shunt resistor in the load circuit of the switching element, in particular by means of a measuring arrangement comprising at least one assembly from the following group: analog-to-digital converter, signal conditioning arrangement, in particular signal conditioner, sample & hold arrangement, in particular sample-hold element.

4. Method according to at least one of the preceding claims, wherein the value for the switching element switch-off delay is determined based on one or more parameters from the group: - Current setpoint, - Input voltage, - Output voltage, - Switching element turn-on delay, - Switching element turn-off delay, especially as a function of current and voltage, - Turn-off delay induced by the gate driver; representative value is determined. 202500226 15 5. Method according to at least one of the preceding claims, wherein a switch-on time setpoint is corrected, in particular by means of a constant value, in particular depending on the (type) characteristics of the switching element, in particular its parasitic capacitances.

6. Method according to at least one of the preceding claims, wherein the determination of the switch-off time delay as a function of the load current is independent of the voltage in the load circuit of the switching element.

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