Fail-safe update of a timer system for pwm in a synchronous controller

Abstract

A method for controlling a power factor correction filter provides that switching signals provided in periods are calculated. The calculated switching signals are stored in a buffer, together with time information that identifies the time position within the period. In an update process, the stored switching signals are output from the buffer. As part of the update process, a check is performed as to whether the stored switching signals relate entirely to the current period. The stored switching signals are output for the current period only if this is the case. The power factor correction filter is operated with the output switching signals.

Description

[0001] Fail-safe updating of a timer system for PWM in a synchronous controller

[0002] Pulse-width modulated switching (PWM) is frequently used to control electrical power devices, with the PWM often being executed synchronously with the control process. A microcontroller is used to perform this. The internal timer system must be updated with the currently calculated values ​​(i.e., switching signals). The timer system is connected to the processing cores (CPUs) via a bus system. It may be intended that the same bus system is used by other subsystems of the microcontroller, thus requiring the bus system to be shared as a resource. Resource conflicts can occur if the timer system updates at a high repetition rate. The update may be delayed or may not be (fully) executed before the current PWM period ends.

[0003] The approach described here addresses this problem and proposes monitoring the time at which the update takes place, and in particular provides a fail-safe mechanism in case the update is not performed on time (late).

[0004] To generate PWM signals, a "shadow mechanism," i.e., a buffer, is provided by the timer system. This buffer can be a register, such as a shadow register. The buffer is provided by the microcontroller. It is configured to update all timers in the timer system simultaneously, particularly at the end of the PWM period.

[0005] The shadow mechanism is deactivated at the beginning (of the PWM period) and reactivated during the penultimate write operation or penultimate write timeslot of the timer system update. The timer system is updated multiple times during a PWM period, in particular at least 3, 4, or 5 times, and especially at least 46 or 10 times. Embodiments provide for updates between 4 and 11 times. Several write timeslots or multiple write operations occur within a PWM period. Updated switching signals (generated by the control method, which is executed in particular by the microprocessor) are written in a write timeslot. The deactivation and reactivation at the penultimate write timeslot ensures that the settings (switching signals) of the timers synchronized by the timer system correspond to each other, i.e., pertain to the same PWM period.At the end of the update, the time position within the (PWM) period is read or recorded and written (to the buffer). In the next PWM period, the control procedure requests a new switching signal (PWM update). It checks whether the last (immediately preceding) update occurred within the current PWM period. If so, the shadow mechanism (i.e., writing to the buffer or shadow register) was reactivated or activated too late, and the desired PWM values ​​(i.e., switching signals) were not yet active (or did not pertain to the current PWM period of the new switching signal). The current timer system request is then not executed; that is, the switching signals are not output for execution or are withheld. The "too late" condition occurs, in particular, if the buffer update does not end in the same period in which it began.

[0006] This ensures that the synchronization between the control process and the execution of the switching signals (PWM values) is maintained.

[0007] The procedure described here is implemented particularly in the context of operating a power factor correction filter, specifically a power factor correction filter (PFC) of a vehicle-side charging circuit for an electric vehicle. This procedure specifically concerns the control of a PFC during the charging of an electric vehicle and / or when drawing electrical power from a vehicle, for example, to supply an AC power grid, particularly a supply network. Charging involves transferring electrical power from an AC power grid, especially a supply network, to an electric vehicle.The procedure described here can also be used to operate an electric drive in a suitable inverter that converts direct current (from a traction battery) into alternating current for operating an electric drive in a vehicle. In this context, "drive" specifically refers to a traction drive.

[0008] A method for controlling a power device, in particular a power factor correction filter, is described. Switching signals (PWM signals) are calculated, especially by a microcontroller. The switching signals are divided into periods. The calculated switching signals are stored in a buffer. The switching signals are transmitted via a bus of the microcontroller. Additional data sources or sinks can be provided on this bus (especially a data bus). The switching signals are stored in the buffer together with time information. The time information indicates the time position within the period. The time position is read from the corresponding memory, either alternatively or in combination with this information (preferably instead of being written).

[0009] In an update process, the stored switching signals are output from the buffer, specifically to an output through which the switching signals to be executed (target switching signals) are output. These switching signals are then sent to the power switches of the power device to control them according to the switching signals. During the update process, it is checked whether the stored switching signals (preferably) relate entirely to the current period (PWM period). The stored switching signals for the current period are output if this is the case. If not, the stored switching signals for the current period are not output (but, for example, only for the next PWM period, in which case updated switching signals for the current period are output instead of the signals that were not output, provided the aforementioned condition is met for them).In particular, instead of the switching signals that should not be output, the switching signals of the previous period are output. The power device, especially the power factor correction filter, is operated with the output switching signals.

[0010] A modular timer module (GTM, generic timer module) maintains a shadow register for multiple timer applications. In exemplary embodiments, the timer applications can communicate over the same bus that also carries the switching signals. The modular timer module is configured to update (i.e., synchronize) the multiple timer applications simultaneously. The shadow register is preferably deactivated for time slots at the beginning of a period (PWM period). The shadow register is specifically activated in the penultimate time slot (of the same period). When the shadow register is activated, the switching signals are written to the shadow register along with their time position. Specifically, the switching signals are written to a main register, which is preferably the register that determines the executed or to-be-executed PWM (i.e., the executed or to-be-executed switching signals).Defined. When the shadow register is deactivated, switching signals are not written to the shadow register or the main register. The shadow register essentially corresponds to the intermediate storage. Specifically, the shadow register is reactivated during the penultimate write operation of the timer unit.

[0011] In some embodiments, the time position (of the period or the current period) is read from the shadow register and stored at the end of the update process, preferably together with the associated switching signal. In particular, a counter register can be provided from which the time position is read (e.g., instead of from the shadow register). It can also be provided that, at the end of the update process, the time position (of the period or the current period) is read from the counter register and stored, preferably together with the associated switching signal. The counter register serves, for example, to count time units. The counter register can be assigned to or correspond to the timer system. The counter register and the main register mentioned here have distinct functions and preferably exist side by side (i.e., they are each individual registers).

[0012] The output of the stored switching signals is preferably withheld if the buffer transitions too late from a deactivated state to an activated state.

[0013] It is assumed that the cache transitions too late from a disabled state to an enabled state if the condition is met that the last cache update takes place within the current period.

[0014] In some embodiments, the intermediate storage is the shadow register. Shadow register updates can be disabled for one or more time slots within a plurality of time slots in a period.

[0015] Preferably, the shadow register for timeslots is deactivated at the beginning of a period and reactivated in the penultimate timeslot of that period.

[0016] The time information can be provided as a timestamp that numerically represents a specific point in time. Alternatively, the time information can be provided by storing the relevant switching signal as a separate memory entry in a specific timeslot, with the time information derived from the temporal assignment of the memory entry to the PWM period.

[0017] A computer program can be provided that executes the procedure described herein when it runs on a processor (microprocessor). In particular, the computer program can implement the claimed method. The computer program can also be provided on a data carrier or can be the subject of data transmission.

[0018] Furthermore, a control device can be provided that is configured to execute the procedure described herein. The control device includes, in particular, the microcontroller described herein along with its intermediate memory. Finally, a power device can be provided with power switches and the control device, which is connected to the power switches for control purposes. The power switches are controlled according to the procedure described herein; this is initiated by the control device. A control mechanism can be implemented in the control device with the control objective of achieving a predetermined power factor at the input of the power device, which is preferably implemented as a power factor correction (PFC).

[0019] Figure 1 shows an example sequence to illustrate the procedure described here.

[0020] The first timeslot, DMA#1, represents the end of the buffer deactivation. This corresponds to the end of the deactivation (DE) for the relevant PWM period. Two timeslots, DMA#2 and DMA#3, follow, during which (for a given switch) the power device's switching signals are updated. In these timeslots, DMA#2 and DMA#3, the update is consistent; this state is described as KA. This state means that the timing signals are not delayed, or that the timing signals pertain to the current PWM period and were written before the penultimate timeslot. Consistent means that if the buffer is deactivated first, the switching signals written in DMA#2 and DMA#3 will match (i.e., be associated with a common switching signal or correspond to each other) as soon as the buffer is reactivated. During this time slot, the PWM switching signals for the current PWM period are stored in the buffer.

[0021] Since a total of five timeslots, DMA#1 - DMA#5, are displayed, the fourth timeslot, DMA#4, is the penultimate timeslot. This represents the end of the active buffer RE, or rather, the timeslot RE for which updating is disabled. In other words, the penultimate timeslot, DMA#4, represents the timeslot for which the buffer is reactivated, specifically to prevent subsequent write attempts for switching signals and to ensure that previously written timeslots are in the state KA, i.e., consistent with each other. This ensures that current switching signals for the current PWM period are available at the last timeslot. Reactivating at the penultimate timeslot prevents switching signals that are delayed due to write delays and pertain to the current PWM period from being available for output in the following PWM period.

[0022] The timestamp is output in the last timeslot, DMA#5. Specifically, timing information stored in the buffer relating to the switching signals (which are stored in DMA#2 and 3) can be checked to determine whether it corresponds to the current PWM period (or whether it is delayed). Timeslots DMA#1-DMA#4, or rather their data, are transferred to a modular timer unit (GTM). The data from timeslot DMA#5 is transferred to a processor (CPU) of the microprocessor. The processor specifically checks whether the stored switching signals relate entirely to the current period or not. If the former is the case, the switching signals are output; otherwise, they are not (instead, the next PWM period is awaited to update the switching signals).

Claims

Patent claims 1. A method for controlling a power factor correction filter, wherein switching signals provided in periods are calculated, the calculated switching signals are stored in a buffer together with time information that identifies the time position within the period, and in an update process the stored switching signals are output from the buffer, wherein, as part of the update process, it is checked whether the stored switching signals relate completely to the current period, and the stored switching signals are output for the current period only if this is the case, and the power factor correction filter is operated with the output switching signals.

2. The method of claim 1, wherein a modular timer unit for multiple timer applications maintains a shadow register configured to update the multiple timer applications simultaneously, wherein the shadow register is deactivated for time slots at the beginning of a period and activated in the penultimate time slot, wherein the switching signals are written to the shadow register or main register when the shadow register is activated, together with the time position.

3. Method according to claim 2, wherein the shadow register is reactivated during the penultimate write operation of the timer unit.

4. Method according to claim 2 or 3, wherein at the end of the update process the time position is read from the shadow register and stored.

5. Method according to one of the preceding claims, wherein the output of the stored switching signals is withheld if the intermediate storage transitions too late from a deactivated state to an activated state.

6. Method according to claim 5, wherein the buffer transitions from a deactivated state to an activated state too late if the last update of the buffer takes place within the current period.

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