Method for providing measurement data for an os task of a real-time operating system

Abstract

The method comprises the following steps in this case: receiving a sample stream provided at the output of a delta-sigma analogue-to-digital converter, delta-sigma ADC (DS ADC); filtering the sample stream using an N-th order infinite impulse response filter, IIR filter; feeding the filtered sample stream to a cascade of filter stages, the cascade having N filter stages and each filter stage having a delay element; reducing the sample rate of the data sample after each delay element by a factor M; and providing the filtered samples at least at the output of the N-th filter stage for further processing by an OS task.

Description

[0001] 202500351

[0002] 1

[0003] Description

[0004] Method for providing measurement data to an OS task of a real-time operating system

[0005] The present disclosure relates to a method and a processor unit for providing measurement data for an OS task of a real-time operating system. Furthermore, the disclosure relates to a measurement module, a DC-DC converter arrangement, a computer program, and a computer-readable medium.

[0006] Onboard chargers should be robust against EMC interference and emit only minimal electromagnetic emissions. Robust operation must be ensured even under noise influence. A more recent measure for minimizing magnetic emission is the application of frequency spreading in pulse-width modulation (PWM). With this method, the PWM output frequency of a modulator, rectifier, power factor correction stage, and / or DC-DC converter is slightly varied to avoid peaks in the emitted spectrum. Spectral peaks are rasterized across multiple frequencies. The implementation of a controller and associated metering system presents the following challenges:

[0007] 1.) Synchronous point measurement of current and voltage at the midpoint of each PWM signal does not fulfill the fundamentals of signal theory with regard to the Nyquist-Shannon sampling theorem. Undersampling leads to aliasing effects.

[0008] 2.) The varying PWM frequency of the spread spectrum cannot be synchronized with the fixed signal acquisition frequency. A constantly frequencyd delta-sigma analog-to-digital converter output cannot be synchronized with PWM at varying frequencies.

[0009] 3.) Asynchronous sampling with similar frequencies leads to different group delays, up to one sample period.

[0010] 4.) A higher acquisition frequency compared to the PWM frequency leads to a loss of acquisition samples.

[0011] One task to be solved is to provide a method for supplying measurement data to an OS task of a real-time operating system, which contributes to enabling cost-effective and precise control of a modulator for a switchable converter, in particular a power factor correction boost converter.

[0012] 2

[0013] The problem is solved by the features of independent patent claims.

[0014] Advantageous embodiments are characterized in the dependent claims.

[0015] The task is solved, according to a first aspect and a second aspect, by a method and a corresponding processor unit for providing measurement data to an operating system task (OS task) of a real-time operating system. The method comprises the following steps:

[0016] Receiving a bitstream provided at the output of a delta-sigma analog-to-digital converter (delta-sigma ADC),

[0017] Filtering the bitstream with an infinite impulse response filter, an nth-order R-filter, and providing a data sample stream at the output of the R-filter, feeding the data sample stream to a cascade of filter stages, wherein the cascade has N filter stages and each filter stage has a delay element, reducing the data sample rate of the data sample stream by a factor M after each delay element.

[0018] Providing the filtered data samples at one or more outputs of the respective filter stage for further processing by an OS task.

[0019] In at least one advantageous embodiment according to the first and second aspects, it is provided that a scheduler provides a number of delay cycles for the respective filter stage from the second filter stage onwards, and that the execution of the respective filter stage is delayed by the corresponding number of delay cycles.

[0020] In at least one advantageous embodiment according to the first and second aspects, it is provided that a single delay clock cycle is equal to one period of the sampling rate at the input of the cascade of filter stages.

[0021] In at least one advantageous embodiment according to the first and second aspects, it is provided that the delay element has the following Z-transfer function:

[0022]

[0023] where k is a filter coefficient.

[0024] In at least one advantageous embodiment according to the first and second aspects, the 11 R filter comprises an integer fixed-point IIR filter.

[0025] 3

[0026] In at least one advantageous embodiment according to the first and second aspects, it is provided that the 11 R filter comprises an integer 24-bit fixed-point IIR filter.

[0027] In at least one advantageous embodiment according to the first and second aspects, it is provided that the II R-filter is a second-order filter and requires a maximum of three multiplication operations with factors that are not equal to 2 or not equal to a multiple of 2, in particular those that are not equal to a power of two.

[0028] In at least one advantageous embodiment according to the first and second aspects, it is provided that the II R-filter has a Direct Form II Transposed structure.

[0029] In at least one advantageous embodiment according to the first and second aspects, it is provided that the method is executed by means of a Generic Timer Module (GTM) of a microcontroller, in particular by a multi-channel sequencer of the GTM.

[0030] In at least one advantageous embodiment according to the first and second aspects, the Delta-Sigma-ADC is provided to have a Delta-Sigma modulator and a cascaded integrator-differentiator filter.

[0031] The processor unit according to the second aspect preferably comprises a co-processor and at least one program memory, wherein the processor unit is configured to execute the method or an optional embodiment thereof.

[0032] The task is solved according to a third aspect by a boost converter arrangement comprising a boost converter and a control device, the control device having a processor unit according to the second aspect.

[0033] According to a fourth aspect, the task is solved by a computer program that includes commands which, when the program is executed by a control computer, cause it to carry out the procedure according to the first aspect.

[0034] The control computer has a processor and program memory. Alternatively, the program memory can be assigned to the control computer. The processor can have a central processing unit (CPU). The processor can be a general-purpose processor, a microprocessor, a microcontroller, a digital signal processor (DSP), or an application-specific integrated circuit.

[0035] 4

[0036] It may be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or another programmable logic device.

[0037] According to a fifth aspect, the task is solved by a computer-readable medium that includes instructions which, when executed by a control computer, cause it to carry out the procedure according to the first aspect.

[0038] The computer program can be stored on a computer-readable storage medium, in particular on non-volatile memory.

[0039] Advantageous designs according to the first and second aspects also apply to the third, fourth and fifth aspects.

[0040] The revealed method makes it possible to utilize sufficient oversampling despite limited computing resources. The 11 R-filter eliminates the need for floating-point arithmetic. The II R-filter can be implemented with a very small number of actual multiplications. The cascade of filter stages allows for the use of 8-bit filter coefficients, rather than requiring very small ones.

[0041] In particular, this method allows measured values ​​to be made available for further processing at different time intervals. Processing within the converter is clocked and time-controlled by a real-time operating system via an OS task scheduler. Current control is also task-based. Thus, the method makes it possible, for example, to provide current measurements for different OS tasks (e.g., a 5 ms task and a 10 ms task) – and therefore, in particular, depending on the timing requirements of the control function to be executed. The current values ​​can have varying degrees of accuracy.

[0042] Further advantageous embodiments are disclosed in the attached claims and in the following description of exemplary embodiments with reference to the attached figures.

[0043] The description of the items listed here is not limited to the individual specific embodiments. Features of different embodiments can be combined with one another – insofar as technically feasible – to create further [202500351]

[0044] 5

[0045] To form exemplary embodiments. For example, variations or modifications described with regard to one of the exemplary embodiments may also be applicable to other exemplary embodiments, unless otherwise stated.

[0046] They show:

[0047] Figure 1 shows an exemplary equivalent circuit of a boost converter.

[0048] Figure 2 shows an exemplary block diagram of an embodiment of a delta-sigma analog-to-digital converter arrangement.

[0049] Figure 3 shows an exemplary block diagram of an implementation of a software filter.

[0050] Figure 4a shows the structure of an 11 R-filter of the software filter,

[0051] Figure 4b shows a generalized Direct Form II transposed structure of an 11 R-filter of second order.

[0052] Figure 5 shows an example flowchart for calculating the data samples of the 11 R filter of the software filter.

[0053] Figure 6 shows an exemplary block diagram for an embodiment of a respective filter stage of a cascade of filter stages of the software filter.

[0054] Figure 7 shows an exemplary time diagram of staggered execution cycles of the respective filter stages of the filter stage cascade of the software filter.

[0055] Figure 8 shows a Bode diagram for the filter stage cascade of the software filter.

[0056] In the equivalent circuit diagrams and block diagrams shown, special or general values, rating data, additions, and the inclusion or exclusion of components are not intended to affect the scope of protection of the invention.

[0057] In the figures, the same reference symbols are used for elements with essentially the same function; however, these elements do not have to be identical in every detail. 202500351

[0058] 6

[0059] Figure 1 shows an exemplary equivalent circuit diagram of a boost converter. The boost converter is, for example, a power factor correction boost converter (PFC boost converter) of a vehicle charging device. The charging device can have several such PFC boost converters, in particular one for each phase.

[0060] The boost converter is driven, for example, by a pulse-width modulator. To reduce interference, frequency spreading is used for the pulse-width modulation. The repetition rate of the pulse-width modulation is therefore varied, for example, between 70 kHz and 90 kHz, in addition to changing the duty cycle. A frequency of 312.5 kHz is used for the measurement repetition, for example.

[0061] For precise, current-based control that minimizes overall harmonic distortion, highly accurate current measurement is required. The current is measured, for example, using a shunt resistor. To achieve sufficient accuracy, delta-sigma analog-to-digital converters (delta-sigma ADCs) are used for shunt current measurements. Due to the high switching frequencies, a compromise must be struck between a sufficiently high delta-sigma ADC output rate and precision, ensuring at least a few converter values ​​per PWM cycle. It should be noted that the current being measured can exhibit significant ripple (especially the second harmonic) with respect to the PWM switching frequency. For current measurement, a sampling rate of 312.5 kHz is used, for example. The delta-sigma ADC samples with an oversampling frequency of 20 MHz.

[0062] Figure 2 shows an exemplary block diagram of an embodiment of a delta-sigma analog-to-digital converter arrangement with a delta-sigma analog-to-digital converter (delta-sigma ADC) DS ADC and a software filter SW-FLT.

[0063] The DS ADC delta-sigma ADC comprises a DS-M delta-sigma modulator and, for example, a cascaded integrator-differentiator (CIC) filter. The CIC filter is a finite impulse response (FIR) filter. The 1-bit data stream at the output of the delta-sigma modulator is converted into a specific multi-bit word by the CIC filter, which is a decimation filter. Optionally, an input signal to the DS ADC is pre-filtered using an LP-FLT low-pass filter.

[0064] 7

[0065] An input signal, i.e., the desired measurement signal, of the delta-sigma ADC DS ADC has, for example, a bandwidth of 160 kHz after low-pass filtering. Sampling by the delta-sigma ADC is performed, for example, at a sampling frequency of 20 MHz. The CIC filter, for example, has three stages, each of which reduces the sampling rate by a factor of 64.

[0066] Decimation involves, for example, averaging. By accumulating the bitstream for a specific period and dividing the sum by the number of periods, the data resolution is increased from 1 bit to a multi-bit word – in exchange for a lower sampling rate. The sampling rate is slowed down during this phase.

[0067] The CIC filter with 3 stages, for example, has an attenuation of 40 dB at the Nyquist frequency.

[0068] For pulse-width modulation control, a short group delay and a high output data rate are required. This can be achieved with a high data output rate. The suitable output rate for a controller with a 70 kHz to 90 kHz varying repetition rate is preferably four times higher (> 300 kHz).

[0069] Figure 3 shows an exemplary block diagram of an embodiment of a software filter SW-FLT that follows the CIC filter CIC.

[0070] The software filter SW-FLT incorporates an nth-order infinite impulse response (II R-filter). II R-filters are best suited for this purpose. However, in cost-effective embedded systems, the problem arises that additional computing resources are required.

[0071] Furthermore, the software filter SW-FLT includes a cascade N_PT1 of N filter stages PT1j and a scheduler S.

[0072] The 11 R filter design is chosen to be suitable for a controller operating with a varying repetition frequency between 70 kHz and 90 kHz and a measurement repetition of 312.5 kHz.

[0073] The 11 R-filter HR preferably comprises an integer fixed-point IIR filter, for example, an integer 24-bit fixed-point I1R filter. That is, only fixed-point arithmetic is used. The operations used are bit shift operations, multiplications, and additions.

[0074] 8

[0075] In particular, divisions that cannot be performed by bit shifting are not carried out.

[0076] The 11 R-Filter HR can be implemented as follows:

[0077] 1. Implementation on the CPU:

[0078] 1 A) Ring result buffer with DMA (direct memory access). The IIR filter algorithm is applied to all newly acquired samples since the invocation with each read access by the control algorithm. This has the advantage of simple implementation. The disadvantage is the high runtime overhead on the kernel where the control algorithm runs.

[0079] or

[0080] 1 B) Sample-by-sample filtering: The IIR filter algorithm is executed for each newly acquired sample. The advantage here is that the core on which the control algorithm runs incurs no runtime overhead. The disadvantage is that significant runtime overhead is incurred on a separate core. This means that an additional, dedicated core is required.

[0081] 2) Implementation on the Bosch Generic Timer Module (GTM), Micro-Channel Sequencer (MCS):

[0082] The IIR filter algorithm is executed for each newly acquired sample on a dedicated MCS unit, commonly found in automotive microcontrollers. This has the advantage of eliminating runtime overhead on the CPU. It works on any microcontroller with a GTM unit. If available, filtering up to the 6th order at 312.5 kHz is possible on a 200 MHz GTM. The disadvantages are that a GTM MCS must be available and the MCS requires specific board programming.

[0083] Filtering with the II R filter is preferably performed by a co-processor – in particular, the Generic Timer Module. This eliminates the need for a second, complete microcontroller or processor core.

[0084] Figure 4a shows the structure of the 11R filter HR. The 11R filter HR is, for example, a second-order filter and has a Direct Form II transposed structure. The structure is very simple, and many arithmetic operations can be performed very easily using bit shift operations.

[0085] 9

[0086] can be executed quickly. The denominator coefficients [bO b1 b2] are in particular b0*

[0121] ,

[0087] A maximum of three multiplication operations with the factors bO, a1 and a2 are required.

[0088] Figure 4b shows, for comparison, a generalized Direct Form II transposed structure of an 11 R-filter of the second order.

[0089] Figure 5 shows an example flowchart for calculating the data samples, where: bO=BO_FAST, a1=A1_FAST and a2=A2_FAST.

[0090] It can be seen that only multiplication, addition, subtraction, and shift operations are performed.

[0091] For low-frequency visualization of measurement data (e.g., for application software functions that use OS tasks of a real-time operating system with a duration of 1ms, 5ms, or 10ms), the sampling rate is too high and must be further reduced.

[0092] A decimation filter that allows a high decimation rate by a factor of 3125 (312.5 kHz -> 100 Hz) would require extremely small filter factors.

[0093] To achieve robust decimation, a cascade with N decimation levels is proposed.

[0094] The software filter SW-FLT therefore has a cascade N_PT1 of filter stages PT1j, where the cascade N_PT1 has N filter stages PT1j, and each filter stage PT1j has a delay element. For example, N = 5. After each delay element, the sample rate is reduced by a factor M. The factor M is, for example, M = 4. This results in the following sample rates: 312.5 kHz, 78 kHz, 19.5 kHz, 5 kHz, 1.25 kHz.

[0095] The IIR filter, for example, has the following dimensioning data:

[0096] • - Input sampling rate: 312.5 kHz (= 20 MHz / 64)

[0097] • Specification: N, Fp, Fst

[0098] • Pass-through slope: 5 kHz

[0099] • - Stop band edge: 156 kHz202500351

[0100] 10

[0101] • Filter order: 2

[0102] • Design method: HR smallest p-norm

[0103] Measurements:

[0104] 3 dB point: 28.8359 kHz

[0105] 6 dB point: 37.1402 kHz

[0106] • Ripple in the passband: 0.001 dB

[0107] • Stopband attenuation: 85.5771 dB

[0108] • Crossover bandwidth: 151 kHz

[0109] Figure 6 shows an example block diagram for the respective filter stage PT1j. Each filter stage PT1j includes a delay element, preferably a PT1 element. That is, the filter exhibits a proportional transfer characteristic with a first-order delay.

[0110] The delay element has a Z-transfer function according to the following equation:

[0111]

[0112] Here, k is a filter coefficient; k can also be called a forgetfulness factor.

[0113] In the embodiment of a delay element shown in Figure 6, k = 1 / 256. This is the smallest value that can be represented with 8 bits. The delay element has a first amplifier V1 with a gain factor of k at its input. Furthermore, the delay element has a feedback loop with a second amplifier V2 and a delay element D. The delay element also includes an addition element that sums the amplified input sample and a feedback sample provided by the feedback loop to form a filter output sample. Each delay element includes a rounding element, `convert`, which rounds a value of the filter output sample so that the value can be represented with a predetermined number of bits, for example, 12 bits.

[0114] Figure 7 shows an example time diagram of staggered execution cycles of filter stages 2 to 5.

[0115] It can be seen that the filter stages PT1 j are not executed synchronously, but with a time offset. These time offsets are controlled by the scheduler S (Figure 3).

[0116] 11

[0117] The scheduler S specifies the time offset for each filter stage PT1 j. This has the advantage that the co-processor executes a maximum of only two filter stages simultaneously.

[0118] Figure 8 shows a Bode plot for the filter stage cascade N_PT1. The magnitude of the output signal is shown for each filter stage PT1 i.

[0119] In order for the signal to be correctly reconstructed, the Nyquist-Shannon sampling theorem stipulates that the original signal must be sampled at a rate (here, e.g., 312.5 kHz) that is more than twice the highest frequency present in the signal (here, for example, 160 kHz at the output of the low-pass filter TP-FL in Figure 2). If the sampling theorem is violated by a sampling rate that is too low, frequency components that were originally higher than half the sampling rate (Nyquist frequency f) will be lost. N s) are interpreted as lower frequencies because undersampling occurs at these frequencies. This unwanted phenomenon is called the aliasing effect.

[0120] As the Bode plot shows, the output signal after the first filter stage exhibits a frequency component above 0.06*f s with f s At 312.5 kHz, an attenuation of 40 dB is observed. The 40 dB cutoff frequencies for the subsequent filter stages can be found in the Bode plot.

[0121] Based on the Nyquist-Shannon sampling theorem, a suitable repetition for correct sampling is obtained for an output signal provided after the first filter stage, for example f. s = 312.5kHz:

[0122] Level 1: fTask >= 0.124fs = 38.8 kHz (tRecurrence <= 6.4ps)

[0123] Level 2: fTask >= 0.0067fs = 2.1 kHz (tRecurrence <= 119ps)

[0124] Level 3: fTask >= 0.0012fs = 380 Hz (tRecurrence <= 0.65 ms)

[0125] Level 4: fTask >= 0.0003fs = 95 Hz (tRecurrence <= 2.65ms)

[0126] Level 5: fTask >= 0.000075 fs = 23.5 Hz (tRecurrence <= 10.5ms)

[0127] This means that after the fourth filter stage, a task with a period of 5 ms can use this signal, and that a task with a period of 10 ms can use the signal at the output of the fifth filter stage.

Claims

1. 202500351 12 Patent claims 1. Method for providing measurement data to an operating system task, OS task, of a real-time operating system, comprising the following steps: - Receiving a bitstream provided at the output of a delta-sigma analog-to-digital converter, delta-sigma ADC (DS ADC), - Filtering the bitstream with an infinite impulse response filter, 11 R-filter, (IIR) nth order and providing a data sample stream at the output of the I IR filter (HR), - Feeding the data sample stream to a cascade (N_PT1) of filter stages (PT1 j), wherein the cascade (N_PT1) has N filter stages (PTT) and each filter stage (PTT) has a delay element, - Reduction of the data sampling rate of the data sample stream by a factor M after each delay element, - Providing the filtered data samples at one or more outputs of the respective filter stage (PT1 j) for further processing by an OS task.

2. The method of claim 1, wherein the method comprises the following further steps: - providing, by means of a scheduler (S), a number of delay cycles for the respective filter stage (PT1j) from the second filter stage (PTI2), and delaying an execution of the respective filter stage (PTT) by the associated number of delay cycles.

3. Method according to claim 2, wherein a single delay clock cycle is equal to one period of the sampling rate at the input of the cascade (N_PT1) of filter stages.

4. Method according to any of the preceding claims, wherein the delay elements have the following Z-transfer function: where k is a filter coefficient.

5. Method according to any one of the preceding claims, wherein the 11 R-filter comprises an integer fixed-point 11 R-filter.

6. A method according to any one of claims 1 to 4 above, wherein the R-filter comprises an integer-24-bit fixed-point R-filter. 13 7. Method according to any one of claims 2 to 4, wherein the IIR filter is a second-order filter and requires a maximum of three multiplication operations with factors that are not powers of two.

8. Method according to any of the preceding claims, wherein the IIR filter has a Direct Form II Transposed structure.

9. Method according to one of the preceding claims, wherein the method is carried out by means of a Generic Timer Module, GTM, a microcontroller, in particular a Multi Channel Sequencer of the GTM.

10. Method according to any of the preceding claims, wherein the Delta-Sigma-ADC (DS-ADC) comprises a Delta-Sigma-Modulator (DS-M) and a cascaded Integrator-Differentiator Filter (CIO).

11. Processor unit comprising a co-processor and at least one program memory, wherein the processor unit is configured to execute the method according to any one of claims 1 to 10.

12. Boost converter arrangement comprising a boost converter and a control device comprising a processor unit according to claim 11.

13. Computer program comprising instructions which, when the program is executed by a control computer, cause the latter to execute the method according to any one of claims 1 to 10.

14. Computer-readable medium comprising instructions which, when executed by a control computer, cause the latter to execute the method according to any one of claims 1 to 10.

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