Composite substrate having a radiofrequency performance level below a predetermined threshold

Abstract

The invention relates to a composite substrate (1) having an HD2 performance level of less than -80 dBm over a temperature range from 0°C to 150°C, the composite substrate comprising a silicon base substrate (4) having a resistivity R of between 100 Ohms.cm and 650 Ohms.cm at room temperature and a surface layer (2) formed of a monocrystalline material arranged on the base substrate. The composite substrate (1) also comprises an intermediate structure (3) arranged between the base substrate (4) and the surface layer (2), the intermediate structure (3) comprising an electric charge-trapping layer (3b). The intermediate structure (3) has an equivalent air thickness EAT, in terms of effective electrical permittivity, greater than a minimum thickness EATmin = -2.67 10^-3 * R + 3.3, when the resistivity R is expressed in Ohm.cm and the thickness is expressed in micrometers.

Description

Composite substrate exhibiting a radiofrequency performance level below a predetermined threshold FIELD OF INVENTION

[0001] The present invention relates to a composite substrate, that is, a substrate comprising a surface layer of a single-crystal material transferred onto a support. The invention also relates to the support substrate itself. The support is generally provided with a dielectric layer. The composite substrate is intended for applications in the field of integrated electronic components, particularly radio frequency (RF) components processing signals with frequencies typically ranging from 20 kHz to 300 GHz, or higher. The surface layer of the composite substrate may be made of a semiconductor material such as silicon or an insulating material, such as a material exhibiting piezoelectric and / or ferroelectric properties. The composite substrate may also find other applications, for example, in the field of photonics. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0002] It is common practice to incorporate a charge-trapping layer into the support of such a composite substrate. This layer (more concisely referred to as the "trapping layer" in the remainder of this description) can take the form of a polycrystalline silicon layer placed between the surface layer and a base substrate, generally chosen to be highly resistive (greater than 1000 Ohms·cm at room temperature). The trapping layer and the base substrate together form the support of the composite substrate. Such a support is generally intended to prevent or limit the electromagnetic coupling that can occur between a component formed on and / or within the surface layer and this support.

[0003] The RF performance of a component can be estimated by performing RF characterization of the composite substrate (and more specifically, the support structure for this composite substrate) on or in which the component is intended to be formed. As documented in the January 2015 publication "White paper – RF SOI Characterisation" by SOITEC, the RF performance of a substrate can be characterized by measuring the second harmonic distortion (HD2) in dBm. This measurement is performed using signals with a defined frequency (typically between 50 MHz and 28 GHz) and a power of 15 dBm, on 2 mm long coplanar lines. These lines may include a central transmission line (26 µm wide), flanked by two ground planes (208 µm wide), with a gap (12 µm wide) between the central transmission line and the ground planes.In this description, we will use the expressions "RF performance" and "HD2 measurement" interchangeably to characterize the RF behavior of a composite substrate.

[0004] The WO2024115410 document lists, in its introduction, other types of trapping layers whose properties can be exploited to improve the RF performance of components formed in and / or on the surface layer.

[0005] He also points out that these components tend to exhibit decreasing RF performance as their temperature increases, particularly when it exceeds 100°C. However, in certain environments, for example when the component is used in the automotive sector, it may be necessary to have components with stable RF performance, even when exposed to temperatures higher than 100°C.

[0006] Document FR3029682 describes how to improve the temperature stability of the RF performance of a composite substrate by implementing a highly resistive, trap-rich layer designed to electrically decouple the surface layer from the base substrate. According to this document, it is not necessary to use a base substrate with very high resistivity, as its resistance can range from 10 to 2000 Ohm·cm in the context presented.

[0007] The paper "Engineering SOI Substrates for RF to mmWave Front-Ends" by F. Alibert et al., published on October 14, 2020 (www.microwavejournal.com / articles / 34713-engineering-soi-substrates-for-rf-to-mmwave-front-ends), presents a composite substrate comprising a trapping layer formed by a thick layer of porous silicon. A composite SOI substrate with such a trapping layer, described in detail in document FR3098342, ensures temperature stability of RF components over a wide temperature range extending beyond 200°C. However, as illustrated in curve A1, this RF performance tends to decrease for signals with frequencies exceeding approximately 1 GHz, falling above the -80 dBm threshold at certain frequencies (close to 5 GHz). The growth in the HD2 measurement indicates a degradation of linearity when the frequency is above approximately 1 GHz.This is primarily due to the low resistivity of the base substrate (typically 0.5 Ohm.cm to 4 Ohm.cm) required for the formation of the porous trapping layer. Generally, the RF performance of a substrate, measured in HD2, should be lower than -80 dBm and improve with increasing signal frequency, which is clearly not the case for the composite substrate with a trapping layer formed from a thick layer of porous silicon proposed in this document.

[0008] However, it is sometimes important that RF performance be stable or decreasing, preferably monotonically, over a wide frequency range, and especially for RF signals with an operating frequency range between 900MHz and 28GHz. SUBJECT OF THE INVENTION

[0009] One object of the invention is to provide such a composite substrate. More specifically, one object of the invention is to provide a composite substrate exhibiting an RF performance level, measured in HD2, of less than -80dBm, for RF signals with an operating frequency between 900MHz and 28GHz, over a temperature range extending at least from 0°C to 150°C. Another object of the invention is to provide a support for a composite substrate exhibiting such RF performance. BRIEF DESCRIPTION OF THE INVENTION

[0010] To achieve one of these goals, the object of the invention proposes a composite substrate exhibiting an HD2 performance level of less than -80dBm in a temperature range between 0°C and 150°C. This composite substrate comprises: a silicon base substrate having a resistivity between 100 Ohms.cm and 650 Ohms.cm at room temperature; a surface layer formed of a single-crystal material disposed on the base substrate; and an interlayer structure disposed between the base substrate (4) and the surface layer (2).

[0011] According to the invention, the interlayer structure comprises an electrical charge trapping layer (3b) and has an equivalent air thickness EAT, in terms of effective electrical permittivity, greater than a minimum thickness EAT min equal to -2.67 10^-3 * R + 3.3, when the resistivity R is expressed in Ohm.cm and the thickness in micrometers.

[0012] According to other advantageous and non-limiting features of the invention, taken alone or in any technically feasible combination: the composite substrate has an HD2 performance level below -100dBm and the interlayer structure has an equivalent air thickness (EAT) greater than a minimum EAT thickness min equal to -5.00 10^-3 * R + 6.5, where the resistivity R is expressed in Ohm.cm and the thickness in micrometers. The base substrate has a resistivity measured at room temperature less than or equal to 300 Ohm.cm; the base substrate has a resistivity less than or equal to 125 Ohm.cm; the electrical charge trapping layer is a dielectric layer with a resistivity greater than or equal to 10^10 Ohm.cm; the electrical charge trapping layer has a resistivity greater than or equal to 10^6 Ohm.cm; the electrical charge trapping layer has a trap density greater than 10 17cm^-3; the electrical charge trapping layer is formed of a polycrystalline semiconductor material having a band gap of at least 3 eV; the electrical charge trapping layer is formed of polycrystalline silicon carbide; the electrical charge trapping layer is formed of polycrystalline or oxygen-rich amorphous silicon; the electrical charge trapping layer also includes nitrogen; the electrical charge trapping layer is formed of porous silicon.

[0013] Other features and advantages of the invention will become apparent from the detailed description of the invention which follows with reference to the attached figure, in which:

[0014]

[0015] Laest is a graph representing the HD2 measurement of a prior art composite substrate (curve A1) and a composite substrate according to the invention (curve A2);

[0016]

[0017] Lare represents a composite substrate according to the invention;

[0018]

[0019] Laest is a graph representing a minimum air thickness that must separate a surface layer from a base substrate for a composite substrate comprising this layer and this base substrate to meet required RF performance of -80dBm or -100dBm;

[0020]

[0021] Laillustre a method for manufacturing a support and a composite substrate conforming to a first aspect of the invention;

[0022]

[0023] Laillustre a method for manufacturing a support comprising a porous electrical charge trapping layer according to another aspect of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0024] For the sake of simplicity in the description to follow, the same references are used for identical elements or elements performing the same function in the different aspects of the invention.

[0025] A composite substrate 1 according to the invention is shown in Figure 3. In a very general way, such a composite substrate is composed of a base substrate 4, an interlayer structure 3 disposed on and in contact with the base substrate 4, and a surface layer 2 formed of a single-crystal material disposed on and in contact with the interlayer structure 3. The base substrate 4 and the interlayer structure 3 together form the support S of the composite substrate.

[0026] Conventionally, the composite substrate 1 can be in the form of a circular plate with a diameter of 100, 150, 200, 300, or even 450 mm. However, this shape and dimension are by no means significant features of the present invention.

[0027] This substrate exhibits an HD2 performance level of less than -80dB within a temperature range of 0°C to 150°C and for an operating frequency of at least 900MHz to 28GHz. This HD2 performance is advantageously and monotonically decreasing over this frequency range.

[0028] The single-crystal surface layer 2 is designed to accommodate components, for example, RF components. It can be of any suitable material, depending on the intended application and the nature of the RF component. It can notably be composed of at least one semiconductor material, such as silicon, strained silicon, germanium, gallium nitride, silicon carbide, diamond, etc. It can also be an insulating material, such as a material exhibiting piezoelectric and / or ferroelectric properties, for example, lithium tantalate, lithium niobate, aluminum nitride, PZT, etc. The surface layer has a thickness that can range from a few nanometers to a few microns, advantageously between 200 nm and 1500 nm.

[0029] To achieve the HD2 performance level within the temperature and frequency range specified above, the basic substrate 4 is chosen to have relatively low resistance. According to the invention, it exhibits a resistivity measured at room temperature (25°C) of between 100 Ohms.cm and 650 Ohms.cm.

[0030] It may seem surprising to choose a relatively low-resistivity base substrate 4 to contribute to the formation of a composite substrate 1 intended for RF applications. However, a highly resistive substrate tends, under the influence of temperature, to generate a high density of charge carriers in the form of electron-hole pairs. Consequently, a highly resistive substrate exhibits a resistivity that degrades sharply with temperature, due to the charge carriers that are released and tend to reduce the effective resistivity of the substrate. By choosing a relatively low-resistivity base substrate, with a resistivity between 100 Ohms·cm and 650 Ohms·cm, this effect is limited or prevented.

[0031] A minimum resistance value of 100 Ohms.cm ensures HD2 performance in the frequency range between 900 MHz and 28 GHz. A threshold value of 650 Ohms.cm ensures temperature stability in the range between 0°C and 150°C. As the temperature range extends towards higher temperatures, a base substrate with lower resistivity should be selected. Thus, to maintain RF performance levels in a temperature range between 0°C and 175°C, a base substrate with an ambient resistivity of 300 Ohms.cm or less (but above 100 Ohms.cm) should be chosen. To maintain performance levels over a temperature range of 0°C to 200°C, a base substrate 4 with an ambient resistivity of less than or equal to 125 Ohm.cm (while remaining greater than 100 Ohm.cm) will be chosen.

[0032] The base substrate 4 of the composite substrate 1, on which the surface layer 2 rests, is typically several hundred micrometers thick and forms the "mechanical" support for this layer. For reasons of availability and cost, the base substrate 4 is preferably made of monocrystalline silicon. For example, it could be a CZ silicon substrate with a low interstitial oxygen content of between 6 and 10 ppm, or an FZ silicon substrate, which naturally has a very low interstitial oxygen content. Alternatively, it could be a CZ silicon substrate with a high interstitial oxygen content (referred to as "High Oi") greater than 26 ppm, which would be heat-treated to ultimately provide the desired resistivity properties.

[0033] Continuing the description of the, a composite substrate 1 according to the invention comprises, disposed between the base substrate 4 and the surface layer 2, an interlayer structure 3. This interlayer structure 3 includes an electrical charge trapping layer 3b.

[0034] In some cases, the interlayer structure may consist solely of the trapping layer 3b. In other cases, the interlayer structure 3 may consist of the trapping layer 3b and a dielectric layer 3a, as illustrated in Figure 1. In this case, the dielectric layer 3a is placed on top of the trapping layer 3b, sandwiched between this layer and the surface layer 2.

[0035] Such a dielectric layer 3a differs from the trapping layer in that the dielectric layer 3a has a resistivity greater than or equal to 10⁻¹⁰ Ω·cm, which is greater than the resistivity of the trapping layer 3b. For example, the dielectric layer 3a may be formed from, or comprise, silicon dioxide, silicon nitride, aluminum nitride, or alumina. The trapping layer 3b advantageously has a resistivity greater than or equal to 10⁶ Ω·cm, but less than that of the dielectric layer 3a when such a layer is present.

[0036] Equipping the interlayer structure 3 with a dielectric layer 3a can offer several advantages. These include reducing the overall permittivity of the structure, thus decreasing its total thickness to achieve the desired minimum thickness, as will be explained in a later section of this description. The dielectric layer 3a can also be used to adjust the coefficient of thermal expansion of the structure 3, for example, to bring it closer to that of the base substrate 4 or that of the surface layer 2. More generally, the dielectric layer 3a can be used to adapt the mechanical and / or acoustic properties of the interlayer structure 3, for example, to enable the fabrication of resonator-type components on the composite substrate 1.

[0037] To ensure the desired RF performance despite the presence of a relatively low-resistivity base substrate 4, the thickness of the interlayer structure 3 is chosen to sufficiently distance the base substrate 4 electrically from the surface layer 2 in or on which the components will be formed. This sufficient thickness naturally depends on the nature of the layer(s) composing the interlayer structure 3 and the resistivity of the base substrate 4.

[0038] To determine whether the interlayer structure 3 sufficiently distances the base substrate 4 from the surface layer 2, regardless of its composition, the equivalent air layer to this interlayer structure is determined in terms of effective electrical permittivity; that is, the air layer exhibiting the same effective electrical permittivity. It is then verified that this equivalent air layer thickness is indeed greater than a minimum air layer thickness. In other words, and according to the invention, the interlayer structure must have an equivalent air thickness, in terms of effective electrical permittivity, greater than a minimum air thickness.

[0039] This equivalent air thickness EAT is calculated as the integral, when an elevation variable z describes the entire thickness of the interlayer, of the expression dz / e(z), in which e(z) expresses the electrical permittivity of the interlayer at the elevation z.

[0040]

[0041] For example, and as shown in Figure 3, when an interlayer 3 with a thickness h of 1.5 micrometers is composed of: a dielectric layer with a thickness h2 of 0.5 micrometers of silicon oxide with a permittivity e2 of approximately 4 over the entire thickness h1, and a trapping layer with a thickness h1 of 1 micrometer of polycrystalline silicon with a permittivity of approximately 11 over the entire thickness h1

[0042] The equivalent air thickness (EAT) is calculated as EAT = h1 / e1 + h2 / e2 = 1 / 11 + 0.5 / 4 = 0.2 micrometers of equivalent air thickness. The calculation of this EAT thickness makes the reasonable assumption that the material of the interlayer layer is homogeneous in the plane, but may vary in its thickness.

[0043] As presented in the Microwave Journal publication cited in the introduction, the Applicant has developed a hybrid model linking the properties of the materials composing a substrate to its RF performance. This hybrid model, combining electro-physical analysis of the materials and experimental measurements, has been validated and calibrated using numerous measurements on substrates exhibiting significant differences in material parameters.

[0044] Based on these definitions, the Applicant used this mixed model to determine the minimum air gap required between the surface layer 2 and the base substrate 4 for the composite substrate 1 to meet the required RF performance. The results of these calculations are shown in Figure 1. This figure shows the equivalent minimum air gap of an interlayer (ordinate axis) as a function of the resistivity R (abscissa axis) of the base substrate 4 measured at room temperature.

[0045] A first curve, C1, shows this minimum EAT thickness as a function of the resistivity of the base substrate to obtain a composite substrate with an RF performance level below -80 dBm. On this first curve, C1, we observe that when the base substrate has a resistivity of 600 Ohm.cm or close to 600 Ohm.cm (which ensures temperature stability over the temperature range between 0 and 150°C), the minimum equivalent air thickness EAT min The thickness of the interlayer structure 3 is 1.7 micrometers. If the resistivity of the base substrate 4 is reduced to 300 Ohm.cm to ensure temperature stability over the range between 0°C and 175°C, the equivalent minimum air thickness EAT minThe thickness of the interlayer structure 3 is 2.5 micrometers. If the resistivity of the base substrate is reduced to 125 Ohm.cm to ensure temperature stability over the range between 0°C and 200°C, the equivalent minimum air thickness EAT min of the intercalated structure 3 is 3 micrometers.

[0046] More generally, and approximating the C1 curve illustrated in the figure with a straight line, to obtain an RF performance below -80dBm, the interlayer structure is configured to have an equivalent thickness EAT, in terms of effective electrical permittivity, greater than a minimum thickness EAT min equal to -2.67 10^-3 * R + 3.3 when the resistivity R is expressed in Ohm.cm and the thickness in micrometers.

[0047] A second curve, C2, was also represented on the map, which delimits the equivalent minimum air thickness EAT. minof the intercalated structure 3 as a function of the resistivity of the base substrate 4 to obtain a composite substrate exhibiting an RF performance level lower this time than -100 dBm.

[0048] Without going into further detail about this second curve C2, and all other things being equal, we observe by comparing curves C1 and C2 that obtaining a better level of RF performance requires an equivalent minimum thickness of EAT air min more important.

[0049] By approximating the curve C2 illustrated in the figure with a straight line, to obtain an RF performance below -100dBm, the interlayer structure 4 is configured to have an equivalent air thickness EAT, in terms of effective electrical permittivity, greater than a minimum EAT thickness min equal to -5.00 10^-3 * R + 6.5, when the resistivity R is expressed in Ohm.cm and the thickness in micrometers.

[0050] The trapping layer can be made of any suitable material, but advantageously, this material is chosen to have a high trap density and thus trap free carriers from its doping, fixed charges present, if any, in the dielectric layer 3a of the intercalated structure 3, and any polarization applied between the base substrate 4 and an electrode located above the dielectric. This sufficient trap density can be greater than 10 17 cm^-3. The trap density can be measured by deep-level transient spectroscopy.

[0051] Advantageously, these traps possess sufficient energy to prevent the electric carriers from being easily released simply by increasing the temperature in the range between 0°C and 150°C or in the extended range between 0°C and 200°C. To achieve this advantage, the trapping layer 3b can be made of a polycrystalline semiconductor material with a band gap of at least 3 eV. Examples include silicon carbide, gallium nitride, aluminum nitride, and their alloys (AlGaN).

[0052] Thus, and advantageously, the trapping layer can be formed from materials rich in relatively deep traps, such as undoped polycrystalline SiC (doping concentration less than 10^14 cm-3) with an electrical permittivity of 10, porous silicon exhibiting the properties described in document FR3098342A1 with an electrical permittivity of 4, or a silicon oxide or oxynitride rich in silicon in amorphous or polycrystalline form, such as, for example, described in document WO2024115410, cited in the introduction, with an electrical permittivity of 5. It is recalled that the electrical permittivity of silicon oxide, which is usually chosen to constitute the dielectric layer, is 4.

[0053] We give below some examples of composite substrates conforming to this description, exhibiting an HD2 measurement below a predetermined threshold for the temperature range [0, 150°] and in a frequency range including at least the 900MHz to 28GHz range.

[0054] Example 1 (symbol E1 on the)

[0055] Surface layer: silicon or lithium tantalate

[0056] Intercalated structure: dielectric layer: 0.5 micrometer of silicon dioxide trapping layer: 7 micrometers of porous silicon EAT: 1.88 micrometer.

[0057] Base substrate: monocrystalline silicon substrate with a resistivity of 600 Ω·cm

[0058] This composite substrate exhibits RF performance less than -80 dBm, for the temperature range [0, 150°] and in a frequency range including at least the 900MHz to 28GHz range.

[0059] Example 2 (symbol E2 on the)

[0060] Surface layer: silicon or lithium tantalate

[0061] Intercalated structure: dielectric layer: 0.5 micrometer of silicon dioxide trapping layer: 20 micrometers of porous silicon EAT: 5.13 micrometer.

[0062] Base substrate: monocrystalline silicon substrate with a resistivity of 300 Ω·cm

[0063] This composite substrate exhibits RF performance less than -100 dBm, for the temperature range [0, 175°] and in a frequency range including at least the 900MHz to 28GHz range.

[0064] Example 3 (symbol E3 on the)

[0065] Surface layer: silicon or lithium tantalate

[0066] Intercalated structure: dielectric layer: 0.2 micrometer of silicon dioxide trapping layer: 12.5 micrometers of silicon-rich silicon oxide EAT: 2.55 micrometers.

[0067] Base substrate: monocrystalline silicon substrate with a resistivity of 300 Ω·cm

[0068] This composite substrate exhibits RF performance less than -80 dBm, for the temperature range [0, 175°] and in a frequency range including at least the 900MHz to 28GHz range.

[0069] Example 4 (symbol E4 on the)

[0070] Surface layer: silicon or lithium tantalate

[0071] Intercalated structure: dielectric layer: 1 micrometer of silicon dioxide trapping layer: 25 micrometers of undoped polycrystalline silicon carbide EAT: 2.75 micrometers.

[0072] Base substrate: monocrystalline silicon substrate with a resistivity of 600 Ω·cm

[0073] This composite substrate exhibits RF performance less than -80 dBm, for the temperature range [0, 175°] and in a frequency range including at least the 900MHz to 28GHz range.

[0074] Example 5 (symbol E5 on the)

[0075] Surface layer: silicon or lithium tantalate

[0076] Intercalated structure: dielectric layer: 1 micrometer of silicon dioxide trapping layer: 27 micrometers of porous silicon EAT: 7 micrometers.

[0077] Base substrate: single-crystal silicon substrate with a resistivity of 125 Ohm.cm.

[0078] This composite substrate exhibits RF performance less than -100 dBm, for the temperature range [0, 200°] and in a frequency range including at least the 900MHz to 28GHz range.

[0079] The manufacture of a composite substrate according to the invention is perfectly accessible to a person skilled in the art, particularly when the trapping layer 3b of the intercalated structure is formed by deposition on the base substrate 4. The possible approaches to preparing the base substrate when it is a question of forming a porous layer on or in such a substrate will be detailed in a later section of this description.

[0080] A manufacturing process, as illustrated in Figure 1, comprises a first step S1 of supplying a basic substrate 4 having a chosen resistivity, ranging from 100 Ohms.cm to 650 Ohms.cm at room temperature. This choice is based on the desired temperature performance range, as is evident from this description.

[0081] In a second step S2, the trapping layer 3b of the intercalated structure 3 can be formed by deposition. This is particularly the case when such a layer 3b is made of a semiconductor material or a silicon-rich oxide. In the latter case, reference can be made to document WO2024115410, which details the operating conditions for this deposition.

[0082] This trapping layer 3b is formed with sufficient thickness, based for example on the graph of the, to achieve a chosen RF performance level.

[0083] It is possible, as already stated and without this being a necessity, to form a dielectric layer 3a on the trapping layer 3b, for example by deposition of a dielectric during a subsequent step S3 of formation of the dielectric layer 3a.

[0084] This completes the preparation of the support S of the composite substrate. A surface layer 2 can be deposited onto this support S using a layer transfer technique. Such a transfer generally includes an assembly step S4 of a source substrate D formed from the single-crystal material from which the surface layer 2 is to be formed on the support S. A dielectric layer can be formed on the assembly surface of the source substrate D before this assembly step, either in addition to or as an alternative to the formation of the dielectric layer 3a in step 3a. The dielectric layer 3a of the composite substrate 1 consists, if such a layer is present, of the dielectric layer formed on the support S and / or the dielectric layer formed superficially on the source substrate D. The thickness of this source substrate D is then reduced to form the surface layer 2 in a thickness reduction step S5.

[0085] In a particularly advantageous approach, this thickness reduction step S5 can be carried out using Smart Cut™ technology, well known to those skilled in the art. In this technology, the surface layer is removed from the source substrate by a step, prior to the assembly step, that weakens the source substrate, for example, during an ion implantation step using so-called "light" species such as hydrogen and / or helium. This light species introduction step leads to the formation of a weak plane 6 along which the source substrate D can be fractured.

[0086] At the end of this sequence of steps, we have a composite substrate 1 exhibiting the desired RF performance.

[0087] Document FR3098342, cited in the introduction, proposes creating a mesoporous silicon trapping layer from a base substrate with a relatively low resistivity on the order of 1 Ohm·cm, and therefore incompatible with a composite substrate as described herein. Porification of a relatively resistive substrate, above 20 Ohm·cm, is difficult because the charge carrier concentration is low.

[0088] To circumvent this, a method is proposed below for preparing a support conforming to this description from a base substrate having the required resistivity, between 100 Ohm.cm and 600 Ohm.cm, this support comprising a mesoporous silicon trapping layer. This method, moreover, constitutes an aspect of the invention in itself.

[0089] As an introduction to this section, it is worth recalling that mesoporous silicon has pores with diameters ranging from 2 nm to 50 nm. It differs from macroporous or microporous silicon, whose pores are respectively larger than 50 nm in diameter or smaller than 2 nm in diameter. The mesoporous pores compatible with the present invention are hollow, not filled with a filler material, but the internal pore walls are lined with an oxide layer whose thickness can be on the order of nanometers. The porosity of the mesoporous layer is advantageously between 40% and 60%, preferably 50%, to ensure a good compromise between its performance and mechanical stability. Due to these properties, such a mesoporous layer exhibits high resistivity throughout its thickness, exceeding 2 kΩ·cm at room temperature.

[0090] Having described these advantageous properties, the manufacturing process for the support with a mesoporous silicon trapping layer comprises, with reference to the, a first step S1' of supplying a basic substrate 4 with a chosen resistivity, ranging from 100 Ohms.cm to 650 Ohms.cm at room temperature. As already noted, this choice is based on the desired temperature performance range.

[0091] This process also includes, in a subsequent preparation step S2', the preparation of a surface layer 7 on a so-called "main" face 4a of the base substrate 4 or within a superficial thickness of the base substrate. This surface layer 7 is prepared to have a resistivity between 0.5 Ohm.cm and 20 Ohm.cm, while the remainder of the base substrate 4 has a resistivity chosen between 100 Ohm.cm and 600 Ohm.cm. This surface layer has a thickness substantially equal to the thickness of the mesoporous layer that is to be superficially formed on the base substrate. Thus, its thickness can be between 5 micrometers and 30 micrometers, for example.

[0092] This surface layer 7, with a lower resistivity compared to the rest of the base substrate, exhibits favorable resistivity characteristics to allow its porosity. Preferably, this resistivity can be chosen to be between 1 Ohm.cm and 4 Ohm.cm, and even more preferably between 1 Ohm.cm and 2 Ohm.cm.

[0093] The S2' preparation step can be implemented in multiple ways. It may include the deposition of a doped layer on the main face 4a of the base substrate 4, the doped layer having the desired resistivity characteristic. It may also involve an "in situ" doped deposition in which dopant gases (for example, diborane (B₂H₆) for boron, phosphine (PH₃) for phosphorus, or arsine (AsH₃) for arsenic) are introduced into a reaction chamber simultaneously with the silicon precursor gases (such as silane, SiH₄).

[0094] Alternatively, the preparation of the surface layer 7 includes the low-energy (on the order of keV) implantation of a dopant, such as boron, phosphorus, or arsenic, through the main surface 4a of the base substrate 4 to introduce these species into the surface portion of this substrate 4a. This implantation can be followed by activation annealing, at a temperature typically between 800°C and 1000°C.

[0095] Alternatively, the surface layer 7 can be prepared by diffusing a dopant into the surface portion of the base substrate 4. This approach can involve exposing the main face 4a of the base substrate 4 to a dopant source or depositing a dopant source onto this face of the substrate. This preliminary phase is followed by high-temperature annealing (1000°C–1200°C) under an inert atmosphere to promote the diffusion of the dopants into the base substrate 4, thus forming the surface layer 7. The temperature and duration of the annealing allow control of the dopant diffusion depth and therefore the thickness of the surface layer 7.

[0096] In these implementation methods, the surface layer preparation step is carried out prior to the next porification step S3'.

[0097] But this does not constitute a limitation and it is possible to consider that this preparation step S2' of the surface layer 7 is carried out during the porification step S3'.

[0098] According to this approach, the preparation step involves illuminating the main face 4a of the base substrate 4 with a light beam. The objective of this illumination is to generate free electric charge carriers, electron-hole pairs, on the main face 4a exposed to the light beam from the base substrate 4, in order to compensate for its low doping. The light beam must therefore have a photon energy greater than the valence band of silicon. In practice, a light beam with a wavelength between 550 nm and 1100 nm can be chosen, and preferably between 750 and 950 nm. The generation of charge carriers is achieved over a thickness of 8 micrometers to 50 micrometers from the illuminated face of the base substrate; this thickness defines the thickness of the surface layer. The luminous flux can present a photon density, on the main face of the base substrate, of between 1.0 10^12 and 5.0 10^13 per cm².

[0099] Once the surface layer 7 has formed, or during its formation (during illumination), it can be porosified to form the electrical charge-trapping layer of mesoporous silicon. This porosification step S3' is typically carried out electrochemically. The electrochemical porosification of a silicon substrate relies on the anodic attack of silicon in an electrolytic solution containing hydrofluoric acid (HF), generally in the presence of an oxidizing agent and a controlled electric current. This process takes place in an electrochemical cell where silicon serves as the anode and a counter electrode (often platinum or, preferably, silicon) acts as the cathode. The porous structure of silicon exhibits a morphology (pore size and density) controlled by the HF concentration, the current density, and the doping of the surface layer.

[0100] When the surface layer 7 is obtained by illuminating the main face 4a of the base substrate 4, it is understood that this illumination must be maintained during its electrochemical transformation into mesoporous silicon. Furthermore, the wavelength of the incident light flux can be increased during the porosification step S3'. This allows carriers to be generated primarily at the interface between the porous portion of the layer and the non-porous portion as it progresses through the thickness of the base substrate 4. This prevents excessive etching of the already porous silicon.

[0101] Once the surface layer 7 has been transformed into a mesoporous layer, an annealing step of the support can be planned under an oxidizing atmosphere at a temperature typically between 300°C and 400°C. Preferably, the duration of the annealing under an oxidizing atmosphere is between 5 min and 200 min.

[0102] Following these steps, a support for a composite substrate S is obtained. This support comprises a silicon base substrate 4 with a resistivity between 100 Ohms.cm and 650 Ohms.cm at room temperature. It also includes a mesoporous silicon charge-trapping layer 3b deposited on the base substrate 4. This trapping layer has a resistivity greater than 2 kOhms.cm at room temperature.

[0103] It is possible to form, for example by deposition, a dielectric layer 3a on the trapping layer 3b, as described in a previous section. Such a support S, whether or not it has a dielectric layer 3a, can be used in a layer transfer process already described to form a composite substrate 1 conforming to this description.

[0104] It is noted in this regard that the possibility of forming a mesoporous silicon trapping layer on a base substrate with a relatively high resistivity, greater than 100 Ohm.cm, makes it possible to maintain the RF performance of the support and the composite substrate incorporating such a support, for signals with a frequency of at least between 900MHz and 28GHz, which was not possible using a support conforming to the state of the art.

[0105] The A2 performance curve of a composite substrate comprising a base substrate with a resistivity greater than 100 Ohm.cm (here 600 Ohm.cm) and a 10-micrometer mesoporous layer (with an EAT of 2.5) is shown. It is noted that this A2 measurement curve HD2 is well below -80 dBm and decreases with the measurement signal frequency (at least between 900 MHz and 28 GHz), unlike the A1 curve representing the prior art.

[0106] Of course the invention is not limited to the implementation methods described and alternative embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Composite substrate (1) exhibiting an HD2 performance level below -80 dBm in a temperature range between 0°C and 150°C, the composite substrate (1) comprising: a silicon base substrate (4) having a resistivity between 100 Ohms.cm and 650 Ohms.cm at room temperature; a surface layer (2) formed of a single-crystal material disposed on the base substrate; and an interlayer structure (3) disposed between the base substrate (4) and the surface layer (2), the interlayer structure (3) having an equivalent air thickness EAT, in terms of effective electrical permittivity, greater than a minimum EAT thickness min equal to -2.67 10^-3 * R + 3.3, when the resistivity R is expressed in Ohm.cm and the thickness in micrometers. Composite substrate (1) according to the preceding claim having an HD2 performance level below -100dBm and wherein the interlayer structure has an equivalent air thickness EAT greater than a minimum thickness EAT min equal to -5.00 10^-3 * R + 6.5, when the resistivity R is expressed in Ohm.cm and the thickness in micrometers. Composite substrate (1) according to any one of the preceding claims wherein the base substrate (4) has a resistivity measured at room temperature less than or equal to 300 Ohm.cm. Composite substrate (1) according to any one of the preceding claims wherein the base substrate has a resistivity less than or equal to 125 Ohm.cm. Composite substrate (1) according to any one of the preceding claims wherein the interlayer structure (3) also comprises, disposed on the electrical charge trapping layer (3b), a dielectric layer (3a) having a resistivity greater than or equal to 10^10 Ohm.cm. Composite substrate (1) according to any one of the preceding claims wherein the electrical charge trapping layer (3b) has a resistivity greater than or equal to 10^6 Ohm.cm. Composite substrate (1) according to any one of the preceding claims, wherein the electrical charge trapping layer (3b) has a trap density greater than 10 17 cm^-3. Composite substrate (1) according to any one of the preceding claims wherein the electrical charge trapping layer (3b) is formed of a polycrystalline semiconductor material having a band gap of at least 3 eV. Composite substrate (1) according to the preceding claim in which the electrical charge trapping layer (3b) is formed of polycrystalline silicon carbide. Composite substrate (1) according to any one of claims 1 to 7 in which the electrical charge trapping layer (3b) is formed of polycrystalline or oxygen-rich amorphous silicon. Composite substrate (1) according to the preceding claim in which the electrical charge trapping layer (3b) also comprises nitrogen. Composite substrate (1) according to any one of claims 1 to 7 in which the electrical charge trapping layer (3b) is formed of porous silicon.

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