Method for producing a semiconductor laser chip and semiconductor laser chip

Abstract

A method for producing a semiconductor laser chip comprising the following steps is specified: - generating a plurality of recesses (1) in an epitaxial semiconductor layer (2), wherein the recesses (1) have openings (5) at a main surface (3) of the epitaxial semiconductor layer (2), - conformally overmolding the main surface (3) of the epitaxial semiconductor layer (2), which has the openings (5) of the recesses (1), with a dielectric protective layer (10), and - epitaxially overgrowing the recesses (1) with a semiconductor material (11), so that closed cavities (12) are formed in the epitaxial semiconductor layer (2). Furthermore, a semiconductor laser chip is specified.

Description

[0001] 2024PF01512 February 17, 2026

[0002] P2024, 1132 WO N - 1 -

[0003] Description

[0004] METHOD FOR MANUFACTURING A SEMICONDUCTOR LASER CHIP AND SEMICONDUCTOR LASER CHIP

[0005] A method for manufacturing a semiconductor laser chip and a semiconductor laser chip are described.

[0006] A method for manufacturing an improved semiconductor laser chip is to be specified. Furthermore, an improved semiconductor laser chip is to be specified. These tasks are accomplished by a method comprising the steps of claim 1 and by a semiconductor laser chip having the features of claim 15.

[0007] Advantageous embodiments and further developments of the method and the semiconductor laser chip are the subject of the dependent claims.

[0008] According to one embodiment of the method, a plurality of recesses are created in an epitaxial semiconductor layer, wherein the recesses have openings on a principal surface of the epitaxial semiconductor layer. The epitaxial semiconductor layer comprises or consists of a plurality of epitaxially stacked epitaxial semiconductor layers arranged one above the other in a growth direction.

[0009] For example, the epitaxial semiconductor layer may feature a II IV semiconductor material, such as a nitride compound semiconductor material, a phosphide compound semiconductor material, or an arsenide compound semiconductor material. It is also possible that the epitaxial semiconductor layer is formed from one of these materials. In particular, the 2024PF01512 dated February 17, 2026, features

[0010] P2024, 1132 WO N 2

[0011] epitaxial semiconductor layer consists of a single semiconductor material or is made of a single semiconductor material.

[0012] For example, the epitaxial semiconductor layer is part of an epitaxial semiconductor layer sequence with other epitaxial semiconductor layers that have different semiconductor materials or are composed of different semiconductor materials than the epitaxial semiconductor layer. For example, the epitaxial semiconductor layers of the epitaxial semiconductor layer sequence differ in their composition and / or their doping. In particular, however, the epitaxial semiconductor layer sequence has materials from the same material system as the epitaxial semiconductor layer or consists of materials from the same material system as the epitaxial semiconductor layer.

[0013] For example, the recesses in the epitaxial semiconductor layer are identical in shape and, in particular, have the same geometry. For example, the recesses are cylindrical, with one axis of rotation of the cylinders running along the growth direction of the epitaxial semiconductor layer. The recesses may also be oval or polygonal in plan view of the epitaxial semiconductor layer sequence, or have another complex shape. For example, the openings may be round, circular, oval, or polygonal in plan view of the main surface.

[0014] For example, the recesses penetrate the epitaxial semiconductor layer starting from the main surface along the growth direction. For example, the recesses are arranged at equidistant distances from each other. 2024PF01512 February 17, 2026

[0015] P2024, 1132 WO N 3

[0016] In particular, the recesses are freely accessible from the outside immediately after creation. In other words, the main surface of the epitaxial semiconductor layer is structured directly after the recesses are created, without any further processing step.

[0017] According to another embodiment of the method, the main surface of the epitaxial semiconductor layer, which has the openings of the recesses, is conformally formed with a dielectric protective layer. The term "conformally formed" means, in particular, that the dielectric protective layer replicates the structure of the structured main surface of the epitaxial semiconductor layer as faithfully as possible. Preferably, the dielectric protective layer precisely replicates the structured main surface of the epitaxial semiconductor layer within the manufacturing tolerances.

[0018] The dielectric protective layer comprises, in particular, a dielectric material or is formed from a dielectric material. In particular, the dielectric protective layer is electrically insulating. The dielectric protective layer has, in particular, at least two atomic layers. For example, the thickness of the dielectric protective layer is between 1 nanometer and 30 nanometers.

[0019] It is also possible to reduce overly large recesses to a desired width by appropriately selecting the thickness of the dielectric protective layer. For this purpose, it is advantageous if the refractive index of the 2024PF01512 17 February 2026

[0020] P2024, 1132 WO N - 4 -

[0021] dielectric protective layer similar to that of the underlying semiconductor material.

[0022] According to another embodiment of the method, the recesses are epitaxially overgrown with a semiconductor material, creating closed cavities in the epitaxial semiconductor layer. For example, the recesses are overgrown with a semiconductor material that matches the semiconductor material of the epitaxial semiconductor layer. Particularly preferably, the epitaxial overgrowth of the recesses takes place in a lateral direction perpendicular to the growth direction. This at least reduces any changes in the geometry of the recesses during the epitaxial overgrowth. The epitaxial overgrowth is carried out, for example, using an ELOG method (ELOG being short for "epitaxial lateral overgrowth").

[0023] According to one embodiment, the method for manufacturing the semiconductor laser chip comprises the following steps: - generating the plurality of recesses in the epitaxial semiconductor layer, wherein the recesses have openings on the main surface of the epitaxial semiconductor layer, - conformally overforming the main surface of the epitaxial semiconductor layer, which has the openings of the recesses, with the dielectric protective layer, and

[0024] - epitaxial overgrowth of the recesses with the semiconductor material, so that the closed cavities are created in the epitaxial semiconductor layer.

[0025] The steps should preferably be carried out in the order given above. 2024PF01512 February 17, 2026

[0026] P2024, 1132 WO N - 5 -

[0027] One idea underlying the present method is to use the dielectric protective layer to at least reduce epitaxial growth of semiconductor material on the sidewalls of the recesses, thereby minimizing changes in the recess geometry during overgrowth. In particular, the method described here makes it possible to obtain predefined, well-defined structures within the epitaxial semiconductor layer during epitaxial overgrowth. Thus, the present method can be used to create an epitaxial semiconductor layer with precisely defined closed cavities as a structural element within a semiconductor laser chip. Specifically, these closed cavities form an optical structure that exerts a targeted optical effect on electromagnetic radiation, such as electromagnetic laser radiation generated by the semiconductor laser chip during operation.

[0028] According to another embodiment of the process, the dielectric protective layer prevents epitaxial deposition of semiconductor material on the side surfaces of the recesses during the overgrowth process. This allows for the targeted preservation of the geometry of the closed cavities created by the overgrowth.

[0029] According to another embodiment of the method, the epitaxial semiconductor layer is p-doped or n-doped. For example, the epitaxial semiconductor layer is part of an epitaxial semiconductor layer sequence that includes an active radiation-generating layer. For example, the active radiation-generating layer has at least one pn junction for generating electromagnetic radiation. 2024PF01512 17 February 2026

[0030] P2024, 1132 WO N - 6 -

[0031] The pn junction can also be part of a double heterostructure, a single quantum well, or a multiple quantum well structure for radiation generation. The active layer is particularly preferably undoped and arranged between the p-doped epitaxial semiconductor layer and the n-doped epitaxial semiconductor layer.

[0032] For example, the closed cavities are created using the present method in the p-doped or the n-doped or in both epitaxial semiconductor layers. It is also possible to create the closed cavities in the active layer using the present method.

[0033] According to another embodiment of the method, the epitaxial semiconductor layer with the closed cavities forms a photonic crystal, which is configured to guide electromagnetic laser radiation into an active region of the semiconductor laser chip. It is also possible that the cavities are part of the photonic crystal. In particular, the semiconductor laser chip is a photonic semiconductor laser chip, such as a photonic surface-emitting semiconductor laser chip (PCSEL).

[0034] Photonic crystals, analogous to the electronic band gap of semiconductors, exhibit a band gap specifically for photons, the so-called photonic band gap. Photons with energies within the photonic band gap cannot propagate through the photonic crystal and are reflected by it. The photonic band gap forms, completely or partially, due to periodic structures, such as the cavities in the 2024PF01512 17 February 2026

[0035] P2024, 1132 WO N 7

[0036] epitaxial semiconductor layer. One dimension of the photonic crystal is determined in particular by one dimension of a periodicity of the structures of the photonic crystal.

[0037] In particular, the photonic crystal in the epitaxial semiconductor layer is a two-dimensional photonic crystal. The photonic crystal is formed, for example, by the closed cavities and the surrounding semiconductor material of the epitaxial semiconductor layer.

[0038] To guide the electromagnetic laser radiation into the active area of ​​the semiconductor laser chip, the photonic crystal is arranged in a near field of the electromagnetic laser radiation generated in the active layer.

[0039] The photonic crystal generates, in particular, an increased photonic density of states in the active layer, so that when the active layer is electrically pumped, electromagnetic laser radiation is generated at least partially within the active layer. The active layer is optically coupled to the photonic crystal, so that at least an evanescent wave of the electromagnetic laser radiation propagates within the photonic crystal.

[0040] The active region refers in particular to the part of the epitaxial semiconductor layer sequence in which electromagnetic laser radiation is generated during operation.

[0041] In particular, the active area of ​​the semiconductor laser chip comprises at least a part of the active layer. 2024PF01512 February 17, 2026

[0042] P2024, 1132 WO N - 8 -

[0043] In particular, the recesses in the present method are immediately closed by lateral overgrowth. This allows the photonic crystal to be positioned closer to the active layer. This increases the confinement factor of the semiconductor laser chip. Furthermore, it enables better interaction between the electromagnetic laser radiation and the photonic crystal.

[0044] The diameter of the recesses and / or cavities and / or openings is, for example, between 10 nanometers and 150 nanometers inclusive. For example, the diameter of the recesses and / or cavities and / or openings is less than one-quarter of the wavelength of the electromagnetic laser radiation. The thickness of the dielectric protective layer is, for example, no greater than 30%, 20%, or 10% of the diameter of the recesses. In other words, the dielectric protective layer is preferably very thin. In this case, the refractive index difference between the material in the cavity and the surrounding semiconductor material is crucial for the optical effect of the cavities. In particular, the effect of the photonic crystal is especially good when the refractive index jump between the cavities and the surrounding semiconductor material is as large as possible.Furthermore, the dielectric protective layer also acts to a particular advantage as passivation of the cavities, which reduces undesirable surface effects.

[0045] According to another embodiment of the method, the closed cavities form an optically active grating, which 2024PF01512 17 February 2026

[0046] P2024, 1132 WO N 9

[0047] The device is configured so that electromagnetic laser radiation couples to the optically active grating. It is also possible that the closed cavities are part of the active optical grating. The cavities form, for example, a one-dimensional grating, where the distance between the cavities is, in particular, a multiple of half the wavelength of the electromagnetic laser radiation. In this case, the semiconductor laser chip is, in particular, a DFB semiconductor laser chip (DFB stands for "distributed feedback laser"). For example, the cavities of the optical grating are strip-shaped and extend below a waveguide of the semiconductor laser chip perpendicular to the growth direction and perpendicular to a propagation direction of the electromagnetic laser radiation. However, it is also possible that the cavities are arranged only laterally to the side of the waveguide.

[0048] According to another implementation form of the process, the cavities are filled with air and / or a process gas.

[0049] Air-filled cavities exhibit a particularly large refractive index jump compared to an adjacent semiconductor material. Effective optical structures can thus be formed using these cavities.

[0050] According to another embodiment of the method, a mask layer is applied to create the recesses on projections between the recesses, and the mask layer is removed before the application of the dielectric protective layer. In particular, to create the recesses, a structured mask layer is applied to the main surface of the epitaxial semiconductor layer, and the 2024PF01512 17 February 2026

[0051] P2024, 1132 WO N 10

[0052] Recesses are created starting from the exposed areas of the main surface in the epitaxial semiconductor layer. After creation, the mask layer is applied to the projections that separate each pair of directly adjacent recesses. The mask layer comprises, for example, one of the following materials or is formed from one of the following materials: photoresist,

[0053] Hydrogen silsesquioxane (HSQ), metal.

[0054] According to another embodiment of the method, the mask layer for creating the recesses is applied to projections between the recesses, and the dielectric protective layer is applied to the mask layer.

[0055] According to another embodiment of the process, the mask layer is removed from the protrusions between the recesses together with the dielectric protective layer before the recesses are overgrown.

[0056] According to another implementation of the process, conformal overmolding with the dielectric protective layer is achieved using ALD (atomic layer deposition) or CVD (chemical vapor deposition). In other words, the dielectric protective layer is deposited specifically by ALD or CVD. It is also possible to deposit the dielectric protective layer using TEOS (tetraethyl orthosilicate).

[0057] In ALD, the surface to be coated is provided within a volume. At least one initial gaseous starting material is supplied to this volume, which is absorbed onto the surface to be coated. After complete or near-complete coverage of the surface, the coating process continues. (2024PF01512 17 February 2026)

[0058] P2024, 1132 WO N 11

[0059] In a self-limiting reaction process, the portion of the first starting material that is not absorbed onto the surface is removed from the volume, and a second starting material is added. This second starting material is designed to chemically react with the first starting material absorbed onto the surface, forming a solid layer—in this case, the dielectric protective layer—in a self-limiting reaction process.

[0060] It is possible that the dielectric protective layer deposited by ALD is partially or completely covalently coupled to the surface to be coated, in this case, the structured main surface of the epitaxial semiconductor layer. A dielectric protective layer deposited by ALD is generally characterized by a very homogeneous layer thickness and a very homogeneous layer structure. In particular, a dielectric protective layer deposited by ALD exhibits few to no defects, such as pinholes, and a high density. The structure of a dielectric protective layer deposited by ALD differs significantly from that of a dielectric protective layer deposited by another method and can be verified on the finished component.

[0061] In CVD, the surface to be coated is also provided in a volume, and a chemical reaction takes place on the surface involving at least two starting materials, resulting in the dielectric protective layer. However, the 2024PF01512 17 February 2026

[0062] P2024, 1132 WO N - 12 -

[0063] Separation by CVD is not necessarily

[0064] self-limiting.

[0065] According to another embodiment of the method, the dielectric protective layer is removed from the projections between the recesses by anisotropic etching before epitaxial growth of the recesses, preferably completely. The dielectric protective layer prevents the epitaxial growth of semiconductor material. Therefore, it is removed before the recesses are overgrown with semiconductor material. For example, the dielectric protective layer is removed from the projections by dry chemical anisotropic etching, such as using RIE (short for "reactive ion etching").

[0066] According to another embodiment of the process, the anisotropic etching of the dielectric protective layer is carried out along the growth direction of the epitaxial semiconductor layer sequence. In other words, a preferred direction of anisotropic etching is perpendicular to the main surface of the epitaxial semiconductor layer. In this embodiment of the process, the dielectric protective layer is removed not only from the end faces of the projections between the recesses, but also from the bottom faces of the recesses. For example, the end faces of the projections run parallel to the bottom faces of the recesses.

[0067] According to another embodiment of the process, the dielectric protective layer is partially removed during anisotropic etching of the side surfaces of the recesses, starting from the openings. For example, the removal of the dielectric protective layer starting from the openings 2024PF01512 17 February 2026

[0068] P2024, 1132 WO N - 13 -

[0069] Symmetrical, meaning that the areas where the semiconductor material is exposed beneath the dielectric protective layer by anisotropic etching are uniformly formed. The areas of the recess sides exposed by anisotropic etching facilitate the growth of semiconductor material to close the recesses and form the closed cavities.

[0070] In particular, lateral overgrowth of the recesses in the lateral direction is facilitated by the exposed areas of the recess's side surface. With the present method, it is advantageously not necessary to adjust a further mask layer onto the recesses for this partial removal of the dielectric protective layer, so that the recesses can have very small dimensions.

[0071] According to another embodiment of the method, the anisotropic etching of the dielectric protective layer is carried out at an angle to the growth direction of the epitaxial semiconductor layer. In particular, the preferred direction of the anisotropic etching includes an angle with the growth direction. Here, the dielectric protective layer is removed from the side surfaces of the recesses, especially asymmetrically. "Asymmetrical" means, in particular, that the areas of the side surfaces where the semiconductor material beneath the dielectric protective layer is exposed by the anisotropic etching are unevenly shaped, especially in a 360° rotation along a rotation axis of the recesses. The angle at which the anisotropic etching of the dielectric protective layer takes place, for example, has a value of at least 30° or at least 60°. 2024PF01512 February 17, 2026

[0072] P2024, 1132 WO N 14

[0073] The semiconductor laser chip described below can be manufactured using this method. Features and

[0074] Therefore, guide forms can also be formed on the semiconductor laser chip and vice versa.

[0075] According to one embodiment, the semiconductor laser chip comprises an epitaxial semiconductor layer with a plurality of cavities. For example, the epitaxial semiconductor layer comprises a plurality of epitaxially grown semiconductor layers of the same material. In particular, the cavities are entirely contained within the epitaxial semiconductor layer and have a principal direction of extension along a growth direction of the epitaxial semiconductor layer. For example, the cavities are of a uniform shape and have a cylindrical geometry. In particular, the side faces of the cavities extend parallel to the growth direction of the epitaxial semiconductor layer.

[0076] According to another embodiment, the semiconductor laser chip comprises an active layer designed to generate electromagnetic radiation. Specifically, the semiconductor laser chip generates electromagnetic laser radiation during operation.

[0077] According to another embodiment of the semiconductor laser chip, the side surfaces of the cavities are at least partially covered with a dielectric protective layer. In particular, the dielectric protective layer passivates the cavities.

[0078] According to one implementation form, the semiconductor laser chip comprises the epitaxial semiconductor layer sequence with the epitaxial semiconductor layer with the multitude of 2024PF01512 17 February 2026

[0079] P2024, 1132 WO N - 15 -

[0080] cavities, and the active layer which is configured to generate electromagnetic radiation, wherein the side surfaces of the cavities are at least partially covered with the dielectric protective layer.

[0081] For example, the semiconductor laser chip is a photonic semiconductor laser chip designed to emit electromagnetic laser radiation from a radiation exit surface located on a main surface of the semiconductor laser chip.

[0082] In particular, the growth direction of the epitaxial semiconductor layer on the radiation-emitting surface of the photonic semiconductor laser chip is perpendicular. In other words, the photonic semiconductor laser chip is typically surface-emitting. Specifically, the photonic semiconductor laser chip comprises a photonic crystal as previously described.

[0083] Furthermore, it is also possible that the semiconductor laser chip is a DFB semiconductor laser chip. The DFB semiconductor laser chip specifically includes an optically active grating to which electromagnetic laser radiation generated in an active region of the DFB semiconductor laser chip optically couples. The optically active grating causes, for example, only a single mode of electromagnetic laser radiation to be amplified in the DFB semiconductor laser chip. Specifically, the DFB semiconductor laser chip is a semiconductor laser chip that emits electromagnetic radiation from a side surface, the side surface being oriented along the growth direction of the epitaxial semiconductor layer. In other words, the radiation-emitting surface of the DFB semiconductor laser chip is encompassed by a side surface of the DFB semiconductor laser chip.

[0084] P2024, 1132 WO N - 16 -

[0085] It consists of a side face of the DFB semiconductor laser chip. The DFB semiconductor laser chip is specifically an edge-emitting semiconductor laser chip.

[0086] For example, the optically active grating of the DFB semiconductor laser chip is located within the active layer. For example, the active layer of the DFB semiconductor laser chip is periodically structured. It is also possible that the DFB semiconductor laser chip additionally or alternatively has an optically active grating located on a surface of the semiconductor laser chip.

[0087] According to another embodiment of the semiconductor laser chip, the dielectric protective layer comprises an oxide, oxynitride, or nitride of one of the following metals: Al, Ce, Ga, Hf, In, Mg, Nb, Nd, Rh, Sb, Si, Sn, Ta, Ti, Zn, Zr. It is also possible for the dielectric protective layer to consist of such an oxide, oxynitride, or nitride. In particular, SiO₂ is suitable as a material for the dielectric protective layer if the semiconductor laser chip is based on an arsenide compound semiconductor material such as GaAs, while for a semiconductor laser chip based on a phosphide compound semiconductor material such as InP, SiO₄ is particularly suitable as a material for the dielectric protective layer.

[0088] According to another embodiment of the semiconductor laser chip, the dielectric protective layer comprises at least two individual layers. The dielectric protective layer can therefore be formed from two or more individual layers or comprise two or more individual layers. In particular, the individual layers of the dielectric protective layer exhibit different properties. 2024PF01512 17 February 2026

[0089] P2024, 1132 WO N - 17 -

[0090] Materials on or consisting of different materials. This allows the average refractive index of the dielectric protective layer and / or the tension of the dielectric protective layer to be adjusted as desired.

[0091] The semiconductor laser chip can be used, for example, in automotive or consumer applications, projectors, or in materials processing. In particular, the semiconductor laser chip is suitable as a light source for a high-energy laser.

[0092] Further advantageous embodiments and developments of the method for manufacturing a semiconductor laser chip and the semiconductor laser chip result from the exemplary embodiments described below in conjunction with the figures.

[0093] Figures 1 to 5 show schematic sectional views of stages of a process for manufacturing a semiconductor laser chip according to an exemplary embodiment.

[0094] Figure 6 shows a schematic sectional view of a semiconductor laser chip according to an exemplary embodiment.

[0095] Figure 7 shows a schematic sectional view of a stage of a process for manufacturing a semiconductor laser chip according to a further embodiment.

[0096] Figure 8 shows a schematic sectional view of a semiconductor laser chip according to a further embodiment .2024PF01512 17 February 2026

[0097] P2024, 1132 WO N 18

[0098] Figures 9 to 11 show schematic sectional views of stages of a process for manufacturing a semiconductor laser chip according to a further embodiment.

[0099] Figures 12 to 15 show schematic sectional views of recesses according to various embodiments.

[0100] Figures 16 and 17 show schematic sectional views of a semiconductor laser chip according to two embodiments.

[0101] Figures 18 and 19 show schematic representations of a semiconductor laser chip according to a further embodiment.

[0102] Figures 20 and 21 show schematic sectional views of stages of a process for manufacturing a semiconductor laser chip according to a further embodiment.

[0103] Identical, similar, or similarly functioning elements are marked with the same reference symbols in the figures. The figures and the relative sizes of the elements depicted within them are not to be considered to scale. Rather, individual elements, particularly layer thicknesses, may be exaggerated for clarity and / or better understanding.

[0104] In the method according to the embodiment shown in Figures 1 to 5, a plurality of recesses 1 are first created in an epitaxial semiconductor layer 2. For this purpose, see 2024PF01512 17 February 2026

[0105] P2024, 1132 WO N - 19 -

[0106] A structured mask layer 4 is first applied to a main surface 3 of the epitaxial semiconductor layer 2. Then, starting from the areas of the main surface 3 of the epitaxial semiconductor layer 2 that are not covered by the structured mask layer 4, the recesses 1 are created in the epitaxial semiconductor layer 2, for example by etching (not shown).

[0107] The recesses 1 have openings 5 ​​on the main surface 3 of the epitaxial semiconductor layer 2. Bottom surfaces 6 of the recesses 1 are arranged opposite the openings 5 ​​(Figure 1). The recesses 1 are separated from each other by projections 7, on whose end faces 8 the mask layer 4 is applied. In particular, the end faces 8 of the projections 7 are completely covered with the mask layer 4. Side surfaces 9 of the recesses 1 extend along, for example parallel to, a growth direction R. w the epitaxial semiconductor layer 2.

[0108] The mask layer 4 is removed from the frontal surfaces 8 of the projections 7 (Figure 2 ).

[0109] The structured main surface 3 of the epitaxial semiconductor layer 2 is conformally overmolded with a dielectric protective layer 10 (Figure 3). For example, the conformal overmolding with the dielectric protective layer 10 takes place using ALD or GVD. The dielectric protective layer 10 preferably follows the structure of the main surface 3 of the epitaxial semiconductor layer 2 with the recesses 1 and the projections 7 as closely as possible.

[0110] Then the dielectric protective layer 10 is separated from the end faces 8 of the projections 7 and from the bottom faces 62024PF01512 17 February 2026

[0111] P2024, 1132 WO N - 20 -

[0112] the recesses 1 are completely removed again. In the present embodiment, the removal of the dielectric protective layer 10 takes place by anisotropic dry chemical etching, the preferred direction of which is R. v along the growth direction R w runs (Figure 4).

[0113] The recesses 1 are then epitaxially overgrown with a semiconductor material 11, so that closed cavities 12 are formed in the epitaxial semiconductor layer 2 (Figure 5). The overgrowth of the recesses 1 takes place along a lateral direction R. L instead, perpendicular to the growth direction R w stands .

[0114] Since the dielectric protective layer 10 is located away from the bottom surfaces 6 of the recesses 1, it is possible that semiconductor material 11 will be deposited on the bottom surfaces 6 as the recesses 1 are overgrown. This can be compensated for by appropriately selecting the depth of the recesses 1.

[0115] The semiconductor laser chip according to the embodiment shown in Figure 6 has an epitaxial semiconductor layer sequence 13 comprising an n-doped epitaxial semiconductor layer 14, an active layer 15, and a p-doped epitaxial semiconductor layer 16. The active layer 15 is arranged between the n-doped epitaxial semiconductor layer 14 and the p-doped epitaxial semiconductor layer 16 and is configured to generate electromagnetic radiation.

[0116] The n-doped epitaxial semiconductor layer 14 comprises a regular arrangement of a plurality of cavities 12. The plurality of cavities 12 are uniformly formed. In particular, the cavities 12 exhibit a 2024PF01512 17 February 2026

[0117] P2024, 1132 WO N 21

[0118] cylindrical shape on . Side surfaces 9 of the cavities 12 are provided with a dielectric protective layer 10. The cavities 12 are in this case air-filled and together with the surrounding semiconductor material of the n-doped epitaxial semiconductor layer 14 form a photonic crystal 17 .

[0119] The photonic crystal 17 is arranged in a near field of the electromagnetic radiation generated in the active layer 15, so that electromagnetic laser radiation is generated in operation in an active region 21 of the epitaxial semiconductor layer sequence 13.

[0120] The semiconductor laser chip according to the embodiment shown in Figure 6 is therefore a photonic semiconductor laser chip.

[0121] In particular, the semiconductor laser chip according to the embodiment shown in Figure 6 can be produced using the method already described with reference to Figures 1 to 5. The bottom surfaces 6 of the cavities 12 are therefore slightly overgrown with the semiconductor material 11.

[0122] In the method according to the embodiment shown in Figure 7, the steps already described with reference to Figures 1 to 3 are first carried out. Then, as in the method according to the embodiment shown in Figures 1 to 5, a dielectric protective layer 10 is removed from the end faces 8 of the projections 7 by dry chemical etching. In contrast to the method shown in Figures 1 to 5, however, the directed anisotropic etching j takes place at an angle α to a growth direction R. wthe epitaxial semiconductor layer 2 instead. Therefore, in this 2024PF01512, February 17, 2026

[0123] P2024, 1132 WO N 22

[0124] In this embodiment, only the end faces 8 of the projections 7 are exposed, but not the bottom faces 6 of the recesses 1. Consequently, the bottom faces 6 of the recesses 1 remain covered with the dielectric protective layer 10.

[0125] Afterwards, the recesses 1 are closed again by epitaxial overgrowth with a semiconductor material 11, so that closed cavities 12 are formed in the epitaxial semiconductor layer 2 (not shown).

[0126] The semiconductor laser chip according to the embodiment shown in Figure 8 can, for example, be produced using the method described with reference to Figure 7. In contrast to the semiconductor laser chip shown in Figure 6, the bottom surfaces 6 of the cavities 12, like the side surfaces 9 of the cavities 12, are covered with the dielectric protective layer 10. Furthermore, the bottom surfaces 6 of the cavities 12 are free of epitaxially grown semiconductor material 11.

[0127] In the method according to the embodiment shown in Figures 9 to 11, recesses 1 are first created in an epitaxial semiconductor layer 2, as already described in connection with Figure 1 (Figure 9).

[0128] Then, a dielectric protective layer 10 is deposited over the structured main surface 3 of the epitaxial semiconductor layer 2, for example using ALD or CVD. The structured mask layer 4 is not removed from the main surface 3 of the epitaxial semiconductor layer 2. Therefore, the dielectric protective layer 10 is conformally deposited on the mask layer 4, on side surfaces 9, and on the bottom surfaces 6 of the recesses 1 (Figure 10). 2024PF01512 February 17, 2026

[0129] P2024, 1132 WO N 23

[0130] The mask layer 4 is then removed, and simultaneously, the dielectric protective layer 10 located on it is partially lifted off. After removal of the dielectric protective layer 10, only the side surfaces 9 and the bottom surfaces 6 of the recesses 1 are completely covered with the dielectric protective layer 10 (Figure 11).

[0131] Subsequently, the recesses 1 are completely closed again by overgrowth, so that cavities 12 are created, as already described for example with reference to Figure 5 (not shown).

[0132] Figures 12 to 15 show sections of the epitaxial semiconductor layer 2 with a recess 1 .

[0133] The recess 1 according to the embodiment of Figure 12 has a dielectric protective layer 10 which completely covers the side surface 9 of the recess 1 and the bottom surface 6 of the recess 1.

[0134] The recess 1 according to the embodiment shown in Figure 13 has a dielectric protective layer 10 which, unlike the embodiment shown in Figure 12, is located away from areas 18 of the side surface 9, starting from an opening 5 of the recess 1. In the area 18 adjacent to the opening 5, the recess 1 is therefore free of the dielectric protective layer 10. In this case, the semiconductor material of the epitaxial semiconductor layer 2, which delimits the recess 1, projects in the growth direction R at the beginning of the overgrowth. w slightly beyond the dielectric protective layer 10. Epitaxial semiconductor material 11, deposited by lateral overgrowth, and the 2024PF01512 February 17, 2026

[0135] P2024, 1132 WO N - 24 -

[0136] To completely close off recess 1, growth occurs on the areas 18 of the side surface 9 of recess 1 that are not covered by the dielectric protective layer 10, thus significantly facilitating lateral growth over recess 1.

[0137] In contrast to the recess 1 of Figure 13, in the embodiment of Figure 14 the dielectric protective layer 10 only partially covers the side surface 9 of the recess 1. The bottom surface 6 of the recess 1, however, is free of the dielectric protective layer 10. Such an arrangement of the dielectric protective layer 10 on the surface of the recess 1 can be achieved, for example, by the method according to Figures 1 to 5.

[0138] The recess 1 according to the embodiment shown in Figure 15 also has a side surface 9 that is partially free of the dielectric protective layer 10. In contrast to the recess 1 in Figure 13, the dielectric protective layer 10 is asymmetrically removed from the side surface 9. Such a structuring of the dielectric protective layer 10 also aids in the lateral overgrowth of the recesses 1 to form closed cavities 10. Such a geometry of the dielectric protective layer 10 can be achieved, for example, by a method in which the dielectric protective layer 10 is removed by anisotropic etching at an angle α, as described with reference to Figure 7.

[0139] The semiconductor laser chip according to the embodiment shown in Figure 16, unlike the semiconductor laser chip according to the embodiment shown in Figure 8, has a photonic 2024PF01512 17 February 2026

[0140] P2024, 1132 WO N - 25 -

[0141] Crystal 17 in the p-doped epitaxial semiconductor layer 16 on .

[0142] The semiconductor laser chip according to the embodiment of Figure 17 has a photonic crystal 17 with cavities 12 in both the p-doped epitaxial semiconductor layer 16 and the n-doped epitaxial semiconductor layer 14.

[0143] The semiconductor laser chip according to the embodiment shown in Figures 18 and 19 is a DFB semiconductor laser chip. The semiconductor laser chip has a plurality of closed cavities 12 that form a one-dimensional optically active grating 19. The optically active grating 19 comprises strip-shaped cavities 12 that are oriented perpendicular to a propagation direction R. A the electromagnetic laser radiation in the semiconductor laser chip.

[0144] As shown in the top view of the semiconductor laser chip according to Figure 18, the semiconductor laser chip comprises a bridge waveguide 20 which runs along the propagation direction R A is arranged . The spacing of the cavities 12 of the one-dimensional optically active grating 19 is a multiple of half the wavelength of the electromagnetic laser radiation emitted by the semiconductor laser chip during operation.

[0145] As shown in the side view of the semiconductor laser chip in Figure 19, the cavities 12 of the optically active grating 19 are arranged within the semiconductor laser chip. 2024PF01512 February 17, 2026

[0146] P2024, 1132 WO N 26

[0147] In the method according to the embodiment shown in Figures 20 and 21, cavities 12 with an asymmetrical geometry are produced. For this purpose, the mask layer 4 and the dielectric protective layer 10 are removed by directed dry chemical etching at an angle α (Figure 20). The dielectric protective layer 10 is completely removed from a portion of the side surface 9 of the recess 1 and from a portion of the bottom surface 6 of the recess 1. In particular, the dielectric protective layer 10 is removed from the side surface 9 of the recess 1 such that an area of ​​the surface of the recess 1 is free of the dielectric protective layer 10, extending from the opening 5 of the recess 1 to the bottom surface 6.

[0148] When the recesses 1 are overgrown to create the closed cavities 12, epitaxial semiconductor material 11 grows on the exposed area 18 of the recess 1, resulting in an oblique geometry of the closed cavities 12 (Figure 21 ).

[0149] The present application claims priority over German application DE 102025109354.7, the disclosure content of which is hereby incorporated by reference.

[0150] The invention is not limited to the description provided by the exemplary embodiments. Rather, the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the claims, even if that feature or combination itself is not explicitly stated in the claims or exemplary embodiments. 2024PF01512 February 17, 2026

[0151] P2024, 1132 WO N 27

[0152] Reference symbol list

[0153] 1 Exclusion

[0154] 2 epitaxial semiconductor layer

[0155] 3 Main area of ​​the epitaxial semiconductor layer 4 Mask layer

[0156] 5 Opening

[0157] 6 Floor area of ​​the recess

[0158] 7 lead

[0159] 8 Front surface of the projection

[0160] 9 Side surface of the recess

[0161] 10 dielectric protective layer

[0162] 11 Semiconductor material

[0163] 12 Cavity

[0164] 13 epitaxial semiconductor layer sequence

[0165] 14 n-doped epitaxial semiconductor layer 15 active layer

[0166] 16 p-doped epitaxial semiconductor layer 17 photonic crystal

[0167] 18 exposed areas of the side surface

[0168] 19 optically active gratings

[0169] 20 Bridge waveguides 20

[0170] 21 active area

[0171] R w direction of growth

[0172] R v Preferred direction

[0173] R L lateral direction

[0174] a angle

[0175] RA direction of propagation

Claims

2024PF01512 February 17, 2026 P2024 , 1132 WO N 28 Patent claims:

1. Method for manufacturing a semiconductor laser chip comprising the following steps: - Generating a plurality of recesses ( 1 ) in an epitaxial semiconductor layer ( 2 ), wherein the recesses ( 1 ) have openings ( 5 ) on a principal surface ( 3 ) of the epitaxial semiconductor layer ( 2 ), - conformal overforming of the main surface (3) of the epitaxial semiconductor layer (2) which has the openings (5) of the recesses (1) with a dielectric protective layer (10), and - epitaxial overgrowth of the recesses ( 1 ) with a semiconductor material ( 11 ) , so that closed cavities ( 12 ) are formed in the epitaxial semiconductor layer ( 2 ), wherein - the dielectric protective layer ( 10 ) on bottom surfaces ( 6 ) of the recesses ( 1 ) is removed .

2. Method according to the preceding claim, wherein the dielectric protective layer ( 10 ) prevents epitaxial deposition of semiconductor material ( 11 ) on side surfaces ( 9 ) of the recesses ( 1 ) during overgrowth of the recesses ( 1 ).

3. Method according to any of the preceding claims, wherein the epitaxial semiconductor layer ( 2 ) is p-doped or n-doped.

4. Method according to one of the preceding claims, wherein the epitaxial semiconductor layer (2) with the closed cavities (12) forms a photonic crystal (17) which is used to guide an electromagnetic laser radiation in a 2024PF01512 17 February 2026 P2024 , 1132 WO N 29 active area ( 21 ) of the semiconductor laser chip is set up .

5. Method according to any one of claims 1 to 3, wherein the closed cavities ( 12 ) form an optically active grating ( 19 ) which is configured to couple electromagnetic laser radiation to the optically active grating ( 19 ).

6. Method according to any of the preceding claims, wherein the cavities ( 12 ) are filled with air and / or a process gas.

7. Method according to one of the preceding claims, wherein a mask layer (4) is applied to produce the recesses (1) on projections (7) between the recesses (1), and - the mask layer ( 4 ) is removed before the application of the dielectric protective layer ( 10 ).

8. Method according to any one of claims 1 to 6, wherein - a mask layer ( 4 ) is applied to create the recesses ( 1 ) on projections ( 7 ) between the recesses ( 1 ), and - the dielectric protective layer ( 10 ) is applied to the mask layer ( 4 ).

9. Method according to the preceding claim, wherein the mask layer (4) is removed from the projections (7) between the recesses (1) together with the dielectric protective layer (10) before the recesses (1) are overgrown. 2024PF01512 17 February 2026 P2024, 1132 WO N 30 10. Method according to any of the preceding claims, wherein the conformal overforming through the dielectric protective layer ( 10) is carried out by means of ALD or CVD .

11. Method according to one of the preceding claims, wherein the dielectric protective layer ( 10 ) is removed prior to epitaxial overgrowth of the recesses ( 1 ) by anisotropic etching of projections (7 ) between the recesses ( 1 ).

12. Method according to the preceding claim, wherein the anisotropic etching of the dielectric protective layer ( 10) along a growth direction (R w ) of the epitaxial semiconductor layer (2 ) .

13. Method according to any one of claims 9 to 12, wherein the dielectric protective layer ( 10 ) is partially removed from the side surfaces ( 9 ) of the recesses ( 1 ) starting from the openings (5) during anisotropic etching.

14. Method according to claims 11 to 13, wherein - the anisotropic etching of the dielectric protective layer ( 10) at an angle (a) to a growth direction (R w ) of the epitaxial semiconductor layer (2 ) takes place, and - the dielectric protective layer ( 10) is removed asymmetrically from the side surfaces ( 9) of the recesses ( 1 ).

15. Semiconductor laser chip comprising an epitaxial semiconductor layer sequence ( 13) with : - an epitaxial semiconductor layer (2 ) with a plurality of cavities ( 12 ) , - an active layer ( 15) which is configured to generate electromagnetic radiation, wherein 2024PF01512 17 February 2026 P2024, 1132 WO N - 31 - - Side surfaces ( 9) of the cavities ( 12 ) are at least partially covered with a dielectric protective layer ( 10 ), wherein the bottom surfaces of the cavities ( 12 ) are free from the dielectric protective layer ( 10 ).

16. Semiconductor laser chip according to claim 15, wherein the dielectric protective layer ( 10) comprises an oxide, an oxynitride or a nitride of one of the following metals: Al, Ce, Ga, Hf, In, Mg, Nb, Nd, Rh, Sb, Si, Sn, Ta, Ti, Zn, Zr .

17. Semiconductor laser chip according to one of claims 15 or 16, wherein the dielectric protective layer ( 10) comprises at least two individual layers .

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