Semiconductor device

Abstract

Provided is a novel semiconductor device. This semiconductor device comprises a first storage circuit including a flip-flop circuit, and a second storage circuit including first to third transistors and a storage element. A first terminal of the first transistor is electrically connected to a first terminal of the first storage circuit. A second terminal of the first transistor is electrically connected to a first terminal of the second transistor and a first terminal of the storage element. A second terminal of the second transistor is electrically connected to a first terminal of the third transistor and a second terminal of the first storage circuit. A magnetic tunnel junction element is used as the storage element.

Description

Semiconductor equipment

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed herein relates to a product, a method, or a method of manufacture. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed herein include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, methods for driving them, or methods for manufacturing them.

[0003] Technological development is progressing on semiconductor devices that can hold charge according to data by combining transistors that use oxide semiconductors in the semiconductor layer where the channel is formed (also called "OS transistors") and transistors that use silicon in the semiconductor layer where the channel is formed (also called "Si transistors").

[0004] The semiconductor device can achieve low power consumption through power gating by being configured to save (also called "recovery," "store," or "backup") or load (also called "restore," "recovery," or "return") programs or data held in flip-flops or the like. For example, Patent Document 1 shows a configuration in which an OS transistor is connected to a flip-flop, which is a volatile memory circuit, to realize a non-volatile flip-flop.

[0005] Japanese Patent Publication No. 2016-82593

[0006] To further reduce the power consumption of semiconductor devices, there is a need to achieve longer power gating times.

[0007] One aspect of the present invention aims to provide a semiconductor device with reduced power consumption. Alternatively, one aspect of the present invention aims to provide a miniaturized semiconductor device. Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device or a novel method for operating a semiconductor device.

[0008] Furthermore, the description of the above problems does not preclude the existence of other problems. Other problems can be naturally identified by those skilled in the art from the description in the specification, drawings, and claims, and it is possible to extract other problems from the description in the specification, drawings, and claims. Furthermore, one aspect of the present invention does not need to solve all of these problems (the above problems and other problems).

[0009] One aspect of the present invention is a semiconductor device having a first memory circuit and a second memory circuit including a first transistor, a second transistor, a third transistor, and a memory element, wherein the first terminal of the first transistor is electrically connected to the first terminal of the first memory circuit, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the memory element, and the second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the second terminal of the first memory circuit, and the memory element is a magnetic tunnel junction element.

[0010] For example, a flip-flop circuit can be used as the first memory circuit. The first memory circuit may also have a selection circuit.

[0011] It is preferable that the first memory circuit and the second memory circuit have overlapping regions. It is preferable that each of the first transistor, the second transistor, and the third transistor includes an oxide semiconductor in the semiconductor layer in which the channel is formed. It is preferable that the first memory circuit includes a transistor that includes silicon in the semiconductor layer in which the channel is formed.

[0012] According to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one aspect of the present invention, a miniaturized semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device or a novel method of operating a semiconductor device can be provided.

[0013] Furthermore, the description of the above effects does not preclude the existence of other effects. Other effects can be naturally found from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. Furthermore, one aspect of the present invention does not need to have all of these effects (the above effects and other effects).

[0014] Figures 1A, 1B1, and 1B2 illustrate examples of semiconductor device configurations. Figures 2A and 2B illustrate examples of semiconductor device configurations. Figures 3A and 3B illustrate examples of semiconductor device configurations. Figure 4 illustrates an example of semiconductor device configuration. Figure 5 illustrates an example of semiconductor device configuration. Figure 6 illustrates an example of semiconductor device configuration. Figure 7 illustrates an example of semiconductor device configuration. Figure 8 illustrates an example of semiconductor device configuration. Figures 9A and 9B are timing charts illustrating examples of semiconductor device operation. Figures 10A and 10B are timing charts illustrating examples of semiconductor device operation. Figure 11 illustrates an example of semiconductor device operation. Figure 12 illustrates an example of semiconductor device operation. Figure 13 illustrates an example of semiconductor device operation. Figure 14 illustrates an example of semiconductor device operation. Figure 15 illustrates an example of semiconductor device operation. Figure 16 illustrates an example of semiconductor device operation. Figure 17 illustrates an example of semiconductor device operation. Figure 18 illustrates an example of semiconductor device operation. Figure 19 illustrates an example of semiconductor device configuration. Figure 20 illustrates an example of a cross-sectional configuration of a semiconductor device. Figures 21A and 21B illustrate an example of a cross-sectional configuration of a semiconductor device. Figures 22A, 22B, and 22C illustrate an example of a transistor configuration. Figures 23A, 23B, and 23C illustrate an example of a transistor configuration. Figure 24 illustrates an example of a transistor configuration. Figures 25A and 25B show an example of an electronic component. Figures 26A, 26B, 26C, 26D, 26E, 26F, 26G, 26H, 26I, and 26J illustrate an example of an electronic device. Figures 27A, 27B, and 27C illustrate an example of an electronic device. Figure 28 shows an example of a space device.

[0015] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and those skilled in the art will readily understand that various changes can be made to the forms and details thereof without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited to the contents described in the following embodiments.

[0016] In the drawings and the like relating to the present specification, the size, the thickness of a layer, or a region may be exaggerated for clarity. Therefore, the invention is not necessarily limited to the size, the aspect ratio, or the like. Note that the drawings schematically show ideal examples, and are not limited to the shapes, values, or the like shown in the drawings.

[0017] In the configuration of the invention according to the embodiments, the same reference numerals are used in common for the same portions or portions having similar functions across different drawings, and repeated description thereof may be omitted. In addition, when referring to similar functions, the same hatching pattern is used, and in some cases no particular reference numeral is assigned. In addition, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views, plan views, or the like.

[0018] In the present specification and the like, ordinal numbers such as "first" and "second" are used to avoid confusion between components. Therefore, they do not limit the number of components. Nor do they limit the order of components. For example, a component referred to as "first" in one embodiment herein may be a component referred to as "second" in other embodiments or in the claims. Further, for example, a component referred to as "first" in one embodiment herein may be omitted in other embodiments or in the claims. In addition, even for terms that are not assigned ordinal numbers in the present specification, ordinal numbers may be assigned in the claims to avoid confusion between components. Further, even for terms that are assigned ordinal numbers in the present specification, different ordinal numbers may be assigned in the claims. Furthermore, even for terms that are assigned ordinal numbers in the present specification, ordinal numbers may be omitted in the claims or the like.

[0019] In this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases described in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0020] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0021] In this specification, terms such as "overlapping" do not limit the stacking order or other states of the constituent elements. For example, the expression "electrode B overlapping insulating layer A" does not exclude not only the state in which electrode B is formed on top of insulating layer A, but also the state in which electrode B is formed below insulating layer A, or the state in which electrode B is formed to the right (or left) of insulating layer A, etc.

[0022] In this specification and the like, the terms "film", "layer", and the like may be interchanged with each other depending on the circumstances. For example, in some cases, the term "conductive layer" may be changed to the term "conductive film". Alternatively, for example, in some cases, the term "insulating film" may be changed to the term "insulating layer". Alternatively, in some cases or depending on the circumstances, these terms such as "film" and "layer" may be replaced with other terms without using such terms. For example, in some cases, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Alternatively, in some cases, the term "conductor" may be changed to the term "conductive layer" or "conductive film". Alternatively, for example, in some cases, the term "insulating layer" or "insulating film" may be changed to the term "insulator". Alternatively, in some cases, the term "insulator" may be changed to the term "insulating layer" or "insulating film".

[0023] In this specification and the like, terms such as "electrode", "wiring", and "terminal" do not functionally limit these constituent elements. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the term "electrode" or "wiring" also includes cases where a plurality of "electrodes" or "wirings" are formed integrally. Also, for example, a "terminal" may be used as part of a "wiring" or an "electrode", and vice versa. Furthermore, the term "terminal" also includes cases where a plurality of "electrodes", "wirings", "terminals", and the like are formed integrally. Therefore, for example, an "electrode" may be part of a "wiring" or a "terminal", and for example, a "terminal" may be part of a "wiring" or an "electrode". In addition, terms such as "electrode", "wiring", and "terminal" may be replaced with terms such as "region", "conductive layer", and the like in some cases.

[0024] In this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other as appropriate or depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line," and vice versa. Terms such as "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line," and vice versa. Furthermore, the term "potential" applied to wiring may be changed to the term "signal," and vice versa.

[0025] In this specification, "source" refers to a source region, a source electrode, or a source wiring. A source region refers to one of two regions of a semiconductor layer adjacent to a channel formation region. A source electrode refers to a conductive layer that includes the portion connected to the source region.

[0026] In this specification, "drain" refers to a drain region, a drain electrode, or drain wiring. A drain region refers to the other of two regions adjacent to a channel formation region within a semiconductor layer. A drain electrode refers to a conductive layer that includes the portion connected to the drain region.

[0027] In this specification, "gate" means gate electrode or gate wiring. A gate electrode is an electrode that overlaps with the semiconductor layer of a transistor and has the function of controlling the resistance between the source and drain of the transistor by the supplied voltage.

[0028] In this specification, one of the source or drain of a transistor may be referred to as the "first terminal," and the other of the source or drain of a transistor may be referred to as the "second terminal."

[0029] In this specification, "parallel" means a state in which two lines are positioned at a relative angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Furthermore, "approximately parallel" or "roughly parallel" means a state in which two lines are positioned at a relative angle of -15° or more and 15° or less. Furthermore, "perpendicular" means a state in which two lines are positioned at a relative angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Furthermore, "approximately perpendicular" or "roughly perpendicular" means a state in which two lines are positioned at a relative angle of 60° or more and 120° or less.

[0030] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage and potential are often interchangeable. In this specification, unless otherwise specified, voltage and potential are considered interchangeable.

[0031] Furthermore, in this specification, the high power supply potential VDD (hereinafter also simply referred to as "VDD") refers to a power supply potential that is higher than the low power supply potential VSS. The low power supply potential VSS (hereinafter also simply referred to as "VSS") refers to a power supply potential that is lower than the high power supply potential VDD. The ground potential GND (hereinafter also simply referred to as "GND") can also be used as VDD or VSS. For example, if VDD is GND, then VSS is at a lower potential than GND, and if VSS is GND, then VDD is at a higher potential than GND.

[0032] In this specification, the "on state" of a transistor means that the source and drain of the transistor are conductive (a state in which current can be conducted). The "off state" of a transistor means that the source and drain of the transistor are non-conductive (a state in which it can be considered blocked).

[0033] Furthermore, in this specification, "on-current" refers to the current that flows between the source and drain when the transistor is in the ON state. "Off-current" refers to the current that flows between the source and drain when the transistor is in the OFF state.

[0034] In this specification, potential H is the potential that turns an n-channel field-effect transistor (also called an "n-type transistor") on, and the potential that turns a p-channel field-effect transistor (also called a "p-type transistor") off. Similarly, potential L is the potential that turns an n-type transistor off, and the potential that turns a p-type transistor on. Therefore, potential H is higher than potential L. Potential H may be equal to VDD. Potential L may be equal to VSS. Furthermore, unless otherwise specified, the transistors described in this specification are enhancement-type (normally-off) transistors.

[0035] Furthermore, in drawings and other diagrams, to clearly indicate the potential of wiring and electrodes, a "H" indicating potential H or a "L" indicating potential L may be enclosed in a box next to the wiring and electrodes. In this case, if the potential has not changed, it will be shown with a dashed box, and if the potential has changed, it will be shown with a solid box. Also, if a transistor is in the off state, an "×" symbol may be superimposed on the transistor. Additionally, an arrow indicating the direction of current flow may be added.

[0036] In this specification, when count values ​​and measured values ​​are referred to as "identical," "same," "equal," or "uniform" (including synonyms thereof), unless otherwise explicitly stated, this shall include an error margin of plus or minus 10%.

[0037] Furthermore, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X-axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction." Also, the X, Y, and Z directions are directions that intersect each other. For example, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0038] Generally, a "capacitor" has a configuration in which two electrodes face each other with an insulator (dielectric) in between. In this specification, the term "capacitor element" includes the case of the aforementioned "capacitor." That is, in this specification, the term "capacitor element" includes cases in which two electrodes face each other with an insulator in between, cases in which two wires face each other with an insulator in between, or cases in which two wires are arranged with an insulator in between. In this specification, one of the two electrodes may be referred to as the "first electrode" or "first terminal," and the other as the "second electrode" or "second terminal."

[0039] In this specification, when the same symbol is used for multiple elements, and especially when it is necessary to distinguish them, the symbol may be accompanied by an identifying code such as "A", "b", "_1", "[n]", or "[m,n]".

[0040] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0041] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0042] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0043] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0044] One aspect of the present invention is all or part of the circuit configuration described herein. Therefore, one aspect of the present invention does not have to include all or part of the operation described herein.

[0045] (Embodiment 1) In this embodiment, an example of the configuration and operation of a semiconductor device according to one aspect of the present invention will be described. Figure 1A shows an example of the circuit configuration of a semiconductor device 100 according to one aspect of the present invention. The semiconductor device 100 shown in Figure 1A has a first memory circuit 110 and a second memory circuit 120.

[0046] A semiconductor device 100 according to one aspect of the present invention functions as a memory device. Furthermore, a semiconductor device 100 according to one aspect of the present invention has the function of storing data held by the first memory circuit 110 in the second memory circuit 120 before the power supply is stopped due to power gating. In other words, a semiconductor device 100 according to one aspect of the present invention has the function of performing backup operations.

[0047] Furthermore, the semiconductor device 100 according to one aspect of the present invention has a function to write back the data held in the second memory circuit 120 to the first memory circuit 110 when power supply is restored. In other words, the semiconductor device 100 according to one aspect of the present invention has a function to perform a recovery operation.

[0048] <<Configuration Example>> The first memory circuit 110 has terminals SD, D, SE, CLK, Q, and QB. The first memory circuit 110 also has a flip-flop circuit 111 and a selection circuit 112. The flip-flop circuit 111 has terminals DF, QF, and QBF. Figure 1A shows an example in which a scan flip-flop circuit is used as the first memory circuit 110.

[0049] The selection circuit 112 has the function of supplying either the signal supplied to terminal SD or the signal supplied to terminal D to terminal DF of the flip-flop circuit 111, according to the signal supplied to terminal SE. In addition, a clock signal is supplied to terminal CLK. This clock signal is supplied to the flip-flop circuit 111 via terminal CLK. Terminals SD, D, SE, and CLK function as input terminals.

[0050] The flip-flop circuit 111 has the function of holding data supplied to terminal DF in synchronization with the rising edge of the clock signal supplied via terminal CLK while power is supplied. The flip-flop circuit 111 also has the function of supplying a signal corresponding to the held data to terminal Q via terminal QF. The flip-flop circuit 111 also has the function of supplying an inverted signal of the held data to terminal QB via terminal QBF. Terminals Q and QB function as output terminals. The first memory circuit 110 has the function of holding 1 bit of data while power is supplied to the semiconductor device 100.

[0051] The second memory circuit 120 has terminals IN, OUT, BL, BK, RE, RST, and SDI. The second memory circuit 120 also has transistors Tr1, Tr2, Tr3, and memory element ME.

[0052] One source or drain of transistor Tr1 is connected to terminal IN, and the other source or drain is connected to one source or drain of transistor Tr2 and one terminal of memory element ME. The gate of transistor Tr1 is connected to terminal BK. The other terminal of memory element ME is connected to terminal BL. The other source or drain of transistor Tr2 is connected to one source or drain of transistor Tr3 and terminal OUT. The gate of transistor Tr2 is connected to terminal RE. The other source or drain of transistor Tr3 is connected to terminal SDI. The gate of transistor Tr3 is connected to terminal RST. Note that one terminal of memory element ME may be referred to as the "first terminal," and the other terminal of memory element ME may be referred to as the "second terminal."

[0053] Furthermore, terminal Q of the first memory circuit 110 is connected to terminal IN of the second memory circuit 120. Also, terminal OUT of the second memory circuit 120 is connected to terminal SD of the first memory circuit 110. In Figure 1A and other diagrams, the region where the other source or drain of transistor Tr1, one source or drain of transistor Tr2, and one terminal of memory element ME are connected and always at the same potential is denoted as node Nd.

[0054] As a memory element (ME), a magnetic tunnel junction (MTJ) element (also called an "MTJ element") can be used. An MTJ element is also called a tunnel magnetoresistance (TMR) element (also called a "TMR element") and is a non-volatile memory element that uses a magnetic material.

[0055] Capacitive elements can also be used as memory elements (MEs). However, when capacitive elements are used as memory elements, there is a risk that data retention capacity may decrease due to natural discharge, etc., if the retention time is long. If the period of power supply interruption due to power gating is long, using MTJ elements as memory elements (MEs) allows for longer-term data retention. Therefore, the reliability of semiconductor devices can be improved.

[0056] Here, we will explain the MTJ element used as a memory element ME using Figures 1B1 and 1B2. The MTJ element is composed of two ferromagnetic layers sandwiched together by a thin insulating layer (insulating layer TI, also called the "tunnel insulating layer") that is thin enough for tunnel current to flow. One of the two ferromagnetic layers is a fixed layer (also called the "reference layer") PL in which the magnetization direction does not change easily, and the other is a free layer FL in which the magnetization direction changes easily.

[0057] It is preferable to use ferromagnetic materials that are less susceptible to magnetization reversal due to thermal energy for the fixed layer PL and the free layer FL. For example, materials containing one or more elements selected from iron, cobalt, and nickel can be used for the fixed layer PL and the free layer FL. For example, an alloy of cobalt, iron, and boron can be used. In addition, an alloy of manganese and gallium, or an alloy of manganese and germanium can be used.

[0058] Magnesium oxide, aluminum oxide, and the like can be used as the insulating layer TI. In particular, it is preferable to use crystalline magnesium oxide as the insulating layer TI that functions as a tunnel insulating layer.

[0059] In Figures 1B1 and 1B2, the magnetization directions of the fixed layer PL and the free layer FL are indicated by arrows. In an MTJ element, the resistance is small when the magnetization directions of the fixed layer PL and the free layer FL are parallel (see Figure 1B1), and large when they are antiparallel (see Figure 1B2). Therefore, an MTJ element can be called a resistive switching element. By relating the magnitude of the resistance of an MTJ element to one bit, one bit of data can be stored.

[0060] By passing a current above a certain level through the MTJ element, the magnetization direction of the free layer FL can be changed. For example, by passing a current above a certain level from the fixed layer PL to the free layer FL, the magnetization direction of the free layer FL can be made parallel to the fixed layer PL. Conversely, by passing a current above a certain level from the free layer FL to the fixed layer PL, the magnetization direction of the free layer FL can be made antiparallel to the fixed layer PL. In other words, by changing the direction in which a current above a certain level flows through the MTJ element, magnetization reversal can be caused in the free layer FL, and data can be written to it. Furthermore, by measuring the resistance value of the MTJ element, the data can be read out.

[0061] Therefore, it is preferable to combine the configurations of the free layer FL, the fixed layer PL, and the insulating layer TI such that the ratio of the resistance value when the magnetization directions of the free layer FL and the fixed layer PL are parallel to the resistance value when they are antiparallel (also called the "magnetoresistance ratio" or "MR ratio") is large.

[0062] Furthermore, magnetization reversal does not occur in the MTJ element unless a current above a certain level flows through it. Therefore, the second memory circuit 120 has the function of holding 1 bit of data input from terminal IN while the power supply to the semiconductor device 100 is stopped.

[0063] The transistors Tr1, Tr2, and Tr3 in the second memory circuit 120 function as switches. In the second memory circuit 120 shown in Figure 2A, transistor Tr1 is replaced with switch SW1, transistor Tr2 is replaced with switch SW2, and transistor Tr3 is replaced with switch SW3.

[0064] Various transistors can be used as transistors Tr1, Tr2, and Tr3. For example, a transistor using silicon in the semiconductor layer where the channel is formed (also called a "Si transistor") can be used. Alternatively, a transistor using oxide semiconductor in the semiconductor layer where the channel is formed (also called an "OS transistor") can be used.

[0065] In particular, OS transistors have a high dielectric breakdown voltage between their source and drain, making them suitable as switches. Furthermore, because OS transistors can be formed as a type of thin-film transistor, they can be superimposed on existing circuits.

[0066] Si transistors often have a larger on-current and faster operating speed than OS transistors. Furthermore, since p-type Si transistors can be implemented, they are suitable for logic circuits and other applications. However, while Si transistors operate quickly, they tend to generate more heat. OS transistors, on the other hand, operate stably even in high-temperature environments and exhibit less characteristic variation. Therefore, even when a circuit containing OS transistors is superimposed on a circuit containing Si transistors, the effects of heat generation are minimal. Thus, the reliability of the semiconductor device 100 can be improved.

[0067] For example, as shown in Figure 3A, a first memory circuit 110 can be formed on layer 10 containing a Si transistor, and a second memory circuit 120 can be formed on layer 20 containing an OS transistor. In other words, the second memory circuit 120 can be superimposed on the region where the first memory circuit 110 is formed. According to one aspect of the present invention, it is possible to significantly reduce the increase in occupied area (area overhead) due to the addition of the second memory circuit 120 to the first memory circuit 110. Furthermore, according to one aspect of the present invention, it is possible to make the area overhead substantially zero. According to one aspect of the present invention, a semiconductor device with reduced occupied area can be realized. According to one aspect of the present invention, the integration density of a semiconductor device can be increased.

[0068] By combining multiple semiconductor devices 100, it is possible to configure a register that can retain multiple bits of data even when the power supply is interrupted. Figure 3B shows an example of a register 150 capable of storing n bits of data (where n is an integer of 1 or more). In Figure 3B, the semiconductor device 100 that stores the first bit of data is shown as semiconductor device 100[1], the first memory circuit 110 of semiconductor device 100[1] is shown as first memory circuit 110[1], and the second memory circuit 120 of semiconductor device 100[1] is shown as second memory circuit 120[1]. The same applies to each semiconductor device 100 that stores the second to fifth bits and the nth bit of data.

[0069] Furthermore, a memory circuit constructed using OS transistors is sometimes called an "OS memory." Therefore, the second memory circuit 120, which uses OS transistors for transistors Tr1, Tr2, and Tr3, is an OS memory. Also, the semiconductor device 100 having the second memory circuit 120 is an OS memory.

[0070] Furthermore, transistors having back gates can be used as transistors constituting the semiconductor device 100.

[0071] The back gate of a transistor can function similarly to the transistor's gate. The back gate can be at the same potential as the gate, or at a reference potential, GND, or any other potential. By changing the back gate's potential independently of the gate's potential, the transistor's threshold voltage can be altered.

[0072] As an example, Figure 2B shows a circuit configuration example of a second memory circuit 120 using transistors Tr1, Tr2, and Tr3, each having a back gate. Transistors Tr1, Tr2, and Tr3 shown in Figure 2B each have a configuration in which the gate and back gate are connected.

[0073] By connecting the gate and back gate, the gate and back gate are always at the same potential. By supplying the potential to turn the transistor ON to both the gate and back gate, the ON current can be increased compared to supplying the potential to only one of them.

[0074] Furthermore, by providing a back gate, a function is obtained that prevents electric fields generated outside the transistor from acting on the channel formation region (particularly an electric field shielding function against static electricity). Therefore, by providing a back gate, the transistor can be operated stably. In addition, the reliability of the semiconductor device containing the transistor can be improved. Moreover, by providing a back gate in addition to the gate, the variation in characteristics between multiple transistors can be reduced. Note that the electric field shielding effect can be obtained even if one or both of the gate and back gate are electrically floating (also called a "floating state"), but the effect can be further enhanced by supplying potential to the gate and back gate.

[0075] Furthermore, as shown in Figure 4, the semiconductor device 100 can be configured such that the terminal IN of the second memory circuit 120 is connected to terminal QB of the first memory circuit 110 instead of terminal Q. In this case, it is preferable to set the potential supplied to terminal SDI to potential H. Alternatively, it is preferable that the first terminal of memory element ME is connected to terminal BL, and the second terminal of memory element ME is connected to node Nd. By doing so, the semiconductor device 100 shown in Figure 4 can be operated in the same way as the semiconductor device 100 shown in Figure 1.

[0076] Furthermore, as shown in Figure 5, the semiconductor device 100 can be configured to connect the gate of transistor Tr3 of the second memory circuit 120 to the gate of transistor Tr1. This reduces the amount of wiring connected to terminal RST and thus the footprint of the semiconductor device 100.

[0077] Furthermore, in the semiconductor device 100 shown in Figure 5, when transistor Tr1 is turned on, transistor Tr3 is also turned on, and a potential L can be supplied to terminals OUT and SD. Therefore, the backup operation period T11, which will be explained later, can be omitted. Thus, the backup operation can be made faster. In addition, the power consumption required for the backup operation can be reduced.

[0078] Furthermore, in the semiconductor device 100 shown in Figure 5, it is preferable to maintain the potentials of terminals OUT and SD during periods when the power supply is stopped. Therefore, if the power supply stoppage period is relatively short, Si transistors can be used for transistors Tr2 and Tr3. On the other hand, if the power supply stoppage period is relatively long, it is preferable to use OS transistors with low off-current for transistors Tr2 and Tr3.

[0079] Furthermore, as shown in Figure 6, it is also possible to configure the semiconductor device 100 without forming the selection circuit 112 of the first memory circuit 110. By not forming the selection circuit 112, the occupied area of ​​the semiconductor device 100 can be reduced. In addition, the number of terminals D and SE can be reduced.

[0080] Furthermore, as shown in Figure 7, it is possible to provide a level shift circuit LS between terminal Q and terminal IN in the semiconductor device 100. The level shift circuit LS can amplify the amplitude of the output signal of the first memory circuit 110. By amplifying the amplitude of the output signal of the first memory circuit 110, data can be written to the memory element ME more accurately.

[0081] Furthermore, as shown in Figure 8 of the semiconductor device 100, it is possible to connect terminal IN to terminal QB and to provide a NOT circuit (inverter 113) between terminal OUT and terminal SD. Figure 8 shows an example in which the input terminal of the inverter 113 is connected to terminal OUT and the output terminal is connected to terminal SD. By providing the inverter 113 between terminal OUT and terminal SD, the amplitude of the voltage supplied to terminal OUT can be amplified and supplied to terminal SD. Therefore, the operation during the restore operation is stabilized, and the reliability of the semiconductor device 100 can be improved.

[0082] <<Operation Example>> Next, an operation example of the semiconductor device 100 shown in Figure 1A will be explained using the drawings. Figures 9A, 9B, 10A, and 10B are timing charts for explaining the operation example of the semiconductor device 100. Figures 11 to 18 are circuit diagrams for explaining the operation example of the semiconductor device 100.

[0083] As a general rule, either potential H or potential L is supplied to each of the aforementioned terminals. In addition, potential H, potential L, or potential V1 is supplied to terminal BL and node Nd. Potential V1 is set to an intermediate potential between potential H and potential L. For example, if potential H is 1.2V and potential L is 0V, then potential V1 can be set to 0.6V.

[0084] In this embodiment, one terminal of the memory element ME, which is an MTJ element, is connected to the fixed layer PL, and the other terminal is connected to the free layer FL. That is, the memory element ME, which is an MTJ element, has the fixed layer PL connected to node Nd, and the free layer FL connected to terminal BL.

[0085] First, we will explain the backup operation performed before the power supply to the semiconductor device 100 is stopped due to power gating or the like. As an initial state, the potential of terminal IN (terminal Q) is H, and the potentials of terminals OUT (terminal SD), RE, RST, SDI, node Nd, and terminal BL are L.

[0086] <Backup Operation 1> An example of the operation in which the data held by the first memory circuit 110 is written (stored) to the second memory circuit 120 before the power supply is cut off is described. Here, we will describe the case where the first memory circuit 110 holds the data "1" and a potential H is output to terminal Q.

[0087] [Period T11] During period T11, a potential V1 is supplied to terminal BL (see Figures 9A and 11). Since the memory element ME is a resistive element, when the potential of terminal BL becomes potential V1, the potential of node Nd also becomes potential V1 via the memory element ME.

[0088] [Period T12] During period T12, a potential H is supplied to terminal BK, turning on transistor Tr1 (see Figures 9A and 12). Since a potential H is supplied to terminal IN, which is connected to terminal Q, a potential H is supplied to node Nd via the source and drain of transistor Tr1. Because the potential of terminal BL is potential V1, when the potential of node Nd becomes potential H, current flows from node Nd to terminal BL. That is, current flows from the fixed layer PL of the memory element ME to the free layer FL, so the resistance of the memory element ME decreases.

[0089] [Period T13] During period T13, a potential L is supplied to terminal BK, turning off transistor Tr1 (see Figure 9A). When transistor Tr1 is turned off, the potential of terminal BL is supplied to node Nd, and the potential of node Nd becomes potential V1. At this time, semiconductor device 100 is in the same state as in Figure 11. In this way, the data "1" can be written to the second memory circuit 120.

[0090] <Backup Operation 2> Next, we will explain the backup operation when the first memory circuit 110 is holding data "0" and a potential L is output to terminal Q. The backup operation when a potential L is output to terminal Q can be performed in the same way as backup operation 1, but the potential change of the second memory circuit 120 during period T12 is different. Therefore, we will explain the operation of the semiconductor device 100 during period T12.

[0091] [Period T12] After period T11, in period T12, a potential H is supplied to terminal BK, turning on transistor Tr1 (see Figures 9B and 13). Since a potential L is supplied to terminal IN, which is connected to terminal Q, a potential L is supplied to node Nd via the source and drain of transistor Tr1. Since the potential of terminal BL is potential V1, when the potential of node Nd becomes potential L, current flows from terminal BL to node Nd. That is, current flows from the free layer FL of memory element ME to the fixed layer PL, so the resistance of memory element ME increases. In this way, the data "0" can be written to the second memory circuit 120.

[0092] Next, we will describe the restore operation in which power is restored to the semiconductor device 100 and the data held by the second memory circuit 120 is supplied (written back) to the first memory circuit 110. As an initial state, terminal IN (terminal Q), terminal OUT (terminal SD), and node Nd are assumed to be in a floating state. Furthermore, it is assumed that a potential L is supplied to terminals RE, RST, SDI, and BL upon restoration of power.

[0093] <Restore Operation 1> First, we will explain the restore operation when the second memory circuit 120 is holding data "1".

[0094] [Period T21] During period T21, a potential H is supplied to terminal RST (see Figures 10A and 14). As a result, transistor Tr3 turns ON, and a potential L is supplied from terminal SDI to terminal OUT (terminal SD) via the source and drain of transistor Tr3.

[0095] [Period T22] Next, during period T22, a potential L is supplied to terminal RST, turning transistor Tr3 to the OFF state (see Figures 10A and 15). Also, a potential H is supplied to terminals RE and BL. When a potential H is supplied to terminal RE, transistor Tr2 turns ON, and current flows from terminal BL to terminal OUT (terminal SD) through the memory element ME and the source and drain of transistor Tr2. As a result, the potential of terminal OUT (terminal SD) rises from potential L to potential H.

[0096] In the first memory circuit 110, if a potential greater than or equal to the logical threshold voltage (for example, potential V1) is supplied to terminal SD, it is determined that potential H has been supplied, and if a potential less than the logical threshold voltage is supplied, it is determined that potential L has been supplied. When the data "1" is held in the second memory circuit 120, the resistance value of the memory element ME is low. For this reason, the potential of terminal OUT (terminal SD) rises faster than when the data "0" is held in the second memory circuit 120, and at the end of period T22, the potential of terminal OUT (terminal SD) becomes greater than or equal to the logical threshold voltage.

[0097] [Period T23] Next, during period T23, a potential L is supplied to terminal RE, turning transistor Tr2 to the OFF state (see Figures 10A and 16). Since a potential H is supplied to terminal BL, the potential of node Nd continues to rise until it reaches potential H. Also, when transistor Tr2 is turned OFF, the rise in potential at terminal OUT (terminal SD) stops.

[0098] The selection circuit 112 supplies the potential of terminal SD to terminal DF of the flip-flop circuit 111. Since the potential of terminal SD is greater than or equal to the logic threshold voltage, the flip-flop circuit 111 holds a potential of H, i.e., data "1", in synchronization with the clock signal. In addition, a potential of H is supplied to terminal Q, and a potential of L is supplied to terminal QB. In this way, the data "1" can be written back to the first memory circuit 110.

[0099] <Restore Operation 2> Next, we will explain the restore operation when the second memory circuit 120 holds the data "0". The restore operation when the second memory circuit 120 holds the data "0" can be performed in the same way as restore operation 1, but the potential changes of the first memory circuit 110 and the second memory circuit 120 during periods T22 and T23 are different. Therefore, we will explain the operation of the semiconductor device 100 during periods T22 and T23.

[0100] [Period T22] Following period T21, in period T22, a potential L is supplied to terminal RST, turning transistor Tr3 to the OFF state (see Figures 10B and 17). Also, a potential H is supplied to terminals RE and BL. When a potential H is supplied to terminal RE, transistor Tr2 turns ON, and current flows from terminal BL to terminal OUT (terminal SD) through the memory element ME and the source and drain of transistor Tr2. Therefore, the potential of terminal OUT (terminal SD) rises from potential L to potential H.

[0101] When the data "0" is held in the second memory circuit 120, the resistance value of the memory element ME is high. Therefore, the potential rise of terminal OUT (terminal SD) is slower than when the data "1" is held in the second memory circuit 120, and at the end of period T22, the potential of terminal OUT (terminal SD) falls below the logical threshold voltage.

[0102] [Period T23] Next, during period T23, a potential L is supplied to terminal RE, turning transistor Tr2 to the OFF state (see Figures 10B and 18). Since a potential H is supplied to terminal BL, the potential of node Nd continues to rise until it reaches potential H. Also, when transistor Tr2 is turned OFF, the rise in potential of terminal OUT (terminal SD) stops. If the data "0" is held in the second memory circuit 120, the rise in potential is slow, so the potential of terminal OUT (terminal SD) stops below the logic threshold voltage.

[0103] The selection circuit 112 supplies the potential of terminal SD to terminal DF of the flip-flop circuit 111. Since the potential of terminal SD is below the logic threshold voltage, the flip-flop circuit 111 holds a potential L, i.e., data "0", in synchronization with the clock signal. In addition, a potential L is supplied to terminal Q and a potential H is supplied to terminal QB. In this way, the data "0" can be written back to the first memory circuit 110.

[0104] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0105] (Embodiment 2) Figure 19 is a block diagram of a semiconductor device 300 to which the semiconductor device 100 described above is applied. The semiconductor device 300 shown in Figure 19 illustrates a state control unit 301, a CPU core 302, and a storage device 371. The CPU core 302 has a control circuit 361, a PC (program counter) 362, a register file 303A, a pipeline register 303B, a pipeline register 303C, a bus interface 363, and an arithmetic unit 304. The semiconductor device 100 according to one aspect of the present invention can be applied to general-purpose registers, pipeline registers 303B, pipeline registers 303C, etc. in the register file 303A. In the register file 303A, a general-purpose register is configured using a plurality of semiconductor devices 100, and a plurality of register banks are configured using a plurality of general-purpose registers.

[0106] The control circuit 361 has the function of decoding and executing instructions contained in a program such as an input application by comprehensively controlling the operation of the PC 362, register file 303A, pipeline register 303B, pipeline register 303C, arithmetic unit 304, storage device 371, and bus interface 363.

[0107] PC362 is a register that stores the address of the next instruction to be executed. The bus interface 363 functions as a data path between the CPU core 302 and various devices outside the CPU core 302 (such as the storage device 371).

[0108] The storage device 371 is equipped with a storage circuit that has the function of storing a program such as an application consisting of multiple instructions executed in the control circuit 361, data used for arithmetic processing in the arithmetic unit 304, and data obtained by arithmetic processing.

[0109] The register file 303A has multiple semiconductor devices 100 that constitute a general-purpose register, and can store data read from the control circuit 361, data obtained during the calculation process of the arithmetic unit 304, or data obtained as a result of the calculation process of the arithmetic unit 304.

[0110] The pipeline register 303B has the function of temporarily storing frequently used instructions (programs) from among the instructions (programs) used in the control circuit 361.

[0111] The pipeline register 303C can be used by the semiconductor device 100 as a register that has the function of temporarily storing data obtained during the calculation process of the arithmetic unit 304, or data obtained as a result of the calculation process of the arithmetic unit 304. It may also have the function of temporarily storing programs such as applications.

[0112] Furthermore, it is preferable that the semiconductor device 100 also includes pipeline registers 303B and 303C, in addition to the general-purpose registers in register file 303A. With this configuration, when power supply is resumed during power gating, not only the data in the general-purpose registers but also the task execution state of the semiconductor device 300 can be restored to the state before the power supply was interrupted. As a result, the continuity of task processing before and after the power supply interruption can be maintained, and power saving can be achieved without reducing computational performance.

[0113] As described above, the semiconductor device 300 of this embodiment can resume processing of the original task based on the backed-up data when power supply is restored, even if the power supply is interrupted due to power gating or the like. Since the data for resuming the task interrupted by power gating or the like is held in a register using the semiconductor device 100 within the CPU core, there is no need to access an external memory, such as a stack area of ​​SRAM or DRAM, to save or load data. Therefore, even when power supply is restored after power gating is completed, it can be done efficiently without causing time lags such as memory access.

[0114] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0115] (Embodiment 3) In this embodiment, we will describe an example of the cross-sectional configuration of the semiconductor device 100 described in the above embodiment.

[0116] <Example of Cross-Sectional Configuration of Semiconductor Device> Figure 20 is a schematic cross-sectional view showing a part of the semiconductor device 100. The semiconductor device 100 shown in Figure 20 shows a part of the first memory circuit 110 and a part of the second memory circuit 120 located above the first memory circuit 110.

[0117] The first memory circuit 110 can be constructed, for example, by providing circuit elements such as transistors and capacitive elements on a substrate 401. The substrate 401 can be a semiconductor substrate (for example, a crystalline substrate made of silicon or germanium). Other substrates that can be used include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films. In this embodiment, the first memory circuit 110 will be described using a semiconductor substrate containing silicon as the substrate on which it is formed.

[0118] By using a semiconductor substrate made of silicon as the substrate 401, the transistors constituting the first memory circuit 110 can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Since Si transistors have high field-effect mobility, they can carry a large on-current. This makes it possible to increase the operating speed of the first memory circuit 110.

[0119] Figure 20 illustrates the transistor 400 in the first memory circuit 110. By using a Si transistor, for example, for the transistor 400, the first memory circuit 110 can be configured as a CMOS circuit including a p-channel transistor and an n-channel transistor. Therefore, the flip-flop circuit 111 and the selection circuit 112 can be configured as CMOS circuits.

[0120] Furthermore, the stacking of the first memory circuit 110 and the second memory circuit 120 can be achieved by directly forming the second memory circuit 120 on top of the first memory circuit 110. As described in the above embodiment, it is preferable to use an OS transistor as the transistor constituting the second memory circuit 120. Since an OS transistor is a thin-film transistor, it can be easily provided on the first memory circuit 110 which includes a Si transistor.

[0121] Furthermore, it is also possible to form the p-channel transistors constituting the first memory circuit 110 with Si transistors and the n-channel transistors with OS transistors. By forming the n-channel transistors with OS transistors, the formation of n-channel Si transistors becomes unnecessary, thereby increasing the productivity of the semiconductor device. It is also possible to form some of the transistors constituting the second memory circuit 120 with Si transistors.

[0122] The transistor 400 provided on the substrate 401 has a conductive layer 431 that functions as a gate, insulating layers 461 and 411 that function as gate insulating films, a channel forming region 471 formed on a part of the substrate 401, and low-resistance regions 472a and 472b formed on a part of the substrate that function as a source region or drain region.

[0123] Furthermore, the transistor 400 shown in Figure 20 has an element isolation layer 402 outside the channel formation region 471, low resistance region 472a, and low resistance region 472b. The element isolation layer 402 can also be said to be provided to separate the multiple transistors 400 formed on the substrate 401. The element isolation layer 402 can be formed using, for example, the LOCOS (Local Oxidation of Silicon) method, the STI (Shallow Trench Isolation) method, or the mesa isolation method.

[0124] Figure 20 shows a schematic cross-sectional view of the transistor 400 in the channel length direction. Figure 21A shows a schematic cross-sectional view of the transistor 400 in the channel width direction. As shown in Figure 21A, the channel formation region 471 (part of the substrate 401) of the transistor 400 can have a convex shape. Furthermore, the side and top surfaces of the channel formation region 471 are covered by a conductive layer 431 via an insulating layer 461. The conductive layer 431 can be made of a material that adjusts the work function. Such a transistor is also called a fin-type transistor or single-fin type transistor because it utilizes the convex portion of the semiconductor substrate. Furthermore, it may have an insulating layer that is in contact with the upper part of the convex portion and functions as a mask for forming the convex portion. In addition, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, it is also possible to form a semiconductor film having a convex shape by processing an SOI substrate.

[0125] Furthermore, in Figure 21A, a conductive layer 136 is provided so as to be in contact with the conductive layer 431 and to fill the opening formed in the insulating layer 412. The conductive layer 136 will function as a contact plug or wiring, as will be described later.

[0126] Furthermore, as shown in Figure 21B, the transistor 400 can have multiple channel-forming regions 471 with a convex shape. Such transistors are also called multi-fin transistors because they have multiple convex portions on the semiconductor substrate. Single-fin transistors can have a higher on-current than multi-fin transistors.

[0127] Note that the transistors shown in Figures 20, 21A, and 21B are examples and are not limited to their structure; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0128] The semiconductor device 100 may be provided with a wiring layer having an interlayer insulating film, wiring, and a plug. Furthermore, multiple wiring layers may be provided depending on the design. In this specification, it is also possible to form the wiring and the plugs connected to the wiring as a single integrated unit. That is, there are cases where a portion of the conductive layer functions as wiring, and cases where a portion of the conductive layer functions as a plug.

[0129] For example, on the transistor 400, insulating layers 412, 481, and 413 are sequentially stacked as interlayer insulating films. A conductive layer 132 is embedded in the insulating layer 412. A conductive layer 133 is embedded in the insulating layers 481 and 413. The conductive layers 132 and 133 function as contact plugs or wiring.

[0130] Furthermore, the insulating layer, which functions as an interlayer insulating film, preferably functions as a planarizing film that covers the uneven shape beneath it. For example, the flatness of the upper surface of the insulating layer 412 can be improved by a planarizing treatment using chemical mechanical polishing (CMP). By improving the flatness of the insulating layer 412, the coverage of the layer formed on the insulating layer 412 can be improved.

[0131] A wiring layer can be provided on the insulating layer 413 and the conductive layer 133. For example, in Figure 20, insulating layers 482, 414, 415, and 416 are sequentially laminated on the insulating layer 413 and the conductive layer 133. Furthermore, a conductive layer 134 is formed on insulating layers 482, 414, and 415. The conductive layer 134 functions as a contact plug or wiring.

[0132] An insulating layer 211 is provided on the insulating layer 416. An insulating layer 281 is provided on the insulating layer 211. An insulating layer 212 is provided on the insulating layer 281. It is preferable that contact plugs or wiring for connecting to circuit elements included in the second memory circuit 120 are embedded in the insulating layer 416, insulating layer 211, and insulating layer 281.

[0133] For example, conductive layers 132, 133, 134, and 136 can be made from materials applicable to conductive layers 232 to 237, which will be described later.

[0134] In Figure 20, each of the transistors Tr1, Tr2, and Tr3 (transistor Tr3 is not shown in Figure 20) included in the second memory circuit 120 is formed above the insulating layer 281. An insulating layer 284 is formed above transistors Tr1, Tr2, and Tr3. An insulating layer 215 is formed on top of the insulating layer 284. The memory element ME is formed on a conductive layer 235 embedded in the insulating layer 215.

[0135] Furthermore, it is preferable that the insulating layers 481, 482, 281, and 284 shown in Figure 20 function as barrier insulating films that suppress the permeation of impurities such as water and hydrogen. Therefore, the insulating layers 481, 482, 281, and 284 are designed to suppress the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N ２ O, NO, or NO ２ It is preferable to use an insulating material that has the function of suppressing the diffusion of impurities such as ) and copper atoms (i.e., the above impurities do not easily permeate). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (for example, oxygen atoms and oxygen molecules, or both) (i.e., the above oxygen does not easily permeate). For materials that can be applied to insulating layer 481, insulating layer 482, insulating layer 281 and insulating layer 284, refer to the description of the insulating layer of the transistor constituent materials.

[0136] Furthermore, conductive layers 234 and 236 are connected to either the source electrode or the drain electrode of transistor Tr1. The other source electrode or drain electrode of transistor Tr1 is connected to a region of conductive layer 235 that functions as the first terminal of the memory element ME. Conductive layers 234 and 236 each function as contact plugs. In addition, a portion of conductive layer 233 functions as the gate electrode of transistor Tr1.

[0137] Furthermore, one of the source electrode or drain electrode of transistor Tr2 is connected to a region of the conductive layer 235 that functions as the first terminal of the memory element ME.

[0138] Furthermore, the gate electrodes of transistors Tr1 and Tr2, as an example, extend along the front-to-depth direction in Figure 20 as a conductive layer 233.

[0139] The conductive layer 234 is provided so as to penetrate and embed the insulating layers 213, 283, 214, and 284, which will be described later. In addition, an insulating layer 215 and a conductive layer 235 are provided on the conductive layer 234 and the insulating layer 284. On the conductive layer 235, a fixed layer PL, an insulating layer TI, and a free layer FL are provided in order. A conductive layer 224 is provided on the free layer FL.

[0140] The conductive layer 224 is provided as a hard mask for forming the fixed layer PL, the insulating layer TI, and the free layer FL. For example, the conductive layer 224 can be made of a material that can be used for the conductive layer 232. The conductive layer 235 can function as the first terminal of the memory element ME. The conductive layer 224 can function as the second terminal of the memory element ME.

[0141] Furthermore, insulating layers 285 are provided on the sides of the fixed layer PL, insulating layer TI, free layer FL, and conductive layer 224, on the conductive layer 235, and on the insulating layer 215. In addition, an insulating layer 216 is provided on the insulating layer 285.

[0142] Furthermore, the conductive layer 236 is provided so as to penetrate the insulating layer 285 and the insulating layer 216. In addition, an insulating layer 217 is provided on the insulating layer 216. Furthermore, the conductive layer 237 is provided on the fixed layer PL. Furthermore, the conductive layer 237 is provided so as to be embedded in the insulating layer 217. Furthermore, an insulating layer 286 is provided on the insulating layer 217 and on the conductive layer 237. Furthermore, an insulating layer 287 is provided on the insulating layer 286.

[0143] Furthermore, insulating layers 215 to 217 can be made of materials applicable to insulating layer 213 or insulating layer 214, as described later. Insulating layers 284 to 287 can be made of materials applicable to insulating layer 281 or insulating layer 283, as described later. Conductive layers 235 to 237 can be made of materials applicable to conductive layer 232, conductive layer 233, or conductive layer 234, as described later.

[0144] Furthermore, if a back gate is provided for one or more of the multiple transistors in the second memory circuit 120, it is preferable not to provide a conductive layer near the back gate in order to avoid the formation of parasitic capacitance with the back gate.

[0145] Preferably, each of the multiple transistors in the second memory circuit 120 is an OS transistor in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Since oxide semiconductors have a band gap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the second memory circuit 120 can be reduced. Therefore, the power consumption of the semiconductor device 100 can be reduced.

[0146] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, threshold voltage and off-current remain virtually unchanged even in high-temperature environments. Specifically, characteristic fluctuations are minimal even in environments between room temperature (e.g., 25°C) and 200°C. Additionally, the on-current does not decrease significantly even in high-temperature environments. For these reasons, semiconductor devices using OS transistors operate stably and offer high reliability even in high-temperature environments.

[0147] In particular, it is preferable to use indium oxide for the oxide semiconductor. By using transistors (IO transistors) in which indium oxide is used for the semiconductor layer where the channel is formed for each of transistors Tr1 to Tr3, it is possible to create transistors with low off-current and high on-current. This can sometimes lead to the realization of a semiconductor device that combines high reliability and fast operating speed.

[0148] <<Transistor Configuration Example 1>> As an example of a transistor configuration applicable to transistors Tr1, Tr2, and Tr3, we will describe a transistor configuration example called a GL structure. Transistor 200A shown in Figures 22A to 22C can be applied, for example, to transistors Tr1 and Tr2 in Figure 20.

[0149] Figure 22A shows a schematic plan view of transistor 200A. Figure 22B is a schematic cross-sectional view of the area indicated by the dashed-dotted line A1-A2 in Figure 22A. Figure 22C is a schematic cross-sectional view of the area indicated by the dashed-dotted line A3-A4 in Figure 22A. Note that Figure 22B shows a schematic cross-sectional view of transistor 200A in the channel length direction, and Figure 22C shows a schematic cross-sectional view of transistor 200A in the channel width direction.

[0150] The transistor 200A shown in Figures 22A to 22C includes a semiconductor layer 251 (semiconductor layer 251a and semiconductor layer 251b), a conductive layer 231 (conductive layer 231a and conductive layer 231b), a conductive layer 232 (conductive layer 232a and conductive layer 232b), a conductive layer 233 (conductive layer 233a and conductive layer 233b), and insulating layers 261 to 264. Note that the transistor 200A may not have all of the above-mentioned components.

[0151] The conductive layer 231 functions as the back gate electrode of the transistor 200A, but it is also possible to have a configuration without the conductive layer 231, as shown in transistors Tr1 and Tr2 in Figure 20.

[0152] In Figures 22A to 22C, an insulating layer 211 is provided on a substrate (not shown), an insulating layer 281 is provided on the insulating layer 211, and an insulating layer 212 and a conductive layer 231 are provided on the insulating layer 281.

[0153] The conductive layer 231 is preferably embedded in the insulating layer 212. Specifically, the conductive layer 231a is preferably provided in contact with the bottom and inner wall of an opening provided in the insulating layer 212. Furthermore, the conductive layer 231b is preferably provided in contact with the conductive layer 231a and adjacent to the bottom and inner wall of the opening. In Figures 22A to 22C, the position of the upper surface of the conductive layer 231b is approximately the same as the upper end of the conductive layer 231a (the highest position when viewed from the substrate surface) and the upper surface of the insulating layer 212.

[0154] The insulating layer 212 preferably functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 412. Therefore, it is preferable to use a material for the insulating layer 212 that functions as a planarizing film, similar to the insulating layer 412.

[0155] Furthermore, it is preferable to use a material with a low dielectric constant for the insulating layer 212. By using a material with a low dielectric constant, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide nitride, or silicon nitride can be used for the insulating layer 212. Alternatively, for example, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, or porous silicon oxide can be used for the insulating layer 212. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or porous silicon oxide are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating. Alternatively, for example, resin can be used for the insulating layer 212. Furthermore, the materials used for the insulating layer 212 can be appropriately combined from the insulating materials described above.

[0156] Furthermore, an insulating layer 261 is provided on the insulating layer 212 and the conductive layer 231, and an insulating layer 262 is provided on the insulating layer 261. Furthermore, an insulating layer 263 is provided on the insulating layer 262. Furthermore, a semiconductor layer 251a and a semiconductor layer 251b are provided sequentially on the insulating layer 263. Furthermore, the conductive layer 232a and the conductive layer 232b are arranged on the semiconductor layer 251b, spaced apart from each other.

[0157] Furthermore, an insulating layer 282 is provided on top of the insulating layer 262, conductive layer 232a, and conductive layer 232b. The insulating layer 282 has regions that are in contact with the conductive layer 232a, conductive layer 232b, semiconductor layer 251a, semiconductor layer 251b, and insulating layer 263. In addition, an insulating layer 213 is provided on top of the insulating layer 282. The insulating layer 213 and the insulating layer 282 have openings that reach the semiconductor layer 251b in the region between the conductive layer 232a and conductive layer 232b.

[0158] Furthermore, an insulating layer 264 is provided in contact with the bottom and inner wall of the opening. The insulating layer 264 has a region in contact with the semiconductor layer 251b, a region in contact with the conductive layer 232a, a region in contact with the conductive layer 232b, a region in contact with the insulating layer 282, and a region in contact with the insulating layer 213. In addition, a conductive layer 233a in contact with the insulating layer 264 and a conductive layer 233b in contact with the conductive layer 233a are provided in the opening. Here, as shown in Figures 22B and 22C, it is preferable that the upper end of the insulating layer 264 and the upper end of the conductive layer 233 substantially coincide with the upper surface of the insulating layer 213.

[0159] Furthermore, the conductive layer 231, the semiconductor layer 251, and the conductive layer 233 have overlapping regions. For example, the conductive layer 233 has a region that functions as a gate electrode, and the conductive layer 231 has a region that functions as a back gate electrode. In this case, a part of the insulating layer 264 functions as a gate insulating film, and a part of the insulating layer 261, insulating layer 262, and insulating layer 263 each functions as a gate insulating film.

[0160] Furthermore, an insulating layer 283 is formed on the insulating layer 213, insulating layer 264, and conductive layer 233, and an insulating layer 214 is provided on the insulating layer 283.

[0161] At the interface between the semiconductor layer 251b and the conductive layer 232a, and in its vicinity, a low-resistance region 271a may be formed. Similarly, at the interface between the semiconductor layer 251b and the conductive layer 232b, and in its vicinity, a low-resistance region 271b may be formed. In this case, region 271a functions as either a source region or a drain region, and region 271b functions as either a source region or a drain region. Therefore, the conductive layer 232a functions as either a source electrode or a drain electrode, and the conductive layer 232b functions as either a source electrode or a drain electrode. Furthermore, the region sandwiched between region 271a and region 271b functions as a channel-forming region.

[0162] In other words, the position of the channel formation region of the semiconductor layer 251 is determined self-aligningly by the formation of an opening that reaches the semiconductor layer 251b as described above. Therefore, the conductive layer 233 can be formed without providing a positioning margin, which reduces the area occupied by the transistor 200A. This allows for a higher integration density of the semiconductor device.

[0163] It is preferable that a conductive layer 234 (conductive layer 234a and conductive layer 234b) is provided, which is connected to the transistor 200A and functions as a plug. Figure 22B shows the insulating layer 214, insulating layer 283, and conductive layer 234a penetrating the insulating layer 213 and reaching the conductive layer 232a. Also in Figure 22B, the conductive layer 234b penetrating the insulating layer 214, insulating layer 283, and insulating layer 213 and reaching the conductive layer 232b.

[0164] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing the diffusion of oxygen as the conductive layer 233a. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b.

[0165] It is preferable to use a conductive material for the conductive layer 233a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen. Furthermore, by having the function of suppressing the diffusion of oxygen in the conductive layer 233a, it is possible to suppress the oxidation of the conductive layer 233b by oxygen contained in the insulating layer 213, etc., which reduces the conductivity. As a conductive material that has the function of suppressing the diffusion of oxygen, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0166] Furthermore, it is preferable to use a conductive layer with high conductivity for the conductive layer 233b. For example, the conductive layer 233b can be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductive layer 233b can also be made of a laminated structure. For example, it can be made of a laminated structure of titanium or titanium nitride and the above conductive material.

[0167] The conductive layer 231 should be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Figure 22C, it is preferable that the conductive layer 231 extends as wiring even in the region outside the edge that intersects with the channel width direction of the semiconductor layer 251. That is, it is preferable that the conductive layer 231 and the conductive layer 233 are superimposed on the outside of the side surface in the channel width direction of the semiconductor layer 251, with an insulating layer in between.

[0168] Furthermore, as shown in Figure 22C, the conductive layer 233 is positioned to cover the side surface of the semiconductor layer 251 in the channel formation region of the semiconductor layer 251. This makes it easier to apply the electric field of the conductive layer 233, which functions as the first gate electrode, to the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. Therefore, the on-current of the transistor 200A can be increased and the frequency characteristics can be improved.

[0169] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as the interlayer insulating film, parasitic capacitance between wirings can be reduced. Therefore, as a material with a low dielectric constant, the insulating layer 213 can be a material that can be used for the insulating layer 212.

[0170] For conductive layers 232a and 232b, it is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress a decrease in the conductivity of conductive layers 232a and 232b. When conductive materials containing metal and nitrogen are used as conductive layers 232a and 232b, conductive layers 232a and 232b become conductive layers having at least a metal and nitrogen. For example, as materials to be applied to conductive layers 232a and 232b, conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen can be selected from the materials that can be applied to conductive layers 233a and 233b respectively as described above.

[0171] <<Transistor Configuration Example 2>> As another example of a transistor configuration applicable to transistors Tr1, Tr2, and Tr3, a configuration example of a vertical channel transistor will be described.

[0172] Figures 23A to 23C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and drain electrode are located at different heights. That is, the channel length direction can be said to have a component in the height direction (vertical direction).

[0173] Vertical channel transistors are sometimes called VFETs (Vertical Field Effect Transistors), vertical transistors, or vertical channel transistors. In this specification, in vertical channel transistors, the electrode located at the bottom of the source electrode or drain electrode may be referred to as the "lower electrode," and the electrode located at the top may be referred to as the "upper electrode."

[0174] In particular, Figure 23A shows a schematic plan view of an example of a vertical channel type transistor, transistor 200B, while Figures 23B and 23C show schematic cross-sectional views of transistor 200B. Figure 23B is a schematic cross-sectional view of the area indicated by the dashed-dotted line A1-A2 in Figure 23A, and Figure 23C is a schematic cross-sectional view of the area indicated by the dashed-dotted line A3-A4 in Figure 23A. Figure 24 shows a schematic perspective view of transistor 200B and its surrounding wiring.

[0175] The transistor 200B shown in Figures 23A to 23C and Figure 24 includes, as an example, a conductive layer 331 that functions as wiring or an electrode, a conductive layer 332 that functions as wiring or an electrode, a semiconductor layer 351 that includes a channel formation region of the transistor 200B, an insulating layer 352 that functions as a gate insulating film of the transistor 200B, a conductive layer 333 that functions as the gate of the transistor 200B, and a conductive layer 334 that functions as wiring.

[0176] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer insulating film. The conductive layer 331 also extends in the Y direction.

[0177] For example, the conductive layer 331 can be a conductive layer applicable to transistors Tr1, Tr2, etc., as described above. The same applies to conductive layers 332 to 334, which will be described later.

[0178] An insulating layer 312 and a conductive layer 332, which function as interlayer insulating films, are formed sequentially on the insulating layer 311 and the conductive layer 331, respectively. The conductive layer 332 extends in the X direction.

[0179] Furthermore, the insulating layer 312 and the conductive layer 332 have openings that reach the conductive layer 331 in the region overlapping with the conductive layer 331. A semiconductor layer 351 is formed at the bottom and inner wall of the opening. In other words, the semiconductor layer 351 has a region in contact with the conductive layer 331 at the opening, a region in contact with the side surface of the insulating layer 312, and a region in contact with the side surface of the conductive layer 332. The semiconductor layer 351 is also formed on a part of the upper surface of the conductive layer 332. The insulating layer 352 has regions in contact with the surface of the semiconductor layer 351 both inside and outside the opening. The insulating layer 352 also has regions in contact with the conductive layer 332. A conductive layer 333 is formed to fill the opening. The conductive layer 333 has a region in contact with the surface of the insulating layer 352 at the opening. The conductive layer 333 also has a region in contact with the insulating layer 352 outside the opening.

[0180] Furthermore, an insulating layer 313, which functions as an interlayer insulating film, is formed on the insulating layer 352 and the conductive layer 333. In addition, an opening that reaches the conductive layer 333 is formed in the region that overlaps with the conductive layer 333. A conductive layer 334 extending in the Y direction is formed on the insulating layer 313. A part of the conductive layer 334 is embedded in the opening. The conductive layer 334 can be formed on the upper surface of the insulating layer 313. Furthermore, an insulating layer 314, which functions as an interlayer insulating film, is formed on both the insulating layer 313 and the conductive layer 334.

[0181] For insulating layers 311 to 314, it is preferable to use an insulating material with a low relative permittivity. By using an insulating material with a low relative permittivity as the interlayer insulating film, parasitic capacitance occurring between wiring can be reduced. For this reason, each of the insulating layers 311 to 314 can be made of a material that is applicable to insulating layer 212 or insulating layer 213.

[0182] Furthermore, since the insulating layer 352 functions as a gate insulating film, the insulating layer 352 can be made of a material that can be used for the insulating layer 264, for example.

[0183] A portion of the conductive layer 331 functions as either the source electrode or the drain electrode in the transistor 200B. A portion of the conductive layer 332 functions as the other source electrode or drain electrode in the transistor 200B. Furthermore, a portion or all of the conductive layer 333 functions as the gate electrode in the transistor 200B.

[0184] As described above, by forming an insulating layer, a conductive layer, and a semiconductor layer, a vertical channel transistor can be formed in which the channel length has a component in the height direction (vertical direction). Furthermore, the channel length of transistor 200B depends on the thickness of the insulating layer 312; the thinner the insulating layer 312, the shorter the channel length, and thus the on-current of transistor 200B can be increased. On the other hand, the thicker the insulating layer 312, the longer the channel length, and thus the off-current of transistor 200B can be decreased.

[0185] Furthermore, since the wirings (conductive layer 331, conductive layer 332, conductive layer 334) connected to the vertical channel transistor are provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows the driving frequency of transistor 200B to be increased, and the driving speed of semiconductor device 100 and the like can be increased.

[0186] <Transistor Components> Next, we will explain the components that can be used in transistor 200 (transistor 200A and transistor 200B).

[0187] [Substrate] When a transistor is mounted on a substrate, there are no major restrictions on the material used for the substrate. The material used for the substrate is determined according to the purpose, taking into consideration factors such as the presence or absence of light transmission and heat resistance sufficient to withstand heat treatment. For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As insulating substrates, for example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, sapphire substrates, and stabilized zirconia substrates (such as yttria-stabilized zirconia substrates) can be used. In addition, semiconductor substrates, flexible substrates, and resin substrates can also be used as substrates.

[0188] Examples of semiconductor substrates include silicon substrates, germanium substrates, and compound semiconductor substrates made from materials such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. In addition, the semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0189] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate.

[0190] Examples of materials that can be used for flexible substrates or resin substrates include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyethersulfone (PES), polyamide (nylon, aramid, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofiber.

[0191] By using the above-mentioned material as a substrate, a lightweight semiconductor device can be provided. Furthermore, by using the above-mentioned material as a substrate, a semiconductor device that is resistant to impact can be provided. Furthermore, by using the above-mentioned material as a substrate, a semiconductor device that is less prone to damage can be provided. It is also possible to use these substrates on which elements are mounted. Elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0192] [Insulating Layers] Insulating layers (insulating layers 211, 281, 212, 261, 262, 263, 282, 213, 283, 214, 264, 311, 312, 352, 313, 314, etc.) are each made of inorganic insulating films. Examples of inorganic insulating films include oxide insulating films, nitride insulating films, oxidoxide-nitriding insulating films, and nitride-oxidation insulating films. Examples of oxide insulating films include silicon oxide films, aluminum oxide films, magnesium oxide films, gallium oxide films, germanium oxide films, yttrium oxide films, zirconium oxide films, lanthanum oxide films, neodymium oxide films, hafnium oxide films, tantalum oxide films, cerium oxide films, zinc gallium oxide films, and hafnium aluminate films. Examples of nitride insulating films include silicon nitride films and aluminum nitride films. Examples of oxidative nitride insulating films include silicon oxidative nitride films, aluminum oxidative nitride films, gallium oxidative nitride films, yttrium oxidative nitride films, and hafnium oxidative nitride films. Examples of nitride oxide insulating films include silicon oxidative nitride films and aluminum oxidative nitride films. Furthermore, organic insulating films can also be used for the insulating layer of semiconductor devices.

[0193] In this specification, "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content. The content of each element can be measured using, for example, the Rutherford backscattering spectroscopy (RBS).

[0194] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using high-k materials for insulating layers that function as gate insulating layers, such as insulating layer 264 and insulating layer 352, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. Furthermore, it becomes possible to thin the equivalent oxide film thickness (EOT) of the gate insulating layer. On the other hand, by using materials with a low relative permittivity for insulating layers that function as interlayer films, parasitic capacitance between wiring can be reduced. Therefore, it is crucial to select materials according to the function of the insulating layer. It should be noted that materials with a low relative permittivity also have high dielectric strength.

[0195] Examples of materials with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0196] Examples of materials with low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxide-nitride, and silicon nitride-oxide, as well as resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with low dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Also, for example, silicon oxide with voids is another example. These silicon oxides may contain nitrogen.

[0197] [Conductive Layers] For the conductive layers (conductive layers 231, 232, 233, 234, 331, 332, 333, 334, etc.), it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy composed of the aforementioned metal elements, or an alloy combining the aforementioned metal elements. As alloys composed of the aforementioned metal elements, it is possible to use nitrides of the alloy or oxides of the alloy. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, it is possible to use semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, and silicides such as nickel silicide.

[0198] Furthermore, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are resistant to oxidation, conductive materials that have the function of suppressing oxygen diffusion, or materials that maintain conductivity even when absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (also known as ITO), indium tin oxide containing titanium oxide, silicon-added indium tin oxide (also known as ITSO), indium zinc oxide (also known as IZO®), and indium zinc oxide containing tungsten oxide. In this specification, a conductive layer formed using an oxygen-containing conductive material may be referred to as an oxide conductive layer.

[0199] Conductive materials mainly composed of tungsten, copper, or aluminum are preferred because they have high conductivity.

[0200] Furthermore, it is possible to use multiple conductive layers formed from the above materials in a laminated structure. For example, it is possible to create a laminated structure by combining the aforementioned metal element material with an oxygen-containing conductive material. It is also possible to create a laminated structure by combining the aforementioned metal element material with a nitrogen-containing conductive material. Furthermore, it is also possible to create a laminated structure by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0201] For example, when using an oxide semiconductor, which is a type of metal oxide, for the semiconductor layer 251 of transistor 200A or the semiconductor layer 351 of transistor 200B, it is preferable to use a laminated structure that combines the aforementioned metal element material with an oxygen-containing conductive material for conductive layers that function as gate electrodes, such as conductive layer 233 and conductive layer 333. In this case, it is preferable to provide the oxygen-containing conductive material on the semiconductor layer side. By providing the oxygen-containing conductive material on the semiconductor layer side, oxygen detached from the conductive material is more easily supplied to the channel formation region of the semiconductor layer.

[0202] When using an oxide semiconductor, which is a type of metal oxide, as the semiconductor layer 251 or semiconductor layer 351, the conductive layers 232, 331, and 332 are conductive layers that are in contact with the semiconductor layer 251 or semiconductor layer 351. Therefore, it is preferable to use conductive materials that are resistant to oxidation, conductive materials that maintain low electrical resistance even when oxidized, conductive metal oxides (also called oxide conductors), or conductive materials that have the function of suppressing oxygen diffusion. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This makes it possible to suppress the decrease in the conductivity of conductive layers 232, 331, and 332.

[0203] By using conductive materials containing oxygen as conductive layers 232, 331, and 332, conductivity can be maintained even if conductive layers 232, 331, and 332 absorb oxygen. For example, even when an insulating layer containing excess oxygen is used as an insulating layer in contact with conductive layers 232, 331, and 332, conductivity can be maintained, making it suitable. Examples of conductive layers 232, 331, and 332 include ITO, ITSO, IZO (registered trademark), etc.

[0204] [Semiconductor Layer] As semiconductor layers (semiconductor layer 251, semiconductor layer 351, etc.), single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, or amorphous semiconductors can be used individually or in combination. As semiconductor materials, for example, silicon and germanium can be used. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, and nitride semiconductors can also be used. As compound semiconductors, organic substances with semiconductor properties or metal oxides with semiconductor properties (also called oxide semiconductors) can be used. It is also possible to include impurities as dopants in these semiconductor materials.

[0205] Furthermore, semiconductors composed of single elements or compound semiconductors can be used as the semiconductor layer. Examples of semiconductors composed of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Oxide semiconductors are also a type of compound semiconductor. It is also possible to include impurities as dopants in these semiconductor materials.

[0206] When silicon is used as a semiconductor layer, examples of silicon that can be used for the semiconductor layer include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. As an example of polycrystalline silicon, low-temperature polysilicon (LTPS) is used.

[0207] It is also possible to use a two-dimensional material that functions as a semiconductor as the semiconductor layer of a transistor. Two-dimensional materials, also called layered materials, are a general term for a group of materials that have a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity as the semiconductor layer, it is possible to provide a transistor with a large on-current.

[0208] Examples of the layered substance include graphene, silicene, and chalcogenides. A chalcogenide is a compound containing chalcogen (an element belonging to group 16). Examples of chalcogenides include transition metal chalcogenides, group 13 chalcogenides, and the like. Specific examples of transition metal chalcogenides applicable as a semiconductor layer of a transistor include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten telluride (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ), and the like.

[0209] When an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, the band gap of the metal oxide is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide having a larger band gap than silicon for the semiconductor layer, the off-state current of a transistor can be significantly reduced. Since an OS transistor has a small off-state current, the power consumption of a semiconductor device can be reduced.

[0210] The metal oxide that can be used in the semiconductor layer of an OS transistor preferably contains at least indium (In). Furthermore, it is preferable that the metal oxide contains at least one of indium (In) or zinc (Zn). Moreover, it is preferable that the metal oxide contains two or three elements selected from indium, element M, and zinc. Element M is a metal or metalloid element with a high bond energy with oxygen, for example, a metal or metalloid element with a higher bond energy with oxygen than indium.

[0211] Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0212] For example, indium oxide (In oxide, indium oxide) can be used as a metal oxide for the semiconductor layer of an OS transistor. Other metal oxides include zinc oxide (Zn oxide, zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as "GZO"), aluminum zinc oxide (Al-Zn oxide, also written as "AZO"), and indium Aluminum zinc oxide (In-Al-Zn oxide, also written as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as "IGZTO"), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as "IGAZO" or "IAGZO"), etc., can be used. Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0213] Examples of crystal structures for metal oxides that function as semiconductors include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), single crystal, and polycrystalline.

[0214] Furthermore, by increasing the ratio of zinc atoms to the sum of the atoms of other metal elements in a metal oxide that functions as a semiconductor, a highly crystalline metal oxide can be obtained, suppressing the diffusion of impurities within the metal oxide. Consequently, fluctuations in the electrical properties of the transistor can be suppressed, improving reliability.

[0215] Furthermore, by increasing the ratio of element M atoms to the sum of the atoms of metal elements among the main constituent elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, resulting in a transistor with low off-current. In addition, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0216] The field-effect mobility of a transistor can be increased by increasing the ratio of indium atoms to the sum of the total number of atoms of all metal elements contained in the metal oxide. Typically, using single-crystal or polycrystalline indium oxide in the semiconductor layer can significantly increase the field-effect mobility of a transistor. Furthermore, transistors using single-crystal or polycrystalline indium oxide in the semiconductor layer can achieve good frequency characteristics.

[0217] The formation of metal oxides is preferably done by sputtering or ALD. When metal oxides are formed by sputtering, films with high crystallinity or high film density can be formed. When metal oxides are formed using the ALD method, atoms can be deposited layer by layer, resulting in film formation with fewer defects such as pinholes, excellent coverage, and the ability to form films at low temperatures. Furthermore, it is preferable to perform an impurity removal treatment after the formation of the metal oxide to remove impurities (typically water, hydrogen, carbon, nitrogen, etc.) from the metal oxide film. Examples of impurity removal treatments include plasma treatment and heat treatment. Microwave plasma treatment is an example of plasma treatment.

[0218] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Microwave plasma processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example. Microwave plasma processing can also be called microwave-excited high-density plasma processing.

[0219] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0220] (Embodiment 4) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0221] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0222] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0223] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0224] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0225] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm−３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0226] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0227] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0228] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0229] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0230] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0231] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0232] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0233] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0234] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0235] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0236] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0237] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V・s) or more is possible.

[0238] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0239] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0240] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0241] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰−２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0242] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0243] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0244] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0245] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0246] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified type structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0247] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0248] (Embodiment 5) This embodiment describes electronic components, electronic devices, etc., that can use the semiconductor device described in the above embodiment.

[0249] One embodiment of the present invention, the semiconductor device 100, can be used as a storage device such as a register, cache memory, or external storage device. By using one embodiment of the present invention in various electronic devices, it is possible to miniaturize and reduce the power consumption of the electronic devices. Furthermore, because one embodiment of the present invention has low power consumption, it generates little heat. Therefore, the adverse effects of heat generation on the semiconductor device itself, peripheral circuits, and modules can be reduced. In addition, by using one embodiment of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0250] <Electronic Components> Figure 25A shows a perspective view of a substrate (mounted substrate 704) on which electronic components 700 are mounted. The electronic component 700 shown in Figure 25A has a semiconductor device 710 within a mold 711. As the semiconductor device 710, a semiconductor device including a semiconductor device 100 according to one embodiment of the present invention can be used.

[0251] Figure 25A omits some details to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is connected to an electrode pad 713, and the electrode pad 713 is connected to the semiconductor device 710 via a wire 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. Multiple such electronic components are combined and connected on the printed circuit board 702 to complete the mounting board 704.

[0252] Next, a perspective view of the electronic component 730 is shown in Figure 25B. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 720 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0253] Electronic component 730 shows an example in which the semiconductor device 710 is used as a high-bandwidth memory (HBM). Furthermore, in electronic component 730, an integrated circuit such as a CPU, GPU, or FPGA (Field Programmable Gate Array) is used as the semiconductor device 720. A semiconductor device 100 according to one aspect of the present invention can be used in the registers, cache memory, etc., of this integrated circuit.

[0254] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0255] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also has the function of connecting integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0256] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0257] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0258] Furthermore, it is preferable to provide a heat sink (heat dissipation plate) on top of the electronic component 730. Providing a heat sink stabilizes the operation of the electronic component and improves its reliability. When providing a heat sink, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the semiconductor device 710 and the semiconductor device 720.

[0259] To mount the electronic component 730 onto another substrate, electrodes 733 can be provided at the bottom of the package substrate 732. Figure 25B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. It is also possible to form the electrodes 733 with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0260] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0261] <Electronic Devices> A semiconductor device according to one aspect of the present invention can be applied to various electronic devices (for example, information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related equipment, etc. Here, "computer" includes tablet computers, notebook computers, desktop computers, as well as large computers such as server systems.

[0262] An example of an electronic device having a semiconductor device according to one aspect of the present invention will be described. Figures 26A to 26J and 27A to 27C illustrate how the electronic component 700 or electronic component 730 having the semiconductor device is included in each electronic device.

[0263] [Mobile Phone] The information terminal 5500 shown in Figure 26A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0264] By applying a semiconductor device according to one aspect of the present invention to the information terminal 5500, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for its operation can be quickly written back to the circuit.

[0265] [Wearable Terminal] Figure 26B also shows an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, a band 5905, and the like.

[0266] By applying a semiconductor device according to one aspect of the present invention to the information terminal 5500, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for its operation can be quickly written back to the circuit.

[0267] [Information Terminal] Figure 26C also shows a desktop information terminal 5300. The desktop information terminal 5300 has an information terminal body 5301, a display unit 5302, and a keyboard 5303.

[0268] Similar to the information terminal 5500 described above, by applying a semiconductor device according to one aspect of the present invention to the desktop information terminal 5300, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for its operation can be quickly written back to the circuit.

[0269] In the above, smartphones, wearable devices, and desktop information terminals were used as examples of electronic devices and illustrated in Figures 26A to (C), respectively. However, other information terminals besides smartphones, wearable devices, and desktop information terminals can also be applied. Examples of other information terminals besides smartphones, wearable devices, and desktop information terminals include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0270] [Electrical Appliances] A semiconductor device 100 according to one aspect of the present invention can be used in electrical appliances. Figure 26D shows an electric refrigerator 5800 as an example of an electrical appliance. The electric refrigerator 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator 5800 is an IoT-compatible electric refrigerator.

[0271] A semiconductor device according to one aspect of the present invention can be applied to the electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal or the like via the internet.

[0272] In the electric refrigerator-freezer 5800, power consumption can also be reduced by power gating. By applying a semiconductor device according to one aspect of the present invention to the electric refrigerator-freezer 5800, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when the power supply to that circuit is resumed, the data necessary for its operation can be quickly written back to that circuit.

[0273] In this embodiment, an electric refrigerator was described as an example of an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment. The semiconductor device 100 according to one aspect of the present invention can also be applied to these electrical appliances.

[0274] [Game Console] Figure 26E also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a housing 5201, a display unit 5202, buttons 5203, etc.

[0275] Furthermore, Figure 26F illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 26F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Moreover, the controller 7522 is not limited to the shape shown in Figure 26F, and its shape can be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles can be designed to operate without controllers, instead incorporating cameras, depth sensors, microphones, and other features, allowing players to control the game using gestures or voice commands.

[0276] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0277] By applying a semiconductor device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is resumed, the data necessary for the operation of that circuit can be quickly written back. In addition, since power gating can reduce heat generation from the circuit, the impact of heat on the circuit itself, surrounding circuits, and modules can be reduced.

[0278] It should be noted that the electronic devices in one aspect of the present invention are not limited to portable game consoles and home console game consoles. Examples of electronic devices in one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0279] [Mobile Devices] One aspect of the present invention can be applied to a mobile device, such as an automobile, and the area around the driver's seat of an automobile.

[0280] Figure 26G shows an example of a mobile device, an automobile 5700.

[0281] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. Furthermore, a display device for showing this information can be installed around the driver's seat.

[0282] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. That is, by displaying images from an imaging device installed on the outside of the automobile 5700 on the display device, blind spots can be compensated for and safety can be enhanced. The display device can also be configured to display temporary information such as road guidance and hazard predictions. It can also be configured to store images from a driving recorder installed in the automobile 5700.

[0283] A semiconductor device according to one aspect of the present invention can hold information, and therefore can be used, for example, to hold necessary information in systems that perform autonomous driving, road guidance, and hazard prediction for an automobile 5700. Furthermore, by applying a semiconductor device according to one aspect of the present invention, data necessary for the operation of a specific circuit can be held for a long period of time even when the power supply to that circuit is stopped due to power gating. In addition, when the power supply to the circuit is restored, the data necessary for the operation of that circuit can be quickly written back.

[0284] While the above explanation uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets).

[0285] [Camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0286] Figure 26H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but in some cases the lens 6246 and housing 6241 are integrated. Furthermore, the digital camera 6240 can also be configured to have a strobe device, viewfinder, etc. attached separately.

[0287] By applying a semiconductor device according to one aspect of the present invention to the digital camera 6240, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for the operation of that circuit can be quickly written back.

[0288] [Video Camera] A semiconductor device according to one aspect of the present invention can be applied to a video camera.

[0289] Figure 26I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, etc. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. It is also possible to configure the device to switch the image on the display unit 6303 according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0290] When recording video footage, it is necessary to perform encoding according to the data recording format. By using the semiconductor device described above, the video camera 6300 can retain temporary files generated during encoding.

[0291] By using a semiconductor device according to one aspect of the present invention in the video camera 6300, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to that circuit is resumed, the data necessary for the operation of that circuit can be quickly written back.

[0292] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0293] Figure 26J is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0294] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that the tip of one wire is placed in the right ventricle and the tip of the other wire is placed in the right atrium.

[0295] The ICD unit 5400 functions as a pacemaker, pacing the heart when the heart rate falls outside a specified range. If pacing does not improve the heart rate (e.g., rapid ventricular tachycardia, ventricular fibrillation), treatment with an electric shock is administered.

[0296] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 700.

[0297] Furthermore, power can be received by the antenna 5404, and this power is used to charge the battery 5401. In addition, the ICD unit 5400 can be made safer by having multiple batteries. Specifically, even if some of the batteries in the ICD unit 5400 become unusable, the remaining batteries can still function, thus also functioning as an auxiliary power source.

[0298] Furthermore, in addition to the antenna 5404 that can receive power, it is also possible to have an antenna that can transmit physiological signals. For example, a system can be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0299] By using a semiconductor device according to one aspect of the present invention in the ICD main unit 5400, data necessary for the operation of a specific circuit can be retained for a long period of time even when the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for the operation of that circuit can be quickly written back.

[0300] [Computer] The computer 5600 shown in Figure 27A is an example of a large computer (supercomputer) mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous calculations, resulting in high power consumption and significant heat generation from the chips. For example, in data centers with multiple supercomputers, the amount of digital data used becomes extremely large. Specifically, the amount of digital data in the world is 10 ２４ (yotta) bytes, or 10 ３０ It is expected to exceed (quetta) bytes.

[0301] By applying a semiconductor device according to one aspect of the present invention to computer 5600, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is restored, the data necessary for the operation of that circuit can be quickly written back. In addition, power gating reduces heat generation from the circuit, thereby reducing the impact of heat on the circuit itself, surrounding circuits, and modules. This is expected to reduce the amount of digital data in the world and make a significant contribution to combating global warming.

[0302] The computer 5600 contains multiple rack-mount type computers 5620 housed in a rack 5610. The computer 5620 can be configured, for example, as shown in the perspective view in Figure 27B. In Figure 27B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0303] The PC card 5621 shown in Figure 27C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 27C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for information on these semiconductor devices.

[0304] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0305] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0306] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0307] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the wiring provided on the board 5622. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0308] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 700 can be used as the semiconductor device 5628.

[0309] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0310] [Space Equipment] A semiconductor device according to one aspect of the present invention can be used in space equipment such as devices for processing and storing information.

[0311] A semiconductor device according to one aspect of the present invention includes an OS transistor and exhibits minimal fluctuations in electrical characteristics due to radiation exposure. In other words, it has high resistance to radiation and is therefore suitable for environments where radiation may be incident. For example, a semiconductor device according to one aspect of the present invention is suitable for use in outer space.

[0312] Figure 28 shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 28, a planet 6804 is shown as an example in outer space. Outer space generally refers to altitudes of 100 km or higher, but as described herein, outer space includes the thermosphere, mesosphere, and stratosphere.

[0313] Furthermore, although not shown in Figure 28, it is possible to provide a battery management system (also called "BMS") or a battery control circuit with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0314] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0315] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0316] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0317] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 has one or more functions selected from, for example, a CPU, a GPU, and a memory device. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation irradiation. A semiconductor device according to one aspect of the present invention is highly reliable even in environments where radiation may be incident, and is suitable as a memory element or memory device for the control device 6807.

[0318] By applying a semiconductor device according to one aspect of the invention to the control device 6807, data necessary for the operation of a specific circuit can be retained for a long period of time even while the power supply to that circuit is stopped due to power gating. Furthermore, when power supply to the circuit is resumed, the data necessary for the operation of that circuit can be quickly written back. In addition, power gating can reduce the power consumption of the control device 6807.

[0319] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0320] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention is suitable for space equipment such as spacecraft, space capsules, and space probes.

[0321] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0322] 10: Layer, 20: Layer, 100: Semiconductor device, 100[1]: Semiconductor device, 110: First memory circuit, 110[1]: First memory circuit, 111: Flip-flop circuit, 112: Selection circuit, 113: Inverter, 120: Second memory circuit, 120[1]: Second memory circuit, 132: Conductive layer, 133: Conductive layer, 134: Conductive layer, 136: Conductive layer, 150: Register, 200: Transistor, 200A: Transistor, 200B: Transistor, 211: Insulating layer, 212: Insulating layer, 213: Insulating layer, 214: Insulating layer, 215: Insulating layer, 216: Insulating layer, 217: Insulating layer 224: conductive layer, 231: conductive layer, 231a: conductive layer, 231b: conductive layer, 232: conductive layer, 232a: conductive layer, 232b: conductive layer, 233: conductive layer, 233a: conductive layer, 233b: conductive layer, 234: conductive layer, 234a: conductive layer, 234b: conductive layer, 235: conductive layer, 236: conductive layer, 237: conductive layer, 251: semiconductor layer, 251a: semiconductor layer, 251b: semiconductor layer, 261: insulating layer, 262: insulating layer, 263: insulating layer, 264: insulating layer, 271a: region, 271b: region, 281: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285 : insulating layer, 286: insulating layer, 287: insulating layer, 300: semiconductor device, 301: state control unit, 302: CPU core, 303A: register file, 303B: pipeline register, 303C: pipeline register, 304: arithmetic unit, 311: insulating layer, 312: insulating layer, 313: insulating layer, 314: insulating layer, 331: conductive layer, 332: conductive layer, 333: conductive layer, 334: conductive layer, 351: semiconductor layer, 352: insulating layer, 361: control circuit, 362: PC, 363: bus interface, 371: memory device, 400: transistor, 401: substrate, 402: Element isolation layer, 411: Insulating layer, 412: Insulating layer, 413: Insulating layer, 414: Insulating layer, 415: Insulating layer, 416: Insulating layer, 431: Conductive layer, 461: Insulating layer, 471: Channel formation region, 472a: Low resistance region, 472b: Low resistance region, 481: Insulating layer, 482: Insulating layer, 700: Electronic component, 702: Printed circuit board, 704: Mounted circuit board, 710: Semiconductor device, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 720: Semiconductor device, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode,5200: Portable game console, 5201: Casing, 5202: Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Casing, 5511: Display unit, 5600: Calculator, 5610: Rack, 5620: Calculator, 5621: PC card, 5622: Board, 5623: Connector, 5624: Connector, 5625: Connector, 5626: Semiconductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connector, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Enclosure, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 62 40: Digital camera, 6241: Housing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First housing, 6302: Second housing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 6800: Artificial satellite, 6801: Aircraft, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable battery, 6807: Control device, 7500: Home game console, 7520: Main unit, 7522: Controller, BK: Terminal, BL: Terminal, CLK: Terminal, DF: Terminal, FL: Free layer, IN: Terminal, LS: Level shift circuit, ME: Memory element, Nd: Node, OUT: Terminal, PL: Fixed layer, QB: Terminal, QBF: Terminal, QF: Terminal, RE: Terminal, RST: Terminal, SD: Terminal, SDI: Terminal, SE: Terminal, T11: Period, T12: Period, T13: Period, T21: Period, T22: Period, T23: Period, TI: Isolation layer, VDD: High power supply potential, VSS: Low power supply potential,

Claims

First memory circuit and It has a second memory circuit including a first transistor, a second transistor, a third transistor, and a memory element, The first terminal of the first transistor is electrically connected to the first terminal of the first memory circuit. The second terminal of the first transistor is electrically connected to the first terminal of the second transistor and the first terminal of the memory element. The second terminal of the second transistor is electrically connected to the first terminal of the third transistor and the second terminal of the first memory circuit. The memory element is a semiconductor device that is a magnetic tunnel junction element. 　 In claim 1, The first memory circuit is a semiconductor device including a flip-flop circuit. 　 In claim 1 or claim 2, The first memory circuit is a semiconductor device including a selection circuit. 　 In claim 1 or claim 2, The first memory circuit and the second memory circuit are semiconductor devices having overlapping regions. 　 In claim 1 or claim 2, Each of the first transistor, the second transistor, and the third transistor is a semiconductor device in which an oxide semiconductor is included in the semiconductor layer in which a channel is formed. 　 In claim 5, The oxide semiconductor is a semiconductor device containing indium. 　 In claim 1 or claim 2, The first memory circuit is a semiconductor device including a transistor in which silicon is included in the semiconductor layer in which the channel is formed.

Images