Method for forming metal oxide, and semiconductor device

Abstract

Provided is a semiconductor device having good electrical properties. This method for forming a metal oxide includes: a first step for forming, on an insulator, an island-shaped first layer having crystals; a second step for forming a metal oxide covering the first layer; a third step for processing the metal oxide into an island shape; and a fourth step for crystallizing the metal oxide. In the third step, the island-shaped metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer. The second region is adjacent to the first region and is located between the first region and the third region. In a plan view, the width of the third region along a first direction is narrower than the width of the second region along the first direction. The third step is performed at a temperature lower than the temperature of the fourth step.

Description

Method for forming metal oxides, and semiconductor device.

[0001] One aspect of the present invention relates to a metal oxide and a method for forming a metal oxide. Another aspect of the present invention relates to a semiconductor device having a metal oxide. Yet another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] Furthermore, examples of the technical fields of one aspect of the present invention disclosed more specifically in this specification include LSI (Large Scale Integration), CPU (Central Processing Unit), GPU (Graphics Processing Unit), FPGA (Field Programmable Gate Array), Application Specific Integrated Circuit (ASIC), AI (Artificial Intelligence) chips, memory (storage device), input device, input / output device, sensor, imaging device, display device, light-emitting device, energy storage device, electronic equipment, methods for driving them, or methods for manufacturing them.

[0003] Furthermore, one aspect of the present invention is not limited to the above-mentioned technical field. One aspect of the invention disclosed herein relates to a product or method; or to a method (process), machine, manufacture, or composition of matter.

[0004] The technology of constructing transistors using semiconductor thin films formed on insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, metal oxides (oxide semiconductors) that exhibit semiconductor properties are also attracting attention as other materials.

[0005] Further, it is known that a transistor including an oxide semiconductor has extremely small leakage current in a non-conductive state. For example, Patent Document 1 discloses a low-power-consumption CPU that utilizes the characteristic of low leakage current. Further, for example, Patent Document 2 discloses a memory device that can retain stored data over a long period of time.

[0006] Further, In ２ O ３ has been reported to be used in thin film transistors (Non-Patent Document 1).

[0007] Examples of oxide semiconductors that can be applied to an active layer of a transistor include indium oxide, indium gallium zinc oxide, and the like. Non-Patent Document 2 discloses a thin film transistor in which hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization is used for an active layer.

[0008] Japanese Patent Application Laid-Open No. 2012-257187 Japanese Patent Application Laid-Open No. 2011-151383

[0009] Dhananjay and C. W. Chu, "Realization of In₂O₃ thin film transistors through reactive evaporation process" Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al., "High-mobility hydrogenated polycrystalline In₂O₃ (In₂O₃:H) thin-film transistors", Nature Communications 13, 1078, (2022).

[0010] One aspect of the present invention has as an object thereof to provide a semiconductor device with favorable electrical characteristics. Alternatively, one object is to provide a semiconductor device with little characteristic variation. Alternatively, one object is to provide a semiconductor device having high current drive capability. Alternatively, one object is to provide a semiconductor device with high reliability. Alternatively, one object is to provide a semiconductor device that can be miniaturized. Alternatively, one object is to provide a semiconductor device with a small occupation area. Alternatively, one object is to provide a semiconductor device that can be arranged with high density. Alternatively, one object is to provide a semiconductor device in which wiring load is reduced. Alternatively, one object is to provide a semiconductor device in which parasitic capacitance is reduced. Alternatively, one object is to provide a semiconductor device with low power consumption. Alternatively, one object is to provide a semiconductor device with high operation speed.

[0011] One aspect of the present invention has as an object thereof to provide a method for forming a metal oxide with high crystallinity. Alternatively, one object is to provide a method for forming a metal oxide with few crystal grain boundaries. Alternatively, one object is to provide a method for forming a single-grain metal oxide. Alternatively, one object is to provide a metal oxide with high crystallinity. Alternatively, one object is to provide a metal oxide with few crystal grain boundaries. Alternatively, one object is to provide a single-grain metal oxide. Alternatively, one object is to provide a semiconductor device using a metal oxide with high crystallinity. Alternatively, one object is to provide a semiconductor device using a metal oxide with few crystal grain boundaries. Alternatively, one object is to provide a semiconductor device using a single-grain metal oxide.

[0012] One aspect of the present invention has as an object thereof to provide a semiconductor device having a novel configuration. One aspect of the present invention has as an object thereof to improve at least one of the problems of the prior art.

[0013] Note that the description of these objects does not preclude the existence of other objects. It is not required that one aspect of the present invention solve all of these objects. Objects other than these can be extracted from the description of the specification, drawings, claims, and the like.

[0014] One aspect of the present invention is a method for forming a metal oxide, comprising: a first step of forming a first island-shaped layer having crystals on an insulator; a second step of forming a metal oxide covering the first layer; a third step of processing the metal oxide into island shapes; and a fourth step of performing a crystallization treatment on the metal oxide. In the third step, the island-shaped metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer. The second region is adjacent to the first region and is located between the first region and the third region. In a plan view, the width of the third region along the first direction is narrower than the width of the second region along the first direction. The third step is performed at a temperature lower than the processing temperature of the fourth step.

[0015] In the above method for forming a metal oxide, it is preferable that the second region and the third region are in contact with an insulator.

[0016] In the above-described method for forming a metal oxide, it is preferable that the first step includes a first step of forming a first layer having metal and oxygen on an insulator, a second step of performing a treatment on the first layer to increase its crystallinity, and a third step of processing the first layer.

[0017] In the above-described method for forming metal oxides, the treatment to enhance crystallinity is preferably microwave-excited plasma treatment.

[0018] In the above method for forming metal oxides, the crystallization treatment is preferably a heat treatment under reduced pressure.

[0019] In the above-described method for forming a metal oxide, it is preferable to have a fifth step between the first step and the second step. In the fifth step, it is preferable to perform microwave-excited plasma treatment on the first layer.

[0020] In the above-described method for forming a metal oxide, it is preferable in the third step to process the metal oxide so that it has a fourth region. In a plan view, it is preferable that the fourth region is located between the second region and the third region. It is preferable that the width of the fourth region along the first direction narrows continuously from the width of the second region to the width of the third region.

[0021] In the above-described method for forming a metal oxide, it is preferable in the third step to process the metal oxide so that it has a fourth region. In a plan view, it is preferable that the fourth region is located between the second region and the third region. It is preferable that the width of the fourth region along the first direction is narrower than the width of the second region along the first direction and wider than the width of the third region along the first direction.

[0022] In the above-described method for forming a metal oxide, it is preferable in the third step to process the metal oxide so that it has a fourth region. In a plan view, it is preferable that the fourth region is located between the second region and the third region. It is preferable that the width of the fourth region along the first direction is narrower than the width of the third region along the first direction.

[0023] In the above method for forming a metal oxide, it is preferable that, in a plan view, the metal oxide has an opening between the first region and the third region of the second region.

[0024] Another aspect of the present invention is a semiconductor device comprising a first insulator, a second insulator, a first layer, a metal oxide, a first conductor, a second conductor, and a third conductor. The metal oxide functions as a channel-forming region of a transistor. The first conductor functions as a gate electrode of a transistor. The first layer is located on the first insulator. The metal oxide is located on the first insulator and on the first layer. The second insulator is located between the metal oxide and the first conductor. The metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer. The second region and the third region are in contact with the first insulator, respectively. The second region is adjacent to the first region and is located between the first region and the third region. In a plan view, the width of a third region along a first direction perpendicular to the channel length direction of the transistor is narrower than the width of a second region along the first direction. The third region of the metal oxide has a first portion that overlaps with the first conductor, a second portion that is in contact with the second conductor, and a third portion that is in contact with the third conductor. The first portion is located between the second and third portions.

[0025] Another aspect of the present invention is a semiconductor device comprising a first insulator, a second insulator, a third insulator, a first layer, a metal oxide, a first conductor, a second conductor, and a third conductor. The metal oxide functions as a channel-forming region of the transistor. The first conductor functions as a gate electrode of the transistor. The first layer is located on the first insulator. The metal oxide is located on the first insulator and on the first layer. The second insulator is located between the metal oxide and the first conductor. The third insulator is located on the first conductor. The second and third conductors are located on the third insulator. The metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer. The second and third regions are in contact with the first insulator, respectively. The second region is adjacent to the first region. Furthermore, it is located between the first region and the third region. In a plan view, the width of the third region along the first direction perpendicular to the channel length direction of the transistor is narrower than the width of the second region along the first direction. The third region of the metal oxide has a first portion that overlaps with the first conductor. The second conductor and the third conductor each have regions that are in contact with the metal oxide through openings formed in the third insulator.

[0026] In the semiconductor device described above, it is preferable that the first portion has a cross-section in which no grain boundaries are observed by analysis using a transmission electron microscope in a direction parallel to the channel length direction of the transistor.

[0027] In the semiconductor device described above, it is preferable that the metal oxide has crystal grains that overlap with a pair of ends of the first conductor that face each other in the channel length direction of the transistor.

[0028] In the semiconductor device described above, it is preferable that the first layer and the metal oxide each contain indium.

[0029] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Or, a semiconductor device with less variation in characteristics can be provided. Or, a semiconductor device with high current drive capability can be provided. Or, a semiconductor device with high reliability can be provided. Or, a semiconductor device that can be miniaturized can be provided. Or, a semiconductor device with a small footprint can be provided. Or, a semiconductor device that can be arranged at high density can be provided. Or, a semiconductor device with reduced wiring load can be provided. Or, a semiconductor device with reduced parasitic capacitance can be provided. Or, a semiconductor device with low power consumption can be provided. Or, a semiconductor device with high operating speed can be provided.

[0030] According to one aspect of the present invention, a method for forming a highly crystalline metal oxide can be provided. Alternatively, a method for forming a metal oxide with few grain boundaries can be provided. Alternatively, a method for forming a single-grain metal oxide can be provided. Alternatively, a highly crystalline metal oxide can be provided. Alternatively, a metal oxide with few grain boundaries can be provided. Alternatively, a single-grain metal oxide can be provided. Alternatively, a semiconductor device using a highly crystalline metal oxide can be provided. Alternatively, a semiconductor device using a metal oxide with few grain boundaries can be provided. Alternatively, a semiconductor device using a single-grain metal oxide can be provided.

[0031] According to one aspect of the present invention, a semiconductor device having a novel configuration can be provided. According to one aspect of the present invention, at least one of the problems of the prior art can be improved.

[0032] Furthermore, the description of these effects does not preclude the existence of other effects. Moreover, one aspect of the present invention does not need to possess all of these effects. Other effects can be extracted from the description in the specification, drawings, claims, etc.

[0033] Figures 1A, 1B, 1C, 1D, and 1E illustrate examples of methods for forming metal oxides. Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, and 2I illustrate examples of methods for forming metal oxides. Figures 3A, 3B, 3C, 3D, 3E, 3F, 3G, 3H, and 3I illustrate examples of methods for forming metal oxides. Figures 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, and 4I illustrate examples of methods for forming metal oxides. Figures 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H illustrate examples of methods for forming metal oxides. Figures 6A, 6B, 6C, 6D, 6E, 6F, 6G, and 6H illustrate examples of methods for forming metal oxides. Figures 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7I illustrate examples of metal oxide formation methods. Figures 8A, 8B, 8C, and 8D illustrate examples of metal oxide formation methods. Figures 9A and 9B illustrate examples of semiconductor device configurations. Figures 10A, 10B, and 10C illustrate examples of semiconductor device configurations. Figures 11A, 11B, 11C, and 11D illustrate methods for manufacturing semiconductor devices. Figures 12A, 12B, and 12C illustrate methods for manufacturing semiconductor devices. Figures 13A and 13B illustrate methods for manufacturing semiconductor devices. Figures 14A, 14B, 14C, 14D, and 14E illustrate examples of semiconductor device configurations. Figures 15A and 15B illustrate examples of semiconductor device configurations. Figure 16 illustrates an example of semiconductor device configuration. Figure 17 is a block diagram illustrating an example of a semiconductor device configuration. Figures 18A, 18B, 18C, 18D, 18E, 18F, 18G, and 18H illustrate an example of a memory cell circuit configuration. Figures 19A, 19B, and 19C are perspective views of a semiconductor device. Figures 20A and 20B show an example of a semiconductor device configuration. Figure 21 shows an example of a semiconductor device configuration. Figures 22A and 22B show an example of an electronic component. Figures 23A, 23B, and 23C show an example of a large-scale computer. Figure 23D shows an example of space equipment. Figure 23E shows an example of a storage system applicable to a data center.Figures 24A and 24B show examples of the composition of the sample related to the example. Figure 24C shows the analysis results of the sample related to the example.

[0034] Embodiments will be described with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the contents of the embodiments shown below.

[0035] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0036] Furthermore, the position, size, thickness, and extent of each component shown in the drawings may be exaggerated for clarity. Therefore, the disclosed invention is not necessarily limited to the position, size, thickness, and extent of each component disclosed in the drawings.

[0037] In addition, in drawings and other illustrations relating to this specification, arrows indicating the X, Y, and Z directions may be included. In this specification, the "X direction" refers to the direction along the X axis, and unless explicitly stated, the forward and reverse directions may not be distinguished. The same applies to the "Y direction" and "Z direction".

[0038] In this specification, the ordinal numbers "first" and "second" are used for convenience only and do not limit the number of components or the order of components (for example, process order or layering order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0039] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "A", "b", "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0040] Furthermore, in this specification, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0041] Furthermore, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." Similarly, the term "conductor" may be replaced with "conductive film" or "conductive layer." Finally, the term "metal oxide" may be replaced with "metal oxide film" or "metal oxide layer."

[0042] In this specification, "oxidized nitride" refers to a material whose composition contains more oxygen atoms than nitrogen atoms, and "nitride oxide" refers to a material whose composition contains more nitrogen atoms than oxygen atoms. For example, when "silicon oxidized nitride" is written, it refers to a material whose composition contains more oxygen atoms than nitrogen atoms, and when "silicon nitride oxide" is written, it refers to a material whose composition contains more nitrogen atoms than oxygen atoms.

[0043] In this specification, the term "semiconductor device" refers to a device that utilizes semiconductor properties, including transistors, circuits containing transistors, and devices having such circuits. It also refers to any device that can function by utilizing semiconductor properties.

[0044] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0045] In this specification, transistors using a metal oxide in the semiconductor layer, and transistors having a metal oxide in the channel formation region, may be referred to as OS transistors. Furthermore, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0046] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate, a drain, and a source. It also has a region (also called a channel-forming region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel-forming region.

[0047] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0048] In addition to the three terminals described above, a back gate may be present. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as the first gate, and the other of the gate or back gate of the transistor may be referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" may be interchangeable.

[0049] Furthermore, unless otherwise specified in this specification, off-current refers to the drain current when the transistor is in the off state (also called the non-conductive state or interrupted state).

[0050] Furthermore, unless otherwise specified in this specification, on-current refers to the drain current when the transistor is in the on state (also called the "conducting state").

[0051] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0052] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0053] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0054] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0055] In this specification, "plan view" means viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0056] In the following, expressions indicating direction, such as "up" and "down," will generally be used in accordance with the orientation shown in the drawings. However, for the purpose of simplifying explanations, the direction referred to as "up" or "down" in the specification may not always coincide with that of the drawings. For example, when explaining the stacking order (or formation order) of a laminate, even if the side on which the laminate is provided (the surface to be formed, the support surface, the adhesive surface, the flat surface, etc.) is located above the laminate in the drawing, the side to be formed may be described as "down," and the direction opposite to the surface to be formed may be described as "up."

[0057] Furthermore, in this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 70 degrees or more and 110 degrees or less.

[0058] In this specification, "matching heights" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, in a manufacturing process, the surfaces of multiple layers may be exposed by planarization (typically CMP processing). In this case, the surfaces subjected to CMP processing will have a configuration in which the heights from the reference surface are equal. However, the heights of the multiple layers may differ due to differences in the processing equipment, processing method, materials of the surfaces subjected to CMP processing, or differences in polishing rate and etching rate. In this specification, this case will also be treated as "matching heights."

[0059] In this specification, "ends coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. This includes, for example, cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern.

[0060] In this specification, space groups are expressed using international notation (or Hermann-Mauguin notation) in short notation. Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by superscripting numbers, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a superscript. Individual orientations within a crystal are represented by [ ], collective orientations representing all equivalent orientations are represented by < >, individual crystal planes are represented by ( ), and collective planes with equivalent symmetry are represented by {}.

[0061] (Embodiment 1) In this embodiment, a method for forming a metal oxide according to one aspect of the present invention will be described with reference to Figures 1A to 4I.

[0062] A metal oxide according to one aspect of the present invention preferably exhibits semiconductor properties. A metal oxide according to one aspect of the present invention can be used, for example, as a semiconductor in a transistor. However, depending on the type, combination, and composition of the elements constituting the metal oxide, a metal oxide according to one aspect of the present invention is not limited to semiconductor materials; it can also be an insulating material or a conductive material. Furthermore, it is preferable to use indium oxide as the metal oxide according to one aspect of the present invention.

[0063] First, an embodiment of the present invention and a method for forming the same will be described using Figures 1A to 1E. Figures 1A and 1B are plan views of the metal oxide, and Figure 1C is a cross-sectional view between the dashed lines A1 and A2 shown in Figure 1A. Figure 1D is a cross-sectional view between the dashed lines A3 and A4 shown in Figure 1A. Figure 1E is an enlarged view of the region P1 enclosed by the dashed lines in Figure 1A.

[0064] In Figure 1C and other figures, an island-shaped first layer 20 having crystals is provided on the insulator 10, and a metal oxide 30 is provided on the first layer 20. As shown in Figures 1A and 1B and other figures, the metal oxide 30 has a first region 30_1, a second region 30_2, and a third region 30_3. The first region 30_1 is in contact with the first layer 20. The second region 30_2 and the third region 30_3 are in contact with the insulator 10. The second region 30_2 is adjacent to the first region 30_1 and is located between the first region 30_1 and the third region 30_3.

[0065] In Figure 1A, the grain boundaries of the metal oxide 30 are shown by solid lines. The first region 30_1 and the second region 30_2 can each have multiple crystal grains. At least one crystal grain in the second region 30_2 extends into the third region 30_3. The grain size of the crystal grain in the second region 30_2 is larger than the grain size of the crystal grain in the first region 30_1. Furthermore, the third region 30_3 has fewer grain boundaries than either or both of the first region 30_1 or the second region 30_2.

[0066] The crystallinity of the first layer 20 and the metal oxide 30 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), electron diffraction (ED), or electron diffraction mapping. Alternatively, a combination of these methods may be used for the analysis.

[0067] Furthermore, crystal grains can be identified, for example, in high-resolution TEM images. Also, crystal grain boundaries can sometimes be identified, for example, in high-resolution TEM images. In other words, crystal grains and crystal grain boundaries of a crystalline film can sometimes be observed in high-resolution TEM images. When acquiring crystal grains and crystal grain boundaries of a crystalline film using TEM images, the overall magnification is preferably 2 million times or more, and more preferably 4 million times or more.

[0068] Furthermore, the grain size of the crystal grains can also be confirmed, for example, using an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM). Additionally, by creating surface irregularities on the first layer 20 and the metal oxide 30 using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed using an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM). When an indium oxide film is used as the first layer 20 and the metal oxide 30, the crystal grains of the indium oxide can be more easily observed by using an etchant containing an acid. For example, one or more of phosphoric acid, oxalic acid, nitric acid, and hydrochloric acid can be used as the acid. Note that if the etching rate is too fast, a portion of the first layer 20 and the metal oxide 30 may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching rate by the concentration of the etchant, temperature, and processing time so that the first layer 20 and the metal oxide 30 do not disappear, but their thickness is reduced (also called half-etching). By performing half-etching, it becomes possible to easily observe the crystal grains.

[0069] Furthermore, the crystallinity of the metal oxide 30 can be evaluated by the grain size. The grain size can be calculated, for example, by calculating the area of ​​the grain and then determining the diameter of a circle that corresponds to that area. This diameter is sometimes called the area circle equivalent diameter.

[0070] Furthermore, the crystallinity of the metal oxide 30 can also be evaluated by the length of the grain boundaries. The length of the grain boundaries can be calculated, for example, by extracting a field of view of a specific area from a TEM image of the film acquired at a total magnification that allows observation of the grain boundaries, and summing the lengths of the grain boundaries observed in that field of view. A longer length of the grain boundaries indicates a higher proportion of grain boundary components. A shorter length of the grain boundaries indicates larger grain sizes, while a longer length of the grain boundaries indicates smaller grain sizes.

[0071] Electron diffraction mapping is a technique that uses electron diffraction from a TEM to analyze the orientation distribution of crystalline samples. Crystal information is obtained by measuring the electron diffraction pattern at each point while scanning the electron probe. For example, grain boundaries can be observed by utilizing the difference in orientation between adjacent measurement points. For instance, grain boundaries can be observed by analyzing orientation differences of 5° or more as grain boundaries.

[0072] Figure 1B is a diagram illustrating the first region 30_1, the second region 30_2, the third region 30_3, the width j2 of the second region 30_2 along the first direction D1, and the width j1 of the third region 30_3 along the first direction D1 in the metal oxide 30 shown in Figure 1A. As shown in Figure 1B, the width j1 of the third region 30_3 along the first direction D1 and the width j2 of the second region 30_2 along the first direction D1 are different from each other. Specifically, it is preferable that the width j1 of the third region 30_3 along the first direction D1 is narrower than the width j2 of the second region 30_2 along the first direction D1. Note that the first direction D1 is the direction parallel to the channel width direction when the third region 30_3 is used as the channel formation region of a transistor. In other words, it is the direction perpendicular to the direction in which the current flows in the channel formation region. Furthermore, the second direction D2 is perpendicular to the first direction D1. When the third region 30_3 is used as the channel formation region of the transistor, the second direction D2 is parallel to the channel length direction. In other words, it is parallel to the direction in which the current flows in the channel formation region.

[0073] In Figure 1A, the corners of the metal oxide 30 are shown to be right angles in a plan view, but as shown in Figure 1E, the corners may have a rounded shape. A rounded shape is, for example, a shape that includes an arc of a circle whose center is outside the metal oxide 30 in a plan view. Alternatively, for example, a shape that includes an arc of a circle whose center is inside the metal oxide 30 in a plan view.

[0074] It is preferable to use indium oxide as the metal oxide 30. For details regarding indium oxide, please refer to the description in Embodiment 3.

[0075] Furthermore, indium oxide may contain metal elements that can form cations. For example, indium oxide doped with metal oxides such as Ge, W, Ga, Sb, Bi, Sn, and Ti can be used. Doping an indium oxide film with such oxides can reduce oxygen deficiencies, indium deficiencies, or both in the indium oxide, thereby improving reliability.

[0076] The metal oxide 30 may be a single layer or a laminated structure of two or more layers. Furthermore, in the case of a laminated structure of two or more layers, different film deposition methods may be used for each layer. For example, a structure may be formed in which indium oxide deposited by sputtering is laminated onto indium oxide deposited by the ALD method. Alternatively, a structure may be formed in which indium oxide deposited by the ALD method is laminated onto indium oxide deposited by sputtering. Alternatively, a structure may be formed in which indium oxide deposited by the ALD method under first film deposition conditions is laminated onto indium oxide deposited by the ALD method under second film deposition conditions. Here, it is preferable that the first and second film deposition conditions are different. For example, in the ALD method, a precursor and an oxidizing agent are used for film deposition, and different film deposition conditions with varying oxidation times by the oxidizing agent can be used.

[0077] The purity of the metal oxide 30 is preferably high. In particular, the purity in the channel-forming region is preferably high. Furthermore, the impurity concentration in the metal oxide 30 is preferably low. In particular, the impurity concentration in the channel-forming region is preferably low. For example, when indium oxide is used as the metal oxide 30, the purity of the metal oxide 30, or the purity in the channel-forming region, is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, more preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher, more preferably 8N (99.999999%) or higher, more preferably 9N (99.9999999%) or higher, and even more preferably 10N (99.99999999%) or higher. It is presumed that impurity elements (elements other than indium and oxygen) in the indium oxide film tend to be concentrated at the grain boundaries. In other words, it is hypothesized that when impurity elements are present in an indium oxide film, the uneven distribution of these impurity elements makes it easier for grain boundaries to form. Therefore, by reducing the amount of impurity elements in the indium oxide film, the formation of grain boundaries in the indium oxide film can be suppressed. As a result, grain boundary scattering or impurity scattering is reduced, and the on-current of the transistor can be increased.

[0078] The first layer 20 functions as a seed or nucleus to enhance the crystallinity of the metal oxide, and can therefore be called a seed layer, seed crystal, crystal nucleus, etc. For example, indium oxide or indium gallium zinc oxide (also written as In-Ga-Zn oxide or IGZO) can be used as the first layer 20. When In-Ga-Zn oxide is used as the first layer 20, it is preferable to have a composition such as In:Ga:Zn = 1:1:1 [atomic ratio] or close to that, In:Ga:Zn = 1:1:1.2 [atomic ratio] or close to that, or In:Ga:Zn = 1:3:2 [atomic ratio] or close to that. Furthermore, the first layer 20 can be zinc oxide, indium gallium oxide (In-Ga oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), or indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®). In addition, yttrium oxide, erbium oxide, etc. can be used. Furthermore, indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (In-Sn-Si oxide, also called ITSO), etc. can be used.

[0079] In-Ga-Zn oxides and In-Sn-Zn oxides, etc., tend to have a CAAC (c-axis aligned crystal) structure. When an oxide having a CAAC structure is used for the first layer 20, the c-axis direction of the first layer 20 is parallel or approximately parallel to the thickness direction of the insulator 10. Therefore, by using an oxide that tends to have a CAAC structure for the first layer 20, the controllability of the crystal planes of the crystal grains of the metal oxide 30f can be improved.

[0080] One aspect of the present invention is a method for forming a metal oxide, comprising: a first step of forming a first island-shaped layer 20 having crystals on an insulator 10; a second step of forming a metal oxide 30 covering the first layer; a third step of processing the metal oxide 30 so that it has a first region 30_1, a second region 30_2, and a third region 30_3; and a fourth step of performing a crystallization treatment on the metal oxide 30. The third step is preferably performed at a temperature lower than the processing temperature of the fourth step.

[0081] In one embodiment of the present invention, a method for forming a metal oxide is used to process the metal oxide 30 to have a first region 30_1, a second region 30_2, and a third region 30_3. After processing, the metal oxide 30 can be crystallized by performing a treatment to enhance its crystallinity. During crystallization, the first region 30_1, which is in contact with the first layer 20, crystallizes. In this case, multiple crystal grains may be formed in the first region 30_1. Therefore, if the first region 30_1 and the third region 30_3 are adjacent, the third region 30_3 is likely to be composed of multiple crystal grains, and there is a risk of many grain boundaries being formed. For this reason, a distance (region) is required between the first region 30_1 and the third region 30_3 for crystal growth.

[0082] Therefore, in one embodiment of the present invention, the metal oxide 30 has a second region 30_2 between a first region 30_1 and a third region 30_3. As a result, crystal grains grow from the first region 30_1 and crystals grow in the second region 30_2. In the second region 30_2, crystal grains with a fast growth rate grow larger, and the number of crystal grains decreases and the size of each crystal grain increases as it moves away from the first region 30_1. This can be called geometric selection in crystal growth. Due to this geometric selection in crystal growth, the crystals grow in the second region 30_2 in such a way that the crystal grains spread out widely. In the metal oxide 30, by selecting crystal grains with a shape in which the width j1 of the third region is narrower than the width j2 of the second region, only the crystal grains that have grown toward the third region 30_3 from among the crystal grains grown in the second region 30_2 can be guided to the third region 30_3 and allowed to grow there. Thus, in addition to geometric selection in the second region 30_2, the shape of the metal oxide 30 also allows for the selection of crystal grains to grow in the third region 30_3. By preferentially growing crystal grains that reach the third region 30_3 in the third region 30_3, the formation of crystal grain boundaries in the third region 30_3 can be suppressed. Alternatively, the third region 30_3 can be made into a region where no crystal grain boundaries are observed. Alternatively, the third region 30_3 can be made into a region having a cross-section along the second direction D2 where no crystal grain boundaries are observed, by analysis using a transmission electron microscope. Alternatively, the third region 30_3 can be made into a region that does not contain crystal grain boundaries when analyzed by electron diffraction mapping, where adjacent measurement points with an orientation difference of 5° or more are considered as crystal grain boundaries. Alternatively, the third region 30_3 can be made into a single-grain crystal.

[0083] Furthermore, in a method for forming a metal oxide according to one aspect of the present invention, only the crystal grains that have grown toward the third region 30_3 from among the crystal grains grown in the second region 30_2 are guided toward the third region 30_3 and allowed to grow crystals there. Therefore, it is preferable to process the metal oxide 30 to have a first region 30_1, a second region 30_2, and a third region 30_3, and then perform a treatment to enhance the crystallinity of the metal oxide 30. For this reason, the processing temperature of the third step in which the metal oxide 30 is processed to have a first region 30_1, a second region 30_2, and a third region 30_3 is preferably lower than the processing temperature of the treatment to enhance the crystallinity of the metal oxide 30.

[0084] Of the metal oxide 30, the third region 30_3 in particular can be used, for example, as the active layer of a transistor. For example, part or all of the third region 30_3 can be used as the channel formation region of the transistor. Furthermore, it is preferable to use the metal oxide 30 such that the direction of current flow in the channel formation region of the transistor is parallel to the second direction D2. The third region 30_3 can be a region in which no grain boundaries are observed. Alternatively, the channel formation region formed in the third region 30_3 can be a single-grain crystal. Alternatively, the channel formation region formed in the third region 30_3 can be a region having a cross-section along the second direction D2 in which no grain boundaries are observed, by analysis using a transmission electron microscope. Alternatively, the channel formation region formed in the third region 30_3 can be a crystal that does not contain grain boundaries when analyzed by electron diffraction mapping, where adjacent measurement points with an orientation difference of 5° or more are considered grain boundaries. This makes it possible to obtain a semiconductor device with good electrical properties. Alternatively, a semiconductor device with high current drive capability can be obtained. Alternatively, a semiconductor device with high reliability can be obtained. A semiconductor device with less variation in characteristics can be provided. One or more channel formation regions can be provided in the third region 30_3. Also, one or more source regions or drain regions can be provided in the third region 30_3. Also, one or more transistor channel formation regions can be provided in the third region 30_3. Furthermore, the first region 30_1 and the second region 30_2, etc., can be used as either or both of the source region or drain region of a transistor.

[0085] An example of a method for producing the metal oxide 30 shown in Figures 1A to 1E, according to one aspect of the present invention, will be described in detail with reference to Figures 2A to 4I. Figures C, F, and I are plan views. Figures A, D, and G are cross-sectional views between the dashed lines A1 and A2 shown in Figures C, F, and I, respectively. Figures B, E, and H are cross-sectional views between the dashed lines A3 and A4 shown in Figures C, F, and I, respectively.

[0086] The insulator 10, the first layer 20, and the metal oxide 30 can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. For ALD, methods such as thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants, can be used. CVD methods that can be used include plasma-enhanced CVD (PECVD), thermal CVD, and photo-CVD.

[0087] An insulator 10 is formed on a substrate (not shown) (see Figures 2A to 2C). Preferably, the insulator 10 has an amorphous structure. If the insulator 10 has a polycrystalline or single-crystal structure, when the metal oxide 30f is formed later, the metal oxide 30 may crystallize in accordance with the crystal structure of the insulator 10, potentially forming a polycrystalline structure with small crystal grains. Therefore, by having an amorphous structure for the insulator 10, unintended crystallization of the metal oxide 30f can be suppressed, making it possible to obtain a metal oxide 30f with large crystal grains.

[0088] For example, silicon oxide, silicon oxide nitride, etc., can be used for the insulator 10. Alternatively, silicon nitride, silicon oxide nitride, hafnium oxide, aluminum oxide, gallium oxide, etc., can be used.

[0089] Furthermore, it is preferable to perform a heat treatment after the insulator 10 is formed. By performing a heat treatment, impurities such as water and hydrogen contained in the insulator 10 can be reduced before the metal oxide film that will become the semiconductor layer is formed.

[0090] The heat treatment is preferably carried out at a temperature of 250°C to 650°C, more preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment is preferably carried out in a reduced pressure atmosphere or an inert gas atmosphere (for example, nitrogen gas, noble gas, or both). Alternatively, an oxygen gas atmosphere or a mixed atmosphere of nitrogen gas and oxygen gas may be used. When performing the treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have an oxygen gas content of about 20%. There are no special limitations on the apparatus used for the heat treatment, and it may be an apparatus that heats the workpiece by heat conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used.

[0091] Furthermore, in order to reduce impurities such as water and hydrogen contained in the insulator 10, it is preferable to use silicon oxide deposited by a sputtering method that does not use hydrogen as the deposition gas.

[0092] The upper surface of the insulator 10 is preferably flat. This configuration suppresses nucleation caused by irregularities on the upper surface of the insulator 10 and promotes crystal growth in the metal oxide layer.

[0093] In this specification, a layer is considered flat if its average surface roughness (Ra) is less than 3 nm. The average surface roughness (Ra) is defined as that specified in JIS B 0601:2013 (ISO 4287:1997). The average surface roughness (Ra) can be evaluated using an atomic force microscope (AFM). For example, the average surface roughness (Ra) can be calculated over a 2 μm square area. If the layer is island-like and does not have a 2 μm square area in plan view, the calculation may be performed over the entire area of ​​the layer in plan view.

[0094] Furthermore, the flatness of the upper surface of a layer can also be evaluated by performing image analysis of the TEM image. For example, it is assumed that the shape of the interface between the first layer and the second layer observed in the TEM image is the roughness curve of the first layer. Then, the arithmetic mean roughness can be calculated from the assumed roughness curve. The reference length may be the length of the upper surface of the first layer observed in the TEM image, or the length of the region where the first layer and the second layer overlap. The reference length may be, for example, 100 nm. In this case, it is preferable that the observation range of the TEM image is 100 nm or more in either the vertical or horizontal direction. If the arithmetic mean roughness of the upper surface of the first layer calculated using this method is less than 3 nm, the upper surface of the first layer can also be said to be flat.

[0095] The average surface roughness (Ra) or arithmetic mean roughness of the upper surface of the insulator 10 is preferably 0 nm or more and less than 3 nm, more preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, more preferably 0 nm or more and 0.5 nm or less, more preferably 0 nm or more and 0.3 nm or less, and even more preferably 0 nm or more and 0.2 nm or less.

[0096] For example, the flatness of the upper surface of the insulator 10 can be improved by performing chemical mechanical polishing (CMP) treatment. When the insulator 10 has a laminated structure of n layers (where n is an integer of 2 or more), CMP treatment can be performed on the uppermost layer (the nth layer) of the insulator 10. Alternatively, CMP treatment can be performed on a layer other than the uppermost layer of the insulator 10 (the kth layer (where k is an integer of 1 or more and n-1 or less)), and the k+1th to nth layers can be formed on the flattened kth layer.

[0097] Furthermore, a hydrogen addition treatment may be performed before forming the metal oxide 30f. For example, the hydrogen addition treatment may be performed after the formation of the insulator 10. The hydrogen addition treatment can be carried out using an ion implanter, an ion doping device, or a plasma treatment device. Alternatively, as a hydrogen addition treatment, microwave-excited plasma treatment can be performed in a hydrogen-containing atmosphere. By adding hydrogen to the surface of the insulator 10, nucleation of the metal oxide 30f near the interface with the insulator 10 can be suppressed.

[0098] A first layer 20f is formed on the insulator 10 (see Figures 2A to 2C). Sputtering, ALD, CVD, PLD, etc., can be used to form the first layer 20f. For example, indium oxide and In-Ga-Zn oxide can be used as the first layer 20f. For example, it is preferable to use indium oxide formed by the ALD method or In-Ga-Zn oxide with an In:Ga:Zn = 1:3:2 [atomic ratio] formed by the sputtering method as the first layer 20f.

[0099] It is preferable to perform a treatment to enhance the crystallinity of the first layer 20f. For example, indium oxide, which has a cubic crystal system, is presumed to grow crystals while maximizing the surface area of ​​the {111} plane at the interface between the crystal and amorphous material, because the interfacial energy of the {111} plane is smaller than that of other planes. In other words, when indium oxide is used for the first layer 20f, it is presumed that it will preferentially orient towards the {111} plane. Therefore, by performing a treatment to enhance the crystallinity, it is possible to form crystal grains in the first layer 20 in which the crystal orientation <111> is oriented parallel to the thickness direction of the insulator 10 (the direction perpendicular to the surface on which the first layer 20 is formed) (also called <111> oriented crystal grains). Furthermore, when In-Ga-Zn oxide, which has a hexagonal crystal system, or a metal oxide having a similar crystal structure is used for the first layer 20f, crystals with a preferential orientation of the {001} plane can be obtained.

[0100] Examples of treatments to enhance crystallinity include microwave-excited plasma treatment (also simply called microwave plasma treatment), heating, plasma treatment, microwave treatment, and light (e.g., ultraviolet light) irradiation. Microwave treatment refers to treatment using a device equipped with a power supply that generates high-density plasma using microwaves, for example. Multiple of these treatments can be performed simultaneously or sequentially. The arrows shown in Figures 2A and 2B indicate heat, plasma, microwaves, radicals, or light, respectively.

[0101] As a treatment to enhance the crystallinity of the first layer 20f, it is preferable to use microwave-excited plasma treatment. In particular, it is especially preferable to perform the microwave-excited plasma treatment in an oxygen-containing atmosphere.

[0102] Microwave-excited plasma processing refers to processing using equipment that has a power supply that generates high-density plasma using microwaves. Microwave-excited plasma processing can also be called microwave-excited high-density plasma processing.

[0103] In microwave-excited plasma processing, it is preferable to use a plasma processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the microwave frequency is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply that applies microwaves to the microwave-excited plasma processing apparatus is preferably 1000 W to 10000 W, and preferably 2000 W to 5000 W. The microwave-excited plasma processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the film.

[0104] When performing microwave-excited plasma processing, it is preferable to set the substrate temperature to room temperature (e.g., 25°C) or higher and 1000°C or lower, 100°C or higher and 800°C or lower, 200°C or higher and 650°C or lower, 300°C or higher and 500°C or lower, 400°C or higher and 500°C or lower, or 400°C or higher and 450°C or lower.

[0105] Microwave-excited plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa being preferred, more preferably 50 Pa to 700 Pa, and even more preferably 100 Pa to 400 Pa.

[0106] Microwave-excited plasma treatment can be performed, for example, using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２The value of +Ar) should be greater than 0% and 100% or less. Preferably, it should be greater than 0% and 50% or less. More preferably, it should be between 10% and 40%. Even more preferably, it should be between 10% and 30%. Typically, it should be 25%. When performing processing using oxygen (O) radicals, it is preferable to increase the oxygen flow rate ratio. On the other hand, a high oxygen flow rate ratio may increase the risk of particle generation, or the risk of damage to the processing chamber, or both. For this reason, the oxygen flow rate needs to be set within an appropriate range.

[0107] Furthermore, microwave-excited plasma treatment can be carried out using, for example, hydrogen gas, oxygen gas, and argon gas. Here, the ratio of the hydrogen gas flow rate to the total gas flow rate is defined as the hydrogen flow rate ratio. For example, when using hydrogen gas, oxygen gas, and argon gas, the hydrogen flow rate ratio represents the ratio of the hydrogen gas flow rate to the sum of the hydrogen gas flow rates, oxygen gas flow rates, and argon gas flow rates. For example, the hydrogen flow rate ratio is preferably greater than 0% and 15% or less, more preferably greater than 0% and 10% or less, and even more preferably greater than 0% and 7.5% or less. By setting the hydrogen flow rate ratio within the above range, the number of active species such as OH radicals or OH ions during microwave-excited plasma treatment increases, which can accelerate the reaction. On the other hand, by increasing the amount of hydrogen above the above range, H ２ The proportion of active species decreases due to an increase in inactive species such as O, H ２ There is a risk that hydrogen in the metal oxide 30 may not be sufficiently removed due to reduction of the metal oxide 30 by this method.

[0108] The shorter the processing time for microwave plasma treatment, the higher the productivity. For example, the processing time for microwave plasma treatment is preferably 1 minute or more and 60 minutes or less, more preferably 1 minute or more and 30 minutes or less, and even more preferably 1 minute or more and 10 minutes or less.

[0109] Furthermore, as a treatment to enhance the crystallinity of the first layer 20f, heat treatment is preferred. The heat treatment is preferably carried out in a reduced-pressure atmosphere or an inert gas atmosphere (for example, nitrogen gas, a noble gas, or both). Alternatively, an oxygen gas atmosphere or a mixed atmosphere of nitrogen gas and oxygen gas may be used. When performing the treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have an oxygen gas content of about 20%. There are no special limitations on the apparatus used for the heat treatment, and it may be an apparatus that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA apparatus such as an LRTA apparatus or GRTA apparatus can be used.

[0110] Subsequently, a resist mask 21 is formed on the first layer 20f (see Figures 2D to 2F).

[0111] Subsequently, the portion of the first layer 20f where the resist mask 21 is not formed is removed by etching to form the first layer 20. After forming the first layer 20, the resist mask 21 is removed (see Figures 2G to 2I). For etching, either a dry etching method or a wet etching method, or both, can be used. For example, by using a wet etching method to form the first layer 20, damage to the insulator 10 can be reduced compared to using a dry etching method. In addition, the flatness of the upper surface of the insulator 10 can be maintained.

[0112] The shape of the first layer 20 in plan view can be island-like or striped. The side surface of the first layer 20 may also have a tapered shape. The number of first layers 20 provided on the insulator 10 may be one or multiple.

[0113] The thickness of the first layer 20 is preferably thin. The thickness of the first layer is greater than 0 nm and 5 nm or less, more preferably greater than 0 nm and 3 nm or less, and even more preferably greater than 0 nm and 2 nm or less. It is preferable that the first layer 20 has a region with the above-mentioned thickness in at least a part of it. By making the thickness of the first layer 20 thin, the step difference that occurs between the first layer 20 and the insulator 10 is reduced. Therefore, the coverage of the metal oxide layer formed later is improved and defects such as porosity can be reduced. In addition, crystal growth of the metal oxide layer can be promoted.

[0114] It is preferable to perform a treatment to increase the crystallinity of the first layer 20f, but the crystallinity of the first layer 20 may also be increased after its formation. This further enhances the crystallinity of the first layer 20. Additionally, the surface or film quality of the portion of the insulator 10 that does not overlap with the first layer 20 can be modified.

[0115] Furthermore, after forming the first layer 20, microwave plasma treatment may be performed in a hydrogen-containing atmosphere. This enhances the crystallinity of the first layer 20 and adds hydrogen to the surface of the portion of the insulator 10 that does not overlap with the first layer 20, thereby suppressing nucleation in the metal oxide 30 near the first layer 20.

[0116] Furthermore, the crystallinity-enhancing treatment performed before processing the first layer 20f (see Figures 2A to 2C) can sometimes be omitted. For example, the crystallinity-enhancing treatment of the first layer 20 can be performed after the first layer 20 has been formed. This further enhances the crystallinity of the first layer 20. Additionally, the surface or film quality of the portion of the insulator 10 that does not overlap with the first layer 20 can be modified.

[0117] Furthermore, it is preferable to perform microwave-excited plasma treatment after forming the first layer 20. This can remove impurities such as carbon from the surface of the first layer 20. It can also remove impurities such as carbon from the film of the first layer 20. By keeping the interface between the first layer 20 and the metal oxide 30 cleaner, impurities in the metal oxide 30 can be reduced and the crystallinity of the metal oxide 30 can be further improved.

[0118] Subsequently, the first layer 20 is covered to form a metal oxide 30f on the insulator 10 (see Figures 3A to 3C). Sputtering, ALD, CVD, PLD, etc., can be used to form the metal oxide 30f. For example, indium oxide can be used as the metal oxide 30f. It is preferable to form a metal oxide with low crystallinity as the metal oxide 30f, for example, a metal oxide with an amorphous structure, a metal oxide containing an amorphous structure, or a metal oxide containing both a crystalline structure and an amorphous structure.

[0119] As the metal oxide 30f, it is preferable to use indium oxide deposited by sputtering. As the sputtering gas, hydrogen (H) ２ It is preferable to use a gas containing ). By introducing hydrogen when forming the metal oxide 30f using the sputtering method, it is possible to form a metal oxide 30f with low crystallinity, for example, a metal oxide 30f with an amorphous structure. In addition, nucleation can be suppressed or crystal nuclei other than the first layer 20 can be promoted during the formation of the metal oxide 30f. As the sputtering gas, hydrogen, noble gas (typically argon), and oxygen (O) are preferred. ２ A mixed gas of the following can be used.

[0120] Furthermore, a sputtering gas that does not contain hydrogen may be used. As the sputtering gas, for example, a noble gas or oxygen as a single gas, or a mixture of a noble gas and oxygen, may be used.

[0121] Furthermore, when forming the metal oxide 30f using the sputtering method, the substrate temperature during film formation of the metal oxide 30f is preferably between room temperature (25°C) and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. It is also preferable because it suppresses nucleation. In addition, the metal oxide layer can be formed at room temperature or without heating the substrate.

[0122] For film formation of metal oxide 30f, it is preferable to use a sputtering target with low impurity concentration, that is, high purity. For example, the purity of the sputtering target is 3N or higher, preferably 4N or higher, more preferably 5N or higher, more preferably 6N or higher, still more preferably 7N or higher, 8N or higher, 9N or higher, or 10N or higher. This enables film formation of metal oxide 30f with low impurity concentration.

[0123] Further, as the metal oxide 30f, for example, indium oxide formed into a film by an ALD method is preferably used. In the ALD method, the metal oxide 30f can be formed by using a raw material gas and an oxidizing agent. Indium oxide can be formed by using a precursor containing indium in the raw material gas and an oxidizing agent. Nucleation in the film can be suppressed by using the ALD method that deposits atoms one layer at a time.

[0124] Examples of the indium-containing precursor include trimethylindium (also referred to as TMI or TMIn), triethylindium (also referred to as TEI or TEIn), ethyldimethylindium, tris(1-methylethyl)indium, triisopropylindium (also referred to as TIPIn), tris(2,2,6,6-tetramethyl-3,5-heptanedionato)indium, cyclopentadienylindium (also referred to as InCp), indium(III) chloride, tris(cyclopentadienyl)indium (InCp ３ or Cp ３ In, also referred to as), indium(III) acetylacetonate, [3-(dimethylamino)propyl]dimethylindium (also referred to as DADI), dimethylaminopropyldiisopropylindium (also referred to as DADII), (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, dimethyl(2-propanolato)indium, and the like can be used.

[0125] Examples of the oxidizing agent include oxidizing agents (ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２), and these mixed gases, as well as these plasmas, radicals, ions, etc., can be used.

[0126] For forming the metal oxide 30f film, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, the purity of the precursor should be 3N or higher, preferably 4N or higher, more preferably 5N or higher, more preferably 6N or higher, and even more preferably 7N or higher, 8N or higher, 9N or higher, or 10N or higher. This allows for the formation of a metal oxide 30f film with a low impurity concentration.

[0127] Subsequently, the metal oxide 30f is processed. It is preferable that the processing between the formation of the metal oxide 30f and the processing to increase the crystallinity of the metal oxide 30 be carried out at a lower temperature than the processing to increase the crystallinity of the metal oxide 30. In particular, it is preferable that the processing temperature of the process for processing the metal oxide to have a first region 30_1, a second region 30_2, and a third region 30_3 (see Figure 1B) be lower than the processing temperature of the process for crystallizing the metal oxide.

[0128] When processing the metal oxide 30, a mask 31 and a mask 32 are formed on the metal oxide 30f (see Figures 3D to 3F). The formation of the masks 31 and 32 is preferably carried out at a temperature lower than the crystallization temperature of the metal oxide 30f, for example, preferably 150°C or lower. For the mask 31, it is preferable to use SOG (Spin On Glass). When SOG is used as the mask 31, it is preferable to set the temperature of the heat treatment performed after coating the SOG to 150°C or lower. For the mask 32, it is preferable to use photoresist. In this embodiment, a two-layer mask structure (mask 31 and mask 32) is shown, but it may also be one layer or three or more layers stacked. In this embodiment, exposure and development treatments are performed to form the mask 32.

[0129] Subsequently, the film that forms the mask 31 in the areas where the mask 32 is not formed is removed, and the mask 31 is formed (see Figures 3G to 3I). After that, the mask 32 is removed. For example, if a photoresist is used for the mask 32, it is preferable to remove it with a resist stripping solution or the like.

[0130] Subsequently, the metal oxide 30f in the areas where the mask 31 is not formed is removed, and the metal oxide 30 is formed (see Figures 4A to 4C). If there are areas in the first layer 20 that do not overlap with the mask 31 in a plan view, it is preferable to remove those areas when forming the metal oxide 30. After that, the mask 31 is removed (see Figures 4D to 4F).

[0131] As explained with reference to Figures 1A to 1E, the metal oxide 30 is formed to have a first region 30_1, a second region 30_2, and a third region 30_3.

[0132] Subsequently, it is preferable to perform a treatment to increase the crystallinity of the metal oxide 30 (see Figures 4G to 4I). As mentioned above, it is preferable that the metal oxide 30f is amorphous. Therefore, the treatment to increase crystallinity here can also be called a crystallization treatment.

[0133] Examples of treatments to enhance crystallinity include microwave-excited plasma treatment, heating treatment, plasma treatment, microwave treatment, and light (e.g., ultraviolet light) irradiation treatment. Multiple of these treatments can be performed simultaneously or sequentially. The arrows shown in Figures 4G and 4I indicate heat, plasma, microwave, radical, or light, respectively. By performing these crystallinity-enhancing treatments, the metal oxide 30 can be crystallized.

[0134] As a treatment to improve the crystallinity of the metal oxide 30, for example, heat treatment is preferred. This heat treatment can be carried out at a temperature higher than 150°C and 650°C or lower, preferably between 155°C and 200°C. The heat treatment is preferably carried out in a reduced pressure atmosphere or an inert gas atmosphere (for example, nitrogen gas, noble gas, or both). Alternatively, a mixed atmosphere of nitrogen gas and oxygen gas may be used. When performing the treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. There are no special limitations on the apparatus used for the heat treatment, and it may be an apparatus that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA apparatus such as an LRTA apparatus or GRTA apparatus can be used. Furthermore, by performing the heat treatment, impurities such as water and hydrogen in the metal oxide that forms the semiconductor layer can be reduced.

[0135] By performing this heat treatment, crystal growth of the metal oxide 30 from the first layer 20 can be promoted, and the crystallinity of the metal oxide 30 can be increased. Alternatively, the metal oxide 30 can be crystallized. If the first layer 20 has crystal grains whose crystal orientation <111> is oriented in the film thickness direction of the first layer 20 (the direction perpendicular to the surface on which the first layer 20 is formed), then the metal oxide 30 also has crystal grains whose crystal orientation <111> is oriented in the film thickness direction of the first layer 20 (the direction perpendicular to the surface on which the first layer 20 is formed). Epitaxial growth can occur at least partially in the metal oxide 30 located on the first layer 20, and crystallization can occur. It is estimated that metal oxide 30 with a cubic crystal structure (typically indium oxide) will grow crystals while maximizing the surface area of ​​the {111} plane, which has low interfacial energy. In other words, it is estimated that the {111} plane will preferentially orient in the film thickness direction. Therefore, by performing a treatment to enhance crystallinity, crystal grains (also called <111> oriented crystal grains) whose crystal orientation <111> is oriented parallel to the thickness direction of the insulator 10 (the direction perpendicular to the surface on which the metal oxide 30 is formed) can be formed in the metal oxide 30. Furthermore, on the first layer 20 which is preferentially oriented to the {111} plane in the film thickness direction, a metal oxide 30 that preferentially oriented to the {111} plane in the film thickness direction can be obtained by at least partial epitaxial growth. When the crystal grains of the metal oxide 30 at the edge of the first layer 20 have an orientation of the (111) plane in the film thickness direction, crystal growth is promoted on planes that are perpendicular to it, such as the (1-10) plane, (-110) plane, (0-11) plane, (01-1) plane, (10-1) plane, and (-101) plane. In this case, since there is a degree of rotational freedom in the horizontal direction with respect to the crystal orientation

[111] in the film thickness direction, the plane orientations of the metal oxide 30 in the film thickness direction preferentially grow on planes with low interfacial energy, but a distribution may occur in the crystal plane orientations in the horizontal direction.

[0136] Furthermore, when the first layer 20 uses hexagonal In-Ga-Zn oxide or a metal oxide with a similar crystal structure, a crystal with the {001} plane preferentially oriented can be obtained as described above. Since the atomic arrangement of the (001) plane of the hexagonal system and the (111) plane of the cubic system are close, the (111) plane of the cubic system tends to grow on the (001) plane of the hexagonal system. Therefore, even when a metal oxide such as In-Ga-Zn oxide is used in the first layer 20, indium oxide with the {111} plane preferentially oriented can be formed in the same way as described above.

[0137] The first region 30_1 is a region on the first layer 20 that forms polycrystals preferentially oriented in the {111} plane with respect to the film thickness direction. The second region 30_2 undergoes crystal growth from the first region 30_1. This crystal growth can be called lateral growth. During this process, geometric selection occurs, and the selection of crystal grains occurs due to competition for crystal growth. Subsequently, the metal oxide 30 selects crystal grains by making the width j1 of the third region narrower than the width j2 of the second region, thereby guiding only the crystal grains that have preferentially grown toward the third region 30_3 into the third region 30_3 and allowing them to grow further.

[0138] A part or all of the third region 30_3 in the metal oxide 30 can be used as the channel formation region of the transistor. Furthermore, it is preferable to use the metal oxide 30 such that the direction of current flow in the channel formation region of the transistor and the second direction D2 of the third region 30_3 are parallel. When the third region 30_3 in the metal oxide 30 has an orientation of the (111) plane in the film thickness direction, it is preferable that the second direction D2 (horizontal direction of the metal oxide 30) in the third region 30_3 is oriented to a plane perpendicular to the (111) plane, such as the (1-10) plane, (-110) plane, (0-11) plane, (01-1) plane, (10-1) plane, or (-101) plane. In this case, since there is a degree of rotational freedom in the horizontal direction with respect to the crystal orientation

[111] in the film thickness direction, the plane orientations of the metal oxide 30 in the film thickness direction preferentially grow on planes with low interfacial energy, but a distribution may occur in the crystal plane orientations in the horizontal direction.

[0139] As a result, a crystalline metal oxide 30 can be formed. Furthermore, a metal oxide 30 having crystal grains can be formed. Furthermore, the formation of crystal grain boundaries in the third region 30_3 can be suppressed. Alternatively, the third region 30_3 can be made into a region in which no crystal grain boundaries are observed. Alternatively, the third region 30_3 can be made into a region having a cross-section along the second direction D2 in which no crystal grain boundaries are observed, by analysis using a transmission electron microscope. Alternatively, the third region 30_3 can be made into a crystal that does not contain crystal grain boundaries when analyzed by electron diffraction mapping, where adjacent measurement points with an orientation difference of 5° or more are considered as crystal grain boundaries. Alternatively, the third region 30_3 can be made into a single-grain crystal.

[0140] Furthermore, the third region 30_3 may be provided with one or more channel formation regions. Also, the third region 30_3 may be provided with one or more source regions or drain regions. Furthermore, the third region 30_3 may be provided with one or more transistor channel formation regions. Additionally, the first region 30_1 and the second region 30_2, etc., can be used as either or both source regions or drain regions of transistors.

[0141] [Modified Forms] Modified forms of the first layer 20 and the metal oxide 30 in plan view, as shown in Figures 1A to 4I, are shown in Figures 5A to 8D. Hereafter, we will mainly explain the parts that differ from the explanation of the first layer 20 and the metal oxide 30 shown in Figures 1A to 4I, and for overlapping parts, please refer to the previous explanation, and explanation may be omitted.

[0142] The metal oxide 30 shown in Figures 5A and 5B has a first region 30_1, a second region 30_2, a third region 30_3, and a fourth region 30_4. The fourth region 30_4 is located between the second region 30_2 and the third region 30_3. The fourth region 30_4 is in contact with the insulator 10.

[0143] The metal oxide 30 shown in Figure 5A has a shape in which the width j3 of the fourth region 30_4 along the first direction D1 narrows continuously from the width j2 of the second region 30_2 along the first direction D1 to the width j1 of the third region 30_3 along the first direction D1. Figure 6A shows a modified example of the metal oxide 30 shown in Figure 5A, in which the corners are rounded. By adopting a shape like that of Figure 6A, unexpected nucleation near the corners can be suppressed. By adopting a shape like that of Figure 5A or Figure 6A, the crystal grains growing from the first region 30_1 can be grown significantly in the second region 30_2 and the fourth region 30_4. For this reason, the fourth region 30_4 can also be said to be a part of the second region 30_2. Then, of the crystal grains grown in the second region 30_2 and the fourth region 30_4, only those crystal grains that have grown toward the third region 30_3 can be guided toward the third region 30_3 and allowed to grow further. Because the width j3 of the fourth region 30_4 narrows from the first region 30_1 toward the third region 30_3, the selection of crystal grains constituting the third region 30_3 is performed more effectively, and the formation of crystal grain boundaries in the third region 30_3 can be suppressed.

[0144] The metal oxide 30 shown in Figure 5B has a shape in which the width j3 of the fourth region 30_4 along the first direction D1 is narrower than the width j2 of the second region 30_2 along the first direction D1, and wider than the width j1 of the third region 30_3 along the first direction D1. Figure 6B shows a modified example of the metal oxide 30 shown in Figure 5B, in which the corners are rounded. By adopting a shape like that of Figure 6B, unexpected nucleation near the corners can be suppressed. By adopting a shape like that of Figure 5B or Figure 6B, the crystal grains growing from the first region 30_1 can be grown larger in the second region 30_2 and the fourth region 30_4. For this reason, the fourth region 30_4 can also be said to be a part of the second region 30_2. In the second region 30_2 and the fourth region 30_4, the crystal grains can be grown significantly. Of the crystal grains growing from the first region 30_1, only those that grow toward the fourth region 30_4 are grown in the fourth region 30_4. Furthermore, only those crystal grains that have grown toward the third region 30_3 are guided to the third region 30_3 for further crystal growth. By adding and forming the fourth region 30_4 in this way, the selection of crystal grains constituting the third region 30_3 is performed more effectively, and the formation of crystal grain boundaries in the third region 30_3 can be suppressed.

[0145] The metal oxide 30 shown in Figure 5C has a first region 30_1, a second region 30_2, and a third region 30_3, as well as a fourth region 30_4 and a fifth region 30_5. The fourth region 30_4 is adjacent to the second region 30_2 and is located between the second region 30_2 and the third region 30_3. The fifth region 30_5 is adjacent to the fourth region 30_4 and is located between the fourth region 30_4 and the third region 30_3. Furthermore, the fourth region 30_4 and the fifth region 30_5 are in contact with the insulator 10. The metal oxide 30 shown in Figure 5C has a shape in which the width j3 of the fourth region 30_4 along the first direction D1 is narrower than the width j2 of the second region 30_2 along the first direction D1 and the width j1 of the third region 30_3 along the first direction D1. The fifth region 30_5 has a shape that extends continuously from the width j3 of the fourth region 30_4 along the first direction D1 to the width j1 of the third region 30_3 along the first direction D1. By having such a continuously extending shape, unexpected nucleation near the corners can be suppressed. Figure 6C shows a modified example of the metal oxide 30 shown in Figure 5C, in which the corners are rounded. By having a shape like that in Figure 6C, unexpected nucleation near the corners can be suppressed. By giving the metal oxide 30 the shape shown in Figure 5C or Figure 6C, only the crystal grains that grow toward the fourth region 30_4 from the crystal grains growing from the first region 30_1 can be grown in the fourth region 30_4, and further, only the crystal grains that have grown toward the third region 30_3 can be guided to the third region 30_3 and allowed to grow there. By making the width j3 of the fourth region 30_4 along the first direction D1 narrower than the width j1 of the third region 30_3 along the first direction D1, the distance from the first region 30_1 to the fourth region 30_4 can be made shorter than the distance from the first region 30_1 to the third region 30_3 of the metal oxide 30 shown in Figures 1A to 1E.

[0146] The metal oxide 30 shown in Figure 5D has an opening in the second region 30_2 between the first region 30_1 and the third region 30_3. The opening may be rectangular, circular, elliptical, or polygonal in plan view. The crystal grains can be grown larger in the distance from the first region 30_1 to the third region 30_3. By providing this opening, in the second region 30_2, only the crystal grains that have grown toward the third region 30_3, among those that have grown while avoiding the opening, can be guided toward the third region 30_3 and allowed to grow there. Figure 6D shows a modified example of the metal oxide 30 shown in Figure 5D, in which the corners are rounded. By giving the metal oxide 30 the shape shown in Figure 6D, unexpected nucleation near the corners can be suppressed.

[0147] The metal oxide 30 shown in Figure 5E has an L-shape in plan view. The metal oxide 30 has a shape in which the width j1 of the third region along the first direction D1 is narrower than the width j2 of the second region along the first direction D1. Furthermore, the metal oxide 30 shown in Figure 5E has a structure in which the third region 30_3 is in contact with the corner of the second region 30_2. In addition, the shape in which one side of the third region 30_3 in the second direction D2 overlaps with the extension of one side of the second region 30_2 in the second direction D2. The crystal grains can be grown to a large size in the distance from the first region 30_1 to the third region 30_3. By giving the metal oxide 30 the shape shown in Figure 5E, it is possible to guide only the crystal grains that have grown toward the third region 30_3 from among the crystal grains that have grown along one side of the second direction D2 of the second region 30_2 toward the third region 30_3 and allow them to grow crystals toward the third region 30_3. Figure 5F has a shape obtained by horizontally inverting and superimposing the shape of the metal oxide 30 shown in Figure 5E. As shown in Figure 5F, multiple third regions 30_3 can be provided for one first region 30_1. Figure 5F shows the third region 30_3a and the third region 30_3b. Each of the multiple third regions 30_3 can be used as a channel formation region of a transistor. In this case, it is preferable that the width along the first direction D1 (for example, width j1a, width j1b) in each third region 30_3 is narrower than the width j2 of the second region 30_2. Furthermore, Figures 6E and 6F show modified examples of the metal oxide 30 shown in Figures 5E and 5F, respectively, in which the corners are rounded. By giving the metal oxide 30 the shape shown in Figures 6E and 6F, unexpected nucleation near the corners can be suppressed.

[0148] Furthermore, Figures 5G and 5H show examples in which the position of the first layer 20 shown in Figures 5E and 5F is rotated by 90° relative to the metal oxide 30, respectively. In the second region 30_2 between the first region 30_1 and the third region 30_3, crystal grains can be grown significantly. In Figures 5G and 5H, among the crystal grains that have grown along the direction parallel to the first direction D1 of the second region 30_2, only those crystal grains that have grown toward the third region 30_3 can be guided toward the third region 30_3 and allowed to grow further. By guiding the crystal grains that have grown along the direction parallel to the first direction D1 of the second region 30_2 toward the third region 30_3 extending in the second direction D2, the selection of crystal grains constituting the third region 30_3 can be performed more effectively, and the formation of crystal grain boundaries in the third region 30_3 can be suppressed. Figures 6G and 6H show modified examples of Figures 5G and 5H, respectively, in which the corners are rounded. By giving the metal oxide 30 the shape shown in Figures 6G and 6H, unexpected nucleation near the corners can be suppressed.

[0149] Figures 7A to 7I show modified examples of the first layer 20 in plan view. Figures 7A to 7C show an example in which, in plan view, two opposite sides of the first layer 20 are curved outward. Figures 7D to 7F show an example in which, in plan view, two opposite sides of the first layer 20 are curved inward. Figures 7G to 7I show an example in which, in plan view, the first layer 20 is circular. The shape of the first layer 20 in plan view is not limited to these, and may be rectangular, elliptical, or polygonal.

[0150] Furthermore, the first layer 20 only needs to be in contact with the metal oxide 30 in some part. In other words, the first layer 20 may have regions that do not overlap with the metal oxide 30.

[0151] In one embodiment of the present invention, multiple metal oxides 30 and first layers 20 can be arranged at any arbitrary positions. For example, Figure 8A shows an example in which the metal oxide 30 and first layer 20 shown in Figure 5A are arranged in two rows and two columns. Also, for example, Figure 8C shows an example in which the metal oxide 30 and first layer 20 shown in Figure 5H are arranged in two rows and two columns. Furthermore, Figure 8B shows a shape in which multiple metal oxides 30 and first layers 20 shown in Figure 5A are combined. As shown in Figure 8B, the metal oxide 30 can also be arranged so that multiple third regions 30_3 are attached to one first layer 20. Furthermore, Figure 8D shows a shape in which multiple metal oxides 30 and first layers 20 shown in Figure 5H are combined. As shown in Figure 8D, the metal oxide 30 can also be arranged so that multiple third regions 30_3 are attached to one first layer 20. Furthermore, the combination of the metal oxide 30 and the first layer 20 in plan view is not limited to Figures 8A to 8D, and the shapes of the metal oxide 30 and the first layer 20 described above may be arbitrarily combined. In this way, multiple metal oxides 30 can be arranged in close proximity. Also, the metal oxide 30 can have multiple third regions 30_3 for one first layer 20. Therefore, when the metal oxide 30 is used as a semiconductor layer in a semiconductor device, a semiconductor device with a small occupied area can be obtained. In addition, a semiconductor device that can be arranged at high density can be obtained.

[0152] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part. Furthermore, if multiple configuration examples or modifications are shown within a single embodiment in this specification, these configuration examples or modifications can be combined as appropriate.

[0153] (Embodiment 2) This embodiment describes an example of the configuration of a semiconductor device according to one aspect of the present invention. The semiconductor device according to one aspect of the present invention has a transistor. The semiconductor layer of the transistor exemplified below can be made of the metal oxide exemplified in Embodiment 1.

[0154] [Example of Semiconductor Device Configuration 1] Figures 9A to 10C show an example of a semiconductor device having a transistor 50. Figure 9A is a plan view of the semiconductor device having the transistor 50. Figure 9B is an enlarged plan view of the first layer 20, metal oxide 30, and conductor 63 shown in Figure 9A. Figure 10A is a cross-sectional view between the dashed lines B1 and B2 shown in Figure 9A. Figure 10B is a cross-sectional view between the dashed lines B3 and B4 shown in Figure 9A. Figure 10C is a cross-sectional view between the dashed lines B5 and B6 shown in Figure 9A.

[0155] The transistor 50 has at least a conductor 57a, a conductor 57b, a conductor 63, a metal oxide 30, and an insulator 62. The transistor 50 also has a conductor 53 and an insulator 54.

[0156] Part or all of the conductor 57a functions as either the source electrode or the drain electrode of the transistor 50. Part or all of the conductor 57b functions as either the source electrode or the drain electrode of the transistor 50. Part or all of the conductor 63 functions as the first gate electrode of the transistor 50. Part or all of the metal oxide 30 functions as the semiconductor of the transistor 50 and functions as a channel-forming region. Part or all of the insulator 62 functions as the first gate insulating film of the transistor 50. Also, part or all of the conductor 53 functions as the second gate electrode of the transistor 50. Part or all of the insulator 54 functions as the second gate insulating film of the transistor 50.

[0157] Furthermore, when transistor 50 is used as a memory cell, one or both of conductors 53 or 63 can function as word lines. Also, conductor 67a or conductor 67b can function as bit lines.

[0158] The semiconductor device having the transistor 50 shown in Figures 9A to 10C has an insulator 51 (insulator 51_1, insulator 51_2 on insulator 51_1) on a substrate (not shown). It also has an insulator 52 on insulator 51. The conductor 53 (conductor 53_1, conductor 53_2 on conductor 53_1) is positioned so as to be embedded in the insulator 52. In other words, the conductor 53 (conductor 53_1, conductor 53_2 on conductor 53_1) is located in the grooves or openings of the insulator 52. Furthermore, the upper surface of the conductor 53 located in the grooves or openings of the insulator 52 and the upper surface of the insulator 52 are at the same height from the substrate surface.

[0159] The insulators 54 (insulator 54_1, insulator 54_2 on insulator 54_1, and insulator 54_3 on insulator 54_2) are located on the conductor 53 and the insulator 52. The insulators 54 can refer to the description of insulator 10.

[0160] A first layer 20 is provided on the insulator 54. The metal oxide 30 is positioned to cover the first layer 20. It is preferable to use indium oxide for the metal oxide 30. As shown in Figure 9B, the metal oxide 30 has a first region 30_1, a second region 30_2, and a third region 30_3. The second region 30_2 is adjacent to the first region 30_1 and is located between the first region 30_1 and the third region 30_3. The first region 30_1 is in contact with the first layer 20. The second region 30_2 and the third region 30_3 are in contact with the insulator 54. The first layer 20, the metal oxide 30, the first region 30_1, the second region 30_2, and the third region 30_3 can be described in reference to Embodiment 1. In Figure 9B, the grain boundaries of the metal oxide 30 are shown by solid lines.

[0161] The conductor 57 (conductor 57_1, conductor 57_2 on conductor 57_1) is located on the metal oxide 30. The conductor 57 also has regions that are in contact with the first region 30_1, the second region 30_2, and the third region 30_3. The insulator 58 is located on the conductor 57. The insulator 59 is located so as to cover the insulator 58, the conductor 57, the metal oxide 30, and the first layer 20. The insulator 59 is in contact with the side surfaces of the metal oxide 30, the side surfaces of conductor 57_1, the side surfaces of conductor 57_2, and the side surfaces of insulator 58. The insulator 59 is also in contact with insulator 54. Furthermore, if the insulator 54 has, for example, an insulator 54_1, an insulator 54_2 on insulator 54_1, and an insulator 54_3 on insulator 54_2, as shown in Figure 10A, then the insulator 59 is in contact with the side surface of insulator 54_3 and insulator 54_2.

[0162] Insulator 60 is located on insulator 59. Grooves are provided in conductor 57, insulator 58, insulator 59, and insulator 60. Insulator 61 is in contact with the side surfaces of conductor 57_2, insulator 58, insulator 59, and insulator 60 in the grooves. Insulator 62 is in contact with insulator 61, the side surface of conductor 57_1, and the upper surface of metal oxide 30. Conductors 63 (conductor 63_1, conductor 63_2 on conductor 63_1) are positioned so as to sandwich the metal oxide 30 and insulator 62 between them. Conductor 63_1 is located between conductor 63_2 and insulator 62. Insulators 61, 62, and conductor 63 are located in the grooves provided in insulator 60. The upper surface of conductor 63 is at the same height from the substrate surface as the upper surface of insulator 60.

[0163] The insulators 64 (insulator 64_1, insulator 64_2 on insulator 64_1, and insulator 64_3 on insulator 64_2) are located on insulator 60. Insulator 64 is in contact with insulator 60, insulator 61, insulator 62, and conductor 63.

[0164] Insulators 58, 59, 60, and 64 (insulator 64_1, insulator 64_2 on insulator 64_1, and insulator 64_3 on insulator 64_2) have openings. Insulator 65 is located in one of these openings and is in contact with the sides of insulator 58, insulator 59, insulator 60, insulator 64_1, insulator 64_2, and insulator 64_3 at the openings. Conductors 66 (conductor 66_1 and conductor 66_2 on conductor 66_1) are located in the openings, are in contact with insulator 65, and are in contact with conductor 57. Conductor 66_1 is located between insulator 65 and conductor 66_2. Conductor 67 is located on insulator 64. Conductor 67a is connected to conductor 57a via conductor 66a. The conductor 67b is connected to the conductor 57 via the conductor 66b.

[0165] In transistor 50, the metal oxide 30 has a first portion that overlaps with the conductor 63. More specifically, the third region 30_3 of the metal oxide 30 has a first portion that overlaps with the conductor 63. This region can function as a channel-forming region of the transistor. In a plan view, it is preferable that the width j1 of the third region along a first direction D1 perpendicular to the channel length direction of the transistor is narrower than the width j2 of the second region along the first direction D1 (see Figure 9B).

[0166] Furthermore, the first region 30_1 and the second region 30_2, etc., can be used as either the source region or the drain region of the transistor, or both.

[0167] Furthermore, in the transistor 50, the metal oxide 30 has a second portion in contact with the conductor 57a and a third portion in contact with the conductor 57b. Also, the third region 30_3 of the metal oxide 30 has a second portion in contact with the conductor 57a and a third portion in contact with the conductor 57b. In the metal oxide 30, the first portion that overlaps with the conductor 63 is located between the second portion in contact with the conductor 57a and the third portion in contact with the conductor 57b.

[0168] Furthermore, in the transistor 50, by using the metal oxide 30 described in Embodiment 1, the first portion of the third region 30_3 of the metal oxide 30 that overlaps with the conductor 63 does not show any grain boundaries when viewed in a cross-sectional view parallel to the channel length direction of the transistor, as can be seen by analysis using a transmission electron microscope.

[0169] The first portion of the third region 30_3 that overlaps with the conductor 63 can be a region where no grain boundaries are observed. Alternatively, the first portion of the third region 30_3 that overlaps with the conductor 63 can be a single-grain crystal. Alternatively, the first portion of the third region 30_3 that overlaps with the conductor 63 can be analyzed using a transmission electron microscope to determine a region having a cross-section along the second direction D2 where no grain boundaries are observed. Furthermore, the first portion of the third region 30_3 that overlaps with the conductor 63 can be analyzed using electron diffraction mapping to determine a crystal that does not contain grain boundaries when adjacent measurement points have an orientation difference of 5° or more. In addition, the metal oxide 30 can have crystal grains that overlap with a pair of ends of the conductor 63 that face each other in the channel length direction (second direction D2). This makes it possible to obtain a semiconductor device with good electrical properties, or a semiconductor device that can carry a large current, or a semiconductor device with high reliability. Furthermore, one or more channel-forming regions may be provided in the third region 30_3.

[0170] [Regarding the constituent materials] The following describes the materials that can be used in the semiconductor device of this embodiment. Note that each layer constituting the semiconductor device of this embodiment may be a single-layer structure or a multilayer structure.

[0171] <Substrate> The substrate for the semiconductor device shown in this embodiment can be any of the following substrates as appropriate.

[0172] For the substrate used to form the transistor, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Furthermore, there are semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates having metal nitrides or metal oxides can also be used. Furthermore, there are substrates in which a conductive layer or semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or insulating layer is provided on a conductive substrate. Alternatively, substrates with elements mounted on them may be used. Elements mounted on the substrate include capacitive elements, resistive elements, switching elements (including transistors), light-emitting elements, and memory elements.

[0173] <Conductors> The conductors 53, 57, 63, 66, and 67 of the semiconductor device shown in this embodiment can be appropriately made from the following conductors. It is preferable to use conductors with high conductivity for the conductors of the semiconductor device. For these conductors, it is preferable to use metal elements selected from, for example, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing such metal elements. Alternatively, nitrides of the above metal elements or alloys containing the above metal elements, or oxides of the above metal elements or alloys containing the above metal elements may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. These are preferred because they are conductors that are resistant to oxidation or maintain their conductivity even after oxidation. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used. Furthermore, tantalum and tantalum nitride are preferred as conductors because they have barrier properties against hydrogen.

[0174] Furthermore, conductive oxides can also be used as conductors in semiconductor devices. Examples of conductive oxides include indium oxide, indium tin oxide (In-Sn oxide, also called ITO), silicon-containing indium tin oxide (In-Sn-Si oxide, also called ITSO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, and In-Ti-Sn oxide. Conductive oxides containing indium are particularly preferred due to their high conductivity. Alternatively, oxide semiconductors applicable to semiconductors can also be used as conductors by increasing the carrier concentration.

[0175] Furthermore, the conductor of the semiconductor device may be a single-layer or multilayer structure of two or more layers using the aforementioned conductor. For example, a single-layer structure of conductive oxide, a single-layer structure of tantalum nitride, a single-layer structure of tungsten, etc., can be used. Also, a two-layer structure in which a conductive oxide is laminated on tungsten, a two-layer structure in which tungsten is laminated on tantalum nitride, a two-layer structure in which tungsten is laminated on a conductive oxide, a two-layer structure in which tungsten is laminated on titanium nitride, etc. can be used. In addition, a three-layer structure in which titanium nitride is laminated on tantalum nitride and tungsten is laminated on the titanium nitride, a three-layer structure in which aluminum is laminated on titanium and titanium is laminated on the aluminum, a three-layer structure in which tungsten is laminated on a titanium nitride film and a conductive oxide is laminated on the tungsten, a three-layer structure in which tungsten is laminated on a conductive oxide and a conductive oxide is laminated on the tungsten film, etc., can be used. Furthermore, a four-layer structure can be used in which tantalum nitride is laminated on tantalum, titanium nitride is laminated on the tantalum nitride, and tungsten is laminated on the titanium nitride; a four-layer structure can be used in which tantalum is laminated on tantalum nitride, titanium nitride is laminated on the tantalum, and tungsten is laminated on the titanium nitride; a four-layer structure can be used in which titanium nitride is laminated on tantalum nitride, tungsten is laminated on the titanium nitride, and a conductive oxide is laminated on the tungsten. In addition, a five-layer structure can be used in which titanium nitride is laminated on titanium, aluminum is laminated on the titanium nitride, titanium is laminated on the aluminum, and titanium nitride is laminated on the titanium.

[0176] <Insulators> The insulators 51, 52, 54, 58, 59, 60, 61, 62, 64, and 65 of the semiconductor device shown in this embodiment can be appropriately replaced with the insulators shown below. Examples of insulators include insulating oxides, insulating nitrides, insulating oxidnitrides, insulating nitride oxides, insulating metal oxides, insulating metal oxidnitrides, and insulating metal nitride oxides.

[0177] As transistors become smaller and more integrated, thinning of the gate insulating film can lead to problems such as leakage current. Using a high-k dielectric constant insulator for the gate insulating film allows for lower voltage operation while maintaining the physical film thickness. On the other hand, using a low dielectric constant insulator for the interlayer insulating layer reduces parasitic capacitance between wiring. Therefore, it is preferable to select materials according to the function of the insulator.

[0178] Examples of insulators with a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium-zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium. In addition, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.

[0179] Examples of insulators with a lower dielectric constant compared to high-k materials include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0180] Examples of insulators with high dielectric strength include silicon oxide, silicon oxide nitride, silicon nitride oxide, and silicon nitride.

[0181] Examples of insulators that suppress leakage current include silicon oxide and silicon oxide-nitride.

[0182] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or in a multilayer structure. Specifically, examples include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride, and silicon nitride.

[0183] Furthermore, it is preferable that the insulator in contact with the oxide semiconductor, such as a gate insulating film, or an insulator provided near the oxide semiconductor, is an insulator having a region containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). For example, an insulator having a region containing excess oxygen can reduce the oxygen vacancies in the oxide semiconductor by releasing oxygen and being in contact with or near the oxide semiconductor. Examples of insulating materials that easily form regions containing excess oxygen include silicon oxide, silicon oxynitride, or silicon oxide having vacancies.

[0184] For insulating layers that come into contact with or near a metal oxide exhibiting semiconductor properties, such as those used in transistor channels, it is preferable to use an insulator that has the function of capturing or fixing hydrogen, or an insulator that has barrier properties against hydrogen. This can suppress the diffusion of hydrogen into the metal oxide.

[0185] Examples of insulators that have the function of capturing or fixing hydrogen include hafnium oxide films, hafnium silicate films, and aluminum oxide films.

[0186] Furthermore, the function of capturing or fixing substance Q can also be described as having the property of making substance Q difficult to diffuse. In this specification, barrier properties refer to the property of making substance Q difficult to diffuse (also referred to as the property of making substance Q difficult to permeate, the property of having low permeability of substance Q, or the function of suppressing the diffusion of substance Q). Therefore, the function of capturing or fixing substance Q can be rephrased as barrier properties. When substance Q is described, hydrogen refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance that is bonded with hydrogen, such as [substance name]. Furthermore, when substance Q is described, unless otherwise specified, it refers to impurities in the channel-forming region or semiconductor layer, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ２ O, NO, and NO ２ This refers to at least one of the following: (etc.), and copper atoms, etc. Furthermore, when oxygen is described as substance Q, it refers to at least one of the following: for example, an oxygen atom and an oxygen molecule, etc.

[0187] Examples of insulators that have barrier properties against hydrogen include silicon nitride, hafnium oxide, aluminum oxide, magnesium oxide, gallium oxide, or silicon nitride oxide.

[0188] Examples of insulators that have barrier properties against oxygen include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0189] Furthermore, a ferroelectric material may be used as the insulator in the semiconductor device. Examples of ferroelectric materials include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide.

[0190] Furthermore, a ferroelectric material can be used in at least a portion of the gate insulating film of the transistor. A transistor having such a gate insulating film can function as an FeFET (Ferroelectric Field Effect Transistor).

[0191] <Gate Insulator> The insulator 62 of the semiconductor device shown in this embodiment can be made from the insulators listed below as appropriate. The insulator 62 functions as a gate insulating film of the transistor. The gate insulating film, such as the insulator 62, can be made from the insulators listed above as appropriate. The gate insulating film, such as the insulator 62, can be made from a single layer or a laminated structure of two or more layers. When the gate insulating film is made from a laminated structure of two or more layers, it is preferable to form it from two or more types of films. By making the gate insulating film, such as the insulator 62, from two or more types of films, multiple functions can be provided.

[0192] Furthermore, the insulator 62 can be made by laminating one or more insulators with a high relative permittivity, an insulator with high dielectric strength, and an insulator that suppresses leakage current. In addition, a ferroelectric material can be used for the insulating layer such as the insulator 62.

[0193] The insulator 62 can have a two-layer structure, comprising a first insulating layer in contact with the metal oxide 30 and a second insulating layer on the conductor 63 side, which functions as the gate electrode. The first insulating layer can be made of an insulator having the function of capturing or fixing hydrogen, and the second insulating layer can be made of an insulator having hydrogen barrier properties, an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, or an insulator having oxygen barrier properties. With such a configuration, the hydrogen concentration of the metal oxide 30 can be reduced, and the diffusion of hydrogen into the metal oxide 30 can be suppressed. In addition, the diffusion of oxygen to the conductor 63 side can be prevented, and the oxidation of the conductor 63 can be suppressed. This makes it possible to realize a highly reliable transistor. When the insulator 62 has a two-layer structure, for example, a hafnium oxide film or a hafnium silicate film can be used as the first insulating layer, and a silicon nitride film can be used as the second insulating layer.

[0194] Alternatively, an insulator with high dielectric strength or an insulator that suppresses leakage current can be used as the first insulating layer, and an insulator having the function of capturing or fixing hydrogen, an insulator having barrier properties against hydrogen, an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, or an insulator having barrier properties against oxygen can be used as the second insulating layer. With such a configuration, the gate leakage current can be reduced and the diffusion of hydrogen into the metal oxide 30 can be suppressed. In addition, the diffusion of oxygen to the conductor 63 can be prevented and the oxidation of the conductor 63 can be suppressed. Therefore, a highly reliable transistor can be realized. When the insulator 62 has a two-layer structure, for example, a silicon oxide film can be used as the first insulating layer and a hafnium oxide film can be used as the second insulating layer.

[0195] Alternatively, the insulator 62 can have a three-layer structure comprising a first insulating layer, a second insulating layer, and a third insulating layer. In this case, the first insulating layer is in contact with the metal oxide 30, and the first insulating layer, the second insulating layer, and the third insulating layer are positioned in that order from the metal oxide 30 side toward the conductor 63 which functions as the gate electrode side. The first insulating layer can be made of an insulator with high dielectric strength or an insulator that suppresses leakage current, the second insulating layer can be made of an insulator that has the function of capturing or fixing hydrogen, and the third insulating layer can be made of an insulator that has barrier properties against hydrogen, an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, or an insulator that has barrier properties against oxygen. With such a configuration, gate leakage current can be reduced and the diffusion of hydrogen into the metal oxide 30 can be suppressed. In addition, the diffusion of oxygen toward the conductor 63 side can be prevented and oxidation of the conductor 63 can be suppressed. Therefore, a highly reliable transistor can be realized. If the insulator 62 has a three-layer structure, for example, a silicon oxide film can be used as the first insulating layer, a hafnium oxide film or a hafnium silicate film can be used as the second insulating layer, and a silicon nitride film can be used as the third insulating layer.

[0196] Alternatively, the insulator 62 can have a four-layer structure comprising a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer. In this case, the first insulating layer is in contact with the metal oxide 30, and the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer are positioned in that order from the metal oxide 30 side toward the conductor 63 which functions as the gate electrode side. The first insulating layer can be an insulator having barrier properties against oxygen, or an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen; the second insulating layer can be an insulator that suppresses insulating leakage current with high dielectric strength; the third insulating layer can be an insulator having the function of capturing or fixing hydrogen; and the fourth insulating layer can be an insulator having barrier properties against hydrogen, or an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen. With such a configuration, the detachment of oxygen from the metal oxide 30 can be suppressed. In addition, the gate leakage current can be reduced and the diffusion of hydrogen into the metal oxide 30 can be suppressed. Furthermore, the diffusion of oxygen to the conductor 63 is prevented, and oxidation of the conductor 63 can be suppressed. Therefore, a highly reliable transistor can be realized. When the insulator 62 has a four-layer structure, for example, an aluminum oxide film can be used as the first insulating layer, a silicon oxide film as the second insulating layer, a hafnium oxide film or hafnium silicate film as the third insulating layer, and a silicon nitride film as the fourth insulating layer.

[0197] The gate insulating film, such as the insulator 62, is preferably a thin film. For example, by setting the film thickness of the insulator 62 to 1 nm to 50 nm, 1 nm to 20 nm, and preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region. The insulator 62 only needs to have a region with the above-mentioned film thickness in at least a part of it.

[0198] Furthermore, the film thickness of each layer constituting the insulating layer such as the insulator 62 is preferably 0.1 nm to 40 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulator 62 only needs to have a region with the above-mentioned film thickness in at least a part of it.

[0199] As a specific example of the insulator 62, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the metal oxide 30 side, with thicknesses of 1 nm, 2 nm, 2 nm, and 1 nm from the metal oxide 30 side. Alternatively, it is preferable to have thicknesses of 1 nm, 30 nm, 1.5 nm, and 1 nm from the metal oxide 30 side. Alternatively, it is preferable to have thicknesses of 1 nm, 30 nm, 1.5 nm, and 5 nm from the metal oxide 30 side.

[0200] Another specific example is to use a four-layer structure in which a hafnium oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the metal oxide 30 side, and it is preferable that the thicknesses of these layers be 1 nm, 2 nm, 2 nm, and 1 nm from the metal oxide 30 side.

[0201] Another specific example is to use a two-layer structure in which a silicon oxide film and a hafnium oxide film are stacked in that order from the metal oxide 30 side, and it is preferable that the thicknesses of these layers be 1 nm and 1.5 nm from the metal oxide 30 side.

[0202] Furthermore, as a specific example, it is preferable to use a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in that order from the metal oxide 30 side, with the thicknesses of these layers being 30 nm, 1.5 nm, and 5 nm from the metal oxide 30 side.

[0203] [Example of Manufacturing Method for Semiconductor Device Configuration Example 1] An example of a manufacturing method for a semiconductor device according to one aspect of the present invention will be described using Figures 11A to 13B. Figures 11A to 13B are cross-sectional views between the dashed lines B1 and B2 shown in Figure 9A. Here, a semiconductor device having the transistor 50 exemplified in the above semiconductor device configuration example 1 will be used as an example.

[0204] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. ALD methods include thermal ALD, which uses only thermal energy to carry out the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, and photo-CVD. Other methods include metal-organic CVD (MOCVD) and metal CVD.

[0205] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet film deposition methods such as spin coating, dip coating, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0206] Furthermore, lithography or the like can be used when processing the thin films that constitute the semiconductor device. Alternatively, the thin films may be processed by nanoimprint lithography, sandblasting, lift-off lithography, or the like. In addition, island-shaped thin films may be directly formed by a film deposition method using a shielding mask such as a metal mask.

[0207] There are two main lithography methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0208] Thin film etching can be performed using methods such as dry etching, wet etching, ashing, plasma treatment, and reverse sputtering. Sandblasting may also be used for etching thin films.

[0209] An insulator 51 is formed on a substrate (not shown) (see Figure 11A). It is preferable to use one or more insulators selected from those having the function of suppressing the permeation of impurities such as hydrogen and oxygen, insulators having the function of capturing or fixing hydrogen, or insulators having barrier properties against hydrogen or oxygen. The above-mentioned insulators can be used as insulators 51_1 and insulators 51_2. For insulator 51_1, it is particularly preferable to use an insulator such as silicon nitride or silicon oxide nitride. For insulator 51_2, it is particularly preferable to use an insulator such as aluminum oxide. This can suppress the diffusion of impurities from structures below the insulator 51 to the metal oxide 30 or insulator 62. For forming the insulator 51, sputtering, ALD, CVD, PLD, etc., can be used. Figure 11A shows an example where the insulator 51 has a two-layer structure consisting of insulator 51_1 and insulator 51_2 on top of insulator 51_1, but it can also be a single-layer or a laminated structure of three or more layers.

[0210] Subsequently, the insulator 52 is deposited on the insulator 51 (see Figure 11A). It is preferable to use one or more insulators with a lower dielectric constant than the high-k material for the insulator 52. This reduces parasitic capacitance between wirings. As the insulator 52, the above-mentioned insulators can be used, but it is particularly preferable to use insulators such as silicon oxide and silicon oxynitride. For depositing the insulator 52, sputtering, ALD, CVD, PLD, etc., can be used.

[0211] Subsequently, a resist mask is formed on the insulator 52, and then grooves reaching the insulator 51 are formed in the insulator 52 by etching. After that, a conductive film to become the conductor 53 is deposited. Then, the conductor 53 on the insulator 52 is removed by the CMP method, and the conductor 53 is formed so as to be embedded in the insulator 52. In other words, the conductor 53 is formed so as to be located in the grooves of the insulator 52. Furthermore, the conductor 53 is formed so that the upper surface of the conductor 53 located in the grooves of the insulator 52 and the upper surface of the insulator 52 are at the same height from the substrate surface.

[0212] The conductor 53 can be formed using film deposition methods such as metal CVD, sputtering, and ALD. Figure 11A shows an example of a two-layer structure of the conductor 53 consisting of conductor 53_1 and conductor 53_2 on conductor 53_1, but it can be a single layer or a laminated structure of three or more layers. One or more of the conductors described above under <Conductors> can be used for the conductor 53. Titanium nitride is particularly preferred as conductor 53_1. Tungsten is particularly preferred as conductor 53_2. By using a material with lower resistance than the conductor used for conductor 53_1, such as tungsten, the wiring resistance of the conductor 53 can be reduced. Furthermore, by using titanium nitride as conductor 53_1, for example, oxidation of the conductor used for conductor 53_2 can be suppressed.

[0213] Subsequently, insulators 54 (insulators 54_1, 54_2, and 54_3) are deposited on the insulator 52 and the conductor 53 (see Figure 11B). Sputtering, ALD, CVD, PLD, and other methods can be used to deposit the insulators 54.

[0214] As the insulator 54, one or more of the insulators described above under <Insulator> can be used. For example, silicon nitride, silicon oxide nitride, aluminum oxide, hafnium oxide, silicon oxide, etc., can be used in a single layer or laminated form in appropriate combinations. Figure 11B shows an example of a three-layer structure in which the insulator 54 is laminated with insulator 54_1, insulator 54_2 on insulator 54_1, and insulator 54_3 on insulator 54_2, but it can be a single layer, two layers, or a laminated structure of four or more layers. In addition, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used for the insulator 54 (insulator 54_1, insulator 54_2, insulator 54_3). Furthermore, a material capable of ferroelectricity can be used for the insulator 54 (insulator 54_1, insulator 54_2, insulator 54_3).

[0215] One or both of the insulator 54_1 or insulator 54_2 can be an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, an insulator having the function of capturing or fixing hydrogen, an insulator having barrier properties against hydrogen, or an insulator having barrier properties against oxygen. For insulator 54_3, it is preferable to use an insulator with high dielectric strength or that suppresses leakage current. For example, silicon nitride is particularly preferable as insulator 54_1. Hafnium oxide is particularly preferable as insulator 54_2. Silicon oxide is particularly preferable as insulator 54_3. When insulators 54_1 and insulators 54_2 are formed using such materials, insulators 54_1 and insulators 54_2 function as layers that suppress the release of oxygen from one or both of the metal oxide 30 or insulator 62 to the substrate side, or the diffusion of impurities such as hydrogen from the layer below insulators 54_1 and insulators 54_2 to the metal oxide 30. By providing insulators 54_1 and 54_2, the formation of oxygen vacancies in the metal oxide 30 can be suppressed.

[0216] Subsequently, the first layer 20 and the metal oxide 30 are formed on the insulator 54 (see Figure 11C). The description of Embodiment 1 can be used when forming the first layer 20 and the metal oxide 30. Furthermore, the description of Embodiment 3 can be used as the material for the first layer 20 and the metal oxide 30.

[0217] Subsequently, conductors 57 (conductor 57_1, conductor 57_2) and insulators 58 are formed on the metal oxide 30 (see Figure 11D). More specifically, conductors 57 (conductor 57_1, conductor 57_2) and insulators 58 are formed as films on the metal oxide 30 and the first layer 20. After that, a resist mask is formed on the insulator 58, and then the conductors 57 (conductor 57_1, conductor 57_2) and insulators 58 are formed by etching. In this case, it is preferable that the resist mask is formed so that, in a plan view, the outer edge of the resist mask is inward from the outer edge of the metal oxide 30. A part of the metal oxide 30 may be removed by etching. Alternatively, a part or all of the first layer 20 may be removed by etching.

[0218] For forming the conductor 57, sputtering, metal CVD, ALD, etc., can be used. Figure 11D shows an example of a two-layer structure of conductor 57, consisting of conductor 57_1 and conductor 57_2 on conductor 57_1, but it can be a single layer or a laminated structure of three or more layers. One or more of the conductors described above under <Conductors> can be used for the conductor 57. The conductor 57 has a region that is in contact with the metal oxide 30. Here, when an oxide semiconductor is used as the metal oxide 30, if an easily oxidized metal such as tungsten or aluminum is used in the region of the conductor 57 that is in contact with the metal oxide 30, an insulating oxide may be formed between the conductor 57 and the metal oxide 30, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide in at least the region of the conductor 57 that is in contact with the metal oxide 30. Therefore, specifically, it is preferable to use a conductive oxide for the conductor 57_1 that comes into contact with the metal oxide 30. This can suppress the increase in contact resistance between the metal oxide 30 and the conductor 57_1. As the conductive oxide used for the conductor 57_1, it is preferable to use, for example, indium tin oxide. Furthermore, it is particularly preferable to use tungsten as the conductor 57_2.

[0219] For forming the insulator 58, sputtering, ALD, CVD, PLD, etc., can be used. The insulator 58 is shown as a single layer example, but it may also be a laminated structure of two or more layers. One or more of the insulators described above under <Insulator> can be used for the insulator 58. The insulator 58 can be used as part or all of the mask for dry etching when forming the insulator 54_3, the first layer 20, the metal oxide 30, and the conductor 57. By providing the insulator 58, it is possible to suppress the occurrence of pattern formation abnormalities such as pattern reduction when forming the insulator 54_3, the first layer 20, the metal oxide 30, and the conductor 57. As the insulator 58, for example, it can be a two-layer structure of silicon nitride and silicon oxide on the silicon nitride.

[0220] Subsequently, the insulator 59 is formed to cover the insulator 54_3, the first layer 20, the metal oxide 30, the conductor 57, and the insulator 58 (see Figure 12A). Sputtering, ALD, CVD, PLD, etc., can be used to form the insulator 59. The insulator 59 is shown as a single layer, but it may also be a laminated structure of two or more layers. One or more of the insulators described above under <Insulator> can be used for the insulator 59.

[0221] As the insulator 59, for example, an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, an insulator having the function of capturing or fixing hydrogen, an insulator having barrier properties against hydrogen, and an insulator having barrier properties against oxygen can be used. Preferably, silicon nitride is used for the insulator 59. The insulator 59 functions as a layer that suppresses the diffusion of impurities such as hydrogen from the layer above it to the metal oxide 30. In addition, the insulator 59 is in contact with the insulator 54_2 located below the metal oxide 30 and surrounds the metal oxide 30, thereby suppressing the diffusion of impurities such as hydrogen from the outside to the metal oxide 30. Furthermore, it can suppress the formation of oxygen vacancies in the metal oxide 30.

[0222] Subsequently, the insulator 60 is formed to cover the insulator 59 (see Figure 12A). The upper surface of the insulator 60 may be planarized using a CMP method or the like so that the upper surface is flat. Sputtering, ALD, CVD, PLD, etc., can be used to form the insulator 60. The insulator 60 is shown as a single layer example, but it may also be a laminated structure of two or more layers. One or more of the insulators described above under <Insulator> can be used for the insulator 60. For example, silicon oxide, silicon oxynitride, etc., can be used for the insulator 60. It is preferable to use a film formed by sputtering, in which the deposition gas does not contain hydrogen, for the insulator 60.

[0223] Furthermore, it is preferable to perform a heat treatment after the insulator 60 is formed. The heat treatment should be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment should be performed in an inert gas atmosphere (e.g., nitrogen gas, noble gas, or both), or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to use an oxygen gas of about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after performing the heat treatment in an inert gas atmosphere (e.g., nitrogen gas, noble gas, or both), it may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. By performing the heat treatment as described above, impurities such as water and hydrogen contained in the insulator 60 can be reduced. Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is 1 ppb (10 −３ ppm) or less, preferably 0.1 ppb (10 −４ ppm) or less, more preferably 0.05 ppb (10 −５ It is preferable to keep the concentration below ppm. By performing the heat treatment using highly purified gas, it is possible to prevent moisture and other substances from being incorporated into the insulator 60 as much as possible. There are no special limitations on the equipment used for the heat treatment; it may be an equipment that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA equipment such as an LRTA equipment or a GRTA equipment can be used. An LRTA equipment is an equipment that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA equipment is an equipment that performs heat treatment using high-temperature gas.

[0224] It is preferable to use an insulator 60 that easily forms regions containing excess oxygen. It is also preferable that it has the function of releasing oxygen. Furthermore, it is possible to perform a process to supply oxygen to the insulator 60. Oxygen is supplied to the insulator 60, and by heat applied in subsequent processes, oxygen can be supplied from the insulator 60 to the metal oxide 30.

[0225] Examples of processes for supplying oxygen include heating in an oxygen-containing atmosphere, or microwave-excited high-density plasma treatment in an oxygen-containing atmosphere. Another example is a method for forming a film of the insulator 60 in an oxygen-containing atmosphere.

[0226] Alternatively, as a means of supplying oxygen, an oxide film (preferably a metal oxide film) may be deposited on the insulator 60 by sputtering in an oxygen-containing atmosphere, thereby supplying oxygen to the insulator 60. It is preferable to remove the deposited oxide film afterward. For example, an oxide film such as aluminum oxide or an oxide semiconductor may be deposited by sputtering and removed by a combination of one or more methods such as CMP, wet etching, or dry etching. If the thickness of the insulator 60 decreases when removing the oxide film by CMP, the insulating layer may be deposited again. The oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２ The atmosphere includes a gas containing oxygen-containing compounds such as O). The substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C. The oxygen supply process described above may be performed multiple times as the same process, or multiple times as a combination of different processes.

[0227] Subsequently, a resist mask is formed on the insulator 60, and then grooves reaching the conductor 57_1 are formed in the conductor 57_2, insulator 58, insulator 59, and insulator 60 by etching, forming conductors 57_2a and 57_2b. Then, a film to become the insulator 61 is deposited, and anisotropic etching is performed to form the insulator 61 that is in contact with the side surfaces of the conductor 57_2, insulator 58, insulator 59, and insulator 60 in the grooves. Furthermore, a portion of the conductor 57_1 is removed by the same anisotropic etching to form conductors 57_1a and 57_1b. The insulator 61 is formed so that it is in contact with the side surface of the conductor 57_2 and the upper surface of the conductor 57_1 in the grooves (see Figure 12B).

[0228] For forming the insulator 61, sputtering, ALD, CVD, PLD, etc., can be used. The insulator 61 is shown as a single layer example, but it may also be a laminated structure of two or more layers. One or more of the insulators described above under <Insulator> can be used for the insulator 61.

[0229] As the insulator 61, for example, an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, an insulator having the function of capturing or fixing hydrogen, an insulator having barrier properties against hydrogen, and an insulator having barrier properties against oxygen can be used. Preferably, silicon nitride is used for the insulator 61. By providing the insulator 61, oxidation of the conductor 63 can be suppressed. In addition, oxidation of the side surface of the conductor 57_2 can be suppressed. As a result, the increase in the resistance of the conductor can be suppressed.

[0230] Subsequently, insulators 62 and conductors 63 (conductor 63_1, conductor 63_2) are deposited to cover the grooves and insulator 61. Then, insulators 62 and conductors 63 (conductor 63_1, conductor 63_2) located on insulator 62 are removed by the CMP method. This forms insulators 62 and conductors 63 located in the grooves. After that, insulators 64 (insulators 64_1, insulators 64_2, insulators 64_3) are deposited on insulators 60 and conductors 63 (see Figure 12C).

[0231] The insulator 62 has a region in the groove that contacts the insulator 61 and a region that contacts the side surface of the conductor 57_1. The insulator 62 also has regions that contact the upper surface and side surface of the metal oxide 30. It is preferable that the upper surface of the conductor 63 and the upper surface of the insulator 60 are at the same height.

[0232] The insulator 62 can be described in the above-mentioned section on "gate insulating film".

[0233] Conductor 63 can refer to the description of conductor 53. For example, conductor 63_1 can refer to the description of conductor 53_1, and conductor 63_2 can refer to the description of conductor 53_2.

[0234] Insulator 64_1, or insulator 64_2, or both, can be an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, an insulator having the function of capturing or fixing hydrogen, an insulator having barrier properties against hydrogen, or an insulator having barrier properties against oxygen. For insulator 64_1, it is preferable to use aluminum oxide produced by the sputtering method, for example. For insulator 64_2, it is preferable to use silicon nitride, for example. Insulator 64_1, or insulator 64_2, or both, function as a layer that suppresses the release of oxygen to the layer above insulator 64_1 and insulator 64_2, or the diffusion of impurities such as hydrogen from the layer above insulator 64_1 and insulator 64_2 to the metal oxide 30.

[0235] Alternatively, oxygen may be supplied to the insulator 60 by depositing an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere using a sputtering method. It is preferable to remove the deposited oxide film afterward. For example, an oxide film such as aluminum oxide or an oxide semiconductor may be deposited by sputtering and removed by a CMP method. If the thickness of the insulator 60 decreases when removing the oxide film by the CMP method, the insulating layer may be deposited again. The oxygen-containing atmosphere may be oxygen gas (O₂O₃). ２ ) as well as ozone (O ３ ) or nitrous oxide (N ２The atmosphere includes a gas containing oxygen-containing compounds such as O). The substrate temperature during plasma treatment shall be between room temperature (25°C) and 450°C. The oxygen supply process described above may be performed multiple times as the same process, or multiple times as a combination of different processes.

[0236] For the insulator 64_3, it is preferable to use an insulator with high dielectric strength or an insulator that suppresses leakage current, for example, silicon oxide is preferred. In addition, the insulator 64_3 functions as an etching stop film when forming the conductor 67.

[0237] Subsequently, a resist mask is formed on the insulator 64, and then etching is performed to create openings in the insulators 58, 59, 60, and 64 (insulators 64_1, 64_2, and 64_3) that reach the conductor 57. Then, a film to become an insulator 65 is deposited, and anisotropic etching is performed to form an insulator 65 that is in contact with the sides of the insulator 58, the insulator 59, the insulator 60, and the insulators 64 (insulators 64_1, 64_2, and 64_3) at the openings (see Figure 13A). The details of insulator 65 can be found in the description of insulator 61.

[0238] Subsequently, conductors 66 (conductor 66_1, conductor 66_2) are deposited on the openings and on the insulator 64. Then, the conductors 66 (conductor 66_1, conductor 66_2) located on the insulator 64 are removed by the CMP method. This forms conductors 66a (conductor 66_1a, conductor 66_2a) and conductors 66b (conductor 66_1b, conductor 66_2b) on the openings. Then, conductor 67 is deposited on the insulator 64 and conductor 66. After that, a resist mask is formed on conductor 67, and then conductors 67a and conductor 67b are formed by etching. Note that the description of conductor 53 can be used for conductor 66.

[0239] Furthermore, the conductor 67 can be formed using film deposition methods such as metal CVD, sputtering, and ALD. Figure 13B shows an example where the conductor 67 is a single layer, but it can be a laminated structure of two or more layers. One or more of the conductors described above under "Conductors" can be used for the conductor 67. In particular, tungsten is preferred as the conductor 67.

[0240] As a result, a semiconductor device having a transistor 50 can be formed.

[0241] [Example of Semiconductor Device Configuration 2] Figures 14A to 14E show an example of a semiconductor device having a transistor 70. Figure 14A is a plan view of the semiconductor device having the transistor 70. Figure 14B is an enlarged plan view of the first layer 20, metal oxide 30, and conductor 77 shown in Figure 14A. Figure 14C is a cross-sectional view between the dashed-dotted lines C1 and C2 shown in Figure 14A. Figure 14D is a cross-sectional view between the dashed-dotted lines C3 and C4 shown in Figure 14A. Figure 14E is a cross-sectional view between the dashed-dotted lines C5 and C6 shown in Figure 14E.

[0242] The transistor 70 has at least a conductor 79a, a conductor 79b, a conductor 77, a metal oxide 30, and an insulator 76. The transistor 70 also has a conductor 72 and an insulator 73.

[0243] Part or all of the conductor 79a functions as either the source electrode or the drain electrode of the transistor 70. Part or all of the conductor 79b functions as either the source electrode or the drain electrode of the transistor 70. Part or all of the conductor 77 functions as the first gate electrode of the transistor 70. Part or all of the metal oxide 30 functions as a semiconductor of the transistor 70 and functions as a channel-forming region. Part or all of the insulator 76 functions as the first gate insulating film of the transistor 70. Part or all of the conductor 72 functions as the second gate electrode of the transistor 70. Part or all of the insulator 73 functions as the second gate insulating film of the transistor 70.

[0244] Furthermore, when transistor 70 is used as a memory cell, one or both of conductors 72 or 77 can function as word lines. Also, conductor 79a or conductor 79b can function as bit lines.

[0245] The semiconductor device having the transistor 70 shown in Figures 14A to 14E has an insulator 71 (insulator 71_1, insulator 71_2 on insulator 71_1) on a substrate (not shown). The contents of insulator 51 can be referenced for insulator 71. For example, the contents of insulator 51_1 can be referenced for insulator 71_1, and the contents of insulator 51_2 can be referenced for insulator 71_2.

[0246] The conductor 72 is located on the insulator 71, and the insulator 73 is provided so as to cover the conductor 72. The conductor 72 can be formed using film deposition methods such as metal CVD, sputtering, or ALD. Figure 14C shows an example where the conductor 72 is a single layer, but it can be a laminated structure of two or more layers. One or more of the conductors described above under "Conductors" can be used for the conductor 72. In particular, tungsten or molybdenum is preferred as the conductor 72. Sputtering, ALD, CVD, PLD, etc. can be used to form the insulator 73. An example of the insulator 73 is shown as a single layer, but it may be a laminated structure of two or more layers. One or more of the insulators described above under "Insulators" can be used for the insulator 73. In particular, silicon nitride, or a structure in which silicon oxynitride is laminated on the silicon nitride, is preferred as the insulator 73.

[0247] The first layer 20 and the metal oxide 30 are located on the insulator 73. As shown in Figure 14B, the metal oxide 30 has a first region 30_1, a second region 30_2, and a third region 30_3. The second region 30_2 is adjacent to the first region 30_1 and is located between the first region 30_1 and the third region 30_3. The first region 30_1 is in contact with the first layer 20. The second region 30_2 and the third region 30_3 are in contact with the insulator 73. The first layer 20, the metal oxide 30, the first region 30_1, the second region 30_2, and the third region 30_3 can be described in the first embodiment. In Figure 14B, the grain boundaries of the metal oxide 30 are shown by solid lines.

[0248] The insulator 76 is located on the metal oxide 30. The conductor 77 is located on the insulator 76, sandwiching the metal oxide 30 and the insulator 76 between them. The conductor 77 can be formed using film deposition methods such as metal CVD, sputtering, or ALD. Figure 14C shows an example where the conductor 77 is a single layer, but it can be a laminated structure of two or more layers. One or more of the conductors described above under "Conductors" can be used for the conductor 77. In particular, it is preferable to use a three-layer structure of titanium nitride, copper on the titanium nitride, and titanium nitride on the copper, or a three-layer structure of titanium, aluminum on the titanium, and titanium on the aluminum. Sputtering, ALD, CVD, PLD, etc., can be used to form the insulator 76. The insulator 76 is shown as a single layer, but it may be a laminated structure of two or more layers. The insulator 76 can be one or more of the insulators described above under <Insulator>. In particular, silicon oxide or silicon oxynitride is preferred as the insulator 76.

[0249] The insulator 78 is provided so as to cover the first layer 20, the metal oxide 30, the insulator 76, and the conductor 77. The insulator 78 also has a region in contact with the upper surface of the metal oxide 30. It also has a region in contact with the upper surface of the insulator 73. Sputtering, ALD, CVD, PLD, etc., can be used to form the insulator 78. The insulator 78 is shown as a single layer example, but it may also be a laminated structure of two or more layers. One or more of the insulators described above under <Insulator> can be used for the insulator 78. It is preferable to use silicon nitride containing hydrogen as the insulator 78. The region of the metal oxide 30 in contact with the insulator 78 can have a lower resistance than the channel-forming region. As a result, the region of the metal oxide 30 in contact with the insulator 78 can function as a source region or a drain region.

[0250] The insulator 78 has an opening that reaches the metal oxide 30. The conductor 79 is located on the insulator 78 and connects to the metal oxide 30 through the opening in the insulator 78. The conductor 79 can be formed using film deposition methods such as metal CVD, sputtering, or ALD. Figure 14C shows an example where the conductor 79 is a single layer, but it can be a laminated structure of two or more layers. One or more of the conductors described above under "Conductors" can be used for the conductor 79. In particular, molybdenum is preferred as the conductor 79.

[0251] An insulator 80 is provided on the conductor 79. Sputtering, ALD, CVD, PLD, and other methods can be used to form the insulator 80. While a single-layer example of the insulator 80 is shown, a multilayer structure of two or more layers may also be used. One or more of the insulators described above under "Insulators" can be used for the insulator 80. In particular, silicon nitride or silicon nitride oxide is preferred as the insulator 80.

[0252] In the transistor 70, the metal oxide 30 has a first portion that overlaps with the conductor 77. More specifically, the third region 30_3 of the metal oxide 30 has a first portion that overlaps with the conductor 77. This region can function as a channel-forming region of the transistor. In a plan view, it is preferable that the width j1 of the third region along a first direction D1 perpendicular to the channel length direction of the transistor is narrower than the width j2 of the second region along the first direction D1 (see Figure 14B).

[0253] Furthermore, in the transistor 70, by using the metal oxide 30 described in Embodiment 1, the first portion of the third region 30_3 of the metal oxide 30 that overlaps with the conductor 77 does not show any grain boundaries when viewed in a cross-sectional view parallel to the channel length direction of the transistor, as can be seen by analysis using a transmission electron microscope.

[0254] The first portion of the third region 30_3 that overlaps with the conductor 77 can be a region where no grain boundaries are observed. Alternatively, the first portion of the third region 30_3 that overlaps with the conductor 77 can be a single-grain crystal. Alternatively, the first portion of the third region 30_3 that overlaps with the conductor 77 can be analyzed using a transmission electron microscope to determine a region having a cross-section along the second direction D2 where no grain boundaries are observed. Alternatively, the first portion of the third region 30_3 that overlaps with the conductor 77 can be analyzed using electron diffraction mapping to determine a crystal that does not contain grain boundaries when adjacent measurement points have an orientation difference of 5° or more. Furthermore, the metal oxide 30 can have crystal grains that overlap with a pair of ends of the conductor 77 that face each other in the channel length direction (second direction D2). This makes it possible to obtain a semiconductor device with good electrical properties. Alternatively, it is possible to obtain a semiconductor device that can carry a large current. Alternatively, it is possible to obtain a semiconductor device with high reliability. Furthermore, one or more channel-forming regions may be provided in the third region 30_3.

[0255] The above is a description of [Example 2 of Semiconductor Device Configuration].

[0256] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples or modifications are shown within a single embodiment in this specification, the configuration examples or modifications can be combined as appropriate.

[0257] (Embodiment 3) In this embodiment, an indium oxide film that can be used in the metal oxide 30 according to one aspect of the present invention will be described.

[0258] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0259] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0260] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0261] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single crystals.

[0262] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm−３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0263] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0264] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0265] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0266] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0267] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at grain boundaries can be suppressed, enabling the realization of transistors that exhibit high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these grain boundaries.

[0268] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0269] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0270] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0271] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0272] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0273] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, and Group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0274] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0275] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0276] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0277] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0278] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Moreover, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰−２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0279] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0280] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0281] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0282] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0283] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified form structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0284] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0285] (Embodiment 4) In this embodiment, a storage device according to one aspect of the present invention will be described with reference to Figures 15A to 16. The storage device according to one aspect of the present invention has a memory cell. The memory cell has a transistor and a capacitive element. The transistor and memory cell can be a transistor and a semiconductor device including the transistor described in Embodiment 2. Detailed descriptions of the transistor and the semiconductor device including the transistor may be omitted as they can be described by referring to the description of Embodiment 2.

[0286] The configuration of a memory device having a transistor and a capacitive element will be explained using Figures 15A and 15B. Figure 15A is a plan view of a memory device having a memory cell 100. Figure 15B is a cross-sectional view corresponding to the dashed line E1-E2 shown in Figure 15A. The memory cell 100 has a capacitive element 90 and a transistor 50. Figures 15A and 15B show an example using a semiconductor device including the transistor 50 shown in Embodiment 2, but the semiconductor device is not limited to including the transistor 50, and one or more types of semiconductor devices including each transistor exemplified in Embodiment 2 can be used.

[0287] Figure 15A is a plan view showing the memory cell 100. One or both of the conductors 53 or 63, which function as word lines, extend in the X direction, and the conductor 67a, which functions as a bit line, extends in the Y direction.

[0288] The memory device shown in Figure 15B has a transistor 50 on a substrate (not shown), and a capacitive element 90 on the transistor 50.

[0289] The capacitive element 90 comprises at least a conductor 67b, an insulator 91, and a conductor 92. The insulator 91 is provided between the conductor 67b and the conductor 92. At least a portion or all of the conductor 67b functions as one of a pair of electrodes of the capacitive element. At least a portion of the conductor 92 functions as the other of a pair of electrodes of the capacitive element. At least a portion of the insulator 91 functions as the dielectric of the capacitive element.

[0290] Furthermore, in the capacitive element 90, the insulator 91 covers the conductor 67b, and in a plan view, the outer edge of the conductor 92 can be formed to be further outward than the outer edge of the conductor 67b. By doing so, the capacitance of the capacitive element 90 can be increased.

[0291] As shown in Figures 15A and 15B, the capacitive element 90 is provided on the transistor 50, overlapping with the transistor 50. Furthermore, the conductor 67b functions as one of the pair of electrodes of the capacitive element 90, and also as one or both of the wiring and electrodes of the semiconductor device including the transistor 50. In this way, the conductor 67 shares a part of the structure between the capacitive element 90 and the semiconductor device including the transistor 50. This configuration reduces the number of manufacturing steps, thereby improving productivity. Additionally, the capacitive element 90 and the transistor 50 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 100, allowing for a higher density arrangement of the memory cell 100 and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0292] The insulator 93 is provided so as to cover the capacitive element 90. The insulator 94 is provided on top of the insulator 93.

[0293] For the insulating layers such as insulator 93 and insulator 94, one or more of the insulators described in <Insulator> of Embodiment 2 can be used. In particular, it is preferable to use one or more of the insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen, insulators that have the function of capturing or fixing hydrogen, insulators that have barrier properties against hydrogen, or insulators that have barrier properties against oxygen for insulator 93. It is preferable that insulator 93 be, for example, silicon nitride or aluminum oxide, or a two-layer structure in which silicon nitride is laminated on aluminum oxide. By using these insulators, the diffusion of hydrogen from structures above insulator 93 to the metal oxide 30 of the transistor 50 can be suppressed. Furthermore, the transistor 50 can be made highly reliable. It is also preferable to use one or more of the insulators that have a lower dielectric constant than high-k materials, insulators with high dielectric strength, or insulators that suppress leakage current for insulator 94. It is preferable to use silicon oxide for insulator 94. Since the insulator 94 functions as an interlayer film, using an insulator with a low dielectric constant can reduce parasitic capacitance between the wiring. Furthermore, the insulator 94 may be planarized using methods such as CMP to ensure its upper surface is flat.

[0294] Conductors such as the conductor 92 can be formed in a single layer or laminate using the materials and configuration described in the <Conductor> section of Embodiment 2. For example, the conductor 92 can be tungsten. Because a highly conductive material such as tungsten can be used, the wiring resistance of the conductor 92 can be reduced.

[0295] The insulator 91 can be formed in a single layer or laminate using one or more of the insulators described in Embodiment 2. It is preferable to use one or more insulators with a high dielectric constant (high-k), an insulator with high dielectric strength, or an insulator that suppresses leakage current for the insulator 91. For example, an insulating film (also called ZAZ) laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. Alternatively, for example, an insulating film (also called ZAZA) laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.

[0296] Furthermore, a ferroelectric material may be used for the insulating layer, such as the insulator 91. For example, hafnium zirconium oxide can be used. When a ferroelectric material is used for the insulator 91, it is preferable to use titanium nitride for at least the portion of one or both of the conductor 67b and the conductor 92 that is in contact with the insulator 91. By using a ferroelectric material for the dielectric of the capacitive element 90, the memory device shown in this embodiment can function as a ferroelectric memory.

[0297] Figure 16 shows an example of a cross-sectional configuration of a memory device in which layers having memory cells 100 as shown in Figures 15A and 15B are stacked on a layer on which a drive circuit including a sense amplifier is provided.

[0298] In Figure 16, a memory cell 100 (capacitive element 90 and transistor 50) is provided above the Si transistor 900. The Si transistor 900 is one of the transistors in the drive circuit, which includes a sense amplifier.

[0299] The Si transistor 900 will now be described. The Si transistor 900 is a Fin-type transistor. Figure 16 shows a schematic cross-sectional view in the channel length direction.

[0300] The Si transistor 900 is provided on a substrate 901 and includes a conductor 908a that functions as a gate electrode, an insulator 907 that functions as a gate insulating film, a semiconductor region 903 that functions as a channel forming region, and a low-resistance region 904 that functions as a source region or drain region.

[0301] For example, a silicon substrate or an SOI substrate can be used as the substrate 901.

[0302] An element isolation layer 902, an insulator 905, and dummy gate electrodes 908b and 908c are provided on the substrate 901. The insulator 905 functions as a sidewall. In addition, insulators 906, 909, 910, 911, 913, 914, 916, 918, and 919 are provided, and these insulating layers function as interlayer insulating films. Insulators 909, 911, 914, and 918 also function as barrier films. Conductors 912, 915, 917, and 920 function as plugs, electrodes, or wiring.

[0303] One of the sources or drains of the Si transistor 900 (in this case, the low-resistance region 904) is connected to the memory cell 100 via a conductive layer.

[0304] The conductor 53a (conductor 53a_1, conductor 53a_2 on conductor 53a_1) is connected to the Si transistor 900 via conductor 920, conductor 917, and conductor 915.

[0305] Insulators 803 and 804 are provided on the memory cell 100. One or more of the insulators described in <Insulator> of Embodiment 2 can be used for the insulating layers such as insulators 803 and 804. In particular, it is preferable to use an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, an insulator that has the function of capturing or fixing hydrogen, an insulator that has barrier properties against hydrogen, or an insulator that has barrier properties against oxygen for the insulating layer such as insulator 803. It is also preferable to use an insulator with a lower dielectric constant than the high-k material for the insulating layer such as insulator 804. By using these insulating films, the diffusion of hydrogen into the metal oxide 30 of the transistor 50 can be suppressed. Furthermore, the transistor 50 can be made highly reliable.

[0306] Conductors 805a, 805b, and 805c are provided so as to be embedded in the insulator 804. The conductive layers such as conductors 805a, 805b, and 805c can be formed in a single layer or laminate using the conductors and configurations described in <Conductors> of Embodiment 2. For example, conductor 805 can have a two-layer structure using tungsten on titanium nitride. Since a highly conductive conductor such as tungsten can be used, the wiring resistance of conductor 805 can be reduced. Alternatively, conductor 805 can have a three-layer structure of tantalum nitride, titanium nitride, and tungsten from the bottom layer. Alternatively, conductor 805 can have a four-layer structure of tantalum nitride, tantalum, titanium nitride, and tungsten from the bottom layer.

[0307] The conductor 802a is provided to connect the conductor 805a and the conductor 53a via the conductors 67c and 66c. The conductor 53a can be manufactured using the same process as the conductor 53. The conductor 66c can be manufactured using the same process as the conductor 66. The conductor 67c can be manufactured using the same process as the conductor 67.

[0308] The conductor 802b is provided to connect the conductor 805b and the conductor 57a.

[0309] The conductor 802c is provided to connect the conductor 805c and the conductor 92.

[0310] Furthermore, the conductive layers such as conductor 802a, conductor 802b, and conductor 802c can be formed as a single layer or in a laminated form using the conductor and configuration described in <Conductor> of Embodiment 2. For example, conductor 802 can be a two-layer structure using tungsten on titanium nitride.

[0311] Conductors 805a, 805b, 805c, 802a, 802b, and 802c function as plugs or wiring.

[0312] Conductors 805a, 805b, and 805c may be configured to be interconnected. Also, conductors 53a and 53 may be configured to be interconnected.

[0313] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0314] (Embodiment 5) In this embodiment, a semiconductor device 8000 according to one aspect of the present invention will be described. The semiconductor device 8000 can function as a storage device.

[0315] Figure 17 shows a block diagram illustrating an example configuration of the semiconductor device 8000. The semiconductor device 8000 shown in Figure 17 includes a drive circuit 8110 and a memory array 8120. The memory array 8120 has one or more memory cells 8130. Figure 17 shows an example in which the memory array 8120 has multiple memory cells 8130 arranged in a matrix.

[0316] The memory cell 8130 can be a storage device as described in Embodiment 4.

[0317] The drive circuit 8110 includes a PSW 8001 (power switch), a PSW 8002, and a peripheral circuit 8003. The peripheral circuit 8003 includes a peripheral circuit 8004, a control circuit 8005, and a voltage generation circuit 8006.

[0318] In a semiconductor device, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0319] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 8005.

[0320] The control circuit 8005 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 8000. For example, the control circuit 8005 performs a logic operation on signals CE, GW, and BW to determine the operating mode of the semiconductor device 8000 (e.g., write operation, read operation). Alternatively, the control circuit 8005 generates control signals for the peripheral circuit 8004 so that this operating mode is executed.

[0321] The voltage generation circuit 8006 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 8006. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 8006, and the voltage generation circuit 8006 generates a negative voltage.

[0322] The peripheral circuit 8004 is a circuit for writing and reading data to and from the memory cell 8130. The peripheral circuit 8004 includes a row decoder 8007, a column decoder 8008, a row driver 8009, a column driver 8010, a sense amplifier 8011, an input circuit 8012, and an output circuit 8013.

[0323] The row decoder 8007 and column decoder 8008 have the function of decoding the ADDR signal. The row decoder 8007 is a circuit for specifying the row to access, and the column decoder 8008 is a circuit for specifying the column to access. The row driver 8009 has the function of selecting the row specified by the row decoder 8007. The column driver 8010 has the function of writing data to the memory cell 8130, reading data from the memory cell 8130, and holding the read data.

[0324] The input circuit 8012 has the function of holding the signal WDA. The data held by the input circuit 8012 is output to the column driver 8010. The output data of the input circuit 8012 is the data (Din) to be written to the memory cell 8130. The data (Dout) read by the column driver 8010 from the memory cell 8130 is output to the output circuit 8013. The output circuit 8013 has the function of holding Dout. The output circuit 8013 also has the function of outputting Dout to the outside of the semiconductor device 8000. The data output from the output circuit 8013 is the signal RDA.

[0325] PSW8001 provides V to peripheral circuit 8003 ＤＤ It has the function of controlling the supply. PSW8002 connects to the line driver 8009. ＨＭ It has a function to control the supply. Here, the high power supply potential of semiconductor device 8000 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW8001 is controlled by signal PON1, and the on / off state of PSW8002 is controlled by signal PON2. In Figure 17, in peripheral circuit 8003, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0326] Using Figures 18A to 18H, other examples of memory cell configurations applicable to the memory cell 8130 will be described.

[0327] [DOSRAM] Figure 18A shows an example of the circuit configuration of a memory cell of a DRAM (Dynamic Random Access Memory). In this specification and elsewhere, a DRAM using an OS transistor is called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 8131 has a transistor M1 and a capacitive element CA.

[0328] Transistor M1 may have a front gate (sometimes simply called a gate) and a back gate. In this case, the back gate may be connected to a wire to which a constant potential or signal is supplied, or the front gate and back gate may be connected.

[0329] The first terminal of transistor M1 is connected to the first terminal of capacitive element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL. The second terminal of capacitive element CA is connected to wiring CAL.

[0330] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0331] Data writing and reading are performed by applying a high-level potential to the wiring WOL, turning on transistor M1, and creating a conductive state (a state in which current can flow) between the wiring BIL and the first terminal of the capacitive element CA.

[0332] Furthermore, the memory cell that can be used in memory cell 8130 is not limited to memory cell 8131, and the circuit configuration can be changed. For example, the memory cell 8132 can be configured as shown in Figure 18B. Memory cell 8132 is an example in which there is no capacitive element CA and wiring CAL. The first terminal of transistor M1 is electrically floating.

[0333] In the memory cell 8132, the potential written via transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, indicated by the dashed line. This configuration significantly simplifies the structure of the memory cell.

[0334] Furthermore, it is preferable to use an OS transistor as transistor M1. OS transistors have the characteristic of having an extremely low off-current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, the written data can be held by transistor M1 for a long time, so the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. In addition, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8131 and 8132.

[0335] [NOSRAM] Figure 18C shows an example of a circuit configuration for a gain cell type memory cell with two transistors and one capacitance element. The memory cell 8133 has a transistor M2, a transistor M3, and a capacitance element CB. In this specification and elsewhere, a memory device having a gain cell type memory cell using an OS transistor for transistor M2 is called NOSRAM (Nonvolatil Oxide Semiconductor RAM).

[0336] The first terminal of transistor M2 is connected to the first terminal of capacitive element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitive element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitive element CB.

[0337] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, during data retention, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to wiring CAL.

[0338] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M2, and creating a conductive state between the wiring WBL and the first terminal of the capacitive element CB. Specifically, when transistor M2 is ON, a potential corresponding to the information to be recorded in the wiring WBL is applied, and this potential is written to the first terminal of the capacitive element CB and the gate of transistor M3. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of the capacitive element CB and the potential of the gate of transistor M3.

[0339] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of transistor M3, and the potential of the first terminal of transistor M3, are determined by the potential of the gate and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CB (or the gate of transistor M3).

[0340] Alternatively, for example, the wiring WBL and wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in Figure 18D. Memory cell 8134 is configured such that the wiring WBL and wiring RBL of memory cell 8133 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL. In other words, memory cell 8134 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0341] The memory cell 8135 shown in Figure 18E is an example where the capacitive element CB and wiring CAL in the memory cell 8133 are omitted. Similarly, the memory cell 8136 shown in Figure 18F is an example where the capacitive element CB and wiring CAL in the memory cell 8134 are omitted. By using such a configuration, the integration density of memory cells can be increased.

[0342] Furthermore, it is preferable to use an OS transistor for at least transistor M2. In particular, it is preferable to use OS transistors for transistors M2 and M3.

[0343] Because the OS transistor has the characteristic of having an extremely low off-current, the written data can be held by transistor M2 for a long time, thus reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether. Furthermore, because the leakage current is very low, multi-level data or analog data can be held in memory cells 8133, 8134, 8135, and 8136.

[0344] Memory cells 8133, 8134, 8135, and 8136, which use an OS transistor as transistor M2, represent one embodiment of NOSRAM.

[0345] Furthermore, a Si transistor may be used as transistor M3. Si transistors can increase field-effect mobility and can also be made into p-channel transistors, thus increasing the flexibility of circuit design.

[0346] Furthermore, if an OS transistor is used as transistor M3, the memory cell can be constructed using only n-type transistors.

[0347] Figure 18G also shows a gain cell type memory cell 8137 with three transistors and one capacitance element. The memory cell 8137 has transistors M4 to M6 and a capacitance element CC.

[0348] The first terminal of transistor M4 is connected to the first terminal of capacitive element CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitive element CC is connected to the first terminal of transistor M5 and to wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitive element CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0349] The BIL wiring functions as a bit line, the WOL wiring functions as a write word line, and the RWL wiring functions as a read word line. The GNDL wiring is a wiring that provides a low level potential.

[0350] Data writing is performed by applying a high-level potential to the wiring WOL, turning on transistor M4, and creating a conductive state between the wiring BIL and the first terminal of the capacitive element CC. Specifically, when transistor M4 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the first terminal of the capacitive element CC and the gate of transistor M5. Subsequently, a low-level potential is applied to the wiring WOL, turning off transistor M4, thereby maintaining the potential of the first terminal of the capacitive element CC and the potential of the gate of transistor M5.

[0351] Data is read by precharging the wiring BIL to a predetermined potential, then electrically freezing the wiring BIL, and applying a high-level potential to the wiring RWL. As the wiring RWL reaches a high-level potential, transistor M6 turns ON, and the wiring BIL and the second terminal of transistor M5 become conductive. At this time, the potential of the wiring BIL is applied to the second terminal of transistor M5, but the potential of the second terminal of transistor M5 and the potential of the wiring BIL change depending on the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5). By reading the potential of the wiring BIL, the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5) can be read. In other words, the information written to this memory cell can be read from the potential held at the first terminal of the capacitive element CC (or the gate of transistor M5).

[0352] Furthermore, it is preferable to use an OS transistor for at least transistor M4.

[0353] Note that Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.

[0354] Furthermore, if OS transistors are used as transistors M5 and M6, the memory cell can be constructed using only n-type transistors.

[0355] [OS-SRAM] Figure 18H shows an example of SRAM (Static Random Access Memory) using an OS transistor. In this specification and elsewhere, SRAM using an OS transistor is called OS-SRAM (Oxide Semiconductor-SRAM). The memory cell 8138 shown in Figure 18H is a memory cell of a backup-capable SRAM.

[0356] The memory cell 8138 includes transistors M7 to M10, transistors MS1 to MS4, and capacitive elements CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, while transistors MS3 and MS4 are n-channel transistors.

[0357] The first terminal of transistor M7 is connected to wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. The first terminal of transistor M8 is connected to wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0358] The second terminal of transistor MS1 is connected to wiring VDL. The second terminal of transistor MS2 is connected to wiring VDL. The second terminal of transistor MS3 is connected to wiring GNDL. The second terminal of transistor MS4 is connected to wiring GNDL.

[0359] The second terminal of transistor M9 is connected to the first terminal of capacitive element CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitive element CD2, and the gate of transistor M10 is connected to wiring BRL.

[0360] The second terminal of capacitive element CD1 is connected to wiring GNDL, and the second terminal of capacitive element CD2 is connected to wiring GNDL.

[0361] Wiring BIL and BILB function as bit lines, wiring WOL functions as a word line, and wiring BRL controls the on and off states of transistors M9 and M10.

[0362] Wiring VDL is a wiring that provides a high-level potential, and wiring GNDL is a wiring that provides a low-level potential.

[0363] Data is written by applying a high-level potential to the wiring WOL and also to the wiring BRL. Specifically, when transistor M10 is ON, a potential corresponding to the information to be recorded in wiring BIL is applied, and this potential is written to the second terminal side of transistor M10.

[0364] Incidentally, since the memory cell 8138 is configured as an inverter loop by transistors MS1 to MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of transistor M8. Because transistor M8 is ON, the potential applied to wiring BIL, i.e., the inverted signal of the signal input to wiring BIL, is output to wiring BILB. Also, because transistors M9 and M10 are ON, the potential of the second terminal of transistor M7 and the potential of the second terminal of transistor M8 are held at the first terminal of capacitive element CD2 and the first terminal of capacitive element CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and wiring BRL, and turning off transistors M7 to M10, the potentials of the first terminal of capacitive element CD1 and the first terminal of capacitive element CD2 are maintained.

[0365] The data reading process is described below. First, wiring BIL and wiring BILB are precharged to a predetermined potential. Next, a high-level potential is applied to wiring WOL and wiring BRL. At this time, the potential of the first terminal of capacitive element CD1 is refreshed by the inverter loop of memory cell 8138 and output to wiring BILB. Also, the potential of the first terminal of capacitive element CD2 is refreshed by the inverter loop of memory cell 8138 and output to wiring BIL. In wiring BIL and wiring BILB, the potential changes from the precharged potential to the potential of the first terminal of capacitive element CD2 and the potential of the first terminal of capacitive element CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of wiring BIL or wiring BILB.

[0366] Furthermore, it is preferable to use OS transistors as transistors M7 to M10. This allows the written data to be retained for a long time by transistors M7 to M10, thereby reducing the frequency of memory cell refreshes. Alternatively, it may be possible to eliminate the need for memory cell refresh operations altogether.

[0367] Furthermore, Si transistors may be used as transistors MS1 to MS4.

[0368] Figures 19A and 19C show perspective views of the semiconductor device 8200A. The semiconductor device 8200A has a layer 8220 on which memory arrays are provided on the arithmetic unit 8210. Memory arrays 8120L1, 8120L2, and 8120L3 are provided on layer 8220. The arithmetic unit 8210 and each memory array have overlapping regions. To make the configuration of the semiconductor device 8200A easier to understand, Figure 19B shows the arithmetic unit 8210 and layer 8220 separately. The arithmetic unit 8210 can be, for example, a CPU, GPU, etc.

[0369] By stacking the layer 8220 containing the memory array and the arithmetic unit 8210, the connection distance between them can be shortened. Therefore, the communication speed between them can be increased. In addition, power consumption can be reduced due to the short connection distance.

[0370] As a method for stacking the layer 8220 having a memory array and the arithmetic unit 8210, one may use a method in which the layer 8220 having a memory array is directly stacked on the arithmetic unit 8210 (also called monolithic stacking), or one may use a method in which the arithmetic unit 8210 and the layer 8220 are formed on different substrates, the two substrates are bonded together, and they are connected using through-via or conductive film bonding technology (such as Cu-Cu bonding). The former does not require consideration of positional misalignment during bonding, so not only can the chip size be reduced, but manufacturing costs can also be reduced.

[0371] Here, the arithmetic unit 8210 does not have a cache, and the memory arrays 8120L1, 8120L2, and 8120L3 provided in layer 8220 can each be used as caches. In this case, for example, memory array 8120L1 can be used as an L1 cache (also called a level 1 cache), memory array 8120L2 can be used as an L2 cache (also called a level 2 cache), and memory array 8120L3 can be used as an L3 cache (also called a level 3 cache). Of the three memory arrays, memory array 8120L3 has the largest capacity and the lowest access frequency. Also, memory array 8120L1 has the smallest capacity and the highest access frequency.

[0372] Furthermore, when the cache provided in the arithmetic unit 8210 is used as the L1 cache, each memory array provided in layer 8220 can be used as a lower-level cache or main memory, respectively. Main memory has a larger capacity than cache and is accessed less frequently.

[0373] Furthermore, as shown in Figure 19B, drive circuits 8110L1, 8110L2, and 8110L3 are provided. Drive circuit 8110L1 is connected to memory array 8120L1 via connecting electrode 8230L1. Similarly, drive circuit 8110L2 is connected to memory array 8120L2 via connecting electrode 8230L2, and drive circuit 8110L3 is connected to memory array 8120L3 via connecting electrode 8230L3.

[0374] Note that while this example shows three memory arrays functioning as a cache, it can also be one, two, or four or more.

[0375] When the memory array 8120L1 is used as a cache, the drive circuit 8110L1 may function as part of the cache interface, or the drive circuit 8110L1 may be configured to be connected to the cache interface. Similarly, the drive circuits 8110L2 and 8110L3 may also function as part of the cache interface, or be configured to be connected to it.

[0376] In Figures 19A and 19B, an example is shown in which one layer 8220 on which a memory array is provided is placed on the arithmetic unit 8210. However, as shown in Figure 19C, two or more layers 8220 on which memory arrays are provided may be placed.

[0377] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0378] (Embodiment 6) A semiconductor device according to one aspect of the present invention will be described. Figure 20A is a schematic perspective view of a semiconductor device 710 according to one aspect of the present invention. Figure 20B is a schematic perspective view of a part of the semiconductor device 710. Figure 21 is a schematic perspective view illustrating the configuration of the semiconductor device 710.

[0379] In Figures 20A, 20B, and 21, the semiconductor device 710 has an element layer 730 below an element layer 720 which includes a substrate 722 which is a semiconductor substrate, and a support substrate 740 above the element layer 720 via an insulating layer 741. The element layer 720 has a plurality of transistors 721 which constitute a functional circuit 711. The element layer 730 has a plurality of transistors 731 which constitute a switch circuit 715. The transistors 731 function as switches to control the conduction and non-conductivity between an external power supply line and a conductive layer 732 which functions as a power line.

[0380] The transistor exemplified in Embodiment 2 can be applied to transistor 731.

[0381] The transistor 721 in element layer 720 is formed on the front side (also called the "first side") of the substrate 722. The element layer 730 is formed on the back side (the side opposite to the front side, also called the "second side") of the substrate 722. Therefore, the transistor 731 in element layer 730 is formed on the second side of the substrate 722.

[0382] In Figure 21, the functional circuit 711 is illustrated by a CPU 712, a GPU 713, and a memory 714.

[0383] Furthermore, the functional circuit 711 is not limited to the CPU 712, GPU 713, and memory 714, and one or more of these can be used. It is also possible to include circuits with other functions.

[0384] To improve the operating speed, mounting density, and power consumption of the semiconductor device 710, the functional circuit 711 requires miniaturization and thinning of transistors, wiring, etc., and reduction of the power supply voltage. The switch circuit 715 can control the supply of externally supplied voltage to each circuit of the functional circuit 711, and to stop the supply. This makes it possible to stop the supply of power voltage to circuits in standby mode, thereby reducing power consumption.

[0385] Furthermore, the transistors constituting the switch circuit 715 require high dielectric strength. One effective way to increase the dielectric strength of the transistors is to thicken the gate insulating film. Thus, transistors 721 and 731 require different performance characteristics. Therefore, different measures are required to improve the characteristics of transistors 721 and 731.

[0386] Furthermore, miniaturization and thinning are required for the functional circuit 711. Therefore, if the switch circuit 715 is constructed using the same process node as the functional circuit 711, not only the routing wiring but also the wiring for supplying power (power lines) will become thinner, and sufficient power cannot be supplied to the functional circuit 711. In addition, if the wiring resistance increases due to miniaturization, uneven power potential is likely to occur within the functional circuit 711 due to voltage drop. In order to stably supply power to the functional circuit 711, it is preferable that the wiring constituting the switch circuit 715 has a lower wiring resistance than the wiring constituting the functional circuit 711. In particular, it is preferable that the wiring that functions as a power line has a lower wiring resistance than the wiring constituting the functional circuit 711. One means of reducing wiring resistance is to increase the cross-sectional area of ​​the conductive layer that functions as wiring. However, in order to increase the cross-sectional area of ​​the conductive layer, it is necessary to increase one or both of the width and height of the conductive layer. Thus, it is preferable to use different process nodes for the functional circuit 711 and the switch circuit 715.

[0387] In a semiconductor device 710 according to one aspect of the present invention, by providing the functional circuit 711 and the switch circuit 715 on different element layers, different improvement measures can be implemented in the functional circuit 711 and the switch circuit 715. Furthermore, the functional circuit 711 and the switch circuit 715 can be formed at different process nodes.

[0388] In one aspect of the present invention, a plurality of conductive layers 732 that function as power lines and a switch circuit 715 can be arranged below the functional circuit 711, thereby reducing the occupied area of ​​the semiconductor device 710. Furthermore, it is preferable that the element layer 730, which is superimposed on the element layer 720, be formed using thin-film formation techniques such as CVD or sputtering. Therefore, the transistor 731 included in the element layer 730 is preferably a thin-film transistor.

[0389] At least a portion of the multiple conductive layers 732 of the element layer 730 can function as power lines. Furthermore, if the element layer 730 has a clock signal generation circuit, at least a portion of the multiple conductive layers 732 can function as clock signal lines. It is also possible to supply either or both of the power supply and / or clock signal supplied from an external source to the functional circuit 711 of the element layer 720 via at least a portion of the multiple conductive layers 732.

[0390] For example, it is possible to manufacture a die (semiconductor chip) containing the functional circuit 711 and a die containing the switch circuit 715 separately, and then mechanically bond them together using 3D integration technology. However, with 3D integration technology, improving the alignment accuracy is difficult because the two are bonded together mechanically, and miniaturizing the bumps used to connect them is also difficult, making it difficult to narrow the pitch of the connection points. As a result, there was a challenge in shortening the wiring distance required to supply power to the necessary parts of the functional circuit 711.

[0391] According to one aspect of the present invention, an element layer 730 including a switch circuit 715 is formed on the back side of the substrate 722 using thin-film formation technology, photolithography technology, or the like. Therefore, the semiconductor device 710 according to one aspect of the present invention is a monolithically stacked semiconductor device.

[0392] By forming the element layer 730 using thin-film formation technology, high-precision alignment at the photolithography level can be achieved. Furthermore, conductive layers that function as power lines can be connected to the necessary locations of the functional circuit 711 over extremely short distances. Therefore, the necessary voltage of power can be supplied to the necessary locations of the functional circuit 711. In addition, in the semiconductor device 710 according to one aspect of the present invention, since the connection distance between the switch circuit 715 and the functional circuit 711 is short, power loss related to power transmission is reduced, and power consumption can be reduced.

[0393] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0394] (Embodiment 7) This embodiment describes an example of an application of a semiconductor device according to one aspect of the present invention. Because a semiconductor device according to one aspect of the present invention can produce a transistor with good electrical characteristics and a small footprint, it is suitable for, for example, electronic components, electronic equipment, large computers, space equipment, and data centers.

[0395] [Electronic Components] Figure 22A shows a perspective view of a substrate (mounted substrate 9109) on which electronic components 9100 are mounted. The electronic component 9100 shown in Figure 22A has a semiconductor device 9101 inside a mold 9104. Some details are omitted in Figure 22A to show the inside of the electronic component 9100. The electronic component 9100 has a land 9105 on the outside of the mold 9104. The land 9105 is electrically connected to an electrode pad 9106, and the electrode pad 9106 is electrically connected to the semiconductor device 9101 via a wire 9107. The electronic component 9100 is mounted on a printed circuit board 9108, for example. Multiple such electronic components are combined and electrically connected on the printed circuit board 9108 to complete the mounted substrate 9109.

[0396] Furthermore, the semiconductor device 9101 includes a drive circuit layer 9102 and a storage layer 9103. The storage layer 9103 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 9102 and the storage layer 9103 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 9102 and the storage layer 9103, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0397] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0398] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 9103 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 9103, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0399] The semiconductor device 9101 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0400] Next, a perspective view of the electronic component 9110 is shown in Figure 22B. The electronic component 9110 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 9110 has an interposer 9111 on a package substrate 9112 (printed circuit board), and a semiconductor device 9114 and a plurality of semiconductor devices 9101 are provided on the interposer 9111.

[0401] Electronic component 9110 shows an example of using semiconductor device 9101 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 9114 can be used in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0402] The package substrate 9112 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 9111 can be, for example, a silicon interposer, a resin interposer, or a glass substrate interposer.

[0403] The interposer 9111 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 9111 also has the function of connecting integrated circuits provided on the interposer 9111 to electrodes provided on the package substrate 9112. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 9111, and these through electrodes may be used to connect the integrated circuits and the package substrate 9112. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0404] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0405] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0406] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 9110, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0407] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 9110. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 9111. For example, in the electronic component 9110 shown in this embodiment, it is preferable to align the heights of the semiconductor device 9101 and the semiconductor device 9114.

[0408] To mount the electronic component 9110 onto another substrate, electrodes 9113 may be provided at the bottom of the package substrate 9112. Figure 22B shows an example in which the electrodes 9113 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 9112, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 9113 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 9112, PGA (Pin Grid Array) mounting can be achieved.

[0409] The electronic component 9110 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0410] [Large-scale computer] Next, Figure 23A shows a perspective view of the large-scale computer 9200. In the large-scale computer 9200 shown in Figure 23A, multiple rack-mount type computers 9220 are housed in rack 9210. The large-scale computer 9200 may also be referred to as a supercomputer.

[0411] The computer 9220 can have the configuration shown in the perspective view in Figure 23B, for example. In Figure 23B, the computer 9220 has a motherboard 9230, which has multiple slots 9231 and multiple connection terminals. A PC card 9221 is inserted into a slot 9231. In addition, the PC card 9221 has connection terminals 9223, 9224, and 9225, which are each connected to the motherboard 9230.

[0412] The PC card 9221 shown in Figure 23C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 9221 has a board 9222. The board 9222 also has connection terminals 9223, 9224, 9225, semiconductor device 9226, semiconductor device 9227, semiconductor device 9228, and connection terminal 9229. Although Figure 23C shows semiconductor devices other than semiconductor device 9226, semiconductor device 9227, and semiconductor device 9228, you can refer to the descriptions of semiconductor device 9226, semiconductor device 9227, and semiconductor device 9228 below for details on these semiconductor devices.

[0413] The connection terminal 9229 has a shape that allows insertion into a slot 9231 of a motherboard 9230, and functions as an interface for connecting the PC card 9221 and the motherboard 9230.

[0414] The semiconductor device 9226 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 9226 and the board 9222 can be connected by inserting the terminals into sockets (not shown) provided on the board 9222.

[0415] Examples of the semiconductor device 9227 include FPGA, GPU, CPU, and the like. As the semiconductor device 9227, for example, the electronic component 9110 can be used.

[0416] Examples of the semiconductor device 9228 include a storage device and the like. As the semiconductor device 9228, for example, the electronic component 9110 can be used.

[0417] The large-scale computer 9200 can also function as a parallel computer. By using the large-scale computer 9200 as a parallel computer, for example, large-scale calculations required for artificial intelligence learning and inference can be performed.

[0418] [Space Equipment] The semiconductor device according to one aspect of the present invention can be suitably used for space equipment.

[0419] The semiconductor device according to one aspect of the present invention includes an OS transistor. Compared with Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation irradiation. In other words, since it has high resistance to radiation, it has high reliability in environments where radiation can be incident and can be suitably used. For example, OS transistors can be suitably used when used in outer space. Specifically, an OS transistor can be used as a transistor constituting a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Note that outer space refers to, for example, an altitude of 100 km or more, but outer space described in this specification may include one or more of the thermosphere, mesosphere, and stratosphere.

[0420] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0421] Figure 23D shows an example of space equipment, specifically a satellite 9300. The satellite 9300 comprises a body 9301, solar panels 9302, an antenna 9303, a secondary battery 9305, and a control device 9306. In Figure 23D, a planet 9304 is shown as an example in outer space.

[0422] Furthermore, although not shown in Figure 23D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 9305. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0423] Furthermore, the control device 9306 has the function of controlling the artificial satellite 9300. The control device 9306 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 9306.

[0424] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0425] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0426] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as by ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0427] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0428] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0429] Figure 23E shows a storage system applicable to a data center. The storage system 9400 shown in Figure 23E has multiple servers 9401sb as hosts 9401 (shown as Host Computer) and multiple storage devices 9403md as storage 9403 (shown as Storage). The host 9401 and storage 9403 are connected via a storage area network 9404 (SAN: Storage Area Network) and a storage control circuit 9402 (shown as Storage Controller).

[0430] Host 9401 corresponds to a computer that accesses data stored in storage 9403. The hosts 9401 may be connected to each other via a network.

[0431] Although the storage 9403 uses flash memory to shorten data access speed, that is, the time required for data storage and output, this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and output in order to solve the access speed problem of the storage 9403.

[0432] The aforementioned cache memory is used within the storage control circuit 9402 and storage 9403. Data exchanged between the host 9401 and storage 9403 is stored in the cache memory within the storage control circuit 9402 and storage 9403, and then output to the host 9401 or storage 9403.

[0433] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0434] This embodiment can be implemented in appropriate combination with other embodiments or examples described herein, at least in part.

[0435] In this example, we will describe the results of forming and analyzing indium oxide according to one embodiment of the present invention.

[0436] Sample 1 was prepared and analyzed using the method shown in Embodiment 1. First, the method for preparing Sample 1 will be explained. Figure 24B is a schematic plan view of Sample 1. Figure 24A is a schematic cross-sectional view of Sample 1 corresponding to the area between the dashed lines F1 and F2 shown in Figure 24B.

[0437] As shown in Figure 24A, sample 1 was prepared by forming a silicon oxide film with a target thickness of 220 nm as an insulator 10 using the sputtering method. Subsequently, the insulator 10 was subjected to CMP treatment.

[0438] Subsequently, an indium oxide film with a target thickness of 2 nm was formed on the insulator 10 as the first layer 20 using the ALD method. After that, microwave-excited plasma treatment was performed. The microwave-excited plasma treatment was carried out using oxygen gas and argon gas with an oxygen flow rate ratio of 25%, at a substrate temperature of 400°C and a pressure of 400 Pa for 30 minutes. After that, the film to be the first layer 20 was processed to form the first layer 20.

[0439] Subsequently, an indium oxide film with a target thickness of 10 nm was formed as the metal oxide 30 by sputtering. Then, a mask was formed on the film to be the metal oxide 30, and the film to be the metal oxide 30 was processed to form the metal oxide 30. The metal oxide 30 was formed at a lower temperature than the treatment to enhance the crystallinity of the metal oxide 30. More specifically, the processing temperature when forming the mask on the film to be the metal oxide 30 was set to a lower temperature than the treatment to enhance the crystallinity of the metal oxide 30. A two-layer structure of an SOG film and a photoresist on the SOG film was used as the mask. When forming the mask, the substrate temperature was set to 150°C during the heat treatment after SOG coating. The substrate temperature was set to 90°C during the heat treatment after photoresist coating.

[0440] The design values ​​for the mask were set as follows: width ja = 350 nm, width jb = 210 nm, width jc = 960 nm, and width jd = 960 nm in Figure 24B. Width ja corresponds to the design value of width j1 along the first direction D1 of the third region 30_3 shown in Embodiment 1. Width jd corresponds to the design value of width j2 along the first direction D1 of the second region shown in Embodiment 1.

[0441] After the formation of the metal oxide 30, a treatment was performed to enhance the crystallinity of the metal oxide 30. This treatment involved heating the substrate at a reduced pressure atmosphere at 195°C for 60 minutes.

[0442] Sample 1 was prepared as described above.

[0443] Sample 1 was analyzed using a planar transmission electron microscope (TEM) image and electron diffraction mapping. TEM images were acquired using a JEOL Ltd. JEM-ARM200F atomic-resolution analytical electron microscope with an acceleration voltage of 200 kV. Electron diffraction mapping was also performed using a JEOL Ltd. JEM-ARM200F atomic-resolution analytical electron microscope with an acceleration voltage of 200 kV, an observation area of ​​5 μm × 5 μm, and an observation step of 20 nm. For crystal orientation analysis, a NanoMegas ASTAR crystal orientation analysis system was used.

[0444] The results of the analysis are shown in Figure 24C. Figure 24C shows a crystal grain map superimposed on the TEM image. Crystal grain boundaries were analyzed where adjacent observation points had an orientation difference of 5° or more, and these are shown as solid lines in Figure 24C. Note that since an i-line exposure machine was used to form the metal oxide 30 in sample 1, the corners of the metal oxide 30 have a rounded shape in plan view.

[0445] In Figure 24C, the first region 30_1 was confirmed to be a region where polycrystallization is formed on the first layer 20. In the second region 30_2 in Figure 24C, crystals grew from the first region 30_1 (this crystal growth can be called lateral growth), suggesting that crystal grain selection occurs through competition for crystal growth by geometric selection. In Figure 24C, the metal oxide 30 selects crystal grains by making the width j1 of the third region narrower than the width j2 of the second region, thereby guiding only the crystal grains that have preferentially grown toward the third region 30_3 to the third region 30_3 and allowing them to grow.

[0446] In other words, in the third region 30_3 in Figure 24C, a tendency for larger grain sizes to be observed compared to the first region 30_1 and the second region 30_2 was confirmed. Furthermore, in the third region 30_3 in Figure 24C, it was suggested that only the grains that grew toward the third region 30_3 from among the grains that grew in the first region 30_1 and the second region 30_2 were guided to the third region 30_3, underwent crystal growth there, and thus the grain size of the grains became larger. In addition, it was confirmed that the preferential growth of grains that reached the third region 30_3 suppressed the formation of grain boundaries in the third region 30_3.

[0447] The configurations, structures, or methods shown in this embodiment can be used in appropriate combination with the configurations, structures, or methods shown in other embodiments or examples.

[0448] 10: Insulator, 20: First layer, 20f: First layer, 21: Resist mask, 30: Metal oxide, 30_1: First region, 30_2: Second region, 30_3: Third region, 30_4: Fourth region, 30_5: Fifth region, 30f: Metal oxide, 31: Mask, 32: Mask, 50: Transistor, 51: Insulator, 51_1: Insulator, 51_2: Insulator, 52: Insulator, 53: Conductor, 53_1: Conductor, 53_2: Conductor, 53a: Conductor, 53a_1: Conductor, 53a_2: Conductor, 54: Insulator, 54_1: Insulator, 54_2: Insulator, 54_3: Insulator, 57: Conductor, 57_1: Conductor, 57_1a: Conductor, 57_1b: Conductor, 57_2: Conductor, 57_2a: Conductor, 57_2b: Conductor, 57a: Conductor, 57b: Conductor, 58: Insulator, 59: Insulator, 60: Insulator, 61: Insulator, 62: Insulator, 63: Conductor, 63_1: Conductor, 63_2: Conductor, 64: Insulator, 64_1: Insulator, 64_2: Insulator, 64_3: Insulator, 65: Insulator, 66: Conductor, 66_1a: Conductor, 66_1b: Conductor, 66_2: Conductor, 66_2a: Conductor, 66_2b: Conductor Electromagnetic material, 66a: Conductor, 66b: Conductor, 66c: Conductor, 67: Conductor, 67a: Conductor, 67b: Conductor, 67c: Conductor, 70: Transistor, 71: Insulator, 71_1: Insulator, 71_2: Insulator, 72: Conductor, 73: Insulator, 76: Insulator, 77: Conductor, 78: Insulator, 79: Conductor, 79a: Conductor, 79b: Conductor, 80: Insulator, 90: Capacitive element, 91: Insulator, 92: Conductor, 93: Insulator, 94: Insulator, 100: Memory cell, 710: Semiconductor device, 711: Functional circuit, 712: CPU, 713: GPU, 714: Memory, 7 15: Switch circuit, 720: Element layer, 721: Transistor, 722: Substrate, 730: Element layer, 731: Transistor, 732: Conductive layer, 740: Support substrate, 741: Insulating layer, 802: Conductor, 802a: Conductor, 802b: Conductor, 802c: Conductor, 803: Insulator, 804: Insulator, 805: Conductor, 805a: Conductor, 805b: Conductor, 805c: Conductor, 900: Si transistor, 901: Substrate, 902: Element isolation layer, 903: Semiconductor region, 904: Low resistance region, 905: Insulator, 906: Insulator, 907: Insulator, 908a: Conductor908b: Dummy gate electrode, 908c: Dummy gate electrode, 909: Insulator, 910: Insulator, 911: Insulator, 912: Conductor, 913: Insulator, 914: Insulator, 915: Conductor, 916: Insulator, 917: Conductor, 918: Insulator, 919: Insulator, 920: Conductor, 8000: Semiconductor, 8001: PSW, 8002: PSW, 8003: Peripheral circuit, 8004: Peripheral circuit, 8005: Control circuit, 8006: Voltage generation circuit, 8007: Row decoder, 8008: Column decoder Coder, 8009: Row driver, 8010: Column driver, 8011: Sense amplifier, 8012: Input circuit, 8013: Output circuit, 8110: Drive circuit, 8120: Memory array, 8130: Memory cell, 8131: Memory cell, 8132: Memory cell, 8133: Memory cell, 8134: Memory cell, 8135: Memory cell, 8136: Memory cell, 8137: Memory cell, 8138: Memory cell, 8200A: Semiconductor device, 8210: Arithmetic unit, 8220: Layer, 9100: Electronic component 9101: Semiconductor device, 9102: Drive circuit layer, 9103: Memory layer, 9104: Mold, 9105: Land, 9106: Electrode pad, 9107: Wire, 9108: Printed circuit board, 9109: Mounted board, 9110: Electronic component, 9111: Interposer, 9112: Package substrate, 9113: Electrode, 9114: Semiconductor device, 9200: Large computer, 9210: Rack, 9220: Computer, 9221: PC card, 9222: Board, 9223: Connector terminal, 9224: Connector terminal 9225: Connector terminal, 9226: Semiconductor device, 9227: Semiconductor device, 9228: Semiconductor device, 9229: Connector terminal, 9230: Motherboard, 9231: Slot, 9300: Satellite, 9301: Aircraft body, 9302: Solar panel, 9303: Antenna, 9304: Planet, 9305: Rechargeable battery, 9306: Control device, 9400: Storage system, 9401: Host, 9401sb: Server, 9402: Storage control circuit, 9403: Storage, 9403md: Memory device,

Claims

A first step involves forming an island-like first layer having crystals on an insulator, A second step involves covering the first layer to form a metal oxide, A third step involves processing the aforementioned metal oxide into an island-like shape, The process includes a fourth step of performing a crystallization treatment on the metal oxide, In the third step described above, the island-shaped metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer, The second region is adjacent to the first region and is located between the first region and the third region. The width of the third region along the first direction is narrower than the width of the second region along the first direction. The third step is a method for forming a metal oxide, wherein the third step is performed at a temperature lower than the processing temperature of the fourth step. 　 In claim 1, A method for forming a metal oxide, wherein the second region and the third region are in contact with the insulator, respectively. 　 In claim 1, The first step described above is, The first step is to form the first layer having metal and oxygen on the insulator, The second step involves performing a treatment on the first layer to increase its crystallinity, A method for forming a metal oxide, comprising a third step of processing the first layer. 　 In claim 3, The aforementioned process for increasing crystallinity is microwave-excited plasma treatment, which is a method for forming metal oxides. 　 In claim 1, The crystallization process is a heat treatment under reduced pressure, which is a method for forming a metal oxide. 　 In claim 1, Between the first step and the second step, there is a fifth step. The fifth step is a method for forming a metal oxide, wherein the first layer is subjected to microwave-excited plasma treatment. 　 In claim 1, In the third step, the metal oxide is processed to have a fourth region, In a plan view, the fourth region is located between the second region and the third region. A method for forming a metal oxide, wherein the width of the fourth region along the first direction is continuously narrowed from the width of the second region to the width of the third region. 　 In claim 1, In the third step, the metal oxide is processed to have a fourth region, In a plan view, the fourth region is located between the second region and the third region. A method for forming a metal oxide, wherein the width of the fourth region along the first direction is narrower than the width of the second region along the first direction and wider than the width of the third region along the first direction. 　 In claim 1, In the third step, the metal oxide is processed to have a fourth region, In a plan view, the fourth region is located between the second region and the third region. A method for forming a metal oxide, wherein the width of the fourth region along the first direction is narrower than the width of the third region along the first direction. 　 In claim 1, A method for forming a metal oxide, wherein, in a plan view, the metal oxide has an opening between the first region and the third region of the second region. 　 It comprises a first insulator, a second insulator, a first layer, a metal oxide, a first conductor, a second conductor, and a third conductor. The aforementioned metal oxide functions as a channel formation region for the transistor. The first conductor functions as the gate electrode of the transistor. The first layer is located on the first insulator, The metal oxide is located on the first insulator and on the first layer. The second insulator is located between the metal oxide and the first conductor. The metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer, The second region and the third region are in contact with the first insulator, The second region is adjacent to the first region and is located between the first region and the third region. In a plan view, the width of the third region along a first direction perpendicular to the channel length direction of the transistor is narrower than the width of the second region along the first direction. The third region of the metal oxide has a first portion that overlaps with the first conductor, a second portion that is in contact with the second conductor, and a third portion that is in contact with the third conductor. The first part is a semiconductor device located between the second part and the third part. 　 It comprises a first insulator, a second insulator, a third insulator, a first layer, a metal oxide, a first conductor, a second conductor, and a third conductor. The aforementioned metal oxide functions as a channel formation region for the transistor. The first conductor functions as the gate electrode of the transistor. The first layer is located on the first insulator, The metal oxide is located on the first insulator and on the first layer. The second insulator is located between the metal oxide and the first conductor. The third insulator is located on the first conductor, The second conductor and the third conductor are located on the third insulator. The metal oxide has a first region, a second region, and a third region. The first region is in contact with the first layer, The second region and the third region are in contact with the first insulator, The second region is adjacent to the first region and located between the first region and the third region. In a plan view, the width of the third region along a first direction perpendicular to the channel length direction of the transistor is narrower than the width of the second region along the first direction. The third region of the metal oxide has a first portion that overlaps with the first conductor, A semiconductor device in which the second conductor and the third conductor each have regions that are in contact with the metal oxide through an opening formed in the third insulator. 　 In either claim 11 or claim 12, The first part is a semiconductor device having a cross-section in which no grain boundaries are observed by analysis using a transmission electron microscope in a direction parallel to the channel length direction of the transistor. 　 In either claim 11 or claim 12, The metal oxide is a semiconductor device having crystal grains that overlap with a pair of ends of the first conductor that face each other in the channel length direction of the transistor. 　 In any one of claims 1 to 12, A semiconductor device comprising the first layer and the metal oxide, respectively, indium.

Images