Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device that has excellent electrical properties. This semiconductor device comprises a metal oxide layer, a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer. The metal oxide layer has a first portion and a second portion on the first portion. The value of the potential barrier of the second portion is lower than the value of the potential barrier of the first portion. The value of the potential barrier of the second portion is at least 0 meV and less than 7 meV. The first portion includes a first element. The first element is at least one of gallium and aluminum.

Description

Semiconductor device, method for manufacturing a semiconductor device

[0001] One aspect of the present invention relates to a semiconductor device and electronic equipment using an oxide semiconductor. Another aspect of the present invention relates to a method for manufacturing the above-mentioned semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (such as liquid crystal displays and light-emitting displays), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs (Large Scale Integration), CPUs (Central Processing Units), and memory are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and capacitors) formed on chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain its contents for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, Patent Document 3 discloses a transistor with a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the upper surface of an oxide semiconductor.

[0009] Also, In ２ O ３ Its use in thin-film transistors has been reported (Non-Patent Document 1).

[0010] Japanese Patent Publication No. 2012-257187, Japanese Patent Publication No. 2011-151383, International Publication No. 2016-125052

[0011] Dhananjay and C. W. Chu, “Realization of In2O3 thin film transistors through reactive evaporation process.” Appl. Phys. Lett. 91, 132111 (2007). Takashi Koida, “High-mobility transparent conductive film,” National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0012] One aspect of the present invention aims to provide a semiconductor device having a transistor with a high on-current. One aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility. One aspect of the present invention aims to provide a semiconductor device having good electrical characteristics. One aspect of the present invention aims to provide a semiconductor device that can be miniaturized or highly integrated. One aspect of the present invention aims to provide a semiconductor device with low power consumption. One aspect of the present invention aims to provide a novel semiconductor device. One aspect of the present invention aims to provide a method for manufacturing a semiconductor device with high productivity. One aspect of the present invention aims to provide a method for manufacturing a novel semiconductor device.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0014] One aspect of the present invention is a semiconductor device having a metal oxide layer, a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer, wherein the potential barrier value of the metal oxide layer is 0 meV or more and less than 7 meV.

[0015] In the above-described semiconductor device, it is preferable that the potential barrier value of the metal oxide layer be calculated using formula (1).

[0016]

[0017] However, in formula (1), μ represents Hall mobility, ０ represents the intrinsic mobility, E ａｃｔ represents the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature.

[0018] In the above-described semiconductor device, it is preferable that the potential barrier value of the metal oxide layer is calculated under conditions where the metal oxide layer is in a carrier degenerate state and the Hall mobility of the metal oxide layer is temperature-dependent.

[0019] Furthermore, one aspect of the present invention is a semiconductor device comprising a metal oxide layer, a source electrode, a drain electrode, and a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer, wherein the metal oxide layer comprises a first portion and a second portion on the first portion, and the potential barrier value of the second portion is smaller than the potential barrier value of the first portion and is 0 meV or more and less than 7 meV.

[0020] In the above-described semiconductor device, it is preferable that the potential barrier value of the first part and the potential barrier value of the second part are calculated using formula (1).

[0021] In the semiconductor device described above, it is preferable that the value of the potential barrier of the first portion is calculated under the conditions that the first portion is in a carrier-degenerate state and the Hall mobility of the first portion is temperature-dependent, and that the value of the potential barrier of the second portion is calculated under the conditions that the second portion is in a carrier-degenerate state and the Hall mobility of the second portion is temperature-dependent.

[0022] In the semiconductor device described above, the first portion preferably includes a first element, and the first element is preferably at least one of gallium or aluminum.

[0023] In the above semiconductor device, the concentration of the first element in the first part is 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following conditions apply, and it is preferable that the concentration of the first element in the second portion is lower than the concentration of the first element in the first portion.

[0024] In the above semiconductor device, the metal oxide layer preferably has crystal grains, and it is preferable that the crystal grains consist of at least a portion of the first part and at least a portion of the second part. Furthermore, it is preferable that the crystal structure of the crystal grains is cubic.

[0025] Further, one aspect of the present invention is a semiconductor device comprising: a metal oxide layer; a source electrode, a drain electrode, and a gate insulating layer on the metal oxide layer; and a gate electrode on the gate insulating layer, wherein the metal oxide layer comprises a first portion, a second portion on the first portion, and a third portion on the second portion, the value of the potential barrier of the second portion is smaller than each of the value of the potential barrier of the first portion and the value of the potential barrier of the third portion, and is 0 meV or more and less than 7 meV.

[0026] In the semiconductor device described above, it is preferable that the value of the potential barrier of the first portion, the value of the potential barrier of the second portion, and the value of the potential barrier of the third portion are each calculated using mathematical formula (1).

[0027] In the semiconductor device described above, it is preferable that the value of the potential barrier of the first portion is calculated under a condition that the first portion is in a carrier degenerate state and the Hall mobility of the first portion has temperature dependence, the value of the potential barrier of the second portion is calculated under a condition that the second portion is in a carrier degenerate state and the Hall mobility of the second portion has temperature dependence, and the value of the potential barrier of the third portion is calculated under a condition that the third portion is in a carrier degenerate state and the Hall mobility of the third portion has temperature dependence.

[0028] In the semiconductor device described above, it is preferable that the first portion contains a first element, the third portion contains a second element, and each of the first element and the second element is at least one of gallium or aluminum.

[0029] In the semiconductor device described above, the concentration of the first element in the first portion is 1×10 １６ atoms / cm ３ or more and 5×10 １９ atoms / cm ３ or less, the concentration of the first element in the second portion is lower than the concentration of the first element in the first portion, and the concentration of the second element in the third portion is 1×10 １６ atoms / cm ３ or more and 5×10 １９ atoms / cm ３The following conditions apply, and it is preferable that the concentration of the second element in the second portion is lower than the concentration of the second element in the third portion.

[0030] In the semiconductor device described above, the metal oxide layer preferably has crystal grains, and it is preferable that the crystal grains consist of at least a portion of the first portion, at least a portion of the second portion, and at least a portion of the third portion. Furthermore, it is preferable that the crystal structure of the crystal grains is cubic.

[0031] In the above-described semiconductor device, the metal oxide layer preferably contains indium.

[0032] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming a first metal oxide film using a sputtering method; a second step of forming a second metal oxide film on the first metal oxide film using atomic layer deposition; a third step of processing the first metal oxide film and the second metal oxide film to form island-shaped metal oxide layers; a fourth step of forming a gate insulating layer on the metal oxide layer; and a fifth step of forming a gate electrode on the gate insulating layer, wherein in the first step, a sputtering target containing a first element, indium, and oxygen is used, and the first element is at least one of gallium or aluminum; in the second step, a precursor containing indium is used; and the potential barrier value of the metal oxide layer is 0 meV or more and less than 50 meV.

[0033] In the above-described method for manufacturing a semiconductor device, the concentration of the first element in the sputtering target is preferably 0.00001 atomic percent or more and 0.5 atomic percent or less.

[0034] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: a first step of forming a first metal oxide film using a sputtering method; a second step of adding a first element to the first metal oxide film; a third step of forming a second metal oxide film on the first metal oxide film using atomic layer deposition; a fourth step of processing the first metal oxide film and the second metal oxide film to form island-shaped metal oxide layers; a fifth step of forming a gate insulating layer on the metal oxide layer; and a sixth step of forming a gate electrode on the gate insulating layer, wherein in the first step, an indium oxide sputtering target is used, the first element is at least one of gallium or aluminum, in the third step, an indium-containing precursor is used, and the potential barrier value of the metal oxide layer is 0 meV or more and less than 50 meV.

[0035] In the above-described method for manufacturing a semiconductor device, it is preferable to use an ion implantation method or an ion doping method in the second step.

[0036] In the above-described method for manufacturing a semiconductor device, the purity of the sputtering target is preferably 5N or higher.

[0037] In the above method for manufacturing a semiconductor device, the purity of the precursor is preferably 5N or higher.

[0038] In the above-described method for manufacturing a semiconductor device, it is preferable that the potential barrier value of the metal oxide layer be calculated using formula (1).

[0039] In the above-described method for manufacturing a semiconductor device, it is preferable that the potential barrier value of the metal oxide layer is calculated under conditions in which the metal oxide layer is in a carrier degenerate state and the Hall mobility of the metal oxide layer is temperature-dependent.

[0040] According to one aspect of the present invention, a semiconductor device having a transistor with a high on-current can be provided. According to one aspect of the present invention, a semiconductor device having a transistor with high field-effect mobility can be provided. According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device with low power consumption can be provided. According to one aspect of the present invention, a novel semiconductor device can be provided. According to one aspect of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0041] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0042] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B, 1C, and 1D are cross-sectional views showing an example of a semiconductor device. Figures 2A, 2B, and 2C are cross-sectional views showing an example of a semiconductor device. Figures 3A, 3B, and 3C are cross-sectional views showing an example of a semiconductor device. Figure 4A is a plan view showing an example of a semiconductor device. Figures 4B, 4C, and 4D are cross-sectional views showing an example of a semiconductor device. Figure 5A is a plan view showing an example of a semiconductor device. Figures 5B, 5C, and 5D are cross-sectional views showing an example of a semiconductor device. Figure 6A is a plan view showing an example of a semiconductor device. Figures 6B, 6C, and 6D are cross-sectional views showing an example of a semiconductor device. Figure 7A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 7B, 7C, and 7D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 8A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 8B, 8C, and 8D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 9A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 9B, 9C, and 9D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 10A is a plan view showing an example of a semiconductor device manufacturing method. Figures 10B, 10C, and 10D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 11A is a plan view showing an example of a semiconductor device manufacturing method. Figures 11B, 11C, and 11D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 12A is a plan view showing an example of a semiconductor device manufacturing method. Figures 12B, 12C, and 12D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figures 13B, 13C, and 13D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figures 14B, 14C, and 14D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figures 15B, 15C, and 15D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figures 16B, 16C, and 16D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method.Figures 17B, 17C, and 17D are cross-sectional views showing an example of a semiconductor device fabrication method. Figure 18A is a plan view showing an example of a semiconductor device fabrication method. Figures 18B, 18C, and 18D are cross-sectional views showing an example of a semiconductor device fabrication method. Figure 19A is a plan view showing an example of a semiconductor device fabrication method. Figures 19B, 19C, and 19D are cross-sectional views showing an example of a semiconductor device fabrication method. Figures 20A and 20B are diagrams illustrating the carrier concentration dependence of Hall mobility. Figure 20C is a cross-sectional view illustrating an indium oxide film. Figures 21A and 21B are examples of the configuration of a display device. Figure 22 is an example of the configuration of a display device. Figures 23A, 23B, 23C, 23D, 23E, and 23F are examples of the configuration of electronic equipment. Figures 24A, 24B, 24C, 24D, 24E, and 24F are examples of the configuration of electronic equipment. Figures 25A, 25B, 25C, 25D, 25E, 25F, and 25G show examples of electronic device configurations. Figure 26 is a block diagram illustrating an example of semiconductor device configuration. Figures 27A and 27B show examples of electronic components. Figures 28A, 28B, and 28C show examples of large-scale computers. Figure 28D shows an example of space equipment. Figure 28E shows an example of a storage system applicable to data centers. Figures 29A, 29B, and 29C show the results of Hall effect measurements according to the embodiment. Figure 30 shows the results of Hall effect measurements according to the embodiment. Figures 31A and 31B are graphs showing the measurement results of electrical characteristics according to the embodiment. Figure 32 is a graph showing the measurement results of external resistance and channel resistance according to the embodiment. Figures 33A and 33B are graphs showing the measurement results of electrical characteristics according to the embodiment. Figures 34A and 34B are graphs showing the measurement results of electrical characteristics according to the embodiment.

[0043] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0044] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0045] Furthermore, for the sake of ease of understanding, the position, size, and scope of each component shown in the drawings may not represent their actual position, size, and scope. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0046] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Furthermore, the ordinal numbers used for components in one part of this specification may not be the same as those used for the same components in other parts of this specification or in the claims.

[0047] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer." Furthermore, the term "conductor" can be interchanged with the terms "conductive layer" or "conductive film" depending on the context or situation. Similarly, the term "insulator" can be interchanged with the terms "insulating layer" or "insulating film" depending on the context or situation.

[0048] An opening can include, for example, grooves and slits. Furthermore, the area in which an opening is formed may also be referred to as an opening.

[0049] Furthermore, although the drawings used in this specification show the side surface of the insulating layer at the opening of the insulating layer perpendicular to the substrate surface or the surface to be formed, it may also be tapered.

[0050] Furthermore, in this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. Note that the side surface of the structure and the substrate surface do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0051] In this specification, "heights match" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as the substrate surface) are equal in a cross-sectional view. For example, if there are two layers with different heights (here referred to as layer A and layer B) with respect to the reference surface, the heights also match if the difference between the height of the top surface of layer A and the height of the top surface of layer B is 10 nm or less.

[0052] In this specification, "side edges coincide" means that, in a plan view (also called a top view), at least a portion of the contours of the stacked layers overlap. For example, in the case of two stacked layers (here referred to as layer A and layer B), if the shortest distance from the side edge of layer A to the side edge of layer B is 10 nm or less in a plan view, then the side edges also coincide.

[0053] In general, it can be difficult to clearly distinguish between "exact match" and "approximate match." Therefore, in this specification, "match" may include both exact matches and approximate matches.

[0054] Furthermore, in this specification, transistors using an oxide semiconductor or metal oxide in the semiconductor layer, and transistors having an oxide semiconductor or metal oxide in the channel formation region, may be referred to as OS transistors. Also, transistors having silicon in the channel formation region may be referred to as Si transistors.

[0055] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the semiconductor device will be described with reference to Figures 1A to 19D.

[0056] <Example of Semiconductor Device Configuration> An example of a semiconductor device configuration will be explained using Figures 1A to 1D. Figure 1A is a plan view of a semiconductor device having a transistor 200, and Figures 1B to 1D are cross-sectional views of the said semiconductor device. Figure 1B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Figure 1C is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1D is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the plan view of Figure 1A, some elements have been omitted for clarity. Figures 2A to 3C show enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0057] A semiconductor device having a transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, oxide layers 231a and 231b spaced apart from each other on the semiconductor layer 230, a conductive layer 242a on the oxide layer 231a, a conductive layer 242b on the oxide layer 231b, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0058] In the semiconductor device described above, the semiconductor layer 230 has a region that functions as a channel formation region of the transistor 200. The conductive layer 260 has a region that functions as the first gate electrode of the transistor 200 (also called the upper gate electrode or top gate electrode). The insulating layer 250 has a region that functions as the first gate insulating layer of the transistor 200. The conductive layer 205 has a region that functions as the second gate electrode of the transistor 200 (also called the lower gate electrode or bottom gate electrode). The insulating layers 224, 222, and 221 each have regions that function as the second gate insulating layers of the transistor 200. The conductive layer 242a has a region that functions as either the source electrode or the drain electrode of the transistor 200, and the conductive layer 242b has a region that functions as the other.

[0059] An insulating layer 271a is provided on the conductive layer 242a, and an insulating layer 271b is provided on the conductive layer 242b. An insulating layer 275 is provided on the insulating layers 271a and 271b, and an insulating layer 280 is provided on the insulating layer 275. An opening 289 is formed in the insulating layer 280 and the insulating layer 275. The opening 289 overlaps with the region between the conductive layer 242a and the conductive layer 242b. The insulating layer 250 and the conductive layer 260 are arranged within the opening 289. The conductive layer 260 is formed self-aligningly so as to fill the opening 289. As a result, the conductive layer 260 can be placed overlapping the above region without the need for alignment.

[0060] The side walls of the opening 289 may be perpendicular to the upper surface of the insulating layer 222, or they may be tapered. By making the side walls tapered, the covering of the insulating layer 250 and the like provided in the opening 289 is improved, and defects such as porosity can be reduced. The side walls of the opening 289 correspond, for example, to the sides of the insulating layer 280 and the like in the opening 289.

[0061] An insulating layer 255 is placed inside the opening 289. The insulating layer 255 is provided in a sidewall shape, in contact with the side wall of the opening 289.

[0062] Insulating layers 282, 283, and 285 are laminated in this order on the insulating layer 280, insulating layer 255, insulating layer 250, and conductive layer 260.

[0063] An insulating layer 216 is provided below the insulating layer 221, and a conductive layer 205 is provided so as to be embedded in the insulating layer 216. An insulating layer 214 is provided below the insulating layer 216 and below the conductive layer 205, and an insulating layer 212 is provided below the insulating layer 214.

[0064] The insulating layers 212, 214, 280, 282, 283, and 285 function as interlayer films.

[0065] Insulating layers 285, 283, 282, 280, 275, and 271a have openings that reach the conductive layer 242a, with the insulating layer 241a provided in contact with the side wall of the opening, and the conductive layer 240a provided inside the insulating layer 241a. In addition, insulating layers 285, 283, 282, 280, 275, and 271b have openings that reach the conductive layer 242b, with the insulating layer 241b provided in contact with the side wall of the opening, and the conductive layer 240b provided inside the insulating layer 241b. The conductive layers 240a and 240b function as vias connecting wiring etc. provided on the transistor 200 to the source or drain of the transistor 200.

[0066] The semiconductor layer 230 uses a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor). Preferably, the semiconductor layer 230 has an oxide containing indium, for example, indium oxide. By having an oxide containing indium in the semiconductor layer 230, the field-effect mobility of the transistor 200 can be increased. In addition, the on-current of the transistor 200 can be increased. Furthermore, a transistor 200 can be provided with good electrical characteristics, frequency characteristics, and reliability, at least one of which is good.

[0067] The band gap of indium-containing oxides (typically indium oxide) is larger than that of silicon (typically 1.1 eV), being 2 eV or more, or 2.5 eV or more. By using an oxide with a larger band gap than silicon in the semiconductor layer 230, the off-current of the transistor 200 can be reduced. By using a transistor with a small off-current in the semiconductor device, the power consumption of the semiconductor device can be significantly reduced.

[0068] The semiconductor layer 230 has a channel formation region and a source region and drain region that are provided so as to sandwich the channel formation region in the transistor 200. At least a portion of the channel formation region overlaps with the conductive layer 260. One of the source region or the drain region overlaps with the conductive layer 242a, and the other overlaps with the conductive layer 242b. The source region and the drain region can be swapped with each other.

[0069] The conductivity of oxide layer 231a and oxide layer 231b is preferably higher than the conductivity of semiconductor layer 230. Depending on its conductivity, oxide layer 231a may function as either a source region or a drain region, or as either a source electrode or a drain electrode. Similarly, depending on its conductivity, oxide layer 231b may function as either a source region or a drain region, or as either the other source electrode or a drain electrode.

[0070] The channel-forming region is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions. Therefore, the channel-forming region can be said to be type i (intrinsic) or substantially type i. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Furthermore, impurities in the semiconductor layer 230 refer to elements other than the main components constituting the semiconductor layer 230. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0071] Furthermore, the source and drain regions are low-resistance regions with high carrier concentrations due to a high oxygen deficiency or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel-forming region.

[0072] In n-type semiconductor metal oxides, a potential barrier exists above the lower end of the conduction band that inhibits the conduction of carriers (electrons). Furthermore, this potential barrier is thought to be caused by fluctuations in the conduction band and is presumed to be thermally activated. In other words, the higher the thermally activated potential barrier, the more electron conduction is inhibited, potentially leading to a smaller on-current in the transistor.

[0073] Therefore, it is preferable to use a metal oxide layer with a low potential barrier as the semiconductor layer 230. For example, it is preferable to use a metal oxide layer with a potential barrier value of 0 meV or more and less than 50 meV, preferably 0 meV or more and less than 30 meV, more preferably 0 meV or more and less than 10 meV, and even more preferably 0 meV or more and less than 7 meV. It is also preferable to use a metal oxide layer with a potential barrier value greater than 0 meV and less than 50 meV, preferably greater than 0 meV and less than 30 meV, more preferably greater than 0 meV and less than 10 meV, and even more preferably greater than 0 meV and less than 7 meV. By using a metal oxide layer with a potential barrier value in the above range as the semiconductor layer 230, inhibition of electron conduction is suppressed, and the on-current of the transistor 200 can be increased. In addition, the field-effect mobility of the transistor 200 can be increased.

[0074] The potential barrier value of the metal oxide layer can be calculated using formula (1).

[0075]

[0076] In equation (1), μ represents Hall mobility, ０ represents the intrinsic mobility, E ａｃｔ θ represents the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature. In this specification, μ in equation (1) may be the carrier (electron) mobility or the field-effect mobility.

[0077] The potential barrier value can be calculated under the condition that the metal oxide layer is in a carrier-degenerate state and that the Hall mobility of the metal oxide layer is temperature-dependent. A carrier-degenerate state refers to a state where the Fermi level is located at or above the lower end of the conduction band, and this can be evaluated by calculating the carrier concentration of the metal oxide layer. For example, if the carrier concentration is, for example, 1 × 10⁻⁶ １８ cm −３ The above 1 x 10 １９ cm −３The metal oxide layer described below can be said to be in a carrier-degenerate state. Furthermore, when the carrier concentration is sufficiently high, the Fermi level is located above the potential barrier, and the Hall mobility becomes temperature-independent.

[0078] Note E ａｃｔ This can also be called the activation energy. The activation energy is the difference between the potential barrier and the Fermi level. When the metal oxide layer is in a carrier-degenerate state and the carrier concentration in the metal oxide layer is not sufficiently high, the Fermi level is located near the lower end of the conduction band. In this case, the activation energy and the height of the potential barrier are equivalent. For this reason, in this specification and elsewhere, the potential barrier and the activation energy can be interpreted as each other.

[0079] Hall mobility and carrier concentration can be evaluated, for example, by measuring the Hall effect.

[0080] The semiconductor layer 230 preferably has an oxide containing indium, and more preferably has indium oxide. This makes it possible to set the potential barrier value of the semiconductor layer 230 within the above range.

[0081] Here, generally speaking, the barrier height at the grain boundaries of low-temperature polysilicon (LTPS) is between 60 meV and 80 meV. By using a metal oxide (e.g., indium oxide) with a lower potential barrier than LTPS for the semiconductor layer 230, it is possible to obtain a transistor with higher field-effect mobility than a transistor using LTPS in the channel formation region (also called an LTPS transistor). Furthermore, it is possible to obtain a transistor with a large on-current. In this specification, the potential barrier and the barrier height at the grain boundaries can be read interchangeably.

[0082] It is preferable that the semiconductor layer 230 has high purity. In particular, it is preferable that the purity in the channel formation region is high. It is also preferable that the impurity concentration in the semiconductor layer 230 is low. In particular, it is preferable that the impurity concentration in the channel formation region is low. For example, when indium oxide is used as the semiconductor layer 230, the purity of the semiconductor layer 230, or the purity in the channel formation region, is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, more preferably 5N (99.999%) or higher, more preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) or higher, more preferably 8N (99.999999%) or higher, more preferably 9N (99.9999999%) or higher, and even more preferably 10N (99.99999999%) or higher. It is presumed that impurity elements (elements other than indium and oxygen) in the indium oxide film tend to be concentrated at the grain boundaries. In other words, it is hypothesized that when impurity elements are present in an indium oxide film, the uneven distribution of these impurity elements facilitates the formation of grain boundaries. Therefore, by reducing the amount of impurity elements in the indium oxide film, or by forming an indium oxide film with a low concentration of impurity elements, the formation of grain boundaries in the indium oxide film can be suppressed, thereby lowering the potential barrier.

[0083] The purity of a layer or film can be evaluated using methods such as inductively coupled plasma mass spectrometry (ICP-MS) or secondary ion mass spectrometry (SIMS). Alternatively, a combination of these methods may be used. For example, the purity of the layer or film can be evaluated by screening for metal elements contained in the layer or film using ICP-MS, and then analyzing the detected metal elements down to low concentrations using SIMS.

[0084] Figures 1B to 1D show a configuration in which the semiconductor layer 230 is a single layer, but the present invention is not limited thereto. The semiconductor layer 230 can also be a stacked structure of two or more layers.

[0085] Figure 2A shows an example where the semiconductor layer 230 has a two-layer structure consisting of semiconductor layer 230a and semiconductor layer 230b on top of semiconductor layer 230a. In this case, the channel formation region, source region, and drain region are mainly formed in semiconductor layer 230b, which is closer to the conductive layer 260.

[0086] It is preferable to use a metal oxide layer with a lower potential barrier than semiconductor layer 230a as the semiconductor layer 230b. This allows the main current path to be in the semiconductor layer 230b. For example, it is preferable that the potential barrier value of semiconductor layer 230b is smaller than the potential barrier value of semiconductor layer 230a, and is between 0 meV and 7 meV.

[0087] Incidentally, two types of current modes are formed in an OS transistor: surface current and bulk current. When the gate voltage is sufficiently large, the surface current becomes the main current of the OS transistor. Therefore, by making the semiconductor layer 230b, which is closer to the conductive layer 260, the main current path, the field-effect mobility of the transistor 200 can be increased. In addition, the ON current of the transistor 200 can be increased.

[0088] Furthermore, the channel formation region, source region, and drain region may each be formed not only on semiconductor layer 230b but also on semiconductor layer 230a. By using semiconductor layer 230a as a path for bulk current, the field-effect mobility of transistor 200 can be increased. In addition, the on-current of transistor 200 can be increased.

[0089] Therefore, it is preferable that the potential barrier value of the semiconductor layer 230a is low, and it is preferable to use a metal oxide layer as the semiconductor layer 230a whose potential barrier value is within the range described above. For example, if an oxide containing indium is used as the semiconductor layer 230b, it is preferable to use an oxide containing indium as the semiconductor layer 230a as well. This makes it possible to provide a semiconductor device having a transistor with high field-effect mobility. Furthermore, it is possible to provide a semiconductor device with good electrical characteristics, frequency characteristics, and reliability at least one of these.

[0090] Furthermore, if the potential barrier value of semiconductor layer 230b is smaller than the potential barrier value of semiconductor layer 230a, the potential barrier value of semiconductor layer 230 having semiconductor layers 230a and 230b will be greater than or equal to the potential barrier value of semiconductor layer 230b and less than or equal to the potential barrier value of semiconductor layer 230a. Therefore, if the potential barrier value of semiconductor layer 230a is 0 meV or more and less than 50 meV, the potential barrier value of semiconductor layer 230 will also be 0 meV or more and less than 50 meV.

[0091] OS transistors can exhibit fluctuating electrical properties and reduced reliability if impurities such as hydrogen and oxygen vacancies are present in the channel formation region of the oxide semiconductor layer. Furthermore, defects where hydrogen fills an oxygen vacancy (hereinafter referred to as V) can also occur. Ｏ A (sometimes called H) is formed, which can generate electrons that act as carriers. Therefore, if oxygen vacancies and hydrogen are present in the channel formation region of the oxide semiconductor layer, the transistor is likely to exhibit normally-on characteristics (a characteristic in which a channel exists and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the channel formation region of the oxide semiconductor layer, impurities, oxygen vacancies, and V are present. Ｏ It is preferable that H is reduced as much as possible. In other words, it is preferable that the channel-forming region in the oxide semiconductor layer has a reduced carrier concentration and is intrinsically i-type or substantially i-type.

[0092] Therefore, it is preferable that the semiconductor layer 230a contains a first element in addition to indium and oxygen. Here, the first element is an element that has a stronger bonding force with oxygen than indium. By including the first element in the semiconductor layer 230a, the formation of oxygen vacancies within the semiconductor layer 230 can be suppressed. Furthermore, it is preferable that the first element is an element that mainly exists as a trivalent cation, the same as indium. This makes it possible to maintain a low carrier concentration in the semiconductor layer 230. Thus, it becomes possible to shift the threshold voltage of the transistor to the positive side. Also, normally-off becomes possible. Therefore, a transistor with good electrical characteristics can be provided.

[0093] Examples of the first element include gallium, aluminum, yttrium, and scandium. The semiconductor layer 230a preferably contains at least one of gallium or aluminum as the first element. The concentration of the first element in the semiconductor layer 230a is 1 × 10⁻⁶. １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable. Furthermore, 0.00001 atomic% to 1 atomic% is more preferable, 0.00001 atomic% to 0.5 atomic% is more preferable, 0.00001 atomic% to 0.1 atomic% is more preferable, and 0.00001 atomic% to 0.06 atomic% is more preferable.

[0094] Furthermore, it is preferable that the concentration of the first element in semiconductor layer 230b is lower than the concentration of the first element in semiconductor layer 230a. This suppresses carrier scattering caused by the first element in semiconductor layer 230b, thereby increasing the on-current of the transistor.

[0095] Since the band gap of an oxide containing the first element is larger than that of indium oxide, it is estimated that the higher the concentration of the first element in indium oxide, the larger its band gap will be compared to that of indium oxide. Therefore, by setting the concentration of the first element in semiconductor layer 230a to 1 atomic percent or less, i.e., within the above range, the band gaps of semiconductor layer 230a and semiconductor layer 230b can be made equal. This allows semiconductor layer 230a to be used as a path for bulk current. Furthermore, it is possible to suppress the increased frequency of carrier scattering caused by the first element. Consequently, the field-effect mobility of transistor 200 can be increased. In addition, the on-current of transistor 200 can be increased.

[0096] Furthermore, by using indium oxide containing the first element in the above-mentioned concentration range in the semiconductor layer 230a, the semiconductor layer 230a and the semiconductor layer 230b may have the same crystal structure. Therefore, crystal grains may be formed extending from the bottom surface to the top surface of the semiconductor layer 230. These crystal grains comprise at least a portion of the semiconductor layer 230a and at least a portion of the semiconductor layer 230b. The crystal structure of these crystal grains is cubic (specifically, bixbyte type). In this case, it may be difficult to confirm the boundary between the semiconductor layer 230a and the semiconductor layer 230b.

[0097] The preferred concentration of the first element in the semiconductor layer 230a is not limited to the above. The concentration of the first element in the semiconductor layer 230a may be higher than 1 atomic percent. For example, the concentration of the first element in the semiconductor layer 230a can be greater than 1 atomic percent and 10 atomic percent or less, preferably 2 atomic percent or more and 10 atomic percent or less, and more preferably 5 atomic percent or more and 10 atomic percent or less. This may result in the electron affinity of the semiconductor layer 230a being lower than that of the semiconductor layer 230b. In this case, the main current path becomes the semiconductor layer 230b, and the path through which carriers flow is moved away from the interface between the insulating layer 224 and the semiconductor layer 230, which may reduce the effect of surface scattering. As a result, it may be possible to increase the on-current or improve reliability. If the first element in the semiconductor layer 230a is 10 atomic percent or less, the crystal grains of the semiconductor layer 230a may have a cubic crystal structure.

[0098] In Figure 2B, the boundary between semiconductor layer 230a and semiconductor layer 230b is shown by a dashed line. In this case, semiconductor layer 230 has a first portion corresponding to semiconductor layer 230a and a second portion corresponding to semiconductor layer 230b. The second portion is located on top of the first portion. In this specification, semiconductor layer 230a can be read as the first portion of semiconductor layer 230, and semiconductor layer 230b can be read as the second portion of semiconductor layer 230.

[0099] Furthermore, the semiconductor layer 230a may also contain a second element instead of the first element. Here, the second element is an element that increases the carrier concentration in the semiconductor layer 230a. By including the second element in the semiconductor layer 230a, the carrier concentration in the semiconductor layer 230 can be increased. This makes it possible to shift the threshold voltage of the transistor to the negative side. It also enables normally-on operation.

[0100] Examples of the second element include boron, phosphorus, titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, and silicon. The semiconductor layer 230a preferably contains at least one of boron or phosphorus as the second element. The concentration of the second element in the semiconductor layer 230a is 1 × 10⁻⁶.１６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable. Furthermore, 0.00001 atomic% to 1 atomic% is more preferable, 0.00001 atomic% to 0.5 atomic% is more preferable, 0.00001 atomic% to 0.1 atomic% is more preferable, and 0.00001 atomic% to 0.06 atomic% is more preferable.

[0101] By setting the concentration of the second element in the semiconductor layer 230a to 1 atomic percent or less, i.e., within the above range, it is possible to suppress the increased frequency of carrier scattering caused by the second element when the semiconductor layer 230a is used as a path for bulk current. Therefore, the field-effect mobility of the transistor 200 can be increased. In addition, the on-current of the transistor 200 can be increased.

[0102] Furthermore, it is preferable that the concentration of the second element in semiconductor layer 230b is lower than the concentration of the second element in semiconductor layer 230a. This suppresses carrier scattering caused by the second element in semiconductor layer 230b, thereby increasing the on-current of the transistor.

[0103] As described above, by supplying the first or second element to the semiconductor layer 230a, precise control of the transistor's threshold voltage becomes possible.

[0104] Furthermore, if the semiconductor device has multiple transistors, at least one semiconductor layer 230a of the multiple transistors may contain the first element, and at least one other semiconductor layer 230a of the multiple transistors may contain the second element. Therefore, transistors can be manufactured in a way that matches the characteristics of the circuit constituting the semiconductor device.

[0105] Figure 3A shows an example where the semiconductor layer 230 has a three-layer structure consisting of semiconductor layer 230a, semiconductor layer 230b on semiconductor layer 230a, and semiconductor layer 230c on semiconductor layer 230b. The composition and materials of semiconductor layer 230a and semiconductor layer 230b can be found in the previously described explanation.

[0106] The semiconductor layer 230c can use materials applicable to the semiconductor layer 230a. For example, a metal oxide layer with a higher potential barrier than the semiconductor layer 230b can be used as the semiconductor layer 230c. This allows the main current path to be the semiconductor layer 230b. Therefore, the channel can be moved away from the surface of the gate insulating layer, and the effects of surface scattering can be reduced. This allows the field-effect mobility of the transistor 200 to be increased. In addition, the on-current of the transistor 200 can be increased. For example, it is preferable that the potential barrier value of the semiconductor layer 230c is greater than the potential barrier value of the semiconductor layer 230b.

[0107] Furthermore, for example, the semiconductor layer 230c preferably contains indium, a first element, and oxygen. Moreover, the concentration of the first element in the semiconductor layer 230c is preferably within the above range. For example, as mentioned above, it is preferable to have a concentration of 1 atomic percent or less. Also, the concentration of the first element in the semiconductor layer 230b is preferably lower than the concentration of the first element in the semiconductor layer 230c. This allows for the provision of a transistor with good electrical characteristics as described above. The first element may be the same or different in the semiconductor layer 230a and the semiconductor layer 230c.

[0108] Furthermore, as mentioned above, the concentration of the first element in the semiconductor layer 230c can be greater than 1 atomic percent. This may result in the electron affinity of the semiconductor layer 230c being smaller than that of the semiconductor layer 230b. In this case, the main current path becomes the semiconductor layer 230b, and the carrier flow path is moved away from the interface between the insulating layer 250 and the semiconductor layer 230, which may reduce the effects of surface scattering. As a result, it may be possible to increase the on-current or improve reliability.

[0109] When an indium-containing oxide is used for semiconductor layers 230a to 230c, as mentioned above, semiconductor layers 230a to 230c may have the same crystal structure. Therefore, crystal grains may be formed extending from the bottom surface to the top surface of semiconductor layer 230. These crystal grains comprise at least a portion of semiconductor layer 230a, at least a portion of semiconductor layer 230b, and at least a portion of semiconductor layer 230c. Furthermore, the crystal structure of these crystal grains is, for example, cubic (specifically, bixbyte type). In this case, it may be difficult to clearly detect the boundaries of each layer contained in semiconductor layer 230.

[0110] In Figure 3B, the boundaries between semiconductor layer 230a and semiconductor layer 230b, and the boundaries between semiconductor layer 230b and semiconductor layer 230c are shown by dashed lines. In this case, semiconductor layer 230 has a first portion corresponding to semiconductor layer 230a, a second portion corresponding to semiconductor layer 230b, and a third portion corresponding to semiconductor layer 230c. The second portion is located on the first portion, and the third portion is located on the second portion. In this specification, semiconductor layer 230c can be read as the third portion of semiconductor layer 230.

[0111] The thickness of the semiconductor layer 230 is more preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. If the thickness of the semiconductor layer 230 is made too thick, the density of grain boundaries in the semiconductor layer 230 will increase, and the field-effect mobility of the transistor may decrease due to the influence of carrier scattering at the grain boundaries. On the other hand, if the thickness of the semiconductor layer 230 is made too thin, the crystallinity of the semiconductor layer 230 will vary within the substrate surface, and the electrical properties may vary.

[0112] Furthermore, if the semiconductor layer 230 has a stacked structure, the film thickness of each layer is preferably 0.5 nm or more, and more preferably 1 nm or more. The film thickness of each of the semiconductor layers 230a to 230c can be appropriately set according to the desired characteristics of the transistor. For example, if you want to improve the ON characteristics, it is preferable to increase the film thickness of the semiconductor layer 230b, which has a low potential barrier.

[0113] Furthermore, the semiconductor layer 230 only needs to have a region with the above-described thickness in at least a portion of it. For example, it is sufficient if the channel formation region of the semiconductor layer 230 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 230 to the above range, the crystallinity of the semiconductor layer 230 can be increased. By using a semiconductor layer 230 with high crystallinity, the field-effect mobility of the transistor 200 can be improved.

[0114] It is preferable to use a conductor that is not easily oxidized as the oxide layer 231a and oxide layer 231b that are in contact with the semiconductor layer 230, for example, a conductive oxide is preferred. This suppresses excessive oxidation of the oxide layer 231a and oxide layer 231b, which reduces the conductivity. It also suppresses the extraction of oxygen from the semiconductor layer 230, which forms an excessive amount of oxygen deficiency.

[0115] For example, as oxide layers 231a and 231b, indium-containing oxides such as indium tin oxide (In-Sn oxide, also called ITO), silicon-containing ITO (In-Sn-Si oxide, also called ITSO), indium zinc oxide (In-Zn oxide, also called IZO®), indium titanium oxide (In-Ti oxide), indium tungsten oxide (In-W oxide), ruthenium oxide, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel can be used. These materials are preferred because they are conductors that are resistant to oxidation, or materials that maintain conductivity even when absorbing oxygen. Furthermore, because these materials are conductive oxides, the contact resistance between oxide layer 231a and semiconductor layer 230, and the contact resistance between oxide layer 231b and semiconductor layer 230 can be reduced. By using such a structure, the field-effect mobility of the transistor 200 can be increased. In addition, the on-current can be increased.

[0116] Furthermore, the indium-containing oxide applicable to oxide layer 231a and oxide layer 231b can be rephrased as an oxide containing indium and a third element. The third element is at least one of tin, zinc, titanium, and tungsten. When an oxide containing indium and a third element is used for oxide layer 231a and oxide layer 231b, it is preferable that the concentration of the third element in semiconductor layer 230 is lower than the concentration of the third element in oxide layer 231a and the concentration of the third element in oxide layer 231b. This suppresses carrier scattering caused by the third element in semiconductor layer 230, and allows for a larger on-current of the transistor.

[0117] In addition, instead of oxide layers 231a and 231b, layers containing, for example, tantalum-containing nitrides, titanium-containing nitrides, molybdenum-containing nitrides, tungsten-containing nitrides, titanium and aluminum-containing nitrides, or ruthenium-containing nitrides can be provided. These materials are also conductors that are resistant to oxidation, or materials that maintain conductivity even when absorbing oxygen, and therefore produce similar effects.

[0118] When an indium-containing oxide is used as the oxide layer 231a and oxide layer 231b, the semiconductor layer 230, oxide layer 231a, and oxide layer 231b may have the same crystal structure. Therefore, crystal grains may be formed extending from the lower surface of the semiconductor layer 230 to the upper surface of the oxide layer 231a. These crystal grains consist of at least a portion of the semiconductor layer 230 and at least a portion of the oxide layer 231a. In this case, it may be difficult to confirm the boundary between the semiconductor layer 230 and the oxide layer 231a. Similarly, crystal grains may be formed extending from the lower surface of the semiconductor layer 230 to the upper surface of the oxide layer 231b. These crystal grains consist of at least a portion of the semiconductor layer 230 and at least a portion of the oxide layer 231b. In this case, it may be difficult to confirm the boundary between the semiconductor layer 230 and the oxide layer 231b.

[0119] In Figure 2C, the boundaries between semiconductor layer 230a and semiconductor layer 230b, the boundary between semiconductor layer 230b and oxide layer 231a, and the boundary between semiconductor layer 230b and oxide layer 231b are shown by dashed lines. In this case, the oxide layer containing indium has a first portion corresponding to semiconductor layer 230a, a second portion corresponding to semiconductor layer 230b, and a fourth portion corresponding to oxide layer 231a or oxide layer 231b. The second portion is located on the first portion, and the fourth portion is located on the second portion. The oxide layer containing indium also has crystal grains, and these crystal grains may have at least a part of the first portion, at least a part of the second portion, and at least a part of the fourth portion. The crystal structure of these crystal grains is, for example, cubic (specifically, bixbyte type). In this specification, oxide layer 231a or oxide layer 231b can be read as the fourth portion of the oxide layer containing indium.

[0120] In Figure 3C, the boundaries between semiconductor layer 230a and semiconductor layer 230b, between semiconductor layer 230b and semiconductor layer 230c, between semiconductor layer 230c and oxide layer 231a, and between semiconductor layer 230c and oxide layer 231b are shown by dashed lines. In this case, the oxide layer containing indium has a first portion corresponding to semiconductor layer 230a, a second portion corresponding to semiconductor layer 230b, a third portion corresponding to semiconductor layer 230c, and a fourth portion corresponding to oxide layer 231a or oxide layer 231b. The second portion is located on the first portion, the third portion is located on the second portion, and the fourth portion is located on the third portion. The oxide layer containing indium also has crystal grains, and these crystal grains may have at least a part of the first portion, at least a part of the second portion, at least a part of the third portion, and at least a part of the fourth portion. The crystal structure of these crystal grains is, for example, cubic (specifically, bixbyte type).

[0121] The conductive layers 242a and 242b can be made of conductors as described in the section "Conductors" below. It is preferable that the conductive layers 242a and 242b have higher conductivity than the oxide layers 231a and 231b. For example, it is preferable that the film thickness of the conductive layers 242a and 242b be greater than the film thickness of the oxide layers 231a and 231b. For example, tungsten can be used as the conductive layers 242a and 242b. This reduces the resistance of the conductive layers 242a and 242b. Therefore, the conductive layers 242a and 242b can function as wiring or electrodes. This improves the operating speed of the semiconductor device.

[0122] The insulating layer 250 is provided within the opening 289 in contact with the upper surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and upper surface of the semiconductor layer 230, the side surface of the oxide layer 231a, the side surface of the oxide layer 231b, and the side surface of the insulating layer 255.

[0123] The insulating layer 250 can have a laminated structure of two or more layers. For example, Figure 2A shows an example in which the insulating layer 250 has a laminated structure consisting of an insulating layer 250a in contact with the semiconductor layer 230, an insulating layer 250b on insulating layer 250a, an insulating layer 250c on insulating layer 250b, and an insulating layer 250d on insulating layer 250c.

[0124] The insulating layer 250 is preferably formed from two or more films. By using two or more films for the insulating layer 250, multiple functions can be imparted to the insulating layer 250. Examples of functions that the insulating layer 250 may have include supplying oxygen to the semiconductor layer 230, extracting excess oxygen contained in the semiconductor layer 230, extracting hydrogen contained in the semiconductor layer 230, and suppressing the diffusion of hydrogen into the semiconductor layer 230.

[0125] For example, the insulating layer 250a preferably has an insulator that has barrier properties against oxygen (also called an oxygen barrier insulator). The insulating layer 250b preferably has an insulator that has the function of supplying oxygen. The insulating layer 250c preferably has an insulator that has the function of capturing or fixing hydrogen. The insulating layer 250d preferably has an insulator that has barrier properties against hydrogen (also called a hydrogen barrier insulator).

[0126] Examples of barrier insulators against oxygen include aluminum oxide and gallium oxide. The insulating layer 250 provided between the channel-forming region of the semiconductor layer 230 and the conductive layer 260 has barrier properties against oxygen, thereby suppressing the diffusion of oxygen contained in the channel-forming region into the conductive layer 260 and preventing the formation of oxygen vacancies in the channel-forming region. Furthermore, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260 and prevent the oxidation of the conductive layer 260.

[0127] Examples of insulators that have the function of supplying oxygen include silicon oxide and silicon oxynitride. Silicon oxide and silicon oxynitride are also materials with high dielectric breakdown voltage. Therefore, by using silicon oxide or silicon oxynitride in the insulating layer 250b, the dielectric breakdown voltage of the transistor 200 can be improved. In addition, it becomes possible to supply oxygen to the semiconductor layer 230 via the insulating layer 250.

[0128] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content, and the term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, when "silicon oxynitride" is written, it refers to a material in which the oxygen content is greater than the nitrogen content, and when "silicon nitride oxide" is written, it refers to a material in which the nitrogen content is greater than the oxygen content.

[0129] Examples of insulators having the function of capturing or fixing hydrogen include metal oxides such as magnesium oxide, aluminum oxide (typically aluminum oxide), hafnium oxide (typically hafnium oxide), and aluminum and hafnium oxide (hafnium aluminate). By using an insulator having the function of capturing or fixing hydrogen in the insulating layer 250c, the hydrogen concentration in the channel formation region of the semiconductor layer 230 can be reduced. Therefore, the V in the channel formation region Ｏ By reducing H, the channel formation region can be made i-type or substantially i-type.

[0130] Furthermore, hafnium oxide has the function of capturing or fixing oxygen in addition to the function of capturing or fixing hydrogen. The presence of hafnium oxide in the insulating layer 250c allows for the capture or fixing of excess oxygen contained in the semiconductor layer 230. Additionally, since hafnium oxide is a high dielectric constant (high-k) material, its use can reduce gate leakage in transistors.

[0131] Examples of hydrogen barrier insulators include nitrides such as silicon nitride and oxides such as tantalum oxide. Silicon nitride is suitable for the insulating layer 250d because it has high barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230.

[0132] By setting the thickness of the insulating layer 250 to 1 nm to 20 nm, preferably 3 nm to 10 nm, the subthreshold swing value (also called the S value), which is one of the transistor characteristics, can be reduced. The S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0133] Furthermore, the film thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that each layer constituting the insulating layer 250 only needs to have a region with the above-mentioned film thickness in at least a portion of it.

[0134] Although the above describes a configuration in which the insulating layer 250 has a four-layer structure, the present invention is not limited to this. The insulating layer 250 can have at least one of the insulating layers 250a to 250d. By configuring the insulating layer 250 with one, two, or three layers from the insulating layers 250a to 250d, the manufacturing process of semiconductor devices can be simplified and productivity can be improved.

[0135] If the material used as the insulating layer 250 is a material that can possess ferroelectric properties, the transistor can be made to function as, for example, an FeFET (Ferroelectric Field Effect Transistor).

[0136] Examples of materials that may possess ferroelectric properties include oxides containing one or both hafnium and zirconium. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium-zirconium oxide. Alternatively, as a material that may possess ferroelectric properties, a material may be used in which element J1 (where element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, scandium, yttrium, lanthanum, strontium, gadolinium, etc.) is added to a metal oxide containing one of hafnium and zirconium.

[0137] Incidentally, the crystal structure (properties) of the materials listed above can change not only depending on the film deposition conditions but also on various processes. Therefore, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but also materials that may possess ferroelectricity.

[0138] The conductive layer 260 can be made of a conductor as described in the section "Conductors" below. It is preferable to use a conductor that is resistant to oxidation or a conductor that has the function of suppressing the diffusion of oxygen as the conductive layer 260. Examples of such conductors include conductors containing nitrogen and conductors containing oxygen. This makes it possible to suppress a decrease in the conductivity of the conductive layer 260.

[0139] As shown in Figures 1B and 1C, the conductive layer 260 is placed within the opening 289 together with the insulating layer 250 and the insulating layer 255. Within the opening 289, the conductive layer 260 is provided so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side surface and upper surface of the semiconductor layer 230, via the insulating layer 250. The conductive layer 260 has a region that overlaps with the semiconductor layer 230. Furthermore, the upper surface of the conductive layer 260 is at the same height as the upper end of the insulating layer 250, the upper end of the insulating layer 255, and the upper surface of the insulating layer 280.

[0140] The conductive layer 260 is preferably provided extending in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when multiple transistors are provided, the conductive layer 260 functions as wiring.

[0141] When the structure described above is adopted, as shown in Figure 1C, a curved surface may be present between the side surface and the top surface of the semiconductor layer 230 in a cross-sectional view in the channel width direction of the transistor 200. In other words, the ends of the side surface and the ends of the top surface may be curved (hereinafter also referred to as rounded). By adopting such a shape, the coverage of the semiconductor layer 230 by the insulating layer 250 and the conductive layer 260 can be improved.

[0142] The insulating layer 255 is positioned within the opening 289 and is in contact with the lower surface of the insulating layer 282, the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the upper surface of the oxide layer 231a, the upper surface of the oxide layer 231b, and the upper surface of the insulating layer 222.

[0143] The insulating layer 255 and the insulating layer 250 are provided to reflect the shape of the opening 289. Therefore, the insulating layer 255 is provided so as to cover the side wall of the opening 289, and the insulating layer 250 is provided so as to cover the bottom of the opening 289 and the insulating layer 255.

[0144] As shown in Figure 2A, in the oxide layer 231a, the portion of the upper surface in contact with the insulating layer 255 is formed to protrude toward the conductive layer 260 from the conductive layer 242a. Similarly, in the oxide layer 231b, the portion of the upper surface in contact with the insulating layer 255 is formed to protrude toward the conductive layer 260 from the conductive layer 242b. Therefore, in a cross-sectional view of the transistor 200 in the channel length direction, the distance L2 between the oxide layer 231a and the oxide layer 231b is smaller than the distance L1 between the conductive layer 242a and the conductive layer 242b. The difference between distance L1 and distance L2 may coincide with or approximately coincide with twice the film thickness of the insulating layer 255. Here, the film thickness of the insulating layer 255 refers to the film thickness in the A1-A2 direction in at least a portion of the insulating layer 255. With this configuration, it is possible to shorten the distance between the source and the drain, and consequently shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing semiconductor devices, it is possible to provide semiconductor devices with improved operating speeds.

[0145] In a top view, the side surface of the insulating layer 280 in the opening 289 may coincide with or approximately coincide with the side surface of the conductive layer 242a and the side surface of the conductive layer 242b. In addition, parts of the oxide layer 231a and oxide layer 231b are formed to protrude inward from the side surface of the insulating layer 280, the side surface of the conductive layer 242a, and the side surface of the conductive layer 242b. Here, a part of the upper surface of the oxide layer 231a is in contact with the conductive layer 242a, and a part of the upper surface of the oxide layer 231b is in contact with the conductive layer 242b. Therefore, within the opening, the insulating layer 255 is in contact with the other part of the upper surface of the oxide layer 231a, the other part of the upper surface of the oxide layer 231b, the side surface of the conductive layer 242a, and the side surface of the conductive layer 242b.

[0146] It is preferable to use an insulator with a low dielectric constant for the insulating layer 255. This reduces the parasitic capacitance between the conductive layer 260 and the conductive layer 242a, and between the conductive layer 260 and the conductive layer 242b. It also reduces the leakage current between the conductive layer 260 and the conductive layer 242a, and between the conductive layer 260 and the conductive layer 242b.

[0147] Furthermore, it is preferable to use an oxygen barrier insulator as the insulating layer 255. This allows the insulating layer 255 to protect the sides of the conductive layer 242a and the conductive layer 242b. Thus, excessive oxidation of the sides of the conductive layer 242a and the conductive layer 242b can be suppressed. In addition, excessive diffusion of oxygen from the insulating layer 280 to the insulating layer 250 can be suppressed. This reduces the amount of oxygen diffusing into the insulating layer 224 and the amount of oxygen diffusing into the semiconductor layer 230.

[0148] The thickness of the insulating layer 255 can be, for example, 0.5 nm to 20 nm, 0.5 nm to 10 nm, or 1 nm to 5 nm. By making the insulating layer 255 the thickness described above and forming the insulating layer 255 and the conductive layer 260 in the opening 289, the width of the gate electrode of the transistor 200 can be made smaller than the width of the opening 289. The insulating layer 255 only needs to have a region with the above-described thickness in at least a portion of it.

[0149] Furthermore, although Figure 2A shows the insulating layer 255 as a single layer, the present invention is not limited to this, and the insulating layer 255 can also be made into a laminated structure of two or more layers. In this case, it is preferable to use an insulator with a low dielectric constant as at least one layer. For example, an insulator such as silicon oxide can be used as the layer of the insulating layer 255 that is in contact with the insulating layer 280, and an insulator with high oxygen barrier properties such as silicon nitride can be used as the layer of the insulating layer 255 that is in contact with the insulating layer 250.

[0150] Furthermore, a barrier insulator against hydrogen is formed near the transistor 200, and V is formed in the channel formation region of the semiconductor layer 230 and in its vicinity. Ｏ It is preferable to reduce H.

[0151] It is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against hydrogen. It is also preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against impurities. Furthermore, it is preferable that at least one of the insulating layers 212, 214, 221, 222, 275, 282, and 283 functions as a barrier insulator against oxygen. Note that it is not necessarily required to provide all of the insulating layers 212, 214, 221, 222, 275, 282, and 283. If sufficient barrier properties against hydrogen, oxygen, etc. are provided, the insulating layers can be appropriately selected from insulating layer 212, insulating layer 214, insulating layer 221, insulating layer 222, insulating layer 275, insulating layer 282, and insulating layer 283. For example, the insulating layer 214 can be omitted, and the insulating layer 216 and conductive layer 205 can be formed in contact with the upper surface of the insulating layer 212.

[0152] In this specification, having a hydrogen barrier property means having a property that makes it difficult for hydrogen to diffuse (also referred to as a property that makes it difficult for hydrogen to permeate, a property that has low hydrogen permeability, or a function that suppresses hydrogen diffusion). Alternatively, it means having a function that captures or fixes hydrogen (also called gettering). Here, hydrogen refers to, for example, hydrogen atoms, hydrogen molecules, and water molecules and OH − This refers to at least one substance bonded with hydrogen, such as [specific example]. Barrier properties against oxygen refer to barrier properties against at least one substance, such as an oxygen atom or oxygen molecule.

[0153] Examples of insulators that have the function of suppressing hydrogen diffusion include silicon nitride and silicon nitride oxide. Other examples include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), and gallium oxide.

[0154] It is preferable to use an insulator that has the function of suppressing hydrogen diffusion for insulating layer 212, insulating layer 221, insulating layer 275, and insulating layer 283. For example, it is preferable to use silicon nitride with high hydrogen barrier properties for insulating layer 212, insulating layer 221, insulating layer 275, and insulating layer 283.

[0155] Insulating layers having the function of capturing or fixing hydrogen preferably have an amorphous structure. In insulating layers having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, insulating layers having an amorphous structure can be said to have a high ability to capture or fix hydrogen. By including silicon in insulating layers having the function of capturing or fixing hydrogen, polycrystallization can be suppressed and it can be made more amorphous. Therefore, metal oxides containing silicon, such as hafnium silicate and aluminum silicate, can be suitably used as insulators having the function of capturing or fixing hydrogen.

[0156] It is preferable to use an insulator having the function of capturing or fixing hydrogen in the insulating layer 214, insulating layer 222, and insulating layer 282. For example, aluminum oxide may be used for the insulating layer 214 and insulating layer 282. Also, for example, it is preferable to use hafnium oxide, which is a high-k material, for the insulating layer 222.

[0157] Furthermore, the inorganic insulators listed as having the function of suppressing hydrogen diffusion, and those having the function of capturing or fixing hydrogen, also possess barrier properties against oxygen.

[0158] As shown in Figure 2A, it is preferable to provide an insulating layer 212 having the function of suppressing hydrogen diffusion and an insulating layer 214 having the function of capturing or fixing hydrogen beneath the transistor 200. By providing the insulating layer 212 beneath the transistor 200, the diffusion of hydrogen from the layer below the transistor 200 can be suppressed. Furthermore, by providing the insulating layer 214 on top of the insulating layer 212, hydrogen contained in the insulating layer 216 and the like can be captured or fixed to the insulating layer 214. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0159] Furthermore, as shown in Figure 2A, it is preferable to provide an insulating layer 221 having the function of suppressing hydrogen diffusion and an insulating layer 222 having the function of capturing or fixing hydrogen beneath the semiconductor layer 230. By providing the insulating layer 221 beneath the semiconductor layer 230, it is possible to suppress the diffusion of hydrogen from the layer below the semiconductor layer 230. Also, by providing the insulating layer 222 on top of the insulating layer 221, hydrogen contained in the insulating layer 224, etc., can be captured or fixed to the insulating layer 222. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0160] Furthermore, as shown in Figure 2A, it is preferable to provide an insulating layer 275 covering the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc. By using an insulator that has the function of suppressing hydrogen diffusion in the insulating layer 275, it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, conductive layer 242a, conductive layer 242b, etc. Also, by using an oxygen barrier insulator in the insulating layer 275, it is possible to prevent oxygen contained in the insulating layer 280 from excessively diffusing into the semiconductor layer 230, conductive layer 242a, and conductive layer 242b.

[0161] Furthermore, as shown in Figure 2A, it is preferable to provide an insulating layer 282 having the function of capturing or fixing hydrogen, and an insulating layer 283 having the function of suppressing hydrogen diffusion, on top of the transistor 200. By providing the insulating layer 283 on top of the transistor 200, the diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Also, by providing the insulating layer 282 below the insulating layer 283, hydrogen contained in the insulating layer 280 and the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in and near the semiconductor layer 230.

[0162] In this way, by surrounding the top and bottom of the transistor 200 with a barrier insulator against hydrogen, the diffusion of hydrogen into the oxide semiconductor is reduced, and the V in the channel formation region is reduced. Ｏ This allows for a reduction in H. This, in turn, improves the electrical characteristics and reliability of transistor 200.

[0163] An insulating layer containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) is provided near the semiconductor layer 230, and by performing heat treatment, oxygen is supplied from the insulating layer to the oxide semiconductor layer, eliminating oxygen deficiencies and V Ｏ H can be reduced. For example, it is preferable to include oxygen that is desorbed by heating in the insulating layer 280. By supplying this oxygen to the semiconductor layer 230 through the insulating layer 250 through heat treatment, oxygen deficiencies in the channel formation region can be reduced.

[0164] The conductive layer 205 is arranged to overlap with the semiconductor layer 230 and the conductive layer 260. Preferably, the conductive layer 205 extends in the channel width direction, as shown in Figures 1A and 1C. With this configuration, when multiple transistors are provided, the conductive layer 205 functions as wiring. The conductive layer 205 can be made from a conductor described in the section "Conductors" below.

[0165] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductive layer 205, without linking it to the potential applied to the conductive layer 260. In particular, by applying a negative potential to the conductive layer 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductive layer 205 reduces the drain current when the potential applied to the conductive layer 260 is 0V compared to not applying a negative potential.

[0166] As shown in Figure 2A, the conductive layer 205 preferably has a two-layer structure consisting of a first conductive layer and a second conductive layer on the first conductive layer. The first conductive layer is provided in contact with the bottom surface and side walls of the opening. The second conductive layer is provided so as to fill the recess of the first conductive layer formed along the opening. Here, it is preferable that the upper surface of the conductive layer 205 is at the same height as the upper surface of the insulating layer 216.

[0167] Here, the first conductive layer of the conductive layer 205 contains oxygen (e.g., at least one such as an oxygen atom and an oxygen molecule), hydrogen (e.g., at least one such as a hydrogen atom and a hydrogen molecule), water molecules, and nitrogen oxide molecules (N). ２ O, NO, NO ２It is preferable to have a conductor that has the function of suppressing the diffusion of impurities such as copper atoms. Examples of conductors that have the function of suppressing the diffusion of such impurities include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The first conductive layer can be a single layer structure or a multilayer structure of the conductor. For example, it is preferable that the first conductive layer has titanium nitride.

[0168] By using a conductor having the function of reducing hydrogen diffusion in the first conductive layer of the conductive layer 205, it is possible to prevent impurities such as hydrogen contained in the second conductive layer of the conductive layer 205 from diffusing into the semiconductor layer 230 via the insulating layer 216, etc. Furthermore, by using a conductor having the function of suppressing oxygen diffusion in the first conductive layer, it is possible to suppress oxidation of the second conductive layer and a decrease in conductivity.

[0169] In Figure 2A, the conductive layer 205 is shown as a laminated structure of a first conductive layer and a second conductive layer. However, the present invention is not limited thereto, and the conductive layer 205 may be a single layer or a laminated structure of three or more layers. For example, the first conductive layer may be a laminated structure using tantalum or tantalum nitride, which has relatively high hydrogen barrier properties. In this case, the first conductive layer can be a laminated film of a tantalum nitride film and a titanium nitride film on the tantalum nitride film. Alternatively, the first conductive layer can be a laminated film of a tantalum nitride film, a tantalum film on the tantalum nitride film, and a titanium nitride film on the tantalum film.

[0170] By using the above configuration, it is possible to prevent impurities such as hydrogen and copper contained in the lower layer of transistor 200 from diffusing into the conductive layer 205. Furthermore, it is possible to prevent impurities such as hydrogen and copper contained in the lower layer of transistor 200 from diffusing into the semiconductor layer 230 via the conductive layer 205.

[0171] The insulating layer 224 preferably has, for example, silicon oxide or silicon oxynitride. Furthermore, the insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. This allows at least a portion of the lower surface of the conductive layer 260 to be located below the lower surface of the semiconductor layer 230, as shown in Figure 1C. Therefore, since the conductive layer 260 can be positioned opposite the upper and side surfaces of the semiconductor layer 230, the electric field of the conductive layer 260 can be applied to the upper and side surfaces of the semiconductor layer 230. The insulating layer 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials.

[0172] Furthermore, in the transistor 200 shown in Figure 2A, the opposing sides of the oxide layer 231a and oxide layer 231b, and the opposing sides of the conductive layer 242a and conductive layer 242b are perpendicular to the upper surface of the semiconductor layer 230b, but the present invention is not limited thereto. For example, the opposing sides of the oxide layer 231a and oxide layer 231b, and the opposing sides of the conductive layer 242a and conductive layer 242b may be tapered.

[0173] The insulating layers 271a and 271b are inorganic insulators that function as etching stoppers during processing of the conductive layers 242a and 242b, protecting them. Furthermore, since insulating layer 271a is in contact with the conductive layer 242a and insulating layer 271b is in contact with the conductive layer 242b, it is preferable that insulating layers 271a and 271b are inorganic insulators that do not easily oxidize the conductive layers 242a and 242b. For example, it is preferable that each of the insulating layers 271a and 271b has a laminated structure of a silicon nitride film and a silicon oxide film on the silicon nitride film. This suppresses oxidation of the conductive layers 242a and 242b and allows them to function as etching stoppers.

[0174] The insulating layer that forms the insulating layer 271a and insulating layer 271b functions as a mask for the conductive layer that forms the conductive layer 242a and conductive layer 242b. Therefore, as shown in Figure 1D, the conductive layer 242b does not have a curved surface between its side and top surfaces. The same applies to the conductive layer 242a. As a result, the ends of the conductive layer 242a and conductive layer 242b where the side and top surfaces meet are angular. The angular shape of the ends of the conductive layer 242a and conductive layer 242b increases the cross-sectional area of ​​the conductive layer 242a and conductive layer 242b compared to when the ends have curved surfaces. Furthermore, by using a nitride insulator (e.g., silicon nitride) that is less likely to oxidize metals for the layer of insulating layer 271a that is in contact with the conductive layer 242a and the layer of insulating layer 271b that is in contact with the conductive layer 242b, it is possible to prevent the conductive layer 242a and conductive layer 242b from being excessively oxidized. As a result of the above, the resistance of conductive layers 242a and 242b is reduced, making it possible to increase the on-current of the transistor.

[0175] As shown in Figure 2A, it is preferable to have a two-layer structure for the conductive layer 260. Here, it is preferable that the conductive layer 260 has a conductive layer 260a and a conductive layer 260b on top of the conductive layer 260a. For example, it is preferable that the conductive layer 260a is arranged in contact with the lower surface and side surface of the conductive layer 260b. In this case, it is preferable to use a conductor that is resistant to oxidation or a conductor that has the function of suppressing the diffusion of oxygen as the conductive layer 260a.

[0176] The conductive layer 260a, like the first conductive layer of the conductive layer 205, contains oxygen (for example, at least one such as an oxygen atom and an oxygen molecule), hydrogen (for example, at least one such as a hydrogen atom and a hydrogen molecule), water molecules, nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductor that has the function of suppressing the diffusion of impurities such as copper atoms. Examples of conductors that have the function of suppressing the diffusion of such impurities include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0177] Furthermore, because the conductive layer 260a has the function of suppressing oxygen diffusion, it is possible to suppress oxidation of the conductive layer 260b and a decrease in conductivity due to oxygen contained in the insulating layer 280, etc. By using a conductor that has the function of reducing hydrogen diffusion in the conductive layer 260a, it is possible to prevent impurities such as hydrogen contained in the conductive layer 260b from diffusing into the semiconductor layer 230 via the insulating layer 250.

[0178] Furthermore, it is preferable that the conductive layer 260b has good conductivity. For example, the conductive layer 260b may have a conductor mainly composed of tungsten, copper, or aluminum. The conductive layer 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the conductor.

[0179] It is preferable that the insulating layer 216, insulating layer 280, and insulating layer 285 each have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between wiring can be reduced.

[0180] For example, it is preferable that the insulating layer 216, insulating layer 280, and insulating layer 285 each contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids.

[0181] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0182] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may be flattened.

[0183] It is preferable that the concentration of impurities such as water and hydrogen in the insulating layer 280 is reduced. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0184] The conductive layers 240a and 240b can be made from the conductors described in the section "Conductors" below. Also, as shown in Figure 2A, the upper surfaces of the conductive layers 240a and 240b can be formed to match the height of the upper surface of the insulating layer 285. Also, as shown in Figure 2A, the lower part of the conductive layer 240a may be formed to be embedded in the conductive layer 242a. Similarly, the lower part of the conductive layer 240b may be formed to be embedded in the conductive layer 242b.

[0185] The conductive layers 240a and 240b are formed by being embedded in openings formed on the surface to be formed. For this reason, it is preferable that each of the conductive layers 240a and 240b has a laminated structure comprising a rod-shaped conductive layer with good conductivity and embedding properties, and a film-like conductive layer that has good adhesion to the rod-shaped conductive layer and is formed to cover the openings well. As shown in Figure 2A, etc., it is preferable that the conductive layer 240a has a conductive layer 240a2 and a conductive layer 240a1 in contact with the side and bottom surfaces of the conductive layer 240a2. It is also preferable that the conductive layer 240b has a conductive layer 240b2 and a conductive layer 240b1 in contact with the side and bottom surfaces of the conductive layer 240b2.

[0186] The conductive layers 240a2 and 240b2 preferably have better conductivity than conductive layer 240a1, etc. For example, it is preferable that they have a conductor mainly composed of tungsten, copper, or aluminum. Furthermore, it is preferable that the conductive layers 240a2 and 240b2 be deposited by a method that provides good embedding properties, for example, by chemical vapor deposition (CVD). For example, tungsten deposited by CVD can be used as the conductive layers 240a2 and 240b2.

[0187] Furthermore, it is preferable that the conductive layer 240a1 and conductive layer 240b1 have good adhesion to the conductive layer 240a2 and conductive layer 240b2. For example, it is preferable to use a conductor whose main component is one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. In addition, it is preferable to deposit the conductive layer 240a1 and conductive layer 240b1 using a method that provides good coverage, for example, by atomic layer deposition (ALD). For example, titanium nitride deposited by thermal ALD can be used as the conductive layer 240a1 and conductive layer 240b1.

[0188] Furthermore, it is preferable that the conductive layer 240a1 and conductive layer 240b1 have barrier properties against impurities. For example, it is preferable to use the above-mentioned conductor for the conductive layer 240a1 and conductive layer 240b1. By having conductive layer 240a1 and conductive layer 240b1 have barrier properties against oxygen, oxidation of conductive layer 240a2 and conductive layer 240b2 can be suppressed, and an increase in wiring resistance can be prevented.

[0189] Furthermore, it is preferable that the conductive layers 240a1 and 240b1 have barrier properties against hydrogen. For example, it is preferable that the hydrogen diffusion distance per unit thickness of conductive layer 240a1 and 240b1 is shorter than that of conductive layer 240a2 and conductive layer 240b2, respectively. The conductive layers 240a and 240b are connected to wiring or electrodes, and there is a risk that hydrogen may diffuse into the vicinity of the transistor 200 via such wiring or electrodes. However, by having barrier properties against hydrogen, it is possible to suppress the diffusion of hydrogen into the semiconductor layer 230.

[0190] Furthermore, while Figure 2A shows an example in which a recess is formed on the upper surface of the conductive layer 242a and a portion of the conductive layer 240a1 is embedded in the upper surface of the conductive layer 242a, the present invention is not limited to this. There are cases in which no recess is formed on the upper surface of the conductive layer 242a and a portion of the conductive layer 240a1 is not embedded in the upper surface of the conductive layer 242a. For example, depending on the conditions of the anisotropic dry etching process when forming the insulating layer 241a, there are cases in which almost no recess is formed on the upper surface of the conductive layer 242a. The same applies to the conductive layer 240b1 as to the conductive layer 240a1.

[0191] As insulating layers 241a and 241b, barrier insulators against oxygen or barrier insulators against hydrogen can be used. For example, silicon nitride is preferably used as insulating layers 241a and 241b. Insulating layers 241a and 241b are in contact with insulating layers 285, 283, 282, 280, 275, 271a, 271b, 222, and 221. This prevents impurities such as water and hydrogen contained in insulating layer 280 from mixing into semiconductor layer 230 through conductive layers 240a and 240b. It also prevents oxygen contained in insulating layer 280 from being absorbed by conductive layers 240a and 240b.

[0192] Furthermore, the insulating layer 241a and the insulating layer 241b may each be in a laminated structure. In this case, it is preferable that the first insulating layer in contact with the side wall of the opening such as the insulating layer 280 and the second insulating layer inside it use an oxygen barrier insulator (e.g., aluminum oxide) and a hydrogen barrier insulator (e.g., silicon nitride), respectively.

[0193] Figure 1B and others show a configuration in which a semiconductor layer 230 is provided in contact with an insulating layer 224, but the present invention is not limited thereto. For example, as shown in Figures 4A to 4D, an oxide layer 232 can also be provided between the semiconductor layer 230 and the insulating layer 224. Here, Figures 4A to 4D correspond to Figures 1A to 1D, respectively, and are the same as Figures 1A to 1D except that they have an oxide layer 232.

[0194] It is preferable to use a film with lower oxygen permeability for the oxide layer 232 than the semiconductor layer 230. A film with low oxygen permeability can also be described as a film with high oxygen barrier properties. By using a film with low oxygen permeability for the oxide layer 232, it is possible to suppress the excessive supply of oxygen to the semiconductor layer 230 even if oxygen diffuses upward from the insulating layer 224. Furthermore, by providing the oxide layer 232 below the semiconductor layer 230, the diffusion of impurities into the semiconductor layer 230 can be suppressed.

[0195] Furthermore, it is preferable that the oxide layer 232 has lower conductivity than the semiconductor layer 230. An insulator or a semiconductor with lower conductivity than the semiconductor layer 230 can be used as the oxide layer 232.

[0196] The oxide layer 232 preferably contains the element M shown below. Furthermore, the oxide layer 232 preferably contains either or both indium and zinc in addition to element M. Element M is a metallic or metalloid element with a high bond energy with oxygen, for example, a metallic or metalloid element with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. The oxide layer 232 contains gallium, which has a strong bonding force with oxygen, allowing it to block more oxygen. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used in this specification may include metalloid elements.

[0197] The oxide layer 232 can be, for example, an oxide containing gallium (e.g., gallium oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also written as GZO), aluminum zinc oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), and the like.

[0198] In the oxide layer 232, it is preferable that the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide is high. By adopting such a configuration, a film with lower oxygen permeability can be made.

[0199] Specifically, the oxide layer 232 can be composed of In:M:Zn = 1:3:2 [atomic ratio] or a composition close to that, or In:M:Zn = 1:3:4 [atomic ratio] or a composition close to that. Note that the composition close to the desired atomic ratio includes a range of ±30%. Furthermore, it is preferable to use gallium as element M.

[0200] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0201] For the analysis of the composition of metal oxides, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), ICP-MS, or inductively coupled plasma-atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods may be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0202] Furthermore, examples of crystalline structures for the metal oxide layer include amorphous, CAAC (c-axis-aligned crystalline), microcrystalline, single-crystal, and polycrystalline. The oxide layer 232 is preferably crystalline. For example, an In-Ga-Zn oxide with a CAAC structure can be used as the oxide layer 232.

[0203] Metal oxides with a CAAC structure have a highly crystalline, dense structure with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization (e.g., between 400°C and 600°C), the CAAC structure metal oxide can be made to have an even more crystalline and dense structure. By increasing the density of the CAAC structure metal oxide in this way, the diffusion of oxygen within the metal oxide can be further reduced.

[0204] Furthermore, while Figure 1A and others show a configuration in which the top view width of conductive layers 240a and 240b is smaller than the top view width of the channel formation region of semiconductor layer 230, the present invention is not limited to this. For example, as shown in Figures 5A to 5D, the top view width of conductive layers 240a and 240b can be larger than the top view width of the channel formation region of semiconductor layer 230. Figures 5A to 5D correspond to Figures 1A to 1D, respectively, and are the same as Figures 1A to 1D except that the top surface shapes of the insulating layer 224, oxide layer 232, semiconductor layer 230, oxide layer 231a, conductive layer 242a, oxide layer 231b, conductive layer 242b, insulating layer 271a, insulating layer 271b, conductive layer 240a, and conductive layer 240b are different.

[0205] As shown in Figure 5A, in a plan view, it is preferable that the width L4 in the A5-A6 direction of the source region or drain region of the semiconductor layer 230 is greater than the width L3 in the A3-A4 direction near the channel formation region of the semiconductor layer 230. In a plan view, width L3 can also be defined as the width in the A3-A4 direction in the region of the semiconductor layer 230 that overlaps with the conductive layer 260. Furthermore, width L4 can also be defined as the width in the A5-A6 direction near the region of the semiconductor layer 230 that overlaps with the conductive layer 240a or conductive layer 240b. This configuration allows for a larger margin when forming the openings for embedding the wider conductive layers 240a and 240b. Therefore, the productivity of semiconductor devices can be improved. Furthermore, the contact area between conductive layer 240a and conductive layer 242a, conductive layer 240b and conductive layer 242b, conductive layer 242a and oxide layer 231a, conductive layer 242b and oxide layer 231b, oxide layer 231a and semiconductor layer 230, and oxide layer 231b and semiconductor layer 230 can be increased, thereby reducing contact resistance. This increases the on-current of transistor 200 and improves the electrical characteristics of the semiconductor device.

[0206] Furthermore, as shown in Figure 5A, it is preferable that the oxide layer 232, insulating layer 224, oxide layer 231a, conductive layer 242a, oxide layer 231b, conductive layer 242b, insulating layer 271a, and insulating layer 271b are formed so as to overlap the upper surface shape of the semiconductor layer 230.

[0207] Furthermore, while Figure 1B and other figures show a configuration in which oxide layers 231a and 231b are provided, the present invention is not limited thereto. For example, as shown in Figures 6A to 6D, a configuration can be made in which oxide layers 231a and 231b are not provided. Figures 6A to 6D correspond to Figures 1A to 1D, respectively, and are the same as Figures 1A to 1D except that oxide layers 231a, 231b, and the insulating layer 255 are not provided.

[0208] As shown in Figure 6B and other figures, the oxide layer 231a, oxide layer 231b, and insulating layer 255 can also be omitted. In this case, as shown in Figures 6B and 6C, the side surface of the insulating layer 250 is in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the conductive layer 242a, and the side surface of the conductive layer 242b. By omitting the oxide layer 231a, oxide layer 231b, and insulating layer 255 in this way, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0209] <Materials for semiconductor devices> The following describes materials that can be used in semiconductor devices. Each layer constituting a semiconductor device may be a single-layer structure or a multilayer structure.

[0210] <<Substrates>> For example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used as the substrate for forming the transistor. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, semiconductor substrates having insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates, can be used. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having metal nitrides, substrates having metal oxides, substrates on which a conductor or semiconductor is provided on an insulating substrate, substrates on which a conductor or insulator is provided on a semiconductor substrate, and substrates on which a semiconductor or insulator is provided on a conductive substrate. Alternatively, substrates equipped with one or more types of elements may be used. Examples of elements provided on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0211] <<Insulator>> In this embodiment, insulating layers 212, 214, 216, 221, 222, 224, 250, 275, 280, 282, 283, 285, 241a, 241b, 271a, 271b, and 255 can be any of the insulators shown below as appropriate. Examples of insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0212] For example, as transistors become smaller and more integrated, thinning of the gate insulating layer can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is preferable to select the material according to the function of the insulator.

[0213] Examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0214] Examples of insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, porous silicon oxide, and resins.

[0215] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing one or more of the following: boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or in a multilayer structure. Specifically, examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride, and silicon nitride.

[0216] Furthermore, the insulator that functions as the gate insulating layer is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by having silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the semiconductor layer 230, the oxygen deficiency in the semiconductor layer 230 can be compensated for.

[0217] <<Conductors>> In this embodiment, conductive layers 205, 242a, 242b, 260, 240a, and 240b can be any of the following conductors as appropriate. As conductors, it is preferable to use metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing the above metal elements, or alloys combining the above metal elements. Examples of conductors include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductors that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0218] When using a laminated conductor, for example, a laminated structure combining a material containing the aforementioned metal element and a conductor containing oxygen, a laminated structure combining a material containing the aforementioned metal element and a conductor containing nitrogen, or a laminated structure combining a material containing the aforementioned metal element, a conductor containing oxygen, and a conductor containing nitrogen may be applied.

[0219] Furthermore, when using an oxide for the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor that functions as the gate electrode, which combines a material containing the aforementioned metal element with a conductor containing oxygen. In this case, it is preferable to place the conductor containing oxygen on the channel formation region side. By placing the conductor containing oxygen on the channel formation region side, oxygen desorbed from the conductor is more easily supplied to the channel formation region.

[0220] Furthermore, a conductor containing the metal element and oxygen contained in the metal oxide in which the channel is formed can be used. Alternatively, a conductor containing the aforementioned metal element and nitrogen may be used. For example, a nitrogen-containing conductor such as titanium nitride or tantalum nitride may be used. Alternatively, one or more of the following may be used: indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like. For this reason, it may be preferable to use the above conductor as a conductor that functions as a gate electrode.

[0221] <Example of Semiconductor Device Fabrication Method> An example of a semiconductor device fabrication method according to one embodiment of the present invention will be described using Figures 7A to 19D. Here, the case of fabricating the semiconductor device shown in Figures 4A to 4D will be used as an example.

[0222] In Figures 7 to 19, (A) in each figure shows a plan view. (B) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A1-A2 in Figure (A), and is also a cross-sectional view of transistor 200 in the channel length direction. (C) in each figure is a cross-sectional view corresponding to the area indicated by the dashed line A3-A4 in Figure (A), and is also a cross-sectional view of transistor 200 in the channel width direction. (D) in each figure is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure (A), and is also a cross-sectional view of transistor 200 in the channel width direction. Note that in the plan view (A) of each figure, some elements have been omitted for clarity.

[0223] In the following, insulating layers, conductive layers, or semiconductor layers can be deposited using methods such as sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), and ALD as appropriate.

[0224] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0225] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD) methods depending on the source gas used.

[0226] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitive elements, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage these components. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in higher yields for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0227] Furthermore, ALD methods that can be used include thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses a plasma-excited reactant.

[0228] Note that precursors used in the ALD method may contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain higher levels of elements such as carbon or chlorine compared to films formed by other film formation methods. The quantity of impurities can be quantified using SIMS or XPS.

[0229] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0230] Furthermore, the CVD method allows for the deposition of films with arbitrary compositions by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0231] Furthermore, the ALD method allows for the deposition of films with any desired composition by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0232] First, a substrate (not shown) is prepared, an insulating layer 212 is deposited on the substrate, and an insulating layer 214 is deposited on the insulating layer 212. It is preferable to use a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, as this can reduce the hydrogen concentration in the insulating layer 212 and the insulating layer 214. For example, silicon nitride can be deposited as the insulating layer 212 using the sputtering method, and aluminum oxide can be deposited as the insulating layer 214 using the sputtering method.

[0233] It is preferable to perform a heat treatment before forming the insulating layer 212 to reduce water and hydrogen adsorbed on the substrate (including the circuit elements and interlayer film formed on the substrate). Furthermore, when forming an insulating layer between the substrate and the insulating layer 212, the heat treatment may be performed with the underlying insulating layer already formed on the substrate. This also reduces water and hydrogen adsorbed on the underlying insulating layer. The heat treatment conditions can be the same as those for the semiconductor layer 230, which will be described later. In this embodiment, the heat treatment temperature is set to 400°C.

[0234] Next, an insulating layer 216 is formed on the insulating layer 214. It is preferable to form the insulating layer 216 using a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 216 can be reduced. For example, silicon oxide can be formed as the insulating layer 216 using a sputtering method.

[0235] Next, an opening is formed in the insulating layer 216 that reaches the insulating layer 214. The opening is formed in the region where the conductive layer 205 is formed. Wet etching may be used to form the opening, but dry etching is preferable for microfabrication. Furthermore, it is preferable to select an insulator for the insulating layer 214 that functions as an etching stopper film when etching the insulating layer 216. For example, if silicon oxide or silicon oxynitride is used for the insulating layer 216, the insulating layer 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0236] After the above-mentioned opening is formed, a conductive film to become the conductive layer 205 is deposited, and CMP treatment is performed until the insulating layer 216 is exposed, thereby removing a portion of the conductive film. This makes it possible to form the conductive layer 205 embedded in the insulating layer 216.

[0237] When the conductive layer 205 has a two-layer structure, for example, the conductive film that will become the conductive layer 205 can be a laminated film of a titanium nitride film deposited using the ALD method and a tungsten film deposited on the titanium nitride film using the CVD method.

[0238] Next, an insulating layer 221 is formed on the insulating layer 216 and the conductive layer 205, and an insulating layer 222 is formed on the insulating layer 221. For example, silicon nitride can be formed as the insulating layer 221 using the PEALD method, and hafnium oxide can be formed as the insulating layer 222 using the thermal ALD method.

[0239] Next, an insulating film 224f, which will become the insulating layer 224, is deposited on the insulating layer 222 (see Figures 7A to 7D). For example, silicon oxide can be deposited as the insulating film 224f using the sputtering method. By using the sputtering method, which does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. This prevents hydrogen from diffusing from the insulating layer 224 to the semiconductor layer 230.

[0240] Next, an oxide film 232f, which will become the oxide layer 232, is deposited on the insulating film 224f (see Figures 8A to 8D). For example, the oxide film 232f can be deposited by sputtering using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2.

[0241] Next, a semiconductor film 230af, which will become the semiconductor layer 230a, is deposited on the oxide film 232f (see Figures 8A to 8D). The semiconductor film 230af can be deposited using a sputtering method. For example, a semiconductor film 230af containing indium, a first element, and oxygen can be deposited by a sputtering method using a sputtering target containing indium, the first element, and oxygen (which can also be called a sputtering target of indium oxide containing the first element). If the first element is gallium or aluminum, the film can be deposited by a sputtering method using an oxide target containing indium and gallium.

[0242] The sputtering target may contain the first element such that it is present in a preferred concentration in the semiconductor layer 230a. For example, the concentration of the first element in the sputtering target is 0.00001 atomic% or more and 1 atomic% or less, preferably 0.00001 atomic% or more and 0.5 atomic% or less, more preferably 0.00001 atomic% or more and 0.1 atomic% or less, and even more preferably 0.00001 atomic% or more and 0.06 atomic% or less.

[0243] In sputtering, the sputtered particles ejected from the target are used for film deposition. Compared to methods such as ALD and CVD, this method allows for the use of particles with higher kinetic energy. Therefore, by using the sputtering method, dense films can be deposited relatively easily.

[0244] Furthermore, when forming a semiconductor film 230af containing indium, a second element, and oxygen, a sputtering target of indium oxide containing the second element can be used. The concentration of the second element in the sputtering target should be within the preferred range of the concentration of the first element in the sputtering target as described above.

[0245] The method for forming the semiconductor film 230af containing indium, a first element, and oxygen is not limited to the above. For example, the semiconductor film 230af can be formed on an oxide film 232f by sputtering using an indium oxide sputtering target, and then the first element can be supplied to the semiconductor film 230af (see Figures 9A to 9D). In Figures 9B to 9D, the supply of the first element is indicated by an arrow. The first element is preferably at least one of gallium or aluminum. The first element can be supplied to the semiconductor film 230af by methods such as ion doping, ion implantation, or thermal diffusion. Thus, a semiconductor film 230af containing indium, a first element, and oxygen can be formed.

[0246] In forming the semiconductor film 230af, it is preferable to use a sputtering target with a low impurity concentration, i.e., a high purity target. For example, the purity of the indium oxide sputtering target is 3N or higher, preferably 4N or higher, more preferably 5N or higher, more preferably 6N or higher, and even more preferably 7N or higher, 8N or higher, 9N or higher, or 10N or higher. Since the preferred concentration of the first element in the semiconductor film 230af (the concentration within the range described above) is relatively low, it becomes difficult to control the concentration of the first element in the semiconductor film 230af when using a low-purity sputtering target. Therefore, by forming a semiconductor film 230af with a low impurity concentration using a high-purity sputtering target, the supply amount of the first element becomes easier to control, and a semiconductor film 230af containing the first element at a desired concentration can be formed.

[0247] Furthermore, when supplying a second element to a semiconductor film 230af deposited by a sputtering method using an indium oxide sputtering target, the method for supplying the second element can be described in the above-mentioned explanation of the method for supplying the first element.

[0248] Furthermore, when fabricating a semiconductor device having multiple transistors, for example, a semiconductor film 230af can be formed by sputtering using an indium oxide sputtering target, followed by supplying a first element to the region that will become at least one semiconductor layer 230a of the multiple transistors and its vicinity, and then supplying a second element to the region that will become at least one other semiconductor layer 230a of the multiple transistors or its vicinity. This makes it possible to fabricate transistors according to the characteristics of the circuit constituting the semiconductor device. When supplying the first element, it is preferable to place a mask above the region where at least the second element is supplied, and when supplying the second element, it is preferable to place a mask above the region where at least the first element is supplied. The order in which the first and second elements are supplied does not matter.

[0249] When using an indium-containing oxide for the semiconductor film 230af, a hydrogen-containing gas (for example, H) is used as the film deposition gas. ２ or H ２It is preferable to use a mixed gas containing O). Furthermore, it is preferable that the deposition temperature of the semiconductor film 230af be low (for example, around room temperature). By depositing the semiconductor film 230af at a low deposition temperature in a hydrogen-containing atmosphere, the hydrogen can suppress the initial crystal nucleation of indium oxide. Therefore, the number of crystal grains produced during the deposition of the semiconductor film 230af can be reduced. Moreover, by depositing the film at a low deposition temperature, it is possible to prevent the hydrogen incorporated into the semiconductor film 230af from diffusing outward, so that the initial crystal nucleation of indium oxide can be sufficiently suppressed by the hydrogen. Therefore, it is possible to deposit a semiconductor film 230af with low crystallinity (for example, amorphous). In this way, by reducing the number of crystal grains in the semiconductor film 230af and performing the heat treatment described later, the number of crystal grains in the semiconductor film 230af can be increased.

[0250] Furthermore, as the sputtering gas, a noble gas (typically argon), a single gas of oxygen, or a mixture of a noble gas and oxygen can be used.

[0251] Next, a semiconductor film 230bf, which will become the semiconductor layer 230b, is deposited on the semiconductor film 230af (see Figures 10A to 10D). Hereinafter, the laminated film of semiconductor film 230af and semiconductor film 230bf may be referred to as semiconductor film 230f. In this embodiment, the semiconductor film 230bf is deposited by the ALD method.

[0252] Indium oxide films, such as indium oxide, deposited by the ALD method tend to have lower potential barriers at similar carrier concentrations compared to similar films deposited by sputtering. Therefore, by depositing the semiconductor layer 230b using the ALD method, a film with a lower potential barrier than the semiconductor film 230af can be deposited. It should be noted that indium oxide films tend to have low potential barriers regardless of the deposition method.

[0253] For the deposition of the semiconductor film 230bf, an indium-containing precursor and an oxidizing agent can be used. When using an indium-containing precursor, it is preferable to use the thermal ALD method. However, it is not limited to this, and the PEALD method can also be used.

[0254] For the deposition of the semiconductor film 230bf, it is preferable to use a precursor with a low impurity concentration, i.e., a high purity precursor. For example, the purity of the precursor should be 3N or higher, preferably 4N or higher, more preferably 5N or higher, more preferably 6N or higher, and even more preferably 7N or higher, 8N or higher, 9N or higher, or 10N or higher. This makes it possible to deposit a semiconductor film 230bf with a low impurity concentration.

[0255] Indium-containing precursors that can be used include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolat)indium.

[0256] For example, a semiconductor film of 230bf can be deposited by a thermal ALD method using triethylindium as a precursor.

[0257] Furthermore, inorganic materials that do not contain hydrocarbons may be used as precursors containing indium. As inorganic materials containing indium, halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide) can be used. Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film deposition by the ALD method can be performed while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0258] As an oxidizing agent, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) and the like can be used. The oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, etc., which do not contain hydrogen, as the oxidizing agent, the amount of hydrogen mixed into the semiconductor film 230bf can be reduced.

[0259] Unless otherwise specified in this specification, when ozone, oxygen, or water are used as oxidizing agents, these shall include not only gaseous or molecular states, but also plasma states, radical states, or ionic states.

[0260] Thus, by depositing the semiconductor film 230af by sputtering and the semiconductor film 230bf by ALD, a semiconductor layer 230 with a potential barrier value within the above range can be formed. Therefore, a semiconductor device having a transistor with high on-current characteristics such as field-effect mobility and on-current can be provided.

[0261] If a semiconductor layer 230 having a potential barrier value within the above range can be formed by depositing a semiconductor film 230af by sputtering and a semiconductor film 230bf by ALD, then the materials applicable to semiconductor layers 230a and 230b are not particularly limited. For example, indium oxide containing the first element mentioned above can be used as semiconductor layer 230b. By including the first element in semiconductor layer 230b, the formation of oxygen vacancies within the semiconductor layer 230 can be suppressed. Furthermore, it is preferable that the first element is an element that mainly exists as a trivalent cation, the same as indium. This allows the carrier concentration of semiconductor layer 230 to be kept low. Therefore, it becomes possible to shift the threshold voltage of the transistor to the positive side. Also, normally-off becomes possible. Therefore, a transistor with good electrical characteristics can be provided.

[0262] The concentration of the first element in semiconductor layer 230b can be the preferred concentration of the first element in semiconductor layer 230a. For example, the concentration of the first element in semiconductor layer 230b can be greater than 1 atomic percent and 10 atomic percent or less, preferably 2 atomic percent or more and 10 atomic percent or less, and more preferably 5 atomic percent or more and 10 atomic percent or less.

[0263] Furthermore, if the semiconductor layer 230b contains the first element, indium oxide can also be used as the semiconductor layer 230a. By including the first element in the semiconductor layer 230b, the release of oxygen upward from the semiconductor layer 230a can be suppressed, thereby suppressing the formation of oxygen vacancies in the semiconductor layer 230a.

[0264] Furthermore, a semiconductor film that will become a semiconductor layer 230c may be formed on the semiconductor film 230bf. By forming this semiconductor film, a semiconductor layer 230 having a three-layer structure can be formed.

[0265] For the method of forming the semiconductor film that will become the semiconductor layer 230c, refer to the description of the method for forming the semiconductor film 230af and the semiconductor film 230bf. It is preferable to form the semiconductor film by the ALD method. Since the ALD method is a film formation method that causes little damage to the surface to be formed, the crystallinity of the semiconductor film may be improved by using the semiconductor film 230bf as a seed or nucleus. In addition, if the semiconductor film contains a first element, the incorporation of the first element into the semiconductor film 230bf can be suppressed.

[0266] Next, a heat treatment is preferable. The temperature for the heat treatment can be, for example, 100°C to 800°C, preferably 250°C to 650°C, and more preferably 350°C to 550°C. Typically, it can be 400°C ± 25°C (375°C to 425°C). The treatment time can be 10 hours or less, for example, 1 minute to 5 hours, or 1 minute to 2 hours. When using an RTA (Rapid Thermal Anneal) device, the treatment time can be, for example, 1 second to 5 minutes.

[0267] There are no special limitations on the heating device used for heat treatment; it may be a device that heats the workpiece by heat conduction or thermal radiation from a heat source such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device performs heat treatment using high-temperature gas.

[0268] By performing a heat treatment, the crystallinity of the semiconductor film 230f can be improved. Furthermore, as described above, by depositing the semiconductor film 230af in a hydrogen-containing atmosphere, the hydrogen is removed by the heat treatment, and the crystallization of indium oxide progresses. Therefore, the crystal grain size in the semiconductor film 230f can be increased. As a result, the on-current, S-value, field-effect mobility, and frequency characteristics of the transistor 200 can be improved, and a semiconductor device with good electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0269] Furthermore, because the semiconductor film 230f has crystal grains, it can be difficult to confirm the boundary between the semiconductor film 230af and the semiconductor film 230bf. In other words, the semiconductor film 230f may be observed as a single indium-containing oxide film. In Figure 10B, the boundary between the semiconductor film 230af and the semiconductor film 230bf is shown by a dashed line.

[0270] The heat treatment is carried out in an inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Examples of inert gases include nitrogen gas and noble gases. For example, when performing the heat treatment in a mixed atmosphere of nitrogen gas and oxygen gas, it is preferable to have about 20% oxygen gas. The heat treatment may also be carried out under reduced pressure. Alternatively, after heat treatment in an inert gas atmosphere, the heat treatment may be carried out again in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the oxygen that has been removed.

[0271] Furthermore, it is preferable that the gas used in the above heat treatment is highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb (0.001 ppm) or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent as much as possible from the incorporation of water and other substances into the semiconductor film 230f, etc. In addition, a highly purified gas can be used in the heat treatment before and after this step as well.

[0272] By performing a heat treatment containing oxygen gas, impurities such as carbon, water, and hydrogen in the semiconductor film 230f can be reduced. By reducing impurities in the film in this way, the crystallinity of the semiconductor film 230f can be improved, resulting in a denser, more compact structure. This increases the crystalline region in the semiconductor film 230f and reduces in-plane variation of the crystalline region within the semiconductor film 230f. Therefore, in-plane variation in the electrical characteristics of the transistor can be reduced.

[0273] Furthermore, by performing a heat treatment, oxygen can be supplied to the semiconductor film 230f, thereby reducing oxygen deficiencies in the semiconductor film 230f. This can improve the reliability of the transistor 200.

[0274] Furthermore, by performing the heat treatment, hydrogen in the insulating layer 216, insulating film 224f, oxide film 232f, and semiconductor film 230f moves to the insulating layer 222 and is absorbed into the insulating layer 222. In other words, hydrogen in the insulating layer 216, insulating film 224f, oxide film 232f, and semiconductor film 230f diffuses into the insulating layer 222. Consequently, the hydrogen concentration in the insulating layer 222 increases, but the hydrogen concentrations in the insulating layer 216, insulating film 224f, oxide film 232f, and semiconductor film 230f decrease. By providing an insulating layer 221 in contact with the lower surface of the insulating layer 222, it is possible to prevent moisture or impurities such as hydrogen from entering from below the insulating layer 221 during the heat treatment.

[0275] In particular, the insulating layer 224 formed from the insulating film 224f functions as a second gate insulating layer of the transistor 200, and a portion of the semiconductor layer 230 formed from the semiconductor film 230f functions as a channel formation region of the transistor 200. A transistor 200 formed using the insulating film 224f, oxide film 232f, and semiconductor film 230f with reduced hydrogen concentration is preferred because it has good reliability.

[0276] Next, oxide films 231f, which will become oxide layers 231a and 231b, are deposited on the semiconductor film 230f (see Figures 10A to 10D). By depositing the oxide films 231f on the semiconductor film 230f without an etching process after the deposition of the semiconductor film 230f, the upper surface of the semiconductor film 230f can be protected by the oxide films 231f. This reduces the diffusion of impurities into the semiconductor layer 230 that constitutes the transistor, thereby improving the electrical characteristics and reliability of the semiconductor device.

[0277] For example, an ITO film can be deposited as an oxide film 231f using the sputtering method. By improving the crystallinity of the semiconductor film 230f before depositing the oxide film 231f, the crystallinity of the oxide film 231f may be improved by using the crystal grains of the semiconductor film 230f as seeds or nuclei. In this case, it may become difficult to confirm the boundary between the semiconductor film 230f and the oxide film 231f. In other words, the semiconductor film 230f and the oxide film 231f may be observed as a single indium-containing oxide film.

[0278] Next, conductive films 242f, which will become conductive layers 242a and 242b, are formed on the oxide film 231f (see Figures 10A to 10D). For example, a tungsten film is formed as the conductive film 242f using the sputtering method.

[0279] Next, an insulating film 271f is deposited on the conductive film 242f (see Figures 10A to 10D). For example, as the insulating film 271f, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film can be deposited by sputtering.

[0280] Next, using lithography, the insulating film 224f, oxide film 232f, semiconductor film 230f, oxide film 231f, conductive film 242f, and insulating film 271f are processed into island-like structures to form the insulating layer 224, oxide layer 232, semiconductor layer 230, oxide layer 231, conductive layer 242, and insulating layer 271 (see Figures 11A to 11D).

[0281] The above processing can be performed using either a dry etching method or a wet etching method. Dry etching is suitable for microfabrication. Furthermore, the processing of the insulating film 224f, oxide film 232f, semiconductor film 230f, oxide film 231f, conductive film 242f, and insulating film 271f may be carried out under different conditions.

[0282] Here, it is preferable to process the insulating layer 224, oxide layer 232, semiconductor layer 230, oxide layer 231, conductive layer 242, and insulating layer 271 together in an island shape. In this case, it is preferable that the side edge of the insulating layer 271 coincides with that of the conductive layer 242. Furthermore, it is preferable that the side edge of the conductive layer 242 coincides with that of the oxide layer 231. Furthermore, it is preferable that the side edge of the oxide layer 231 coincides with that of the semiconductor layer 230. Furthermore, it is preferable that the side edge of the semiconductor layer 230 coincides with that of the oxide layer 232. Furthermore, it is preferable that the side edge of the oxide layer 232 coincides with that of the insulating layer 224. By adopting such a configuration, the number of processes for the semiconductor device according to one aspect of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with good productivity can be provided.

[0283] Furthermore, the island-shaped laminate, consisting of an insulating layer 224, an oxide layer 232, a semiconductor layer 230, an oxide layer 231, a conductive layer 242, and an insulating layer 271, is formed such that at least a portion of it overlaps with the conductive layer 205. In addition, the insulating layer 222 is exposed in the region that does not overlap with the island-shaped laminate.

[0284] As shown in Figure 11B, the sides of the island-shaped laminate may be tapered. The taper angle of the side of the island-shaped laminate may be, for example, 60° or more and less than 90°. By making the sides tapered in this way, the coverage of the insulating layer 275 and other components is improved in subsequent processes, and defects such as porosity can be reduced.

[0285] In lithography, the resist is first exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Then, by etching through this resist mask, conductors, semiconductors, or insulators can be processed into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. Alternatively, immersion technology may be used, where a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. In addition, an electron beam or ion beam may be used instead of the aforementioned light. When using an electron beam or ion beam, a mask may not be necessary in some cases.

[0286] Furthermore, the resist mask that is no longer needed after processing can be removed by dry etching, such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching, wet etching after dry etching, or dry etching after wet etching.

[0287] Furthermore, a hard mask consisting of an insulating layer or a conductive layer may be used beneath the resist mask. When using a hard mask, an insulating film or conductive film that will serve as the hard mask material is formed on the insulating film 271f, a resist mask is formed on top of it, and a hard mask of the desired shape can be formed by etching the hard mask material. For example, tungsten may be used as the hard mask material. Etching of the insulating film 271f may be performed after removing the resist mask, or it may be performed while the resist mask remains. In the latter case, the resist mask may disappear during etching. The hard mask may also be removed by etching after etching of the semiconductor film 230f, etc. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not always necessary to remove the hard mask.

[0288] Alternatively, a configuration may be used in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are deposited between the workpiece and the resist mask. By using the SOC film and SOG film as masks, the adhesion to the resist mask can be improved, and the durability of the mask pattern can be enhanced. For example, lithography can be performed by depositing the SOC film, SOG film, and resist mask in that order on the workpiece.

[0289] For dry etching, an etching gas containing halogens can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as an etching gas, C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ Gas, or BBr ３Gases or the like may be used alone, or two or more gases may be mixed for use. Further, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas or the like may be appropriately added to the above etching gas. Further, depending on the workpiece to be subjected to dry etching treatment, a gas containing no halogen gas but containing hydrocarbon gas or hydrogen gas can be used as the etching gas. As the hydrocarbon used for the etching gas, methane (CH ４ 4), ethane (C ２ 2H ６ 6), propane (C ３ 3H ８ 8), butane (C ４ 4H １０ 10), ethylene (C ２ 2H ４ 4), propylene (C ３ 3H ６ 6), acetylene (C ２ 2H ２ 2), and propyne (C ３ 3H ４ 4) can be used singly or in combination. Etching conditions can be appropriately set according to the object to be etched.

[0290] As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Furthermore, a configuration in which multiple different high-frequency voltages are applied to the parallel plate electrodes may be used. Such a CCP etching apparatus is called a dual-frequency excited capacitively coupled plasma (DF-CCP) etching apparatus. In a DF-CCP etching apparatus, a configuration in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes may be used. Alternatively, a configuration in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes may be used. Alternatively, a dry etching apparatus having a high-density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source. The etching apparatus can be appropriately configured according to the object to be etched. In addition, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side of the dry etching apparatus to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thus enabling highly anisotropic etching.

[0291] Furthermore, in the etching process described above, the insulating layer 271 can function as an etching stopper to protect the conductive layer 242. For example, if a metallic hard mask is formed on the insulating layer 271 in the etching process described above, it may be difficult to obtain a suitable etching selectivity ratio with respect to the conductive layer 242 when removing the hard mask. However, by forming the insulating layer 271 on the conductive layer 242, the insulating layer 271 can function as an etching stopper to protect the conductive layer 242 during the etching process for removing the hard mask. This prevents the formation of a curved surface between the side and top surfaces of the conductive layer 242, so that the conductive layers 242a and 242b formed later have angular edges where the side and top surfaces intersect, as shown in Figure 1D. The angular shape of the edges where the side and top surfaces of the conductive layer 242 intersect increases the cross-sectional area of ​​the conductive layer 242 compared to when the edges have curved surfaces. Furthermore, by using a nitride insulator that is less likely to oxidize metals for the insulating layer 271, it is possible to prevent the conductive layer 242 from being excessively oxidized. As a result, the resistance of conductive layers 242a and 242b is reduced, allowing the on-current of the transistor to be increased.

[0292] Furthermore, by processing the insulating layer 224 into an island shape, the insulating layer 275 can be provided in contact with the side surface of the insulating layer 224 and the upper surface of the insulating layer 222 in a process described later. In other words, the insulating layer 224 can be separated from the insulating layer 280 by the insulating layer 275. With this configuration, it is possible to prevent excess amounts of oxygen and hydrogen and other impurities from entering the semiconductor layer 230 from the insulating layer 280 through the insulating layer 224.

[0293] Next, an insulating layer 275 is formed over the island-shaped laminate, and then an insulating layer 280 is formed on top of the insulating layer 275 (see Figures 12A to 12D).

[0294] For example, silicon nitride can be deposited as the insulating layer 275 using the PEALD method.

[0295] For example, silicon oxide can be deposited as the insulating layer 280 using a sputtering method. By depositing the insulating layer 280 using a sputtering method in an oxygen-containing atmosphere, an insulating layer 280 containing excess oxygen can be formed. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced.

[0296] Furthermore, by performing CMP treatment on the insulating layer 280, the upper surface of the insulating layer 280 can be made flat. Alternatively, silicon nitride may be deposited on the insulating layer 280 by, for example, a sputtering method, and then CMP treatment may be performed on the silicon nitride until it reaches the insulating layer 280.

[0297] Next, the conductive layer 242, insulating layer 271, insulating layer 275, and insulating layer 280 are processed using lithography to form an opening 289 that reaches the oxide layer 231 and insulating layer 222 (see Figures 13A to 13D). Here, the areas of the conductive layer 242 and insulating layer 271 that overlap with the opening 289 are removed. As a result, the conductive layer 242 is divided to form conductive layers 242a and 242b, and the insulating layer 271 is divided to form insulating layers 271a and 271b. The opening 289 is formed in the area where the semiconductor layer 230b and the conductive layer 205 overlap. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening 289 corresponds to the distance L1 shown in Figure 2A. That is, the width of the opening 289 is greater than the distance L2 shown in Figure 2A.

[0298] The lithography method can be appropriately adapted to the above method. To finely process the aperture 289, it is preferable to use a lithography method using short-wavelength light such as i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), ultraviolet light, KrF laser light, ArF laser light, EUV light, or an electron beam.

[0299] For example, a lithography method can be performed by depositing an SOC film, an SOG film, and a resist mask in that order on an insulating layer 280. A resist mask with an aperture is formed using short-wavelength light such as EUV light or an electron beam, and the SOG film, SOC film, insulating layer 280, insulating layer 275, insulating layer 271, and conductive layer 242 are processed using the resist mask.

[0300] The above processing is preferably carried out using a dry etching method. Since the dry etching method allows for anisotropic etching, it is suitable for forming an aperture 289 with a high aspect ratio. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. Furthermore, the etching treatment of the SOG film, SOC film, insulating layer 280, insulating layer 275, insulating layer 271, and conductive layer 242 may be carried out under different conditions.

[0301] For example, when tungsten is used for the conductive layer 242 and ITO is used for the oxide layer 231, the ICP etching apparatus will produce CF ４ and Cl ２ and O ２ By using as the etching gas, the conductive layer 242 can be etched. Here, since the conductive layer 242 is etched superimposed on the opening 289, the distance between the separated conductive layer 242a and conductive layer 242b becomes distance L1.

[0302] In addition, the etching process described above may etch up to the top of the oxide layer 231. In this case, the film thickness of the oxide layer 231a and oxide layer 231b in contact with the insulating layer 255 will be thinner than the film thickness of other parts.

[0303] Next, an insulating film 255f is formed to cover the insulating layer 280, the oxide layer 231, and the insulating layer 222, forming the insulating layer 255 (see Figures 14A to 14D). Since the insulating film 255f is formed along the side walls of the opening 289, it is preferable that it has good coverage. Therefore, it is preferable to form the insulating film 255f using a method such as the ALD method, which has good coverage. For example, it is preferable to form silicon nitride as the insulating film 255f using the PEALD method.

[0304] Next, a portion of the insulating film 255f is removed by anisotropic etching to form a sidewall-shaped insulating layer 255 within the opening 289 (see Figures 15A to 15D). As a result, the insulating layer 255 is formed within the opening 289 in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, the side surface of the insulating layer 271a, the side surface of the insulating layer 271b, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the upper surface of the oxide layer 231, and the upper surface of the insulating layer 222. In some cases, a portion of the insulating layer 255 may be formed in contact with the side surface of the insulating layer 224, the side surface of the oxide layer 232, the side surface of the semiconductor layer 230, or the side surface of the oxide layer 231.

[0305] In a cross-sectional view along the channel length, since the insulating layer 255 is formed within the opening 289, the shortest distance between the insulating layer 255 on side A1 and the insulating layer 255 on side A2 is shorter than the distance L1.

[0306] For anisotropic etching of the insulating film 255f, a dry etching method is preferable. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. For example, when silicon nitride is used for the insulating film 255f, an ICP etching apparatus is used, and CHF ３ and O ２ Etching can be performed by using this as the etching gas.

[0307] Next, anisotropic etching is used to remove the region of the oxide layer 231 exposed from the insulating layer 255, thereby forming oxide layer 231a and oxide layer 231b (see Figures 16A to 16D). In other words, the oxide layer 231 is processed using the insulating layer 280 and insulating layer 255 as masks, dividing the oxide layer 231 into oxide layer 231a and oxide layer 231b. By processing the oxide layer 231 using anisotropic etching, side etching of the insulating layer 255 can be suppressed. In this way, by processing the oxide layer 231 using the insulating layer 255 as a mask, in a cross-sectional view of the transistor 200, oxide layer 231a is formed so that its side edge coincides with that of the insulating layer 255, and oxide layer 231b is formed so that its side edge coincides with that of the insulating layer 255. In a cross-sectional view in the channel length direction, the shortest distance between oxide layer 231a and oxide layer 231b corresponds to the distance L2 shown in Figure 2A.

[0308] For anisotropic etching, it is preferable to use a dry etching method. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. For example, when ITO is used for the oxide layer 231, an ICP etching apparatus is used, ２ Etching can be performed using Ar as the etching gas.

[0309] As described above, an insulating layer 255 can be formed on the oxide layer 231 using anisotropic etching, and the oxide layer 231 can be divided using the insulating layer 255 as a mask. In this way, the insulating layer 255 that functions as a mask can be formed self-aligned. As a result, the number of masks and the number of processes can be reduced in the semiconductor device manufacturing process shown in this embodiment. Therefore, a highly productive method for manufacturing semiconductor devices can be provided.

[0310] Furthermore, by using the above method, the island-shaped semiconductor layer 230 can be exposed to dry etching only during the processing of the oxide layer 231. In other words, the upper surface of the island-shaped semiconductor layer 230 can be prevented from being exposed to dry etching during the formation of the insulating layer 255. This reduces the damage (for example, damage due to ion collisions) that the semiconductor layer 230b, which functions as the channel formation region of the transistor 200, suffers from dry etching. During the dry etching process of the oxide layer 231, the damage to the semiconductor layer 230 can be further reduced by lowering the bias power midway through the process.

[0311] Furthermore, as shown in Figure 16B, recesses may be formed in the portions of the semiconductor layer 230 that are exposed from the oxide layers 231a and 231b. For example, if indium oxide is used for the semiconductor layer 230 and ITO is used for the oxide layer 231, the semiconductor layer 230 and the oxide layer 231 both contain oxygen and indium, making it difficult to selectively etch the oxide layer 231 relative to the semiconductor layer 230. In this case, as shown in Figure 2A, the film thickness of the semiconductor layer 230 in the region overlapping with the insulating layer 250 becomes thinner than the film thickness of the semiconductor layer 230 in the region overlapping with the oxide layer 231a or the oxide layer 231b.

[0312] In this case, for the semiconductor layer 230b to be used as a current path, it is preferable that the semiconductor layer 230b remains in the region overlapping with the insulating layer 250. For example, it is preferable that the film thickness of the semiconductor layer 230 in the region overlapping with the insulating layer 250 is greater than the film thickness of the semiconductor layer 230a. As a result, even if the film thickness of the semiconductor layer 230 in the region overlapping with the insulating layer 250 becomes thinner, the semiconductor layer 230b remains, thereby suppressing a decrease in on-current and field-effect mobility.

[0313] Furthermore, when the semiconductor layer 230 has the three-layer structure shown in Figure 3A, it is preferable that the semiconductor layer 230c remains in the region overlapping with the insulating layer 250. This reduces the effect of surface scattering and increases the field-effect mobility of the transistor 200. It also increases the on-current of the transistor 200. Alternatively, the semiconductor layer 230c in the region overlapping with the insulating layer 250 may be removed, exposing the upper surface of the semiconductor layer 230b. In this case, since the semiconductor layer 230b remains, a decrease in on-current and field-effect mobility can be suppressed.

[0314] Furthermore, an ashing treatment using oxygen plasma may be performed after processing the oxide layer 231. By performing such oxygen plasma treatment, impurities generated in the etching process and diffused into the semiconductor layer 230 can be removed. These impurities may be caused by components contained in the workpiece subjected to the etching process, or by components contained in the gas used for etching. Examples include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, as shown in the etching process, if chlorine gas is used in processing the oxide layer 231, the semiconductor layer 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine adhering to the semiconductor layer 230. By removing impurities adhering to the semiconductor layer 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0315] Furthermore, the above-mentioned oxygen plasma treatment may cause oxidation of at least a portion of the insulating layer 255. In other words, oxygen may be present in the insulating layer 255. Note that if the oxidation of the insulating layer 255 progresses, at least a portion of the insulating layer 255 may become silicon oxidized nitride or silicon nitride oxide after the formation of the transistor 200.

[0316] As described above, oxide layers 231a and 231b with low contact resistance with the semiconductor layer 230 can be formed beneath conductive layers 242a and 242b, which have good conductivity. Furthermore, an oxidation-resistant insulating layer 255 can be formed in contact with the sides of conductive layers 242a and 242b. With this configuration, conductive layers 242a and 242b, which have good conductivity, can be used as the source and drain electrodes of the transistor 200, and the parasitic capacitance between conductive layer 260 and conductive layer 242a, and between conductive layer 260 and conductive layer 242b can be reduced. Therefore, the field-effect mobility and frequency characteristics of the transistor 200 can be improved.

[0317] Furthermore, it is preferable to perform a cleaning process to remove impurities and other contaminants adhering to the surface of the semiconductor layer 230 during the etching process described above. Cleaning methods include wet cleaning using a cleaning solution (which can also be called wet etching), plasma treatment using plasma, and cleaning by heat treatment, and these cleaning methods may be combined as appropriate. Note that the grooves may become deeper as a result of this cleaning process.

[0318] Wet cleaning may be performed using an aqueous solution obtained by diluting one or more of oxalic acid, phosphoric acid, and hydrofluoric acid with carbonated water or distilled water. Alternatively, wet cleaning may be performed using an aqueous solution obtained by diluting ammonia water with carbonated water or distilled water. Alternatively, wet cleaning may be performed using distilled water or carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, distilled water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate. In this specification, an aqueous solution obtained by diluting hydrofluoric acid with distilled water is sometimes called diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with distilled water is sometimes called diluted ammonia water. The concentration, temperature, etc. of the aqueous solution should be adjusted as appropriate depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned.

[0319] Furthermore, the above cleaning process may be performed multiple times, and the cleaning solution may be changed each time. For example, the first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and the second cleaning process may be performed using pure water or carbonated water.

[0320] It is preferable to perform a heat treatment after etching or cleaning as described above. The temperature of the heat treatment should be between 100°C and 650°C, preferably between 250°C and 600°C, more preferably between 300°C and 550°C, and even more preferably between 350°C and 400°C. The heat treatment should be performed in an atmosphere of inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. It is preferable to perform the heat treatment in an atmosphere containing oxygen, for example, by setting the flow rate ratio of nitrogen gas to oxygen gas to 4:1 and performing the treatment at a temperature of 350°C for 1 hour. This allows oxygen to be supplied to the semiconductor layer 230, thereby reducing oxygen deficiency. Furthermore, by performing such a heat treatment, the crystallinity of the semiconductor layer 230 can be improved. In addition, the supplied oxygen reacts with the hydrogen remaining in the semiconductor layer 230, thereby converting the hydrogen into H ２ It can be removed as O (dehydrated). As a result, the hydrogen remaining in the semiconductor layer 230 recombines with the oxygen vacancy and V Ｏ The formation of H can be suppressed. Therefore, the electrical characteristics of the transistor provided with the semiconductor layer 230 can be improved, and its reliability can be enhanced. In addition, variations in the electrical characteristics of multiple transistors formed on the same substrate can be suppressed. The above heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an oxygen atmosphere, followed by continuous heat treatment in a nitrogen atmosphere without exposure to the atmosphere.

[0321] As described above, an insulating layer 255 having an inorganic insulator that is resistant to oxidation is provided in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b. This prevents the conductive layer 242a and conductive layer 242b from being excessively oxidized by the heat treatment, even if a tungsten film or the like, which is relatively easy to oxidize, is used for the conductive layer 242a and conductive layer 242b. Furthermore, it prevents the interface between the conductive layer 242a and the oxide layer 231a, and the interface between the conductive layer 242b and the oxide layer 231b from being excessively oxidized.

[0322] Next, an insulating film 250f, which will become the insulating layer 250, is formed to cover the opening 289 (see Figures 17A to 17D).

[0323] For example, the insulating film 250f is preferably deposited using the ALD method. The insulating film 250f is preferably formed with a thin film thickness, and it is necessary to minimize variations in film thickness. In this regard, the ALD method is a film deposition method that alternately introduces a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness adjustment. Furthermore, the insulating film 250f needs to be deposited with good coverage on the bottom and sides of the opening 289. By using the ALD method, layers of atoms can be deposited one by one on the bottom and sides of the opening 289, so the insulating film 250f can be formed with good coverage on the opening 289.

[0324] Furthermore, when depositing the insulating film 250f using the ALD method, ozone (O) is used as the oxidizing agent. ３ ), oxygen (O ２ ), water (H ２ O) can be used. Hydrogen-free ozone (O) ３ ), oxygen (O ２ By using oxidizing agents such as ), the amount of hydrogen diffusing into the semiconductor layer 230 can be reduced.

[0325] The insulating layer 250 can be in a laminated structure, as shown in Figure 2A. Below, we will describe a method for forming the insulating film 250f when the insulating layer 250 has a four-layer structure consisting of insulating layers 250a to 250d, similar to Figure 2A.

[0326] First, a first film, which will be an insulating layer 250a, is formed to cover the opening 289, and then a second film, which will be an insulating layer 250b, is formed on the first film. For example, hafnium oxide can be formed as the first film by thermal ALD, and silicon oxide can be formed as the second film by PEALD.

[0327] Next, it is preferable to perform microwave plasma treatment in an oxygen-containing atmosphere. Here, microwave plasma treatment refers to treatment using a device that has a power supply that generates high-density plasma using microwaves, for example. In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0328] In microwave plasma processing, it is preferable to use a microwave plasma processing apparatus that has a power supply for generating high-density plasma using microwaves. Here, the frequency of the microwave plasma processing apparatus is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the power of the power supply for applying microwaves to the microwave plasma processing apparatus is preferably 1000 W to 10000 W, more preferably 2000 W to 5000 W. The microwave plasma processing apparatus may also have a power supply for applying RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by the high-density plasma can be efficiently guided into the semiconductor layer 230.

[0329] Furthermore, the above microwave plasma treatment is preferably carried out under reduced pressure, with a pressure of 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature is preferably 750°C or lower, more preferably 500°C or lower, and can be, for example, around 250°C. In addition, after the oxygen plasma treatment, a continuous heat treatment may be performed without exposure to the outside air. The heat treatment temperature is preferably, for example, 100°C to 750°C, and more preferably 300°C to 500°C.

[0330] Furthermore, for example, the above microwave plasma treatment can be carried out using oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / ( O ２ The amount of +Ar) is greater than 0% and less than or equal to 100%, preferably greater than 0% and less than or equal to 50%, more preferably between 10% and 40%, and even more preferably between 10% and 30%. In this way, by performing microwave plasma treatment in an oxygen-containing atmosphere, the carrier concentration in the region between the conductive layer 242a and the conductive layer 242b of the semiconductor layer 230 can be reduced. Furthermore, by preventing the introduction of an excessive amount of oxygen into the chamber during microwave plasma treatment, it is possible to prevent an excessive decrease in the carrier concentration in the semiconductor layer 230.

[0331] By performing microwave plasma treatment in an oxygen-containing atmosphere, the oxygen gas is converted into plasma using microwaves or high frequencies such as RF, and this oxygen plasma can be applied to the region of the semiconductor layer 230 between the conductive layer 242a and the conductive layer 242b. Hydrogen can be removed from this region by the action of plasma, microwaves, etc. Here, it is preferable to use an insulating film (for example, aluminum oxide) that has the function of capturing or fixing hydrogen as the first film. With this configuration, the hydrogen generated by the microwave plasma treatment can be captured or fixed to the first film. In this way, the V included in the channel formation region Ｏ H can be reduced. As a result, oxygen deficiency in the channel formation region and V can be reduced. Ｏ This reduces H and lowers the carrier concentration. Furthermore, by supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be lowered.

[0332] The oxygen injected into the channel formation region can take various forms, including oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or molecules), and oxygen radicals (oxygen atoms, molecules, or ions with unpaired electrons). The oxygen injected into the channel formation region may be one or more of the above forms, with oxygen radicals being particularly preferred. Furthermore, the film quality of the insulating layer 250 can be improved, thereby enhancing the reliability of the transistor. Additionally, the above microwave plasma treatment can supply oxygen to the insulating layer 250a, insulating layer 250b, etc. Excess oxygen in the insulating layer 250a and insulating layer 250b can be supplied to the channel formation region of the semiconductor layer 230 by subsequent heat treatment.

[0333] On the other hand, the semiconductor layer 230 has a region that overlaps with either the conductive layer 242a or the conductive layer 242b. This region can function as a source region or a drain region. Here, it is preferable that the conductive layer 242a and the conductive layer 242b function as shielding films against the above-mentioned effects when microwave plasma processing is performed in an oxygen-containing atmosphere. For this reason, it is preferable that the conductive layer 242a and the conductive layer 242b have the function of shielding electromagnetic waves between 300 MHz and 300 GHz, for example, between 2.4 GHz and 2.5 GHz.

[0334] The above effect is shielded by conductive layers 242a and 242b, and therefore does not extend to the region of the semiconductor layer 230 that overlaps with either conductive layer 242a or conductive layer 242b. As a result, the microwave plasma treatment does not affect the source region and drain region. Ｏ Because H is reduced and excessive oxygen supply does not occur, a decrease in carrier concentration can be prevented.

[0335] Furthermore, an insulating layer 255 is provided in contact with the sides of the conductive layers 242a and 242b, and has barrier properties against oxygen. In addition, a first film and a second film are provided covering the oxide layers 231a, 231b, and 255. This makes it possible to suppress the formation of oxide films on the sides of the conductive layers 242a and 242b by microwave plasma treatment.

[0336] As described above, oxygen vacancies and V are selectively formed in the channel formation region of the oxide semiconductor. Ｏ By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region functioning as the source or drain region can be suppressed, and the conductivity (low resistance state) before microwave plasma treatment can be maintained. This suppresses variations in the electrical characteristics of the transistor and prevents variations in the electrical characteristics of the transistor within the substrate surface.

[0337] Furthermore, by modifying the film quality of the first and second films through microwave plasma treatment, the diffusion of hydrogen, water, impurities, etc., can be suppressed. Therefore, by post-processing such as deposition of a conductive film to form the conductive layer 260, or post-treatment such as heat treatment, the diffusion of hydrogen, water, impurities, etc., into the semiconductor layer 230, etc., through the insulating layer 250 can be suppressed. In this way, by improving the film quality of the insulating layer 250, the reliability of the transistor can be improved.

[0338] Next, a third film, which will be an insulating layer 250c, is deposited on the second film, and a fourth film, which will be an insulating layer 250d, is deposited on the third film. For example, hafnium oxide can be deposited as the third film by thermal ALD, and silicon nitride can be deposited as the fourth film by PEALD. In this way, an insulating film 250f having the first to fourth films can be formed. Microwave plasma treatment may be performed again after the deposition of the third film.

[0339] Although the above describes an example in which microwave plasma treatment is performed after the formation of the second film and after the formation of the third film, the present invention is not limited to this. The present invention can also be configured to perform microwave plasma treatment after the formation of the second and third films. The present invention can also be configured to perform microwave plasma treatment after the formation of up to the fourth film. Alternatively, the present invention can be configured to perform microwave plasma treatment before the formation of the first film. Furthermore, the present invention may be configured to perform microwave plasma treatment three or more times.

[0340] Further, heat treatment may be performed while maintaining the reduced pressure state after microwave plasma treatment. By performing such heat treatment, hydrogen in the insulating film 250f and the semiconductor layer 230 can be efficiently removed. Further, by performing such heat treatment, oxygen supplied to the insulating layer 250b or the like by the microwave plasma treatment can be supplied to the channel formation region of the semiconductor layer 230. Alternatively, the step of performing heat treatment while maintaining the reduced pressure state after microwave plasma treatment may be repeated a plurality of times. By repeatedly performing heat treatment, hydrogen in the insulating film 250f and the semiconductor layer 230 can be removed more efficiently. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0341] Next, a conductive film 260f to be the conductive layer 260 is formed over the insulating film 250f (see FIGS. 18A to 18D). For example, as shown in FIG. 2A, in the case of a stacked structure of a conductive layer 260a and a conductive layer 260b, titanium nitride can be formed by an ALD method as the conductive film to be the conductive layer 260a, and tungsten can be formed by a CVD method as the conductive film to be the conductive layer 260b.

[0342] The conductive film to be the conductive layer 260a can be formed by a thermal ALD method using a precursor containing an inorganic material, without using a hydrogen-containing gas. For example, as the inorganic material, TiCl ４ can be used. At this time, NH can be used as a nitriding agent ３ gas can be used. By forming the film by the above method, the conductive layer 260a can be a conductive film with a low hydrogen concentration as described above. Accordingly, these conductive films can be prevented from serving as hydrogen sources and diffusing hydrogen into the oxide semiconductor.

[0343] Here, the conductive layer 260a overlaps the semiconductor layer 230 with the thin insulating layer 250 interposed therebetween, and is close to the channel formation region of the semiconductor layer 230. For this reason, when treatment containing hydrogen is performed in the step of forming the conductive layer 260a, hydrogen easily diffuses into the channel formation region of the semiconductor layer 230. Therefore, as described above, it is preferable that the conductive layer 260a is a conductive film with a low hydrogen concentration.

[0344] Next, the insulating film 250f and the conductive film 260f are polished by CMP processing until the insulating layer 280 and the insulating layer 255 are exposed. In other words, portions of the insulating film 250f and the conductive film 260f exposed from the opening 289 are removed. Accordingly, the insulating layer 250 and the conductive layer 260 can be formed in the opening 289 in a self-aligning manner.

[0345] Next, an insulating layer 282 is formed over the insulating layer 255, over the insulating layer 250, over the conductive layer 260, and over the insulating layer 280 by film deposition. The insulating layer 282 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 282 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0346] Here, by depositing the insulating layer 282 in an oxygen-containing atmosphere using a sputtering method, oxygen can be added to the insulating layer 280 during deposition. This allows the insulating layer 280 to contain excess oxygen. At this time, it is preferable to deposit the insulating layer 282 while heating the substrate.

[0347] Next, an insulating layer 283 is formed over the insulating layer 282 by film deposition. The insulating layer 283 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 283 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0348] For example, aluminum oxide can be deposited as the insulating layer 282 by a sputtering method, and silicon nitride can be deposited as the insulating layer 283 by a sputtering method.

[0349] Next, an insulating layer 285 is formed over the insulating layer 283 (see FIGS. 19A to 19D). The insulating layer 285 is preferably formed by a sputtering method. The hydrogen concentration in the insulating layer 285 can be reduced by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas. For example, silicon oxide can be deposited as the insulating layer 285 by a sputtering method.

[0350] Next, openings reaching the conductive layer 242a are formed in insulating layers 271a, 275, 280, 282, 283, and 285, and openings reaching the conductive layer 242b are formed in insulating layers 271b, 275, 280, 282, 283, and 285. These openings may be formed using lithography. It is preferable to process the workpiece using a dry etching method for forming these openings. Dry etching is suitable for forming openings with a high aspect ratio because it allows for anisotropic etching. When performing anisotropic etching, it is preferable to perform reactive ion etching, for example. The conditions for the dry etching method and the dry etching apparatus can be found in the description above. The shape of the opening in a top view can be a circle, an ellipse or other approximate circle, a quadrilateral or other polygon, or a quadrilateral or other polygon with rounded corners.

[0351] Next, a film that will become the insulating layer 241 is formed along the shape of the opening. Since the film is formed in an opening with a large aspect ratio, it is preferable to form the film using the ALD method. As the film, it is preferable to use an insulating film that has the function of suppressing oxygen permeation. For example, it is preferable to form silicon nitride using the PEALD method. Silicon nitride is preferred because it has high barrier properties against hydrogen.

[0352] Next, the above film is anisotropically etched to form insulating layers 241a and 241b. Here, insulating layer 241a is formed to cover the side walls of the openings on the conductive layer 242a, and insulating layer 241b is formed to cover the side walls of the openings on the conductive layer 242b. For the anisotropic etching of the above film, a dry etching method or the like may be used. For example, reactive ion etching is preferred.

[0353] Next, a film to become the conductive layer 240 is formed. This film is a laminated film consisting of a first film that will become the conductive layer 240a1 and conductive layer 240b1, and a second film that will become the conductive layer 240a2 and conductive layer 240b2, as shown in Figure 2A.

[0354] As the first film, titanium nitride can be deposited using the thermal ALD method, and as the second film, tungsten can be deposited using the CVD method. The first film can be deposited using the thermal ALD method with an inorganic material precursor, without using a hydrogen-containing gas. For example, TiCl can be used as the inorganic material. ４ In this case, NH can be used as the nitride agent. ３ A gas can be used. By forming the film using the method described above, the conductive layer 240a1 and the conductive layer 240b1 can be made into conductive films with a low hydrogen concentration as described above. Therefore, these conductive films can act as a hydrogen source, preventing hydrogen from diffusing into the oxide semiconductor.

[0355] Next, the film that will become the conductive layer 240 is subjected to CMP treatment to remove a portion of the film, exposing the upper surface of the insulating layer 285. As a result, conductive layers 240a and 240b with flat upper surfaces can be formed, with the film remaining only at the openings (see Figures 1A to 1D). As described above, conductive layers 240a and 240b can be formed in parallel in the same process. For this reason, conductive layers 240a1 and 240b1 are formed using the same conductor. Conductive layers 240a2 and 240b2 are also formed using the same conductor. Note that the CMP treatment may remove a portion of the upper surface of the insulating layer 285.

[0356] Based on the above, the semiconductor devices shown in Figures 1A to 1D can be manufactured.

[0357] The semiconductor device according to this embodiment has an OS transistor. In this embodiment, the semiconductor layer of the OS transistor uses a multilayer film consisting of a metal oxide layer formed by sputtering and a metal oxide layer deposited thereon by ALD. This allows the surface current path of the semiconductor layer to be formed in the metal oxide layer deposited by ALD, which has a low potential barrier. Therefore, a transistor with high field-effect mobility can be provided. Furthermore, a transistor with a large on-current can be provided.

[0358] This embodiment can be appropriately combined with other embodiments and examples. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, the configuration examples can be appropriately combined.

[0359] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0360] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0361] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0362] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 20A shows silicon (Si) and indium oxide (InO Ｘ Figure 20B is a schematic diagram of the carrier concentration dependence of hole mobility with respect to IGZO.

[0363] First, as indicated by the arrows in Figure 20B, IGZO tends to show higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 20A, indium oxide tends to show higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 2). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 20A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 20A.

[0364] In Figure 20A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0365] Furthermore, in indium oxide, the region where the carrier concentration is in the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0366] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0367] In the case of indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides are conductive or semiconducting. As for the supply method of elements that increase the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. In this specification, unless otherwise specified, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions by mass separation is called ion implantation, and a method of supplying ions without mass separation is called ion doping.

[0368] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require the formation of strain in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 20A within the indium oxide film, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0369] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0370] In addition, the i-type nature of a semiconductor means that the Fermi level (Ef) and the intrinsic Fermi level (Ei) are the same (Ef = Ei). As shown in Figure 20B, in IGZO, the lower the carrier concentration, the lower the hole mobility. Therefore, when Ef = Ei is reached, there are no carriers left (in other words, the material has properties similar to an insulator), and it may cease to function as a transistor. On the other hand, in indium oxide, as shown in Figure 20A, the lower the carrier concentration, the higher the hole mobility, and when Ef = Ei is reached, the hole mobility is maximized. That is, transistors containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Furthermore, because transistors containing indium oxide have a low carrier concentration, they tend to be normally off. Therefore, transistors containing indium oxide can be normally off and achieve high field-effect mobility.

[0371] Normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated using the transistor's threshold voltage (Vth) or shift value (Vsh). Unless otherwise specified, Vth will be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the transistor's Id-Vg characteristic, where Vth is 1nA (1 × 10⁻¹⁰). −９ Let Vg be the gate voltage (Vg) when A) is true. Also, Vsh is defined as the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with line A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0372] Furthermore, in transistors containing indium oxide, the film configuration in contact with the indium oxide film is crucial for making the semiconductor i-type, that is, for achieving Ef = Ei. For example, in transistors containing indium oxide, a film configuration can be obtained in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in contact with the indium oxide film. By using this film configuration, it is possible to create a semiconductor device that satisfies Ef = Ei and is highly reliable.

[0373] Furthermore, in the above film configuration, oxygen-containing films such as silicon oxide-nitride films, silicon oxide nitride films, aluminum oxide films, and gallium oxide films can be used instead of the silicon oxide film. Also, in the above film configuration, silicon oxide nitride films, silicon oxide nitride films, etc. can be used instead of the silicon nitride film. In addition, the hafnium oxide film located on the indium oxide side of the silicon nitride film functions as a hydrogen gettering site.

[0374] Furthermore, the above film configuration can also be viewed as a layered structure consisting of a film that can supply oxygen to the indium oxide film (e.g., a silicon oxide film), a film that can getter hydrogen (e.g., a hafnium oxide film), and a film that suppresses the intrusion of oxygen and hydrogen (e.g., a silicon nitride film). With this configuration, oxygen deficiencies in the indium oxide film are compensated for by oxygen in the silicon oxide film. Also, hydrogen in the indium oxide film is captured by the hafnium oxide film through heat treatment or other means. In addition, the silicon nitride film provides a film configuration that minimizes the intrusion of oxygen and hydrogen from the outside. In other words, by using the above film configuration, the indium oxide film can be made closer to type i. Therefore, transistors having the above-described indium oxide film have high field-effect mobility and high reliability.

[0375] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (that is, has crystal grains). Examples of the film having crystal grains include a single crystal film, a polycrystalline film, and an amorphous film containing crystal grains (also referred to as a microcrystalline film). In particular, the indium oxide film is preferably a polycrystalline film, more preferably a single crystal film. A single crystal film does not have grain boundaries (also referred to as grain boundaries). Impurities that impede carrier flow (typically, insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. By using a single crystal film, carrier scattering at grain boundaries can be suppressed, and a transistor exhibiting high field effect mobility can be realized. In addition, the present technology provides an excellent effect such that variation in transistor characteristics caused by the grain boundaries can be suppressed.

[0376] Further, a polycrystalline film is preferable because it can reduce carrier scattering and exhibits high field effect mobility as compared with a microcrystalline film or an amorphous film. When a polycrystalline film is used, it is preferable to use a film in which the size of crystal grains is as large as possible and the number of grain boundaries is small. Note that in a transistor to which a polycrystalline indium oxide film is applied, when the channel formation region has no grain boundary or no grain boundary is observed, the channel formation region is located in a single crystal region included in the polycrystalline film, and thus the transistor can be regarded as a transistor to which single crystal indium oxide is applied.

[0377] Note that the crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD: X-Ray Diffraction), transmission electron microscope (TEM: Transmission Electron Microscope), or electron diffraction (ED: Electron Diffraction). Alternatively, analysis may be performed by combining a plurality of these methods.

[0378] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0379] The channel formation region refers to the area within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0380] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit crystal growth in the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the impurities mentioned above.

[0381] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (specifically, a bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0382] Furthermore, the indium oxide film described herein has a high film density. The theoretical value of the film density of the indium oxide film is 7.18 g / cm³. ３ In this specification, the range of film density for indium oxide films is 6.70 g / cm³. ３ 7.18g / cm or more ３ The following, preferably 6.90 g / cm³ ３ 7.18g / cm or more ３ The following, and more preferably 7.00 g / cm³ ３ 7.18g / cm or more ３ The following applies:

[0383] Furthermore, film density can be evaluated using methods such as Rutherford backscattering (RBS) or X-ray reflectivity (XRR). Differences in film density can sometimes be evaluated using transmission electron microscopy (TEM) images of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image.

[0384] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0385] One of the characteristics of indium oxide films is that they have higher oxygen permeability (diffusivity) compared to IGZO films. As shown in Figure 20C, indium oxide films (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and oxygen molecules (O) ２ It is released as water molecules (H) by reacting with hydrogen contained in the membrane. ２ It may also be released as O. Furthermore, oxygen deficiencies (V) can form in the membrane. ＯIf oxygen atoms are present, diffusing oxygen atoms will fill the oxygen deficiency. Indium oxide films allow oxygen to diffuse easily, so they can be said to fill oxygen deficiencies more easily than IGZO films.

[0386] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0387] Furthermore, as shown in Figure 20C, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and forms hydrogen molecules (H ２ It is released as ) or by reacting with oxygen contained in the film, and released as water molecules. The above-mentioned oxygen and hydrogen diffuse through the indium oxide film by heat treatment. The temperature of the heat treatment is 200°C to 700°C, preferably 350°C to 650°C, and more preferably 400°C to 500°C.

[0388] Transistors using indium oxide films are storage-type transistors that use electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, in a transistor, the on-current or field-effect mobility of the transistor can be increased.

[0389] Table 1 shows single crystal indium oxide (here, In ２ O ３The effective masses of indium oxide and single-crystal silicon (Si) are shown below. As shown in Table 1, indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also called f-characteristics) can be realized. In addition, because the effective hole mass is large, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) in an environment of 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) Less than or equal to 1aA (1 × 10) in a room temperature (25°C) environment. −１８ A) Less than or equal to, or 1zA (1 × 10⁻¹⁰ −２１ A) The following is possible. Also, as shown in Table 1, indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, so it may be possible to realize a transistor with higher field-effect mobility and lower off-current than a Si transistor.

[0390]

[0391] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This improves the crystallinity of the indium oxide film. A substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0392] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２It is calculated as ) × 100. Here, L1 is the length of the unit cell vector of the crystal that the formed film has or the lattice constant, L ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0393] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0394] Here, the indium oxide crystal has a cubic structure (specifically, the bixbite type). For example, the yttria-stabilized zirconia (YSZ) crystal can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0395] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified form structures. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal with a crystalline structure is IGZO. Indium oxide single crystal films can be formed not only on YSZ substrates but also on insulating films. On the other hand, it is difficult to form silicon single crystal films on insulating films. Silicon crystals have a diamond structure. Thus, in terms of single crystals, indium oxide and silicon have similar properties. However, when comparing indium oxide and silicon from the perspective of whether single crystals can be formed on insulating films, they have different properties.

[0396] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0397] (Embodiment 3) This embodiment describes an example of the configuration of a display device to which a transistor according to one aspect of the present invention can be applied.

[0398] Since the transistor according to one aspect of the present invention can be made extremely small, a display device to which the transistor according to one aspect of the present invention is applied can be an extremely high-resolution display device. For example, the display device according to one aspect of the present invention can be used in the display section of information terminals (wearable devices) such as wristwatches and bracelets, and in the display section of head-mounted displays (HMDs) such as VR devices such as head-mounted displays and AR devices such as glasses.

[0399] [Display Module] Figure 21A shows a perspective view of the display module 580. The display module 580 includes a display device 500A and an FPC 590.

[0400] The display module 580 has substrates 591 and 592. The display module 580 has a display unit 581. The display unit 581 is an area for displaying an image.

[0401] Figure 21B shows a schematic perspective view illustrating the configuration of the substrate 591. A circuit section 582, a pixel circuit section 583 on the circuit section 582, and a pixel section 584 on the pixel circuit section 583 are stacked on the substrate 591. A terminal section 585 for connecting to the FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel section 584. The terminal section 585 and the circuit section 582 are electrically connected by a wiring section 586, which is composed of multiple wires.

[0402] The pixel section 584 has a plurality of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of Figure 21B. The pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0403] The pixel circuit section 583 has a plurality of periodically arranged pixel circuits 583a. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices that one pixel 584a has. A single pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device. For example, each pixel circuit 583a may have at least one selection transistor, one current control transistor (drive transistor), and a capacitive element. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix type display panel.

[0404] The circuit section 582 has circuits for driving each pixel circuit 583a of the pixel circuit section 583. For example, it is preferable to have one or both of a gate line drive circuit and a source line drive circuit. In addition, it may have at least one of the following: an arithmetic circuit, a memory circuit, and a power supply circuit. Furthermore, transistors provided in the circuit section 582 may constitute a part of the pixel circuit 583a. That is, the pixel circuit 583a may be composed of transistors in the pixel circuit section 583 and transistors in the circuit section 582.

[0405] The FPC 590 functions as wiring for supplying video signals and power potential, etc., to the circuit section 582 from an external source. An IC may also be mounted on the FPC 590.

[0406] The display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are superimposed on the lower side of the pixel section 584, thereby making the aperture ratio (effective display area ratio) of the display section 581 extremely high. For example, the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95%, and more preferably 60% or more and 95%. Furthermore, it is possible to arrange the pixels 584a at an extremely high density, making the resolution of the display section 581 extremely high. For example, it is preferable that the pixels 584a in the display section 581 are arranged at a density of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, with a resolution of 20000 ppi or less, or 30000 ppi or less.

[0407] Because such a display module 580 is extremely high-resolution, it is suitable for VR devices such as head-mounted displays, or AR devices such as glasses. For example, even in a configuration where the display part of the display module 580 is viewed through lenses, the display module 580 has an extremely high-resolution display part 581, so even when the display part is magnified with lenses, pixels are not visible, and a highly immersive display can be provided. Furthermore, the display module 580 is not limited to this, and is suitable for electronic devices with relatively small display parts. For example, it is suitable for the display part of wearable electronic devices such as wristwatches.

[0408] [Display device 500A] The display device 500A shown in Figure 22 has a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitive element 140, a transistor 310, and a transistor 520. For example, the aforementioned circuit unit 582 has a transistor 310, and the aforementioned pixel circuit unit 583 has a transistor 520.

[0409] Substrate 311 corresponds to substrate 591 in Figure 21A.

[0410] The transistor 310 is a transistor having a channel-forming region in the substrate 311. The substrate 311 can be a semiconductor substrate such as a single-crystal silicon substrate. The transistor 310 comprises a portion of the substrate 311, a conductor 316, a low-resistance region 314, an insulator 315, and an insulator 317. The conductor 316 functions as a gate electrode. The insulator 315 is located between the substrate 311 and the conductor 316 and functions as a gate insulating layer. The low-resistance region 314 is a region of the substrate 311 doped with impurities and functions as either a source or a drain. The insulator 317 is provided covering the side surface of the conductor 316.

[0411] Furthermore, an element isolation layer 318 is provided between two adjacent transistors 310 so as to be embedded in the substrate 311.

[0412] Transistor 520 is a transistor in which an oxide semiconductor is applied to the semiconductor layer where the channel is formed. Transistor 520 has a semiconductor layer 230, an oxide layer 232, a conductive layer 205, an insulating layer 222, an insulating layer 224, a conductive layer 242a, a conductive layer 242b, an insulating layer 250, and a conductive layer 260, etc. Interlayer films are formed on transistor 310 in the order of insulating layer 212, insulating layer 216, insulating layer 222, insulating layer 280, insulating layer 282, insulating layer 283, and insulating layer 285. Conductive layer 240 and insulating layer 241 are formed in openings formed in insulating layer 280, insulating layer 282, insulating layer 283, and insulating layer 285.

[0413] The transistor 520 can be the transistor 200 exemplified in Embodiment 1. This allows a transistor with high field-effect mobility to be used as transistor 520.

[0414] A capacitive element 140 is provided on an insulating layer 285. The capacitive element 140 has a conductive layer 141, a conductive layer 145, and an insulating layer 143 located between them. The conductive layer 141 functions as one electrode of the capacitive element 140, the conductive layer 145 functions as the other electrode of the capacitive element 140, and the insulating layer 143 functions as the dielectric of the capacitive element 140.

[0415] The conductive layer 141 is provided on the insulating layer 285 and embedded in the insulating layer 154. The conductive layer 141 is electrically connected to the conductive layer 242a of the transistor 520 by the conductive layer 240. The insulating layer 143 is provided covering the conductive layer 141. The conductive layer 145 is provided in the region that overlaps with the conductive layer 141 via the insulating layer 143.

[0416] An insulating layer 155a is provided to cover the capacitive element 140, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.

[0417] A plug 156 is embedded in insulating layers 155a, 155b, and 155c. The upper surface of the plug 156 is at the same height as the upper surface of insulating layer 155c. Various conductive materials can be used for the plug.

[0418] Insulating layers 155a, 155b, and 155c can each preferably be made of inorganic insulating films. For example, it is preferable to use silicon oxide films for insulating layers 155a and 155c, and silicon nitride films for insulating layer 155b. This allows insulating layer 155b to function as an etching protective film. In this embodiment, an example is shown in which a part of insulating layer 155c is etched and a recess is formed, but the insulating layer 155c does not necessarily have to have a recess.

[0419] A light-emitting element 110R, a light-emitting element 110G, and a light-emitting element 110B are provided on the insulating layer 155c.

[0420] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting elements 110R, 110G, and 110B. Note that the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are sometimes collectively referred to as the pixel electrode 111.

[0421] The organic layer 112R of the light-emitting element 110R contains at least a luminescent organic compound that emits red light. The organic layer 112G of the light-emitting element 110G contains at least a luminescent organic compound that emits green light. The organic layer 112B of the light-emitting element 110B contains at least a luminescent organic compound that emits blue light. The organic layers 112R, 112G, and 112B can each also be called EL layers and each contains at least a luminescent organic compound (luminescent layer).

[0422] The display device 500A has different light-emitting devices for each light-emitting color, resulting in minimal change in chromaticity between low-brightness and high-brightness illumination. Furthermore, because the organic layers 112R, 112G, and 112B are separated, crosstalk between adjacent sub-pixels can be suppressed even in high-resolution display panels. Therefore, a display panel with high resolution and high display quality can be realized.

[0423] An insulating layer 125, a resin layer 126, and a layer 128 are provided in the region between adjacent light-emitting elements.

[0424] Each of the pixel electrodes 111R, 111G, and 111B is electrically connected to the conductive layer 242a of the transistor 520 via the plug 156, the conductive layer 141, and the conductive layer 240.

[0425] Furthermore, a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B. The substrate 170 is bonded to the protective layer 121 by an adhesive layer 171.

[0426] There is no insulating layer covering the upper edge of the pixel electrode 111 between two adjacent pixel electrodes 111. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made.

[0427] This embodiment can be appropriately combined with other embodiments and examples.

[0428] (Embodiment 4) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 23A to 25G.

[0429] The electronic device of this embodiment has a display panel (display device) to which a transistor according to one aspect of the present invention is applied in the display unit. The display device according to one aspect of the present invention can be easily made high-definition and high-resolution, and can achieve high display quality. Therefore, it can be used in the display unit of various electronic devices.

[0430] Examples of electronic devices include television sets, desktop or laptop computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0431] In particular, a display panel according to one embodiment of the present invention is suitable for electronic devices having a relatively small display area because it can increase resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0432] A display panel according to one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (resolution) of the display panel according to one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display panel having either high resolution or high detail, or both, it becomes possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display panel in one embodiment of the present invention. For example, the display panel can support various aspect ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0433] The electronic device of this embodiment may have sensors (including those with the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0434] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0435] Figures 23A to 23F illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device that has the function to display at least one of the following content types, such as AR, VR, SR, and MR, it is possible to enhance the user's sense of immersion.

[0436] The electronic device 700A shown in Figure 23A includes a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0437] A display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created. Furthermore, a semiconductor device according to one embodiment of the present invention can be applied to the control unit (not shown). This makes it possible to reduce the power consumption of the electronic device.

[0438] The electronic device 700A can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, the electronic device 700A is an electronic device capable of AR display.

[0439] The electronic device 700A may be equipped with a camera capable of capturing images of the area in front of it, as an imaging unit. Furthermore, the electronic device 700A can also be equipped with an acceleration sensor such as a gyro sensor to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0440] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0441] Furthermore, the electronic device 700A is equipped with a battery that can be charged wirelessly, wired, or both.

[0442] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0443] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0444] The electronic device 800A shown in Figure 23B and the electronic device 800B shown in Figure 23C each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0445] A display device according to one aspect of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be made possible. This allows the user to experience a high level of immersion. Furthermore, a semiconductor device according to one aspect of the present invention can be applied to the control unit 824. This makes it possible to reduce the power consumption of the electronic device.

[0446] The display unit 820 is located inside the housing 821 in a position visible through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can be achieved.

[0447] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0448] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0449] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 23B and other figures as resembling the temples (or arms) of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0450] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0451] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0452] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This allows users to enjoy video and audio simply by wearing the electronic device 800A, without needing separate audio equipment such as headphones, earphones, or speakers.

[0453] Electronic devices 800A and 800B may each have input terminals. Cables can be connected to the input terminals to supply video signals from video output devices, etc., and power for charging batteries provided in the electronic devices.

[0454] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 23A has a function for transmitting information to the earphone 750 through its wireless communication function.

[0455] Furthermore, the electronic device may have an earphone section. The electronic device 800B shown in Figure 23C has an earphone section 827. For example, the earphone section 827 and the control unit 824 can be connected to each other by wire. Part of the wiring connecting the earphone section 827 and the control unit 824 may be located inside the housing 821 or the mounting section 823. Also, the earphone section 827 and the mounting section 823 may have magnets. This allows the earphone section 827 to be fixed to the mounting section 823 by magnetic force, which is preferable as it makes storage easier.

[0456] Furthermore, the electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have an audio input terminal and / or an audio input mechanism. For example, a sound-collecting device such as a microphone can be used as the audio input mechanism. By having an audio input mechanism, the electronic device may be given the function of a so-called headset.

[0457] Figures 23D and 23E show perspective views of a goggle-type electronic device 850A for VR. Figures 23D and 23E show an example in which a pair of curved display devices 840 (display device 840_R and display device 840_L) are located inside a housing 845. The electronic device 850A also includes a motion detection unit 841, a gaze detection unit 842, a calculation unit 843, a communication unit 844, lenses 848, operation buttons 851, a wearable device 854, a sensor 855, a dial 856, and the like.

[0458] Having two display devices 840 allows the user to view one display device per eye. This enables the display of high-resolution images, even when performing 3D displays using parallax. Furthermore, the display device 840 is curved in an arc shape with the user's eye as the approximate center. This ensures that the distance from the user's eye to the display surface of the display device 840 remains constant, allowing the user to see more natural images. Additionally, even if the display device 840 exhibits so-called viewing angle dependence, where the brightness or chromaticity of the light changes depending on the viewing angle, the configuration allows the user's eye to be positioned in the direction of the normal to the display surface of the display device 840. Therefore, the effect can be practically ignored, especially in the horizontal direction, resulting in the display of more realistic images.

[0459] As shown in Figure 23E, the lens 848 is positioned between the display device 840 and the user's eye. Figure 23E shows an example where a dial 856 is used to change the position of the lens for diopter adjustment. However, if the electronic device 850A has an autofocus function, the dial 856 for diopter adjustment may not be necessary.

[0460] Figure 23F shows a goggle-type electronic device 850B having a single display device 840. This configuration allows for a reduction in the number of components.

[0461] The display device 840 can display two images side by side in two regions, one for the right eye and one for the left eye. This allows for the display of stereoscopic images using binocular parallax. The display device 840 may display two different images using parallax, or it may display two identical images side by side without using parallax.

[0462] Alternatively, a single image visible to both eyes may be displayed across the entire surface of the display device 840. This makes it possible to display a panoramic image across both ends of the field of view, thereby enhancing the sense of realism.

[0463] A display device according to one embodiment of the present invention can be applied to the display device 840. Because the display device according to one embodiment of the present invention has extremely high resolution, even when magnified using the lens 848, the user cannot see the pixels, and a more realistic image can be displayed.

[0464] The electronic device 6500 shown in Figure 24A is a portable information terminal that can be used as a smartphone.

[0465] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 6502, the control device 6509, etc. Using a semiconductor device according to one aspect of the present invention as the control device 6509 is preferable because it can reduce power consumption.

[0466] A display panel according to one embodiment of the present invention can be applied to the display unit 6502.

[0467] Figure 24B is a schematic cross-sectional view of the housing 6501 including the end on the microphone 6506 side.

[0468] A light-transmitting protective member 6510 is provided on the display side of the housing 6501, and the display panel 6511, optical member 6512, touch sensor panel 6513, printed circuit board 6517, battery 6518, etc. are arranged in the space enclosed by the housing 6501 and the protective member 6510.

[0469] The protective member 6510 is fixed to the display panel 6511, the optical member 6512, and the touch sensor panel 6513 by an adhesive layer (not shown).

[0470] In the area outside the display unit 6502, a portion of the display panel 6511 is folded back, and the FPC 6515 is connected to this folded portion. IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to terminals provided on the printed circuit board 6517.

[0471] A display device according to one embodiment of the present invention can be applied to the display panel 6511. As a result, an extremely lightweight electronic device can be realized. Furthermore, because the display panel 6511 is extremely thin, a large-capacity battery 6518 can be installed while keeping the thickness of the electronic device low. In addition, by folding back a part of the display panel 6511 and placing the connection part with the FPC 6515 on the back of the pixel section, an electronic device with a narrow bezel can be realized.

[0472] Figure 24C shows an example of a television system. The television system 7100 has a display unit 7000 incorporated into a housing 7101. Here, the housing 7101 is shown to be supported by a stand 7103.

[0473] The television device 7100 shown in Figure 24C can be operated using the operation switches on the housing 7101 and a separate remote control unit 7111. Alternatively, the display unit 7000 may be equipped with a touch sensor, and the television device 7100 can be operated by touching the display unit 7000 with a finger or the like. The remote control unit 7111 may have a display unit that displays information output from the remote control unit 7111. Channels and volume can be controlled and the image displayed on the display unit 7000 can be controlled using the operation keys or touch panel on the remote control unit 7111.

[0474] The television system 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0475] Figure 24D shows an example of a notebook computer. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is incorporated into the casing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device according to one aspect of the present invention can be applied to the display unit 7000, the control device 7216, etc. Using a semiconductor device according to one aspect of the present invention as the control device 7216 is preferable because it can reduce power consumption.

[0476] Figures 24E and 24F show examples of digital signage.

[0477] The digital signage 7300 shown in Figure 24E includes a housing 7301, a display unit 7000, and a speaker 7303, etc. Furthermore, it may include LED lamps, operation keys (including a power switch or operation switch), connection terminals, various sensors, a microphone, etc.

[0478] Figure 24F shows a digital signage 7400 mounted on a cylindrical column 7401. The digital signage 7400 has a display unit 7000 that is provided along the curved surface of the column 7401.

[0479] The larger the display area 7000, the more information can be provided at once. Furthermore, a larger display area 7000 is more eye-catching, which can, for example, enhance the effectiveness of advertising.

[0480] Applying a touch panel to the display unit 7000 is preferable because it not only allows images or videos to be displayed on the display unit 7000, but also enables intuitive operation by the user. Furthermore, when used for purposes such as providing route information or traffic information, intuitive operation can enhance usability.

[0481] Furthermore, as shown in Figures 24E and 24F, it is preferable that the digital signage 7300 or digital signage 7400 can be linked wirelessly with an information terminal 7311 or information terminal 7411 such as a smartphone owned by the user. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or information terminal 7411. Also, the display on the display unit 7000 can be switched by operating the information terminal 7311 or information terminal 7411.

[0482] Furthermore, the digital signage 7300 or digital signage 7400 can be used to run games using the screen of the information terminal 7311 or information terminal 7411 as the control device (controller). This allows an unspecified number of users to participate in and enjoy the game simultaneously.

[0483] In Figures 24C to 24F, a display panel according to one embodiment of the present invention can be applied to the display unit 7000.

[0484] The electronic device shown in Figures 25A to 25G includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), connection terminals 9006, a sensor 9007 (including a function to detect, detect, or measure force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0485] The electronic devices shown in Figures 25A to 25G have various functions. For example, they may have functions to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date or time, a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. However, the functions of electronic devices are not limited to these and can have various functions. Electronic devices may have multiple display units. Furthermore, electronic devices may be equipped with a camera, etc., and have functions to capture still images or videos and save them to a recording medium (external or built into the camera), a function to display the captured images on a display unit, etc.

[0486] Details of the electronic equipment shown in Figures 25A to 25G will be explained below.

[0487] Figure 25A is a perspective view showing a personal digital information terminal (PDI) 9101. The PDI 9101 can be used, for example, as a smartphone. The PDI 9101 may also be equipped with a speaker 9003, connection terminals 9006, sensors 9007, etc. The PDI 9101 can also display text and image information on multiple surfaces. Figure 25A shows an example where three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on other surfaces of the display unit 9001. Examples of information 9051 include notifications of incoming emails, SNS messages, and phone calls, the subject of an email or SNS message, the sender's name, date and time, battery level, and signal strength. Alternatively, icons 9050 or the like may be displayed in the location where the information 9051 is displayed.

[0488] Figure 25B is a perspective view showing the personal digital assistant (PDA) 9102. The PDA 9102 has the function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, a user can check information 9053, which is displayed in a position that can be observed from above the PDA 9102, while the PDA 9102 is stored in the breast pocket of their clothing. The user can check the display without taking the PDA 9102 out of their pocket and decide, for example, whether or not to answer a call.

[0489] Figure 25C is a perspective view showing the tablet terminal 9103. The tablet terminal 9103 can run various applications, such as mobile phone calls, email, document viewing and creation, music playback, internet communication, and computer games. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the housing 9000. The left side of the housing 9000 has operation keys 9005 as buttons for operation, and the bottom has connection terminals 9006.

[0490] Figure 25D is a perspective view showing a wristwatch-type personal information terminal 9200. The personal information terminal 9200 can be used, for example, as a smartwatch. The display unit 9001 has a curved display surface, allowing it to display information along the curved surface. The personal information terminal 9200 can also make hands-free calls by communicating with, for example, a wireless communication headset. Furthermore, the personal information terminal 9200 can transmit data to other information terminals and be charged via a connection terminal 9006. Charging may be performed by wireless power supply.

[0491] Figures 25E to 25G are perspective views showing a foldable portable information terminal 9201. Figure 25E shows the portable information terminal 9201 in an unfolded state, Figure 25G shows it in a folded state, and Figure 25F shows a perspective view of the state in between, transitioning from one of Figures 25E or 25G to the other. The portable information terminal 9201 offers excellent portability in its folded state and excellent readability of the display due to its seamless, wide display area in its unfolded state. The display unit 9001 of the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm to 150 mm.

[0492] This embodiment can be appropriately combined with other embodiments and examples.

[0493] (Embodiment 5) In this embodiment, a semiconductor device 900 according to one aspect of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0494] Figure 26 shows a block diagram of an example configuration of a semiconductor device 900. The semiconductor device 900 shown in Figure 26 includes a drive circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Figure 26 shows an example in which the memory array 920 has multiple memory cells 950 arranged in a matrix.

[0495] A high-field-effect-mobility transistor, as exemplified in Embodiment 1, can be applied to the memory cell 950. For example, the memory cell 950 can have a DRAM-type circuit configuration with one transistor and one capacitance element. Alternatively, the memory cell 950 can have a gain-cell-type circuit configuration with two transistors and one capacitance element. Furthermore, the memory cell 950 can have an SRAM (Static Random Access Memory)-type circuit configuration. By using the above-mentioned transistors, the operating speed of the memory device can be improved. In addition, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacity per unit area of ​​the memory device can be increased.

[0496] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0497] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0498] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data signal, and signal RDA is the read data signal. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 912.

[0499] The control circuit 912 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on signals CE, GW, and BW to determine the operating mode of the semiconductor device 900 (e.g., write operation, read operation). Alternatively, the control circuit 912 generates control signals for the peripheral circuit 911 so that this operating mode is executed.

[0500] The voltage generation circuit 928 has the function of generating voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 928. For example, when a high-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates voltage.

[0501] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0502] The row decoder 941 and column decoder 942 have the function of decoding the ADDR signal. The row decoder 941 is a circuit for specifying the row to access, and the column decoder 942 is a circuit for specifying the column to access. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cell 950, reading data from the memory cell 950, and holding the read data.

[0503] The input circuit 925 has the function of holding the signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is the data (Din) to be written to the memory cell 950. The data (Dout) read by the column driver 924 from the memory cell 950 is output to the output circuit 926. The output circuit 926 has the function of holding Dout. The output circuit 926 also has the function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is the signal RDA.

[0504] PSW931 provides V to peripheral circuit 915 ＤＤ It has the function of controlling the supply. PSW932 has the function of V to line driver 923 ＨＭ It has a function to control the supply. Here, the high power supply potential of the semiconductor device 900 is V ＤＤ Therefore, the low power supply potential is GND (ground potential). Also, V ＨＭ This is a high power supply potential used to raise the word line to a high level, V ＤＤ It is higher than that. The on / off state of PSW931 is controlled by signal PON1, and the on / off state of PSW932 is controlled by signal PON2. In Figure 26, in peripheral circuit 915, V ＤＤ The number of power domains supplied is set to one, but it can be multiple. In this case, a power switch should be provided for each power domain.

[0505] This embodiment can be appropriately combined with other embodiments and examples.

[0506] (Embodiment 6) In this embodiment, an example of an application of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 27A to 28E.

[0507] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, lower power consumption and higher performance can be achieved in electronic components, large computers, space equipment, data centers, and various electronic devices. For details of the electronic device, please refer to Embodiment 4.

[0508] [Electronic Components] Figure 27A shows a perspective view of a substrate (mounted substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in Figure 27A has a semiconductor device 981 inside a mold 984. Some details are omitted in Figure 27A to show the inside of the electronic component 980. The electronic component 980 has a land 985 on the outside of the mold 984. The land 985 is electrically connected to an electrode pad 986, and the electrode pad 986 is electrically connected to the semiconductor device 981 via a wire 987. The electronic component 980 is mounted, for example, on a printed circuit board 988. Multiple such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounted substrate 989.

[0509] Furthermore, the semiconductor device 981 has a drive circuit layer 982 and a storage layer 983. The storage layer 983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 982 and the storage layer 983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the storage layer 983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0510] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0511] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0512] Furthermore, the drive circuit layer 982 can also be configured to use an OS transistor. The OS transistor shown in the above embodiment is capable of carrying a large current. This makes it possible to operate the semiconductor device 994 at high speed.

[0513] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0514] In the above, an example of the semiconductor device 981 functioning as a memory device was shown, but the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, GPU, or FPGA (Field Programmable Gate Array). In this case, it is preferable to use an OS transistor in the semiconductor device 981. The OS transistor shown in the above embodiment is capable of supplying a large current. This makes it possible to operate the semiconductor device 981 at high speed.

[0515] Next, a perspective view of the electronic component 990 is shown in Figure 27B. The electronic component 990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 are provided on the interposer 991.

[0516] Electronic component 990 shows an example where semiconductor device 981 is used as a high-bandwidth memory (HBM). Furthermore, semiconductor device 994 can be used in integrated circuits such as CPUs, GPUs, or FPGAs.

[0517] Furthermore, it is preferable to use an OS transistor in the semiconductor device 994. The OS transistor shown in the above embodiment is capable of supplying a large current. This makes it possible to operate the semiconductor device 994 at high speed.

[0518] The package substrate 992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 991 can be, for example, a silicon interposer or a resin interposer.

[0519] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also has the function of connecting integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 991, and these through electrodes may be used to connect the integrated circuits and the package substrate 992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0520] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0521] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0522] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0523] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 981 and the semiconductor device 994.

[0524] To mount the electronic component 990 onto another substrate, electrodes 993 may be provided at the bottom of the package substrate 992. Figure 27B shows an example in which the electrodes 993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0525] The electronic component 990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0526] [Large-scale computer] Next, Figure 28A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 shown in Figure 28A has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0527] The computer 5620 can have the configuration shown in the perspective view in Figure 28B, for example. In Figure 28B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0528] The PC card 5621 shown in Figure 28C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 28C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0529] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0530] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0531] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0532] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 990 can be used as the semiconductor device 5627.

[0533] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 990 can be used as the semiconductor device 5628.

[0534] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0535] [Space Equipment] One embodiment of the present invention is suitable for space equipment.

[0536] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used in transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers to, for example, an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0537] Figure 28D shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 28D, a planet 6804 is shown as an example in outer space.

[0538] Furthermore, although not shown in Figure 28D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0539] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0540] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0541] The satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0542] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0543] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0544] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention is suitable for space equipment such as spacecraft, space capsules, and space probes.

[0545] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0546] [Data Center] One embodiment of the present invention is suitable for storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as ensuring the immutability of data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required to hold the data, which necessitates the construction of larger buildings.

[0547] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0548] Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0549] Figure 28E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 28E has multiple servers 7001sb as hosts 7001, and multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0550] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0551] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In storage systems, to solve the problem of the slow access speed of storage 7003, cache memory is usually provided within the storage to shorten the time required for data storage and retrieval.

[0552] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0553] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0554] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention can reduce carbon dioxide (CO2) emissions. ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0555] This embodiment can be appropriately combined with other embodiments and examples.

[0556] In this embodiment, an oxide semiconductor film according to one aspect of the present invention is fabricated, and the results of evaluation by Hall effect measurement are described.

[0557] Hall effect measurement is a method for measuring electrical properties such as carrier concentration and mobility by utilizing the Hall effect, which occurs when a magnetic field is applied perpendicular to the direction of the current to a material carrying an electric current, causing an electromotive force to appear perpendicular to both the current and the magnetic field. The mobility calculated using the results of Hall effect measurement is sometimes called Hall mobility. Here, resistivity was measured without applying a magnetic field, followed by Hall effect measurement using the Van der Pauw method. Electrical conductivity was then calculated from the measured resistivity.

[0558] Samples 1A and 1B were prepared as samples to be used for measuring the Hall effect.

[0559] In sample 1A, an indium oxide film with a thickness of 10 nm was deposited on a quartz substrate using the sputtering method. ２ O ３ A target was used. The deposition gases used were 0.5 sccm of oxygen gas, 49 sccm of argon gas, and 2.6 sccm of hydrogen gas. Other deposition conditions for the indium oxide film were: deposition pressure of 0.6 Pa, deposition power of 200 W using a DC power supply, and substrate temperature at room temperature.

[0560] In sample 1B, an indium oxide film with a thickness of 10 nm was deposited on a quartz substrate using the thermal ALD method. Triethylindium (TEI) was used as a precursor for the indium oxide film deposition. Ozone gas was used as the oxidizing agent, and the introduction time of the oxidizing agent was set to 9 seconds per cycle. The substrate temperature during film deposition was set to 200°C.

[0561] For both Sample 1A and Sample 1B, after the formation of the indium oxide film, a heat treatment was performed at 1000°C for 1 minute with an oxygen gas to nitrogen gas flow rate ratio of 4:1. A GRTA apparatus was used for the heat treatment.

[0562] Next, a titanium film with a thickness of 200 nm was formed on both sample 1A and sample 1B as an electrode for measuring the Hall effect.

[0563] Based on the above, Sample 1A and Sample 1B were prepared.

[0564] Hall effect measurements were performed on samples 1A and 1B. A ResiTest 8300 manufactured by Toyo Technica Co., Ltd. was used for the Hall effect measurements. Measurements were taken at nine temperature levels: 40K, 50K, 60K, 80K, 100K, 140K, 180K, 220K, 260K, and 300K.

[0565] The results of Hall effect measurements for sample 1A and sample 1B are shown in Figures 29A to 29C. In Figure 29A, the vertical axis is the carrier concentration [cm³]. −３ In Figure 29B, the vertical axis is plotted as electrical conductivity [S / cm], the first horizontal axis (lower horizontal axis) is plotted as temperature T [K], and the second horizontal axis (upper horizontal axis) is plotted as temperature T [°C]. In Figure 29C, the vertical axis is plotted as Hall mobility [cm ２ The formula is [V·s], with temperature T [K] plotted on the first horizontal axis (lower horizontal axis) and temperature T [°C] plotted on the second horizontal axis (upper horizontal axis). The square plots in Figures 29A to 29C represent the results for sample 1A, and the circular plots represent the results for sample 1B.

[0566] Figure 29A confirms that the carrier concentration in both sample 1A and sample 1B is temperature-independent. In other words, it was confirmed that the indium oxide film was in a carrier-degenerate state in both sample 1A and sample 1B. Furthermore, the carrier concentrations in sample 1A and sample 1B were almost the same. Specifically, the carrier concentration in sample 1A was 2.6 × 10⁻⁶. １８ cm −３ Therefore, the carrier concentration of sample 1B is 3.9 × 10⁻⁶. １８ cm −３ The mobility of an oxide semiconductor film changes depending on the carrier concentration, so the mobilities of sample 1A and sample 1B, which have approximately the same carrier concentration, can be compared and evaluated.

[0567] Figure 29B confirms that the electrical conductivity of sample 1B is greater than that of sample 1A. Figure 29C confirms that the Hall mobility of sample 1B is greater than that of sample 1A. Therefore, by using an indium oxide film deposited by the ALD method as the semiconductor layer of a transistor, it is possible to fabricate a transistor with a high on-current.

[0568] As mentioned above, in both sample 1A and sample 1B, the indium oxide film is in a carrier-degenerate state. From Figure 29C, the Hall mobility is temperature-dependent in both sample 1A and sample 1B. Therefore, it can be seen that in both sample 1A and sample 1B, the carriers (electrons) must overcome the potential barrier for conduction. Accordingly, the potential barrier values ​​for sample 1A and sample 1B were calculated. The potential barrier values ​​were calculated using formula (1) explained in Embodiment 1.

[0569] In Figure 29C, the vertical axis is the natural logarithm of Hall mobility, and the horizontal axis is the reciprocal of temperature T (1000 / T) [1 / K]. The results are shown in Figure 30. Figure 30 shows Hall mobility as an Arrhenius plot. In Figure 30, the approximate lines for the plots of sample 1A and sample 1B are shown as solid lines. The potential barrier is calculated from the slope of this approximate line, and the eigenmobility is calculated from the y-intercept of this approximate line (the intercept between the approximate line and the vertical axis). In Figure 30, the square plots are the results for sample 1A, and the circular plots are the results for sample 1B. Figure 30 also shows the formula for the above approximate line. In this formula, x is the reciprocal of temperature T (1000 / T), and y is Hall mobility.

[0570] The calculated potential barrier for sample 1A was 25.6 meV, and the potential barrier for sample 1B was 5.5 meV. Furthermore, the intrinsic mobility of sample 1A was 39.4 cm⁻¹. ２ The intrinsic mobility of sample 1B is 80.2 cm² / (V·s). ２The value was / (V・s). From the above, it was found that indium oxide films deposited by the ALD method have a lower potential barrier and higher intrinsic mobility compared to indium oxide films deposited by the sputtering method. Therefore, by using indium oxide films deposited by the ALD method as the semiconductor layer of a transistor, it is possible to fabricate transistors with high on-current.

[0571] The configurations, methods, etc., shown in this embodiment can be implemented in appropriate combination with other embodiments and examples described herein, at least in part.

[0572] In this embodiment, samples having the transistor 200 shown in Figures 4A to 4D were fabricated and their electrical characteristics were evaluated. As samples for this embodiment, sample 2A was fabricated with a two-layer semiconductor layer 230 as shown in Figure 2A, and sample 2B was fabricated with a three-layer semiconductor layer 230 as shown in Figure 3A. The configurations of samples 2A to 2B are the same except for the configuration of the semiconductor layer 230. For the configurations of the samples for this embodiment, refer to the descriptions in Figures 4A to 4D, Figure 2A, and Figure 3A.

[0573] A silicon nitride film with a thickness of 60 nm, deposited by sputtering, was used as the insulating layer 212. An aluminum oxide film with a thickness of 40 nm, deposited by sputtering, was used as the insulating layer 214. A silicon oxide film with a thickness of 40 nm, deposited by sputtering, was used as the insulating layer 216.

[0574] The conductive layer 205 used a laminated film consisting of a titanium nitride film deposited by the ALD method and a tungsten film deposited by the CVD method.

[0575] A silicon nitride film with a thickness of 5 nm, deposited by the PEALD method, was used as the insulating layer 221. A hafnium oxide film with a thickness of 30 nm, deposited by the thermal ALD method, was used as the insulating layer 222. A silicon oxide film with a thickness of 20 nm, deposited by the sputtering method, was used as the insulating layer 224.

[0576] As the oxide layer 232, an In-Ga-Zn oxide with a thickness of 10 nm, deposited by sputtering, was used. For the deposition of the oxide layer 232, an oxide target with an In:Ga:Zn ratio of 1:3:2 [atomic ratio] was used. 42 sccm of oxygen gas and 167 sccm of argon gas were used as the deposition gases. Other deposition conditions included a deposition pressure of 1.0 Pa, a deposition power of 1000 W using an RF power supply, and a substrate temperature of 250°C.

[0577] In sample 2A, the semiconductor layer 230 had a two-layer structure consisting of semiconductor layer 230a and semiconductor layer 230b, while in sample 2B, the semiconductor layer 230 had a three-layer structure consisting of semiconductor layers 230a through 230c. The film deposition conditions for semiconductor layer 230a and semiconductor layer 230b were the same for both samples 2A and 2B, except for the difference in their respective film thicknesses.

[0578] As the semiconductor layer 230a, an indium oxide film deposited by sputtering was used. For the deposition of the semiconductor film 230af, In ２ O ３ A target was used. The deposition gases used were 0.5 sccm of oxygen gas, 49 sccm of argon gas, and 2.6 sccm of hydrogen gas. Other deposition conditions included a deposition pressure of 0.6 Pa, a deposition power of 200 W using a DC power supply, and a substrate temperature of room temperature. The thickness of the semiconductor film 230af was 6 nm for sample 2A and 3 nm for sample 2B.

[0579] An indium oxide film deposited by thermal ALD was used as the semiconductor layer 230b. Triethylindium (TEI) was used as the precursor for the deposition of the semiconductor film 230bf. Ozone gas was used as the oxidizing agent, and the introduction time of the oxidizing agent in one cycle was set to 9 seconds. The substrate temperature during film deposition was set to 200°C. One cycle consisted of the introduction of the precursor, purging of the precursor, introduction of the oxidizing agent, and purging of the oxidizing agent. The film thickness of the semiconductor film 230bf was set to 4 nm for sample 2A and to 3 nm for sample 2B.

[0580] As the semiconductor layer 230c, an In-Ga oxide film with a thickness of 4 nm, deposited by thermal ALD, was used. TEI and triethylgallium (TEG) were used as precursors for the deposition of the film that would become the semiconductor layer 230c. Ozone gas was used as the oxidizing agent. The substrate temperature during film deposition was set to 200°C.

[0581] For one cycle of thermal ALD of indium oxide (referred to as the InOx cycle), TEI was introduced for 0.1 seconds, followed by a 3-second purge, followed by a 9-second introduction of the oxidizing agent, and then a 3-second purge. For one cycle of thermal ALD of gallium oxide (referred to as the GaOx cycle), TEG was introduced for 0.1 seconds, followed by a 10-second purge, followed by a 9-second introduction of the oxidizing agent, and then a 3-second purge.

[0582] In sample 2B, the above InOx cycle was performed four times, followed by the above GaOx cycle once, and this process was repeated until the desired film thickness was reached, thereby forming a film that would become the semiconductor layer 230c.

[0583] After forming the film that would ...

Claims

It comprises a metal oxide layer, a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer, A semiconductor device wherein the potential barrier value of the metal oxide layer is 0 meV or more and less than 7 meV. 　 In claim 1, The potential barrier value of the metal oxide layer is calculated using formula (1) in a semiconductor device. (However, in formula (1), μ represents Hall mobility, μ ０ represents the intrinsic mobility, E ａｃｔ (where represents the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature.) 　 In claim 2, A semiconductor device in which the potential barrier value of the metal oxide layer is calculated under the conditions that the metal oxide layer is in a carrier degenerate state and the Hall mobility of the metal oxide layer is temperature-dependent. 　 In any one of claims 1 to 3, The aforementioned metal oxide layer contains indium, and is a semiconductor device. 　 It comprises a metal oxide layer, a source electrode, a drain electrode, and a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer. The metal oxide layer has a first portion and a second portion on the first portion. A semiconductor device wherein the potential barrier value of the second portion is smaller than the potential barrier value of the first portion, and is between 0 meV and 7 meV. 　 In claim 5, A semiconductor device in which the potential barrier value of the first part and the potential barrier value of the second part are each calculated using formula (1). (However, in formula (1), μ represents Hall mobility, μ ０ represents the intrinsic mobility, E ａｃｔ (where represents the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature.) 　 In claim 6, The value of the potential barrier in the first portion is calculated under the condition that the first portion is in a carrier degenerate state and the Hall mobility of the first portion is temperature-dependent. A semiconductor device in which the value of the potential barrier of the second portion is calculated under the conditions that the second portion is in a carrier degenerate state and the Hall mobility of the second portion is temperature-dependent. 　 In any one of claims 5 to 7, The aforementioned metal oxide layer contains indium, and is a semiconductor device. 　 In claim 8, The first part comprises a first element, A semiconductor device wherein the first element is at least one of gallium or aluminum. 　 In claim 9, The concentration of the first element in the first portion is 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following: A semiconductor device in which the concentration of the first element in the second portion is lower than the concentration of the first element in the first portion. 　 It comprises a metal oxide layer, a source electrode, a drain electrode, and a gate insulating layer on the metal oxide layer, and a gate electrode on the gate insulating layer. The metal oxide layer has a first portion, a second portion on the first portion, and a third portion on the second portion. A semiconductor device wherein the potential barrier value of the second portion is smaller than the potential barrier value of the first portion and the potential barrier value of the third portion, and is between 0 meV and 7 meV. 　 In claim 11, A semiconductor device in which the potential barrier values ​​of the first part, the second part, and the third part are each calculated using formula (1). (where, in formula (1), μ represents Hall mobility, μ ０ represents intrinsic mobility, E ａｃｔ represents a potential barrier, k represents Boltzmann constant, and T represents absolute temperature.) 　 In claim 12, The value of the potential barrier in the first portion is calculated under the condition that the first portion is in a carrier degenerate state and the Hall mobility of the first portion is temperature-dependent. The value of the potential barrier in the second portion is calculated under the condition that the second portion is in a carrier degenerate state and the Hall mobility of the second portion is temperature-dependent. A semiconductor device in which the value of the potential barrier of the third portion is calculated under the conditions that the third portion is in a carrier degenerate state and the Hall mobility of the third portion is temperature-dependent. 　 In any one of claims 11 to 13, The aforementioned metal oxide layer contains indium, and is a semiconductor device. In claim 14, The first part comprises a first element, The third portion includes the second element, A semiconductor device in which each of the first and second elements is at least one of gallium or aluminum. 　 In claim 15, The concentration of the first element in the first portion is 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following: The concentration of the first element in the second portion is lower than the concentration of the first element in the first portion. The concentration of the second element in the third portion is 1 × 10⁻⁶ １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following: A semiconductor device wherein the concentration of the second element in the second portion is lower than the concentration of the second element in the third portion. 　 A first step involves forming a first metal oxide film using a sputtering method, A second step involves forming a second metal oxide film on the first metal oxide film using atomic layer deposition, A third step involves processing the first metal oxide film and the second metal oxide film to form island-shaped metal oxide layers, A fourth step involves forming a gate insulating layer on the metal oxide layer, A fifth step involves forming a gate electrode on the gate insulating layer, It has, In the first step described above, a sputtering target containing a first element, indium, and oxygen is used. The first element is at least one of gallium or aluminum. In the second step described above, an indium-containing precursor is used, A method for manufacturing a semiconductor device, wherein the potential barrier value of the metal oxide layer is 0 meV or more and less than 50 meV. 　 In claim 17, A method for manufacturing a semiconductor device, wherein the concentration of the first element in the sputtering target is 0.00001 atomic percent or more and 0.5 atomic percent or less. 　 A first step involves forming a first metal oxide film using a sputtering method, A second step of adding a first element to the first metal oxide film, A third step involves forming a second metal oxide film on the first metal oxide film using atomic layer deposition, A fourth step involves processing the first metal oxide film and the second metal oxide film to form island-shaped metal oxide layers, A fifth step involves forming a gate insulating layer on the metal oxide layer, A sixth step involves forming a gate electrode on the gate insulating layer, It has, In the first step described above, an indium oxide sputtering target is used, The first element is at least one of gallium or aluminum. In the third step described above, an indium-containing precursor is used, A method for manufacturing a semiconductor device, wherein the potential barrier value of the metal oxide layer is 0 meV or more and less than 50 meV. 　 In claim 19, A method for manufacturing a semiconductor device, wherein the second step involves using an ion implantation method or an ion doping method. 　 In claim 19, A method for manufacturing a semiconductor device, wherein the purity of the sputtering target is 5N or higher. 　 In any one of claims 17 to 21, A method for manufacturing a semiconductor device, wherein the purity of the precursor is 5N or higher. In any one of claims 17 to 21, A method for manufacturing a semiconductor device, wherein the potential barrier value of the metal oxide layer is calculated using formula (1). (However, in formula (1), μ represents Hall mobility, μ ０ represents the intrinsic mobility, E ａｃｔ (where represents the potential barrier, k represents the Boltzmann constant, and T represents the absolute temperature.) 　 In claim 23, A method for manufacturing a semiconductor device, wherein the potential barrier value of the metal oxide layer is calculated under the conditions that the metal oxide layer is in a carrier degenerate state and the Hall mobility of the metal oxide layer is temperature-dependent.

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