Method for manufacturing semiconductor element and plasma processing method

Abstract

Provided is a technique for protecting each of an upper portion and a side wall of a dummy gate with a first protective film and a second protective film during etching of a spacer in a step of forming a gate side wall spacer of a transistor. Provided is a technique comprising: a first step for forming a first protective film so as to cover a semiconductor layer formed in a line shape and forming a channel, and a spacer layer formed so as to cover a dummy gate formed in a line shape orthogonal to the semiconductor layer; a second step for, after the first step, forming a second protective film different from the first protective film so as to cover the first protective film; a third step for, after the second step, removing the second protective film formed on the side wall of the dummy gate and the second protective film formed on the side wall and the upper surface of the semiconductor layer by performing isotropic etching selectively with respect to the second protective film formed on the upper surface of the dummy gate; and a fourth step for, after the third step, removing the first protective film formed on the side wall of the semiconductor layer by anisotropic etching.

Description

Method for manufacturing semiconductor devices and plasma processing method

[0001] This disclosure relates to a method for manufacturing semiconductor devices and a plasma processing method.

[0002] The evolution of integrated circuit chip performance has been achieved through the high integration of transistors mounted on integrated circuits. This high integration of transistors has been driven for over half a century by technologies that reduce the pitch of wiring and miniaturize transistor elements. However, with the miniaturization of transistors, a current leakage known as the "short channel effect" has become apparent, and in order to overcome this, significant changes have been made in transistor structure and the materials that make up transistors in recent years. Examples include the introduction of strain into the source and drain regions of metal oxide semiconductor field effect transistors (MOSFETs), the introduction of high dielectric gate insulators and metal gates, and changes in transistor channel structure from planar type to fin type with a three-dimensional structure. Furthermore, in recent years, there have been plans to introduce gate all-around FET (GAA) structures in which the channel is a wire-like or sheet-like laminate, and the entire periphery of the channel is covered by the gate. FETs that improve gate controllability and suppress short-channel effects by increasing the region where the gate and channel overlap, such as Fin-type transistors and GAA-type FETs, are called multi-gate MOS FETs.

[0003] A metal gate replacement process is applied to the fabrication of these multi-gate MOS FETs. This metal gate replacement process is disclosed, for example, in Patent Document 1. In the case of a GAA-type FET, a linear Fin pattern composed of a laminated film of Si (silicon) / SiGe (silicon germanium) is formed on a substrate, and after forming a linear dummy gate orthogonal to the pattern, a gate spacer is deposited along the sidewall of the dummy gate. The dummy gate is composed of polycrystalline silicon, and a hard mask of an insulating film necessary for forming the line pattern is formed on the polycrystalline silicon. The gate spacer is deposited on each of the sidewall of the dummy gate and the sidewall of the Fin. Next, the gate spacer is vertically etched to remove the gate spacer deposited on the top of the Fin and the sidewall of the Fin. Then, using the gate spacer as a mask, the Fin composed of the Si / SiGe laminated film exposed in the gap region between gates by the etching of the gate spacer is vertically etched, to process the source / drain formation regions. Thereafter, a semiconductor crystal to be the source / drain is formed by growing an epitaxial layer starting from the silicon surface exposed on the sidewall of the gate spacer. After that, an oxide film is formed on the semiconductor crystal to be the source / drain to fill the space between gates, the dummy gate is removed, and the dummy gate is replaced with a metal gate having a function as a gate, thereby forming a gate composed of a metal material.

[0004] The etching of the gate spacer in the above process needs to be performed to a certain depth in order to remove the spacer material deposited on the sidewall of the Fin by vertical etching. If the etching depth exceeds the film thickness of the hard mask on the dummy gate, the dummy gate composed of the polycrystalline silicon will be exposed, and there is a possibility that an epitaxial layer grows also on the dummy gate during the formation of the source / drain. In addition, there is a problem of defect occurrence due to etching damage to the spacer.

[0005] To solve the above problems, for example, Patent Document 2 protects the gate spacer at the top of the dummy gate by forming a helmet-shaped protective film only on the top of the dummy gate.

[0006] Furthermore, in Patent Document 3, in order to reduce etching damage to the sidewall of the gate spacer, after the formation of the dummy gate, the first gate spacer and the second gate spacer are sequentially deposited along the sidewall of the dummy gate. When etching the fin present between the gates, the first gate spacer can be protected by the by-product (polymer) generated by the reaction with the second gate spacer.

[0007] U.S. Patent Application Publication 2023 / 0223304 Specification U.S. Patent Application Publication 2022 / 0399336 Specification U.S. Patent Application Publication 2022 / 0102527 Specification

[0008] When the process disclosed in Patent Document 2 is applied, the upper part of the gate spacer at the top of the dummy gate is protected. However, the gate spacer formed on the side wall of the dummy gate is not protected. In dry etching, which removes the spacer formed on the fins present in the gap between gates and the fins themselves, it is necessary to reach the bottom of the gap between the dummy gates, where the pitch is approximately 50 nm, with the etchant. Therefore, a high voltage must be applied to improve the straightness of the etchant, and as a result, the etchant with high energy may bounce off the fins present in the gap between gates, potentially damaging the gate spacer on the side wall of the dummy gate.

[0009] Furthermore, when the process disclosed in Patent Document 3 is applied, two vertical etchings equal to the height of the Fin pattern must be performed to remove the second and first gate spacers deposited on the side walls of the Fin, respectively. As a result, the first gate spacers deposited on the dummy gate are exposed to high-energy etchants for a long time on top of the dummy gate, and the etching of the first gate spacers may proceed beyond the height of the Fin pattern, potentially exposing the dummy gate.

[0010] Furthermore, combining Patent Document 3 and Patent Document 2, that is, a method in which a first gate spacer and a second gate spacer are formed along the side wall of the dummy gate as in Patent Document 3, and then a third protective film having a helmet shape is formed only on the upper part of the dummy gate as in Patent Document 2, can also be considered as an example of a gate spacer protection process. In this case, the upper part of the dummy gate is protected by the second gate spacer and the helmet-shaped third protective film, and the first gate spacer on the side wall of the dummy gate is protected by the second gate spacer.

[0011] However, since the third protective film, which has a helmet shape, also deposits on the side walls above the gate, the first gate spacer, the second gate spacer, and the third protective film are formed on the hard mask above the gate. For this reason, as transistor miniaturization progresses, there is a concern that the gaps between gates will be filled with these multilayer films above the dummy gate. Also, if the third protective film is prevented from depositing on the side walls in order to avoid the above phenomenon, the upper part of the second gate spacer will be exposed at the corners above the dummy gate, and for the reasons mentioned above, etching of the first gate spacer may proceed beyond the height of the fin pattern, potentially exposing the dummy gate.

[0012] The present disclosure aims to provide a technique that enables the protection of the top and sidewalls of a dummy gate with a first protective film and a second protective film, respectively, during the etching of a spacer in the gate sidewall spacer formation process of a transistor.

[0013] One embodiment of the present disclosure provides a technology (method for manufacturing a semiconductor device and a plasma processing method) characterized by comprising: a semiconductor layer formed in a linear shape to form a channel; a first step of forming a first protective film so as to cover a spacer layer formed so as to cover a dummy gate formed in a linear shape perpendicular to the semiconductor layer; a second step of forming a second protective film different from the first protective film so as to cover the first protective film after the first step; a third step of selectively removing the second protective film formed on the sidewall of the dummy gate and the second protective film formed on the sidewall and upper surface of the semiconductor layer from the second protective film formed on the upper surface of the dummy gate by isotropic etching after the second step; and a fourth step of removing the first protective film formed on the sidewall of the semiconductor layer by anisotropic etching after the third step.

[0014] According to one embodiment of the present disclosure, in the gate spacer formation process on a dummy gate during the metal gate replacement process of a multi-gate FET, a laminated protective film consisting of a first protective film and a second protective film is formed on the upper part of the dummy gate, the first protective film is formed on the sidewall of the dummy gate, and a structure is formed in which the protective film is not left on the fins present in the gaps between the dummy gates. By making the width of the second protective film formed on the upper part of the dummy gate larger than the width of the dummy gate including the spacer, when the spacer deposited on the fins is removed by etching, the upper part and sidewall of the dummy gate can be protected simultaneously, thereby suppressing etching damage to the gate spacer.

[0015] This is a bird's-eye view showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of the transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1.This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the Fin region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a process flow diagram showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 1. This is a diagram showing an example of the configuration of a plasma processing apparatus. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2.This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 2. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a process flow diagram showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 3. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 4.This is a cross-sectional view of the gate region of a transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 4. This is a cross-sectional view of the gate region of a transistor in a direction parallel to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 4. This is a cross-sectional view of the gate region of the transistor in a direction perpendicular to the gate, showing the manufacturing process of the gate spacer formation process in the GAA FET of Example 4.

[0016] Embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to the embodiments described below, and various modifications are possible within the scope of its technical concept. In all the drawings used to illustrate the embodiments, components having the same function are denoted by the same reference numerals, and repeated explanations may be omitted. Furthermore, it goes without saying that many changes are possible to the content disclosed as these embodiments, such as changing the combination of materials or manufacturing processes. Also, the drawings are not necessarily to scale accurately, and important parts are emphasized and depicted schematically to clarify the logic. In addition, the drawings may be represented schematically compared to the actual embodiments in order to make the explanation clearer, but these are merely examples and do not limit the interpretation of this disclosure.

[0017] In Example 1, we will describe in detail the process of forming a gate spacer in the manufacturing process (semiconductor manufacturing method or plasma processing method) of a GAA-type FET (Gate All Around type Field Effect Transistor) as a semiconductor device, in which a protective layer including a first protective film and a second protective film is formed on the upper part of the dummy gate, and the first protective film is formed on the side wall of the dummy gate, and no protective film remains on the trench bottom between the dummy gates and on the fins of the source / drain region. For the above explanation, Figures 1, 2A to 13A, 2B to 13B, 14 and 15 will be used as drawings.

[0018] Figure 2A illustrates a cross-sectional view of an intermediate stage in the formation of a GAA transistor, according to some embodiments of the disclosure. The corresponding process is also schematically reflected in the procedure flow shown in Figure 14.

[0019] Figure 1 is a bird's-eye view of the structure of a GAA-type FET immediately before gate spacer formation in the manufacturing process. Figures 2A to 13A are cross-sectional views of the Fin region of the transistor in a direction parallel to the gate (line AA' in Figure 1), showing the gate spacer formation process. Figures 2B to 13B are cross-sectional views of the gate region of the transistor in a direction perpendicular to the gate (line BB' in Figure 1), showing the gate spacer formation process. Figure 14 is a flow chart of the series of manufacturing processes shown in Figures 2A to 13A and Figures 2B to 13B.

[0020] In Figure 1, a single-crystal semiconductor substrate 1 is partially processed into a line shape, and between the lines, an element isolation (STI: Shallow Trench Isolation) insulating film (referred to as an STI insulating film) 2 is formed, constituting an element isolation region. On the semiconductor substrate 1, there is a Fin structure 5 in which multiple layers of semiconductor channel layers 3 and sacrificial layers 4 are alternately stacked and oriented parallel to the line pattern. The line pattern of the Fin structure 5 is a pattern of semiconductor layers formed in a line shape to form a channel, and can be rephrased as Fin pattern 5 or first pattern. Perpendicular to the line pattern of the Fin structure 5, a dummy gate stacking pattern 6 for a transistor is formed so as to cover the top surface and side walls of the Fin structure 5. This dummy gate stacking pattern 6 includes a dummy gate insulating film 7, a dummy gate layer 8, and a hard mask layer 9. The dummy gate stacking pattern 6 can be rephrased as a second pattern of dummy gates formed in a line shape orthogonal to the first pattern.

[0021] For the semiconductor substrate 1, for example, silicon (Si) is preferable, but a substrate with a silicon germanium (SiGe) film deposited on Si is also acceptable, or an SOI (Silicon on Insulator) substrate using a laminated film of an insulating film such as a silicon oxide film (SiO2) and a Si layer on a Si substrate may be used. As a processing process for forming the Fin pattern 5, for example, a laminated film (SiGe / Si laminated film) in which multiple layers of Si semiconductor channel layers 3 and SiGe sacrificial layers 4 are alternately stacked is formed on the semiconductor substrate 1, and after patterning using lithography technology, a method is used in which the laminated film and a part of the semiconductor substrate 1 are etched in the vertical direction. For patterning, for example, when using a laser with argon fluoride gas (ArF) as the light source, if the pattern period is, for example, 80 nm or more, single exposure (Single Patterning) can be used, and if it is between 40 nm and 80 nm, self-aligned double patterning (SADP) can be used. Furthermore, if the pattern period is, for example, 20 nm or more and 40 nm or less, self-aligned quadruple patterning (SAQP) can be used. Also, when performing extreme ultraviolet (EUV) exposure at a wavelength of 13.5 nm, single exposure can be used if the pattern period is, for example, 40 nm or more. If the pattern period is, for example, 20 nm or more and 40 nm or less, SADP can be used. Using the above pattern, the SiGe / Si multilayer film is etched perpendicularly to the semiconductor substrate 1. The number of layers of semiconductor channel layers 3 and sacrificial layers 4 included in Fin 5 is determined in consideration of the characteristics of the transistor, and it is desirable that the semiconductor channel layers 3 be approximately 2 to 6 layers. Furthermore, the above SiGe / Si multilayer films are formed by chemical vapor deposition (CVD), for example, using hydrogen-diluted monosilane (SiH4) or disilane (Si2H6) as the raw material gas for the Si film, and a mixed gas of hydrogen-diluted SiH4 or Si2H6 and a gas such as Germanine (GeH4) as the raw material gas for the SiGe film.

[0022] The STI insulating film 2 is formed by depositing an insulating film such as an SiO2 film, a silicon oxynitride film (SiON), or a silicon carbon oxide film (SiCO) by CVD or the like, and then etching back these STI insulating films 2 until the SiGe / Si multilayer film is exposed.

[0023] The dummy gate stacked pattern 6 is formed by depositing a dummy gate insulating film 7 made of SiO2 or a similar insulating film, a dummy gate layer 8 made of amorphous Si or polycrystalline Si, and a hard mask layer 9 made of silicon nitride (Si3N4), SiO2, or silicon carbonitride (SiCN) on a Fin 5 and STI insulating film 2 made of a SiGe / Si stacked film, and then processing a periodic or similar line-shaped pattern oriented perpendicular to the SiGe / Si stacked film pattern. For the patterning, single exposure using the ArF light source or the SADP method is used depending on the pattern period. The size of the gate pattern is preferably set to a gate pitch of 40 nm to 70 nm and a dummy gate width, i.e., gate length, in the range of 10 nm to 30 nm.

[0024] Figure 2A shows the bird's-eye view shown in Figure 1, viewed from a cross-section of the transistor's fin pattern (line AA' in Figure 1) in a direction parallel to the gate. The figure shows the case where three semiconductor channel layers 3 are stacked, but the number of stacked layers is not limited to three and can be any value. Figure 2B shows the bird's-eye view shown in Figure 1, viewed from a cross-section of the transistor's gate pattern (line BB' in Figure 1) in a direction perpendicular to the gate.

[0025] A spacer layer 10, which serves as a gate spacer, is deposited on the structure shown in Figures 2A and 2B to obtain the structure shown in Figures 3A and 3B. This spacer layer is selected from materials such as SiCO, Si3N4, SiO2, SiCN, SiON, and silicon oxynitride film (SiOCN), and is formed using CVD or ALD (Atomic Layer Deposition) methods. The spacer layer 10 may be a single layer or a multilayer structure formed by stacking multiple layers of the above materials. The thickness of the spacer layer 10 may be in the range of approximately 4 nm to 8 nm. This step shown in Figures 3A and 3B corresponds to the initial pattern formation S0 in the process flow diagram shown in Figure 14.

[0026] Next, a first protective film 11 is deposited on the structure shown in Figures 3A and 3B to obtain the structure shown in Figures 4A and 4B. The film deposition can be performed using either the CVD method or the ALD method. The film deposition should be carried out under conditions that ensure uniform film thickness across the entire surface of the structure shown in Figures 4A and 4B. The material for the first protective film 11 is selected from, for example, SiO2, SiON, or SiCN. The film thickness of the first protective film is controlled to, for example, approximately 1 nm to 3 nm. In the case of an SiO2 film deposited by the ALD method, trimethyl silane (TMS), tris-dimethylaminosilane (TDMAS), tetraethyl orthosilicate (TEOS), or tetrachlorosilane (SiCl4) can be used as the raw material for Si, and oxygen radicals or water can be used as the raw material for oxygen. The above SiO2 film may be formed by CVD, in which case TEOS or SiH4 may be used. When SiCN is used as the first protective film, it may be formed by ALD using, for example, hexachlorodisilane (Si2Cl6) as the Si raw material and methylamine (CH3NH2) as the carbon and nitrogen raw materials, or by CVD using SiH4 or SiCl4 and a gas made by adding methane (CH4) and inert gases such as Ar and He to ammonia (NH3) or nitrogen (N2) as raw materials. The above ALD or CVD method may be a thermal ALD or thermal CVD method in which the raw material gas is decomposed on the surface of the semiconductor substrate 1 by heat, or a plasma ALD or plasma CVD method in which thermal decomposition is performed by irradiating the semiconductor substrate 1 with plasma. The process shown in Figures 4A and 4B corresponds to the first protective film formation S1 in the process flow diagram shown in Figure 14. The first protective film formation S1 can be rephrased as the first step. In other words, the first step (S1) is a step of forming a first protective film 11 so as to cover the first pattern 5 of semiconductor layers formed in a line shape to form a channel, and the dummy gate layer 8 formed in a line shape perpendicular to the semiconductor layer 5, and so as to cover the spacer layer 10.

[0027] Next, a second protective film 12 is deposited on the structures shown in Figures 4A and 4B to obtain the structures shown in Figures 5A and 5B. The film deposition can be performed using either CVD or ALD. The deposition should be carried out under conditions such that, during subsequent etching, the second protective film 12 remains only on the upper part of the dummy gate in Figure 5B, compared to the thickness (t1, t2, t3) of the second protective film on the upper part and sidewalls of Fin 5 in Figure 5A and the sidewalls of the dummy gate. This can be achieved by increasing the thickness (t4) of the second protective film 12 on the upper part of the dummy gate in Figure 5B, or by improving the film quality of the second protective film 12 only on the upper part of the dummy gate to enhance etching resistance. For example, Si3N4 can be used as the material for the second protective film 12. The thickness of the second protective film 12 is controlled to approximately 1 nm to 10 nm. In the case where the second protective film 12 is a Si3N4 film deposited by the ALD method, the raw material for Si may be, for example, bis(tert-butylamino)silane (BTBAS), bis(diethylamino)silane (BDEAS), or dichlorosilane (SiH2Cl2), and the raw material for nitrogen may be N2 gas, a mixture of N2 gas and hydrogen (H2) gas, or a nitrogen-containing gas such as NH3 gas. The above Si3N4 film may also be deposited by the CVD method, in which case SiH4, NH3, N2, etc. may be used as the raw material gas. The above ALD method or CVD method may be a thermal ALD or thermal CVD method in which the raw material gas is decomposed on the surface of the semiconductor substrate by heat, or a plasma ALD or plasma CVD method in which thermal decomposition is performed by irradiating the semiconductor substrate with plasma. When using the ALD or CVD method, rotating the wafer while the film is being deposited allows the reaction material species to be preferentially deposited on the upper part of the pattern because they are insufficient in the grooves between the patterns. The deposition rate can also be adjusted by adjusting the deposition time and the flow rate and pressure of the reaction gas. This process, shown in Figures 5A and 5B, corresponds to the second protective film formation S2 in the process flow diagram shown in Figure 14, and is preferably performed continuously in the same plasma processing apparatus chamber (see Figure 15) following the first protective film deposition S1 shown in Figures 4A and 4B.The second protective film formation S2 can be rephrased as the second step. The second step S2 is a step in which, after the first step S1, a second protective film 12 different from the first protective film 11 is formed so as to cover the first protective film 11. The second protective film 12 formed in the second step S2 is formed such that the film thickness of the second protective film 12 deposited on the upper surface of the second pattern 6 is thicker than the film thickness of the second protective film 12 deposited on other areas. In other words, the second protective film is formed in the second step S2 such that the film thickness of the second protective film 12 deposited on the upper surface of the dummy gate layer 8 is thicker than the film thickness of the second protective film 12 deposited on areas other than the upper surface of the dummy gate layer 8.

[0028] Next, the second protective film 12 is isotropically etched from the structure shown in Figures 5A and 5B to obtain the structure shown in Figures 6A and 6B. This etching is performed under selective etching conditions for the first protective film 11. For example, if the second protective film 12 is Si3N4, the etching gas should be a gas such as fluoroform (CHF3), difluoromethane (CH2F2), or fluoromethane (CH3F), or a mixed gas of fluorocarbon gases such as methane tetrafluoride (CF4) or cyclobutane octafluoride (C4F8) and H2, or a gas similar thereto. In this etching, the etching time is adjusted so that the second protective film 12 on the upper part of the dummy gate in Figure 5B remains, while the first protective film on the upper part and side walls of Fin 5 in Figure 5A is removed. The process shown in Figures 6A and 6B corresponds to the second protective film isotropic etching S3 in the process flow diagram shown in Figure 14, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the second protective film formation S2 shown in Figures 5A and 5B. The second protective film isotropic etching S3 can be rephrased as the third process S3. In other words, the third process S3 is a process in which, after the second process S2, the second protective film 12 formed on the sidewall of the dummy gate layer 8 and the second protective film 12 formed on the sidewall and upper surface of the semiconductor layer 5 are selectively removed by isotropic etching with respect to the second protective film 12 formed on the upper surface of the dummy gate layer 8. The width of the second protective film 11 after the third process S3 is configured to be greater than the sum of the width of the dummy gate layer 8 and the width of the spacer layer 10.

[0029] After the steps shown in Figures 6A and 6B above, if the maximum width W2 of the second protective film 12 is smaller than the width W1 of the pattern consisting of the spacer layer 10 and the dummy gate layer 8, the following cycle process is performed.

[0030] The above cycle process first involves isotropically etching the first protective film 11 from the structure shown in Figures 6A and 6B to obtain the structure shown in Figures 7A and 7B. When the material of the first protective film 11 is SiO2, the etching gas should be a halogen gas containing carbon, such as methane tetrafluoride (CF4) or cyclobutane octafluoride (C4F8), or a mixed gas to which oxygen (O2), nitrogen (N2), or argon (Ar) or helium (He) is added. This etching is performed under selective etching conditions for the spacer layer 10 and the second protective film 12. This etching is performed under conditions that leave the first protective film 11 directly beneath the second protective film 12 in Figure 6B, while removing the first protective film 11 deposited on the upper and side walls of the Fin pattern 5 in Figure 6A, and further on the side walls of the dummy gate stacking pattern 6 in Figure 6B. The process shown in Figures 15A and 15B corresponds to the isotropic etching S4 of the first protective film 11 in the process flow diagram shown in Figure 14, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the isotropic etching S3 of the second protective film 12 shown in Figures 6A and 6B. The isotropic etching S4 of the first protective film 11 can be rephrased as the fourth process. The fourth process S4 is a process that performs isotropic etching after the third process S3 to remove the first protective film 11 deposited on the sidewalls of the second pattern 6 and the sidewalls and top surface of the first pattern 5. Furthermore, the fourth process S4 is a process that removes the first protective film 11 formed on the sidewalls of the dummy gate layer 8 and the first protective film 11 formed on the sidewalls and top surface of the semiconductor layer 5 by isotropic etching.

[0031] From the step shown in S4 in Figure 14, steps S5, which is the same process as the step shown in S1 in Figure 14, S6, which is the same process as the step shown in S2 in Figure 14, and S7, which is the same process as the step shown in S3 in Figure 14, are performed again. By performing steps S4, S5, S6, and S7 consecutively multiple times, the cycle process S8 shown in Figure 14 is constructed. Step S5 can be rephrased as a fifth step S5 in which a new first protective film 11 is formed after the fourth step S4. Similarly, step S6 can be rephrased as a sixth step S6 in which a new second protective film 12 is formed after the fifth step S5. Step S7 can be rephrased as the seventh step S7, which, after the sixth step S6, performs isotropic etching to remove the second protective film 12 deposited on the side walls of the second pattern 6 and the side walls and top surface of the first pattern 5, while leaving the second protective film 12 deposited on the upper surface of the second pattern (6) intact. The cycle process S8 can be rephrased as the cycle process S8, which repeats the fourth steps S4 to the seventh steps S7 multiple times. After the execution of the cycle process S8, the horizontal width of the structure including the second protective film 2b in the uppermost layer becomes larger than the horizontal width of the second pattern 6 and the spacer layer 10 combined.

[0032] Figures 8A and 8B show an example in which the cycle process S8 shown in Figure 14 is repeated twice, starting from the step S3 shown in Figure 14. In this case, to briefly explain the structure, as shown in Figure 8B, the first protective film 11a is provided on the second protective film 12 by the first S5, and the second protective film 12a is provided on the first protective film 11a by the first S6. Furthermore, the first protective film 11b is provided on the second protective film 12a by the second S5, and the second protective film 12b is provided on the first protective film 11b by the second S6.

[0033] The number of repetitions of the above cycle process S8 is limited to the number of times that the maximum width W3 of the uppermost second protective film 12b shown in Figure 8B becomes greater than the width W1 of the pattern consisting of the spacer layer 10 and the dummy gate layer 8. The series of steps from the step shown in S1 in Figure 14 to the multiple repetitions of the cycle process S8 are preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15).

[0034] After performing cycle process S8, vertical etching of the first protective film 11 is performed. If the cycle process S8 is repeated twice, vertical etching of the first protective film 11 is performed from the structure shown in Figures 8A and 8B to obtain the structure shown in Figures 9A and 9B. When the material of the first protective film 11 is SiO2, it is preferable to use a halogen gas containing carbon, such as CF4 or C4F8, or a mixed gas to which gases such as O2, N2, Ar, or He are added as the etching gas. This etching is performed under conditions that result in selective etching of the second protective film 12 and the spacer layer 10, and is continued until the first protective film 11 deposited on the spacer layer 10 on the upper and side walls of the Fin pattern 5 shown in Figure 8A is removed. In this process, since the maximum width W3 of the second protective film 12 is greater than the width W1 of the pattern consisting of the spacer layer 10 and the dummy gate layer 8, the first protective film 11 deposited on the side walls of the spacer layer 10 on the dummy gate layer 8 is protected during etching. Therefore, after etching, the spacer layer 10 deposited on the upper and side walls of the Fin pattern 5 is exposed, while the spacer layer 10 deposited on the dummy gate layer 8 is protected by the first protective film 11. The process shown in Figures 9A and 9B corresponds to the first protective film 11 etching S9 in the process flow diagram shown in Figure 14, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the cycle process S8 shown in Figure 14. The first protective film 11 etching S9 can be rephrased as the eighth step S9. The eighth step S9 is a step in which the first protective film 11 formed on the side walls of the semiconductor layer 5 is removed by anisotropic etching. The eighth step S9 removes part or all of the first protective film 11.

[0035] In other words, the first example configuration of the semiconductor device manufacturing process (or plasma processing method) can be summarized as follows.

[0036] 1) Perform the first step S1 to the third step S3.

[0037] 2) The fourth step S4 is carried out.

[0038] 3) After the fourth step S4, perform a fifth step S5 of forming a first protective film so as to cover the spacer layer 10.

[0039] 4) After the fifth step S5, perform a sixth step S6 of forming a second protective film 12 so as to cover the first protective film 11.

[0040] 5) After the sixth step S6, perform a seventh step S7 of selectively removing, by isotropic etching, the second protective film 12 formed on the side wall of the dummy gate layer 8 and the second protective film 12 formed on the side wall and upper surface of the semiconductor layer 5 with respect to the second protective film 12 formed on the upper surface of the dummy gate layer 8.

[0041] 6) Next, perform an eighth step S9 of removing the first protective film 11 formed on the side wall of the semiconductor layer 5 by anisotropic etching.

[0042] 7) When N is a natural number of 2 or greater, after performing the first step S1 to the third step S3, repeat the fourth step S4 to the seventh step S7 N times (cycle process S8).

[0043] 8) After repeating the fourth step S4 to the seventh step S7 N times, if the width of the second protective film 12 formed on the upper surface of the dummy gate layer 8 and located in the uppermost layer is larger than the sum of the width of the dummy gate layer 8 and the width of the spacer layer 10, perform the eighth step S9 after repeating the fourth step S4 to the seventh step S7 N times.

[0044] Further, the second configuration example of the manufacturing process of a semiconductor element (or the plasma treatment method) can also be summarized as follows.

[0045] 1) Perform the first step S1 to the third step S3.

[0046] 2) Next, perform a fourth step S9 of removing the first protective film 11 formed on the side wall of the semiconductor layer 5 by anisotropic etching.

[0047] The first protective film 11 etching S9 can be rephrased as the eighth step S9 in the first configuration example of the manufacturing process of a semiconductor element, and can be rephrased as the fourth step in the second configuration example of the manufacturing process of a semiconductor element.

[0048] In a first configuration example of a semiconductor device manufacturing process, an eighth step S9 is performed after repeating fourth to seventh steps S4 to S7 N times (after a cycle process S8). Part or all of a first protective film 11 is removed by the eighth step S9.

[0049] On the other hand, in a second configuration example of a semiconductor device manufacturing process, a fourth step S9 is a step of removing, after a third step S3, the first protective film 11 deposited on a sidewall of a semiconductor layer 5 by anisotropic etching such as vertical etching. Part or all of the first protective film 11 is removed by the fourth step S9.

[0050] Next, from the structure shown in FIGS. 9A and 9B, vertical etching or isotropic etching is used to remove the spacer layer 10 deposited on the top and sidewalls of the Fin pattern 5. When the number of repetitions of the cycle process S8 shown in FIG. 14 is two, the structure shown in FIGS. 10A and 10B is obtained after the present etching. This etching is performed under conditions that provide selective etching for the first protective film 11, the second protective film 12, and further the semiconductor channel layer 3 and the sacrificial layer 4 constituting the Fin pattern 5. For example, when the spacer layer 10 is made of a material such as SiOCN, it is preferable to use a mixed gas of a fluorine compound such as NF3 and an inert gas such as Ar, or a gas equivalent thereto, as a source gas. In this etching, the spacer layer 10 deposited on the top and sidewalls of the pattern of the dummy gate layer 8 is protected by the second protective film 12 and the first protective film 11, respectively. There is no concern that the dummy gate layer 8 will be exposed during etching, and damage to the spacer layer 10 caused by ions or radicals can also be reduced. This step shown in FIGS. 9A and 9B corresponds to gate spacer etching S10 in the process flow diagram shown in FIG. 14, and is preferably performed continuously in a chamber of the same plasma processing apparatus (see FIG. 15) subsequent to first protective film vertical etching S9.

[0051] Gate spacer etching S10 can be rephrased as a ninth step S10 in the first configuration example of the semiconductor device manufacturing process. The ninth step S10 is a step of etching away part or all of the spacer layer 10 deposited on the sidewall of the semiconductor layer 5 after the eighth step S9.

[0052] On the other hand, gate spacer etching S10 can be rephrased as the fifth step S10 in the second example of the semiconductor device manufacturing process. The fifth step S10 is a step in which, after the fourth step S9, part or all of the spacer layer 10 deposited on the side wall of the semiconductor layer 5 is etched off.

[0053] Next, vertical etching is performed on the semiconductor channel layer 3 and sacrificial layer 4 that constitute the Fin pattern 5, based on the structures shown in Figures 10A and 10B. When the cycle process S8 shown in Figure 14 is repeated twice, the structures shown in Figures 11A and 11B are obtained after this etching. This etching is performed under conditions of selective etching with respect to the spacer layer 10. When the semiconductor channel layer 3 is Si and the sacrificial layer 4 is SiGe, it is preferable to use a halogen-based gas such as CF4, sulfur hexafluoride (SF6), or germanium tetrafluoride (GeF4) as the etching gas, and a mixed gas to which gases such as O2, N2, Ar, or helium (He) are added. The etching is performed until the etched surface reaches the same level as the top surface of the STI insulating film 2, or even further down. In this etching, the spacer layer 10 deposited on the upper and side walls of the dummy gate layer 8 pattern is protected by the second protective film 12 and the first protective film 11, respectively, which reduces damage to the spacer layer 10 by ions and radicals during etching. The process shown in Figures 11A and 11B corresponds to Fin etching S11 in the process flow diagram shown in Figure 14, and is preferably performed in the same plasma processing apparatus chamber (see Figure 15) following gate spacer etching S10.

[0054] Fin etching S11 can be rephrased as the tenth step S11 in the first example of the semiconductor device manufacturing process. The tenth step S11 is a step in which the semiconductor layer 5 is removed by anisotropic etching such as vertical etching after the ninth step S10.

[0055] On the other hand, Fin etching S11 can be rephrased as the sixth step S11 in the first example of the semiconductor device manufacturing process. The sixth step S11 is a step in which the semiconductor layer 5 is removed by anisotropic etching such as vertical etching after the fifth step S10.

[0056] Next, the first protective film 11 and the second protective film 12 are etched away from the structures shown in Figures 11A and 11B to obtain the structures shown in Figures 12A and 12B. This etching is performed under conditions that result in selective etching of the semiconductor channel layer 3, the sacrificial layer 4, and the spacer layer 10. When the material of the first protective film 11 is SiO2 and the material of the second protective film 12 is Si3N4, it is preferable to use a mixed gas of a fluoride compound such as NF3 and an inert gas such as Ar or N2, or a gas similar thereto, as the etching gas. This step shown in Figures 12A and 12B corresponds to the first protective film / second protective film removal S12 in the process flow diagram shown in Figure 14, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the fin etching S11.

[0057] The removal of the first protective film / second protective film S12 can be rephrased as the eleventh step S12 in the first example of the semiconductor device manufacturing process. The eleventh step S12 is a step of removing the first protective film 11 and the second protective film 12 after the ninth step S10 or after the tenth step S11.

[0058] Next, an inner spacer layer 13 and a source / drain epitaxial layer 14 are formed from the structures shown in Figures 12A and 12B to obtain the structures shown in Figures 13A and 13B. To form the inner spacer layer 13, first, the sacrificial layer 4 is selectively etched horizontally to deposit a low dielectric constant insulating film. Then, the insulating film is isotropically etched to form the inner spacer layer 13 in the grooves created by the horizontal selective etching of the sacrificial layer 4. Subsequently, the inner spacer layer 13 is selectively formed on the semiconductor channel layer 3 and the semiconductor substrate 1 using selective epitaxial growth on the semiconductor layer. For horizontal selective etching of the sacrificial layer 4, if the semiconductor channel layer 3 is Si and the sacrificial layer 4 is SiGe, it is preferable to use a fluorine-containing gas such as SF6, CF4, or NF3, or a mixture of these gases, or a gas to which a noble gas such as O2, Ar, or He, or an inert gas such as N2, or a mixture of these gases is added. The conditions such as the gas flow rate ratio, ion energy during etching, combination of etching gases, and pressure in the etching chamber should be adjusted so that the etching of the SiGe sacrificial layer 4 is isotropic and the etching rate is approximately 1 to 200 times that of the Si semiconductor substrate 1 and the Si semiconductor channel layer 3. The etching amount should be approximately equal to the film thickness of the spacer layer 10, and the width of the remaining sacrificial layer 4 should be approximately equal to that of the dummy gate layer 8. The insulating film forming the inner spacer layer 13 should be a SiCO film or SiOCN film, similar to that used for the spacer layer 10. For example, if the low dielectric constant insulating film is a SiCO film, the etching gas should be a mixed gas of fluorine-containing gases such as CHF3, CH2F2, CH3F, or NF3 with N2 or O2, or a similar gas.

[0059] The source / drain epitaxial layer 14 is grown using a mask and patterning to deposit different epitaxial layers in the n-type transistor region and the p-type transistor region. A Si layer doped with phosphorus (P) or arsenic (As) is preferably deposited in the n-type transistor region, while a SiGe layer doped with boron (B) or the like is preferably deposited in the p-type transistor region. CVD or similar methods are used for deposition; for example, hydrogen dilution gases containing phosphine (PH3) as the source gas for P, arsine (AsH3) as the source gas for As, and diborane (B2H6) as the source gas for B are preferably used. The horizontal selective etching of the sacrificial layer 4 in this process may be performed continuously in the same plasma processing apparatus chamber (see Figure 15) following the removal of the first / second protective film S12 in Figure 14.

[0060] By using a plasma processing apparatus equipped with ALD film deposition function or CVD film deposition function, and anisotropic and isotropic etching control function, the entire process from the formation of the first protective film S1 (Figures 4A and 4B) to the removal of the first and second protective films S12 (Figures 12A and 12B) can be processed continuously within the same plasma processing apparatus. The plasma processing apparatus may be any of the following: an etching apparatus using inductively coupled plasma (ICP), an etching apparatus using capacitively coupled plasma (CCP), or an etching apparatus using microwave electron cyclotron resonance (ECR) plasma.

[0061] As an example, Figure 15 shows the configuration of a plasma processing apparatus 100 using microwave ECR plasma. The plasma processing apparatus 100 has a processing chamber 101, which is connected to a vacuum exhaust device (not shown) via a vacuum exhaust port 102, and during plasma processing, the inside of the processing chamber 101 is maintained at a vacuum of, for example, 0.1 Pa to 10 Pa. The processing chamber 101 also has a window portion 103 that serves to transmit microwaves and hermetically seal the processing chamber 101, and a perforated plate 104 for shielding ions. The perforated plate 104 divides the processing chamber 101 into an upper portion (upper region) 101A and a lower portion (lower region) 101B. The material of the window portion 103 is made of a material that transmits microwaves, for example, a dielectric material such as quartz is used. The perforated plate 104 has multiple holes, and the material of the perforated plate 104 is preferably made of a dielectric material such as quartz or alumina.

[0062] The gas supply mechanism includes a gas source 105, a gas supply device 106, and a gas inlet 107, and supplies raw material gas for plasma processing. The gas source 105 has multiple types of gas necessary for processing. The gas supply device 106 includes a control valve that controls the supply and shutoff of gas, and a mass flow controller that controls the gas flow rate. The gas inlet 107 is provided between the window portion 103 and the perforated plate 104.

[0063] A waveguide 109 for propagating electromagnetic waves is connected to the upper part of the processing chamber 101, and a high-frequency power supply 108 for plasma generation, which is a high-frequency power supply, is connected to the end of the waveguide 109. The high-frequency power supply 108 for plasma generation is a power source for generating electromagnetic waves for plasma generation, and for example, microwaves with a frequency of 2.45 GHz are used as electromagnetic waves. Microwaves generated from the high-frequency power supply 108 propagate through the waveguide 109 and enter the processing chamber 101. Because the waveguide 109 has a vertical waveguide that extends vertically and a waveguide converter that also serves as a corner that bends the direction of microwaves by 90 degrees, microwaves are incident perpendicularly on the processing chamber 101. The microwaves propagate perpendicularly inside the processing chamber 101 via the window section 103. A magnetic field generating coil 110 arranged on the outer periphery of the processing chamber 101 forms a magnetic field in the processing chamber 101. The microwaves emitted from the high-frequency power supply 108 for plasma generation interact with the magnetic field formed by the magnetic field generating coil 110 to generate a high-density plasma in the processing chamber 101.

[0064] Below the processing chamber 101, a sample stage 112 is positioned opposite the window 103. For example, aluminum or titanium can be used as the material for the sample stage 112. The sample stage 112 holds the semiconductor substrate 111, which is the sample, on its upper surface. Here, the central axes of the waveguide 109, processing chamber 101, sample stage 112, and semiconductor substrate 111 coincide. Furthermore, electrodes for electrostatically adsorbing the semiconductor substrate 111 are provided inside the sample stage 112, and the semiconductor substrate 111 is electrostatically adsorbed to the sample stage 112 by applying a DC voltage. In addition, a high-frequency voltage is applied to the sample stage 112 from a high-frequency bias power supply 113 to control the isotropy and anisotropy of the etching. The frequency of the applied high-frequency bias may be, for example, 400 kHz.

[0065] Each mechanism of the plasma processing apparatus 100 is controlled by a control signal 121 from the control unit 120. The control unit 120 controls each mechanism by instructing it to perform a predetermined operation using the control signal 121, according to the processing conditions (anisotropic etching, isotropic etching, ALD film deposition, etc.) performed by the plasma processing apparatus 100. For example, the control unit 120 controls the high-frequency power supply 108 for plasma generation and controls the ON-OFF of electromagnetic waves for plasma generation. The control unit 120 also controls the gas supply mechanism and adjusts the type and flow rate of gas introduced into the processing chamber 101. The control unit 120 also controls the high-frequency bias power supply 113 and controls the intensity of the high-frequency voltage applied to the semiconductor substrate 111 on the sample stage 112.

[0066] When performing anisotropic etching using this plasma processing apparatus 100, the control unit 120 controls the magnetic field generating coil 110 so that the plasma is generated in the lower region 101B of the processing chamber 101 below the porous plate 104. Since the porous plate 104 is made of dielectric material, microwaves pass through the porous plate 104 and interact with the magnetic field in the lower region 101B of the processing chamber 101 to generate plasma. Furthermore, a high-frequency bias is applied to the sample stage 112 on which the Si substrate 1, which serves as the semiconductor substrate 111, is placed. As a result, ions in the plasma are attracted to the semiconductor substrate 111 without being obstructed by the porous plate 104, etc., enabling anisotropic etching while maintaining perpendicularity.

[0067] When performing isotropic etching using this plasma processing apparatus 100, the control unit 120 controls the magnetic field generating coil 110 so that the plasma generation position is in the upper region 101A of the processing chamber 101 above the porous plate 104. Of the plasma generated in the upper region 101A of the processing chamber 101, ions are shielded by the porous plate 104, so only radicals in the plasma are supplied to the lower region 101B of the processing chamber 101. This makes isotropic etching using radicals possible.

[0068] When performing film deposition by ALD using this plasma processing apparatus 100, it is preferable to apply the following cycle process controlled by the control unit 120. For example, when depositing a Si3N4 film by ALD, use BTBAS or BDEAS as the Si raw material, or SiH2Cl2 as a gas. When using BTBAS or BDEAS as a liquid raw material, vaporize the liquid raw material and send it to the gas line as a gas. The raw material gas is sent into the processing chamber 101 together with the carrier gas Ar, and adsorbs onto the substrate surface as a Si precursor. Then, unwanted precursors in the processing chamber 101 are exhausted using a purge gas such as Ar gas. Next, nitrogen-containing gases such as N2 gas, a mixture of N2 gas and H2 gas, or NH3 gas are introduced into the processing chamber 101 to create plasma and react with the substrate surface. After this, an inert gas such as Ar is introduced into the processing chamber 101 again to purge the processing chamber 101 and exhaust unwanted gases from the processing chamber 101. Through this series of processes, a Si3N4 film with a thickness at the atomic layer level is deposited on the substrate surface in principle. By repeating this series of processes (performing a cycle process), a thin insulating film is formed by the ALD method.

[0069] In this embodiment, the process shown in the process flow diagram in Figure 14 is shown to be repeated multiple times. However, if, at the stage of isotropic etching of the second protective film S3 in Figure 14 (Figures 6A and 6B), the maximum width W2 of the second protective film 12 is greater than the width W1 of the pattern consisting of the spacer layer 10 and the dummy gate layer 8, then the above cycle process S8 does not need to be performed.

[0070] Furthermore, although this embodiment describes the manufacturing process of a GAA FET as an example, it can also be applied to fin-type FETs and complementary FETs (CFETs) in which n-type and p-type transistors are stacked vertically.

[0071] In Example 2, during the process of forming the inner spacer layer 13 shown in Figures 13A and 13B of Example 1, the sidewalls of the spacer layer 10 are protected with the first protective film 11 when forming the inner spacer layer 13, thereby providing a method to suppress etching damage to the sidewalls of the spacer layer 10 during isotropic etching of the inner spacer layer 13.

[0072] From the structure shown in Figures 11A and 11B of Example 1, an inner spacer layer 213 is formed to obtain the structure shown in Figures 16A and 16B. To form the inner spacer layer 213, similar to Example 1, first the sacrificial layer 204 is selectively etched horizontally to deposit a low dielectric constant insulating film. Then, the insulating film is isotropically etched to form the inner spacer layer 213 in the grooves created by the horizontal selective etching of the sacrificial layer 204. The deposition conditions and etching conditions should be the same as those in Example 1. In this example, when isotropically etching the low dielectric constant insulating film that will become the inner spacer layer 213, the sidewall of the spacer layer 210, which will serve as the gate spacer, is covered with the first protective film 211, so the spacer layer 210 is protected during isotropic etching to form the inner spacer layer 213. Since both the inner spacer layer 213 and the spacer layer 210 are composed of a low dielectric constant insulating film, there is a high possibility that they will be the same film. Therefore, there is a high concern that the spacer layer 210 will also be etched when isotropic etching is performed on the low dielectric constant insulating film to form the inner spacer layer 213. By applying this embodiment, it is possible to prevent etching damage to the spacer layer 210.

[0073] Next, the first protective film 211 and the second protective film 212 are etched away from the structures shown in Figures 16A and 16B to obtain the structures shown in Figures 17A and 17B. This etching is performed under conditions that result in selective etching of the semiconductor channel layer 203, the sacrificial layer 204, and the spacer layer 210. This etching may be performed by dry etching or wet etching using the same conditions as in Example 1.

[0074] Next, a source / drain epitaxial layer 214 is formed from the structures shown in Figures 17A and 17B to obtain the structures shown in Figures 18A and 18B. The selective growth conditions for the source / drain epitaxial layer 214 should be the same as those used in Example 1.

[0075] In Example 3, the vertical etching of the semiconductor channel layer 3 and sacrificial layer 4 in Figures 11A and 11B of Example 1 is performed after the removal of the first protective film 11 and the second protective film 12, thereby providing a method that makes it possible to widen the source / drain region (14) shown in Figure 13B.

[0076] From the structure shown in Figures 10A and 10B of Example 1, the spacer layer 210 is etched horizontally using isotropic etching to obtain the structure shown in Figures 19A and 19B. This etching is performed under conditions that result in selective etching of the first protective film 311, the second protective film 312, and the semiconductor channel layer 303 and sacrificial layer 304 that constitute the Fin pattern 305. The specific etching conditions should be the same as those in Example 1. The optimal etching amount in this etching should be approximately the same as that of the first protective film 311. In this case, the horizontal width of the remaining spacer layer 310 can be made uniform at any position on the side wall of the dummy gate layer 308. This process shown in Figures 19A and 19B corresponds to gate spacer isotropic etching S111 in the process flow diagram shown in Figure 23, and should be performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following gate spacer etching S110 shown in Figures 10A and 10B.

[0077] Next, the first protective film 311 and the second protective film 312 are etched away from the structures shown in Figures 19A and 19B to obtain the structures shown in Figures 20A and 20B. This etching is performed under conditions that result in selective etching of the semiconductor channel layer 303, the sacrificial layer 304, and the spacer layer 310. Specifically, it is preferable to use conditions equivalent to those shown in Figures 12A and 12B of Example 1. This step shown in Figures 20A and 20B corresponds to the first protective film / second protective film removal S112 in the process flow diagram shown in Figure 23, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the spacer etching S111 shown in Figures 19A and 19B.

[0078] Next, vertical etching is performed on the semiconductor channel layer 303 and sacrificial layer 304 constituting the Fin pattern 305 from the structures shown in Figures 20A and 20B to obtain the structures shown in Figures 21A and 21B. This etching is performed under conditions that result in selective etching of the spacer layer 310. For the specific etching conditions and etching amount, it is preferable to use conditions equivalent to those shown in Figures 11A and 11B of Example 1. This step shown in Figures 21A and 21B corresponds to Fin etching S113 in the process flow diagram shown in Figure 23, and is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the first protective film / second protective film removal S112 shown in Figures 20SA and 20B.

[0079] Next, an inner spacer layer 313 and a source / drain epitaxial layer 314 are formed from the structures shown in Figures 21A and 21B to obtain the structures shown in Figures 22A and 22B. The methods for selective horizontal etching of the sacrificial layer 304, formation of the inner spacer layer 313, and formation of the source / drain epitaxial layer 314 may be carried out under the same conditions as in Example 1. The selective horizontal etching of the sacrificial layer 304 in this step may be carried out continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the removal of the first protective film / second protective film S113 in Figure 14.

[0080] In this embodiment, compared to Embodiment 1, the spacing between patterns in the dummy gate layer 308 is wider in the Fin pattern 305, and the epitaxial layer 314 in the source / drain region is wider in the gate cross-section shown in Figure 22B. As a result, the electrical resistance of the epitaxial layer 314 in the source / drain region can be reduced compared to Embodiment 1.

[0081] In Example 4, in the vertical etching process of the first protective film 11 shown in Figure 9 of Example 1, the etching is performed up to the middle of the height of the Fin pattern 5, leaving a portion of the first protective film 11 on the side wall of the Fin pattern 5, thereby providing a method for controlling the shape of the subsequent source / drain epitaxial layer 14.

[0082] From the structure shown in Figures 8A and 8B of Example 1, vertical etching of the first protective film 11 is performed to obtain the structure shown in Figures 24A and 24B. This etching is performed under conditions that result in selective etching of the second protective film 412 and the spacer layer 410 which serves as a gate spacer, and it is preferable to use the same conditions as in Example 1. After the above etching, the etching time is adjusted so that a portion of the first protective film 411 remains on the side wall of the Fin pattern 405. This step is preferably performed continuously in the same plasma processing chamber following the vertical etching S4 of the first protective film 11 shown in Figures 8A and 8B of Example 1.

[0083] Next, from the structures shown in Figures 24A and 24B, the spacer layer 410 deposited on the upper and side walls of the Fin pattern 405 is partially removed using vertical etching or isotropic etching to obtain the structures shown in Figures 25A and 25B. This etching is performed under conditions that result in selective etching of the first protective film 411, the second protective film 412, and the semiconductor channel layer 403 and sacrificial layer 404 that constitute the Fin pattern 405. Specifically, it is performed under conditions equivalent to those in Figures 10A and 10B of Example 1. After the above etching, the etching time is adjusted so that a portion of the spacer layer 410 remains on the side walls of the Fin pattern 405. In this etching, the spacer layer 410 deposited on the upper and side walls of the dummy gate layer 408 pattern is protected by the second protective film 412 and the first protective film 411, respectively, so there is no concern that the dummy gate layer 408 will be exposed during etching, and damage to the spacer layer 410 by ions and radicals can also be reduced. Furthermore, in the etching process described above, the spacer layer 410 is also protected by the first protective film 411 on the sidewalls of the Fin pattern 405, thereby reducing damage from ions and radicals. The process shown in Figures 25A and 25B is preferably carried out continuously in the same plasma processing apparatus chamber (see Figure 15) following the first protective film vertical etching shown in Figures 24A and 24B.

[0084] Next, vertical etching is performed on the semiconductor channel layer 403 and sacrificial layer 404 constituting the Fin pattern 405 from the structure shown in Figures 25A and 25B to obtain the structure shown in Figures 26A and 26B. This etching is performed under conditions that result in selective etching of the spacer layer 410, and it is preferable to use conditions equivalent to those of the process shown in Figures 11A and 11B of Example 1. The etching is performed until the etched surface reaches the same level as the upper surface of the STI insulating film 402, or even further down. In this etching, the spacer layer 410 deposited on the upper and side walls of the pattern of the dummy gate layer 408 is protected by the second protective film 412 and the first protective film 411, respectively, and damage to the spacer layer 410 by ions and radicals during etching is reduced. This process shown in Figures 25A and 25B is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the gate spacer etching shown in Figures 24A and 24B.

[0085] Next, the first protective film 411 and the second protective film 412 are etched away from the structure shown in Figures 26A and 26B to obtain the structure shown in Figures 27A and 27B. This etching is performed under conditions that result in selective etching of the semiconductor channel layer 403, the sacrificial layer 404, and the spacer layer 410, and it is preferable to use conditions equivalent to those used in the process shown in Figures 12A and 12B of Example 1. This process shown in Figures 26A and 26B is preferably performed continuously in the chamber of the same plasma processing apparatus (see Figure 15) following the spacer etching shown in Figures 25A and 25B.

[0086] Next, an inner spacer layer 413 and a source / drain epitaxial layer 414 are formed from the structures shown in Figures 27A and 27B to obtain the structures shown in Figures 28A and 28B. The selective etching of the sacrificial layer 404 in the horizontal direction, the formation of the inner spacer layer 413, and the formation of the source / drain epitaxial layer 414 should be carried out under the same conditions as in Example 1. In this process, as shown in Figure 28B, when the source / drain epitaxial layer 414 epitaxially grows in the cross-section of the Fin pattern 405, the presence of a spacer layer 410 on the side wall suppresses the horizontal spreading of the source / drain epitaxial layer 414. As a result, it becomes possible to reduce the distance between adjacent transistors.

[0087] 1, 201, 301, 401: Semiconductor substrate, 2, 202, 302, 402: Element isolation (STI) insulating film, 3, 203, 303, 403: Semiconductor channel, 4, 204, 304, 404: Sacrificial layer, 5, 205, 305, 405: Fin pattern, 6, 206, 306, 406: Dummy gate pattern, 7, 207, 307, 407: Dummy gate insulating film, 8, 208, 308, 408: Dummy gate, 9, 209, 309, 409: Hard mask layer, 10, 210, 310, 410: Spacer layer, 11, 211, 311, 411: First protective film, 12, 212, 31 2, 412: Second protective film, 13, 213, 313, 413: Inner spacer layer, 14, 214, 314, 414: Source / drain epitaxial layer, 101: Processing chamber, 101A: Upper region of processing chamber, 101B: Lower region of processing chamber, 102: Vacuum exhaust port, 103: Window section, 104: Perforated plate, 105: Gas source, 106: Gas supply device, 107: Gas inlet, 108: High-frequency power supply for plasma generation, 109: Waveguide, 110: Magnetic field generating coil, 111: Semiconductor substrate, 112: Sample stage, 113: High-frequency bias power supply, 120: Control unit, 121: Control signal.

Claims

1. A method for manufacturing a semiconductor device, comprising: a first step of forming a first protective film over a semiconductor layer formed in a linear shape to form a channel, and a spacer layer formed to cover a dummy gate formed in a linear shape perpendicular to the semiconductor layer; a second step of forming a second protective film different from the first protective film over the first protective film after the first step; a third step of selectively removing the second protective film formed on the sidewall of the dummy gate and the second protective film formed on the sidewall and upper surface of the semiconductor layer from the second protective film formed on the upper surface of the dummy gate by isotropic etching after the second step; and a fourth step of removing the first protective film formed on the sidewall of the semiconductor layer by anisotropic etching after the third step.

2. A method for manufacturing a semiconductor device according to claim 1, characterized in that a part or all of the first protective film is removed in the fourth step.

3. A method for manufacturing a semiconductor device according to claim 1, characterized in that the width of the second protective film after the third step is greater than the sum of the width of the dummy gate and the width of the spacer layer.

4. A first step of forming a first protective film so as to cover a semiconductor layer formed in a linear shape to form a channel, and a spacer layer formed so as to cover a dummy gate formed in a linear shape perpendicular to the semiconductor layer; a second step of forming a second protective film different from the first protective film so as to cover the first protective film after the first step; a third step of selectively removing the second protective film formed on the side wall of the dummy gate and the second protective film formed on the side wall and top surface of the semiconductor layer from the second protective film formed on the top surface of the dummy gate by isotropic etching after the second step; a fourth step of removing the first protective film formed on the side wall of the dummy gate and the first protective film formed on the side wall and top surface of the semiconductor layer by isotropic etching; a fifth step of forming the first protective film so as to cover the spacer layer after the fourth step; A method for manufacturing a semiconductor device, comprising: a sixth step of forming a second protective film so as to cover the first protective film after the fifth step; a seventh step of selectively removing the second protective film formed on the sidewall of the dummy gate and the second protective film formed on the sidewall and upper surface of the semiconductor layer from the second protective film formed on the upper surface of the dummy gate by isotropic etching after the sixth step; and an eighth step of removing the first protective film formed on the sidewall of the semiconductor layer by anisotropic etching, wherein the first to third steps are performed, and when N is a natural number of 2 or more, the fourth to seventh steps are repeated N times after the first to third steps are performed; and after the fourth to seventh steps are repeated N times, if the width of the second protective film formed on the upper surface of the dummy gate and present in the uppermost layer is greater than the sum of the width of the dummy gate and the width of the spacer layer, the fourth to seventh steps are repeated N times, and then the eighth step is performed.

5. A method for manufacturing a semiconductor device according to claim 3, further comprising: a fifth step of removing part or all of the spacer layer formed on the side wall of the semiconductor layer after the fourth step; and a sixth step of removing part of the semiconductor layer by anisotropic etching after the fifth step.

6. A method for manufacturing a semiconductor device according to claim 4, further comprising: a ninth step of removing part or all of the spacer layer formed on the side wall of the semiconductor layer after the eighth step; and a tenth step of removing part of the semiconductor layer by anisotropic etching after the ninth step.

7. A method for manufacturing a semiconductor device according to claim 6, further comprising an eleventh step of removing the first protective film and the second protective film after the ninth step or after the tenth step.

8. A method for manufacturing a semiconductor device according to claim 4, characterized in that a part or all of the first protective film is removed by the eighth step.

9. A method for manufacturing a semiconductor device according to claim 1 or claim 4, characterized in that the first protective film is a silicon oxide film and the second protective film is a silicon nitride film.

10. A method for manufacturing a semiconductor device according to claim 1 or claim 4, characterized in that, by the second step, the second protective film is formed such that the thickness of the second protective film formed on the upper surface of the dummy gate is greater than the thickness of the second protective film formed on surfaces other than the upper surface of the dummy gate.

11. A method for manufacturing a semiconductor device according to claim 7, characterized in that the first to eleventh steps are performed in the same plasma processing apparatus in which a sample on which a semiconductor device is formed is subjected to plasma treatment.

12. A plasma processing method characterized by comprising: a first step of forming a first protective film over a semiconductor layer formed in a linear shape to form a channel, and a spacer layer formed to cover a dummy gate formed in a linear shape perpendicular to the semiconductor layer; a second step of forming a second protective film different from the first protective film over the first protective film after the first step; a third step of selectively removing the second protective film formed on the sidewall of the dummy gate and the second protective film formed on the sidewall and upper surface of the semiconductor layer from the second protective film formed on the upper surface of the dummy gate by isotropic etching after the second step; and a fourth step of removing the first protective film formed on the sidewall of the semiconductor layer by anisotropic etching after the third step.

13. A plasma treatment method according to claim 12, characterized in that a part or all of the first protective film is removed by the fourth step.

14. A first step of forming a first protective film so as to cover a semiconductor layer formed in a linear shape to form a channel, and a spacer layer formed so as to cover a dummy gate formed in a linear shape perpendicular to the semiconductor layer; a second step of forming a second protective film different from the first protective film so as to cover the first protective film after the first step; a third step of selectively removing the second protective film formed on the side wall of the dummy gate and the second protective film formed on the side wall and top surface of the semiconductor layer from the second protective film formed on the top surface of the dummy gate by isotropic etching after the second step; a fourth step of removing the first protective film formed on the side wall of the dummy gate and the first protective film formed on the side wall and top surface of the semiconductor layer by isotropic etching; a fifth step of forming the first protective film so as to cover the spacer layer after the fourth step; A plasma processing method comprising: a sixth step of forming a second protective film so as to cover the first protective film after the fifth step; a seventh step of selectively removing the second protective film formed on the side wall of the dummy gate and the second protective film formed on the side wall and upper surface of the semiconductor layer from the second protective film formed on the upper surface of the dummy gate by isotropic etching after the sixth step; and an eighth step of removing the first protective film formed on the side wall of the semiconductor layer by anisotropic etching, wherein the first to third steps are performed, and when N is a natural number of 2 or more, the fourth to seventh steps are repeated N times after the first to third steps are performed; and after the fourth to seventh steps are repeated N times, if the width of the second protective film formed on the upper surface of the dummy gate and present in the uppermost layer is greater than the sum of the width of the dummy gate and the width of the spacer layer, the fourth to seventh steps are repeated N times, and then the eighth step is performed.

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