Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which the occurrence of cracks during firing in a firing furnace can be suppressed.　A multilayer ceramic capacitor according to the present invention comprises: a multilayer body including a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, the multilayer body having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction orthogonal to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction orthogonal to the stacking direction and the first direction; and first to fourth external electrodes disposed on the multilayer body. The plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers. The first internal electrode layer includes a first counter electrode portion facing the second internal electrode layer via the dielectric layer, a first extension portion extending from the first counter electrode portion and led out to the fifth surface, and a second extension portion extending from the first counter electrode portion and led out to the sixth surface. The dielectric layer on which the first internal electrode layer is disposed includes a first side portion located between the fifth surface and the first counter electrode portion and including the first extension portion, and a second side portion located between the sixth surface and the first counter electrode portion and including the second extension portion. The size of the multilayer ceramic capacitor in the first direction is 0.30 mm-0.70 mm, and the size of the multilayer ceramic capacitor in the second direction is 0.10 mm-0.40 mm. In the first and second side portions, the Ni content in one and the Ni content in the other are different from each other with respect to the first and second extension portions as the center.

Description

Multilayer Ceramic Capacitor

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] For example, decoupling capacitors used to stabilize the power supply voltage supplied to high-speed operating integrated circuit components (ICs), and feed-through multilayer ceramic capacitors used for noise suppression on power supply lines supplying integrated circuit components (ICs) are known. In general, a feed-through multilayer ceramic capacitor includes a ceramic base (laminated body) having an outer surface formed of first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end faces opposing each other. Inside the ceramic base, a plurality of first internal electrodes and a plurality of second internal electrodes are alternately arranged in the lamination direction. Both ends of each first internal electrode are led out to the first side surface and the second side surface, and connected to a third external electrode and a fourth external electrode respectively. Both ends of each second internal electrode are led out to the first end face and the second end face, and connected to a first external electrode and a second external electrode respectively.

[0003] Generally, in the process of firing a multilayer chip, the chips are mounted on a setter, and firing is performed by passing the setter through a tunnel kiln.

[0004] Japanese Unexamined Patent Publication No. 2003-022932

[0005] However, when the orientation of chips on the setter is random, temperature variations occur inside the chips when the chips enter the firing furnace, and there is a risk that cracks occur inside the chips due to dimensional shrinkage differences caused by such temperature variations.

[0006] Therefore, a main object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of cracks in the multilayer ceramic capacitor during firing in a firing furnace.

[0007] The multilayer ceramic capacitor according to this invention includes a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and comprises a laminate having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction, and a first external electrode disposed on the third surface, a second external electrode disposed on the fourth surface, a third external electrode disposed on the fifth surface, and a fourth external electrode disposed on the sixth surface, wherein the plurality of internal electrode layers have a plurality of first internal electrode layers and a plurality of second internal electrode layers, and the first internal electrode layers face each other with respect to the second internal electrode layers via the dielectric layer. The dielectric layer on which the first internal electrode layer is arranged has a first opposing electrode portion, a first extension portion extending from the first opposing electrode portion and drawn out to a fifth surface, and a second extension portion extending from the first opposing electrode portion and drawn out to a sixth surface, and has a first side portion located between the fifth surface and the first opposing electrode portion and including the first extension portion, and a second side portion located between the sixth surface and the first opposing electrode portion and including the second extension portion, the size of the multilayer ceramic capacitor in the first direction is 0.30 mm or more and 0.70 mm or less, the size of the multilayer ceramic capacitor in the second direction is 0.10 mm or more and 0.40 mm or less, and the first and second side portions have different Ni content in one and the other, centered on the first and second extension portions.

[0008] Generally, in the process of firing multilayer chips, the multilayer chips are mounted in a sheath, and the firing is performed by passing the sheath through a tunnel firing furnace. However, if the orientation of the multilayer chips on the sheath is random, temperature variations occur within the multilayer chip when it enters the firing furnace, and there is a risk that cracks will occur inside the multilayer chip due to the resulting difference in dimensional shrinkage. In addition, as the size of the component decreases, the proportion of the area where the internal electrode layer is not printed relative to the total volume of the multilayer increases, so there is a risk that the effect of the difference in shrinkage between the area where the internal electrode layer is printed and the area where it is not printed will become larger. According to the multilayer ceramic capacitor of this invention, the dielectric layer on which the first internal electrode layer is arranged has a first side portion located between the fifth surface and the first opposing electrode portion and including a first extension portion, and a second side portion located between the sixth surface and the first opposing electrode portion and including a second extension portion. The size of the multilayer ceramic capacitor in the first direction is 0.30 mm or more and 0.70 mm or less, and the size of the multilayer ceramic capacitor in the second direction is 0.10 mm or more and 0.40 mm or less. The first and second side portions have different Ni content on one side and the other side, centered on the first and second extension portions. Therefore, sintering tends to proceed more easily on the side with a higher Ni content, resulting in a larger dimensional shrinkage rate. By placing the side with a lower Ni content into the firing furnace first, the difference in dimensional shrinkage due to temperature variations can be reduced, and structural defects can be suppressed.

[0009] This invention provides a multilayer ceramic capacitor that can suppress the occurrence of cracks in the multilayer ceramic capacitor during firing in a firing furnace.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings.

[0011] This is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. This is a cross-sectional view along line V-V in Figure 1. This is a cross-sectional view along line VI-VI in Figure 1. This is a cross-sectional view along line VII-VII in Figure 4. This is a cross-sectional view along line VIII-VIII in Figure 4. This is a modified dielectric layer on which the first internal electrode layer shown in Figure 7 is arranged. This is a modified dielectric layer on which the second internal electrode layer shown in Figure 8 is arranged.

[0012] 1. Multilayer Ceramic Capacitor The multilayer ceramic capacitor 10 according to the first embodiment of this invention will be described. The multilayer ceramic capacitor 10 is a through-type multilayer ceramic capacitor (a three-terminal multilayer ceramic capacitor).

[0013] Figure 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 2 is a top view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 3 is a bottom view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 4 is a side view showing an example of a multilayer ceramic capacitor according to an embodiment of the present invention. Figure 5 is a cross-sectional view taken along line V-V in Figure 1. Figure 6 is a cross-sectional view taken along line VI-VI in Figure 1. Figure 7 is a cross-sectional view taken along line VII-VII in Figure 4. Figure 8 is a cross-sectional view taken along line VIII-VIII in Figure 4.

[0014] As shown in Figures 1 to 8, the multilayer ceramic capacitor 10 includes, for example, a laminate 12 and an external electrode 30.

[0015] The laminate 12 has a plurality of stacked dielectric layers 14 and a plurality of internal electrode layers 16 stacked on the dielectric layers 14. The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b. Details of the first internal electrode layer 16a and the second internal electrode layer 16b will be described later.

[0016] The laminate 12 has a first surface 12a and a second surface 12b that are opposite to the stacking direction x, a third surface 12c and a fourth surface 12d that are opposite to the first direction y which is perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f that are opposite to the second direction z which is perpendicular to the stacking direction x and the first direction y.

[0017] The laminate 12 has a rectangular parallelepiped shape, and it is preferable that the corners and edges of the laminate 12 are rounded. The corners are the parts where three faces of the laminate 12 intersect, and the edges are the parts where two faces of the laminate 12 intersect. In addition, some or all of the first face 12a and the second face 12b, the third face 12c and the fourth face 12d, and the fifth face 12e and the sixth face 12f may have irregularities or other features formed on them.

[0018] The dimensions of the laminate 12 are not particularly limited.

[0019] The laminate 12 includes a volume-forming portion 18, and a first outer layer portion 20a located on the first surface 12a side and a second outer layer portion 20b located on the second surface 12b side, which are arranged to sandwich the volume-forming portion 18 in the stacking direction x.

[0020] In the capacitance forming section 18, the first internal electrode layer 16a and the second internal electrode layer 16b are alternately stacked via the dielectric layer 14.

[0021] The first outer layer 20a is located on the first surface 12a side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the first surface 12a and the capacitance forming portion 18 closest to the first surface 12a. The second outer layer 20b is located on the second surface 12b side of the laminate 12 and is an assembly of multiple dielectric layers 14 located between the second surface 12b and the capacitance forming portion 18 closest to the second surface 12b. Furthermore, the region sandwiched between the first outer layer 20a and the second outer layer 20b is the capacitance forming portion 18.

[0022] Here, as shown in Figure 5, the laminate 12 is located between the volume-forming portion 18 and the third surface 12c, and between the volume-forming portion 18 and the fourth surface 12d, and has ends (L-gap) 24a, 24b of the laminate 12 including the first lead portion 27a and the second lead portion 27b of the second internal electrode layer 16b.

[0023] The dielectric layer 14 can be made of a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as the ceramic material. Alternatively, a material may be used in which minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds are added to the main components.

[0024] The thickness of the dielectric layer 14 is preferably 0.30 μm or more and 2.00 μm or less. Furthermore, the number of dielectric layers 14 to be stacked is preferably 90 or more and 650 or less. Note that this number of dielectric layers 14 is the sum of the number of dielectric layers 14 in the capacitance forming section 18 and the number of dielectric layers 14 in the first outer layer section 20a and the second outer layer section 20b.

[0025] (Internal electrode layer) The internal electrode layer 16 has a first internal electrode layer 16a and a second internal electrode layer 16b.

[0026] The first internal electrode layer 16a is arranged on a plurality of dielectric layers 14. The first internal electrode layer 16a is also extended to the fifth surface 12e and the sixth surface 12f.

[0027] More specifically, as shown in Figure 7, the first internal electrode layer 16a extends between the fifth surface 12e and the sixth surface 12f of the laminate 12 and has a first opposing electrode portion 25a in its central part, a first extension portion 26a extending from the first opposing electrode portion 25a and drawn out to the fifth surface 12e, and a second extension portion 26b extending from the first opposing electrode portion 25a and drawn out to the sixth surface 12f. The first opposing electrode portion 25a is formed in a rectangular shape so as to extend in the direction of the third surface 12c and in the direction of the fourth surface 12d. The first opposing electrode portion 25a is located in the central part of the dielectric layer 14. The first extension portion 26a is exposed to the fifth surface 12e of the laminate 12, and the second extension portion 26b is exposed to the sixth surface 12f of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the third surface 12c and the fourth surface 12d of the laminate 12.

[0028] The shapes of the first opposing electrode portion 25a, the first extension portion 26a, and the second extension portion 26b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded.

[0029] The second internal electrode layer 16b is arranged on a plurality of dielectric layers 14. The second internal electrode layer 16b is also drawn out to a third surface 12c and a fourth surface 12d. The second internal electrode layer 16b is arranged on a dielectric layer 14 that is different from the dielectric layer 14 on which the first internal electrode layer 16a is arranged.

[0030] More specifically, as shown in Figure 8, the second internal electrode layer 16b extends between the third surface 12c and the fourth surface 12d of the laminate 12 and has a second opposing electrode portion 25b located in its central part, a first leading portion 27a extending from the second opposing electrode portion 25b and leading out to the third surface 12c of the laminate 12, and a second leading portion 27b extending from the second opposing electrode portion 25b and leading out to the fourth surface 12d of the laminate 12. The second opposing electrode portion 25b is located in the central part of the dielectric layer 14. The first leading portion 27a is exposed to the third surface 12c of the laminate 12, and the second leading portion 27b is exposed to the fourth surface 12d of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed to the fifth surface 12e and the sixth surface 12f of the laminate 12.

[0031] The shape of the second internal electrode layer 16b is not particularly limited, but it is preferably rectangular in plan view. Similarly, the shapes of the second opposing electrode portion 25b, the first lead portion 27a, and the second lead portion 27b of the second internal electrode layer 16b are not particularly limited, but they are preferably rectangular in plan view. However, the corners may be rounded.

[0032] The first opposing electrode portion 25a of the first internal electrode layer 16a and the second opposing electrode portion 25b of the second internal electrode layer 16b are facing each other. In this embodiment, the first opposing electrode portion 25a of the first internal electrode layer 16a and the second opposing electrode portion 25b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0033] The number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 37 to 300. Similarly, the number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 37 to 300. Therefore, the total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 74 to 600.

[0034] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.30 μm or more and 2.0 μm or less. The thickness of the second internal electrode layer 16b is also not particularly limited, but is preferably, for example, 0.30 μm or more and 2.0 μm or less.

[0035] Furthermore, by including a Sn layer between the first internal electrode layer 16a and the second internal electrode layer 16b and the dielectric layer 14, electric field concentration at the interface between the internal electrode layer 16 and the dielectric layer 14 can be mitigated, leading to improved high-temperature load reliability.

[0036] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0037] The dielectric layer 14 on which the first internal electrode layer 16a is arranged is located between the fifth surface 12e and the first opposing electrode portion 25a and has a first side portion 22a including a first extension portion 26a, and a second side portion 22b located between the sixth surface 12f and the first opposing electrode portion 25a and including a second extension portion 26b. The first side portion 22a in the dielectric layer 14 on which the first internal electrode layer 16a is arranged has one first side portion 22a1 located on the third surface 12c side and the other first side portion 22a2 located on the fourth surface 12d side, with the first extension portion 26a in between. The second side portion 22b of the dielectric layer 14 on which the first internal electrode layer 16a is arranged has a second side portion 22b1 located on the third surface 12c side and a second side portion 22b2 located on the fourth surface 12d side, with the second extension portion 26b in between.

[0038] The Ni content in one first side portion 22a1 is different from the Ni content in the other first side portion 22a2. For example, the Ni content in one first side portion 22a1 is greater than the Ni content in the other first side portion 22a2. The Ni content in one second side portion 22b1 is different from the Ni content in the other second side portion 22b2. For example, the Ni content in one second side portion 22b1 is greater than the Ni content in the other second side portion 22b2.

[0039] When the Ni content of the other first side portion 22a2 of the dielectric layer 14 on which the first internal electrode layer 16a is located is set to 1, the Ni content of the other first side portion 22a1 is 1.70 or more. When the Ni content of the other second side portion 22b2 of the dielectric layer 14 on which the first internal electrode layer 16a is located is set to 1, the Ni content of the other second side portion 22b1 is 1.70 or more.

[0040] When the brightness value of the other first side portion 22a2 of the dielectric layer 14 on which the first internal electrode layer 16a is located is set to 1, it is preferable that the brightness value of the other first side portion 22a1 is 0.98 or less. When the brightness value of the other second side portion 22b2 of the dielectric layer 14 on which the first internal electrode layer 16a is located is set to 1, it is preferable that the brightness value of the other second side portion 22b1 is 0.98 or less.

[0041] Furthermore, if the Ni content on the side opposite to the side that enters the firing furnace is increased too much, the dimensional shrinkage rate on the opposite side will increase, resulting in a difference in dimensional shrinkage and potentially causing structural defects. For this reason, when the Ni content of the other first side portion 22a2 and the other second side portion 22b2 is set to 1, it is preferable that the Ni content of one first side portion 22a1 and the other second side portion 22b1 be 2.65 or less. Also, when the luminance value of the other first side portion 22a2 and the other second side portion 22b2 is set to 1, it is preferable that the luminance value of one first side portion 22a1 and the other second side portion 22b1 be 0.86 or more.

[0042] The dielectric layer 14, on which the second internal electrode layer 16b is disposed, includes a third side portion 23a located between the fifth face 12e and the second counter electrode portion 25b, and a fourth side portion 23b located between the sixth face 12f and the second counter electrode portion 25b. The third side portion 23a in the dielectric layer 14 on which the second internal electrode layer 16b is disposed, centered at the position where the first extension portion 26a is located, includes one third side portion 23a1 located on the third face 12c side, and the other third side portion 23a2 located on the fourth face 12d side. The fourth side portion 23b in the dielectric layer 14 on which the second internal electrode layer 16b is disposed, centered at the position where the second extension portion 26b is located, includes one fourth side portion 23b1 located on the third face 12c side, and the other fourth side portion 23b2 located on the fourth face 12d side.

[0043] The Ni content in said one third side portion 23a1 may be different from the Ni content in said other third side portion 23a2. For example, the Ni content in said one third side portion 23a1 may be higher than the Ni content in said other third side portion 23a2. The Ni content in said one fourth side portion 23b1 may be different from the Ni content in said other fourth side portion 23b2. For example, the Ni content in said one fourth side portion 23b1 may be higher than the Ni content in said other fourth side portion 23b2.

[0044] Note that, as shown in FIG. 9, the entire first side portion 22a in the dielectric layer 14 on which the first internal electrode layer 16a is disposed may be a region with a low Ni content, and the entire second side portion 22b may be a region with a higher Ni content than the Ni content in the entire first side portion 22a. Further, as shown in FIG. 10, the entire third side portion 23a in the dielectric layer 14 on which the second internal electrode layer 16b is disposed may be a region with a low Ni content, and the entire fourth side portion 23b may be a region with a higher Ni content than the Ni content in the entire third side portion 23a.

[0045] (External electrodes) External electrodes 30 are disposed on the third face 12c side and the fourth face 12d side, as well as the fifth face 12e side and the sixth face 12f side of the laminate 12. The external electrode 30 includes a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0046] The first external electrode 30a is disposed on the third face 12c. Also, the first external electrode 30a is connected to the second internal electrode layer 16b. Furthermore, the first external electrode 30a may also be disposed on part of the first face 12a, part of the second face 12b, part of the fifth face 12e, and part of the sixth face 12f.

[0047] The second external electrode 30b is disposed on the fourth face 12d. Also, the second external electrode 30b is connected to the second internal electrode layer 16b. Furthermore, the second external electrode 30b may also be disposed on part of the first face 12a, part of the second face 12b, part of the fifth face 12e, and part of the sixth face 12f.

[0048] The third external electrode 30c is disposed on the fifth face 12e. Also, the third external electrode 30c is connected to the first internal electrode layer 16a. Furthermore, the third external electrode 30c may optionally include: a first covering portion 30c1 covering the first internal electrode layer 16a exposed at the fifth face 12e, a first folded portion 30c2 formed on the first face 12a in parallel with the first internal electrode layer 16a, and a second folded portion 30c3 formed on the second face 12b in parallel with the first internal electrode layer 16a. By including the second folded portion 30c3, the reliability of electrical connection with the mounting substrate 50 can be further maintained.

[0049] The fourth external electrode 30d is positioned on the sixth surface 12f. The fourth external electrode 30d is also connected to the first internal electrode layer 16a. Furthermore, the fourth external electrode 30d may have a second covering portion 30d1 (not shown) that covers the first internal electrode layer 16a exposed on the sixth surface 12f, a third folded portion 30d2 formed on the first surface 12a parallel to the first internal electrode layer 16a, and a fourth folded portion 30d3 formed on the second surface 12b parallel to the first internal electrode layer 16a. Having the fourth folded portion 30d3 allows for better maintenance of electrical connection reliability with the mounting substrate 50.

[0050] The external electrode 30 includes a base electrode layer 32 placed on the surface of the laminate 12 and a plating layer 34 placed so as to cover the base electrode layer 32.

[0051] The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0052] The plating layer 34 has a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0053] In other words, the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. The second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. The third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c. The fourth external electrode 30d has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0054] The first base electrode layer 32a is placed on the surface of the third surface 12c of the laminate 12 and is formed to extend from the third surface 12c and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The second base electrode layer 32b is placed on the surface of the fourth surface 12d of the laminate 12 and is formed to extend from the fourth surface 12d and cover a portion of each of the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f. The first base electrode layer 32a may be placed only on the surface of the third surface 12c of the laminate 12, and the second base electrode layer 32b may be placed only on the surface of the fourth surface 12d of the laminate 12.

[0055] The third base electrode layer 32c is placed on the surface of the fifth surface 12e of the laminate 12 and is formed to extend from the fifth surface 12e and cover parts of the first surface 12a and the second surface 12b, respectively. The fourth base electrode layer 32d is placed on the surface of the sixth surface 12f of the laminate 12 and is formed to extend from the sixth surface 12f and cover parts of the first surface 12a and the second surface 12b, respectively.

[0056] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer will be described below.

[0057] (In the case of a baked layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is obtained by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be obtained by simultaneously baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 and the conductive paste applied to the laminate chip, or by baking the laminate chip having the internal electrode layer 16 and the dielectric layer 14 to obtain the laminate 12, and then applying the conductive paste to the laminate 12 and baking it. Furthermore, when firing a laminated chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the laminated chip simultaneously, it is preferable to form the firing layer by firing a material to which a dielectric material has been added instead of a glass component.

[0058] The thickness of the first base electrode layer 32a located on the third surface 12c in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably 10 μm or more and 50 μm or less. Similarly, the thickness of the second base electrode layer 32b located on the fourth surface 12d in the first direction y connecting the third surface 12c and the fourth surface 12d at the center of the lamination direction x is preferably 10 μm or more and 50 μm or less.

[0059] When the first base electrode layer 32a is provided on a part of the first surface 12a and a part of the second surface 12b, and a part of the fifth surface 12e and a part of the sixth surface 12f, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the first surface 12a and the second surface 12b is preferably, for example, 5 μm or more and 20 μm or less. Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the first base electrode layer 32a located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 5 μm or more and 20 μm or less.

[0060] Furthermore, when the second base electrode layer 32b is provided on a part of the first surface 12a and a part of the second surface 12b, and a part of the fifth surface 12e and a part of the sixth surface 12f, the thickness in the stacking direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the first surface 12a and the second surface 12b is preferably, for example, 5 μm or more and 20 μm or less. Moreover, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the second base electrode layer 32b located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 5 μm or more and 20 μm or less.

[0061] The thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the third base electrode layer 32c, located on the fifth surface 12e, is preferably 5 μm or more and 20 μm or less. Furthermore, the thickness in the second direction z connecting the fifth surface 12e and the sixth surface 12f at the center of the first direction y connecting the third surface 12c and the fourth surface 12d of the fourth base electrode layer 32d, located on the sixth surface 12f, is preferably 5 μm or more and 20 μm or less.

[0062] The thickness of the third base electrode layer 32c located on the first surface 12a in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 1 μm or more and 20 μm or less. Similarly, the thickness of the fourth base electrode layer 32d located on the first surface 12a in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 1 μm or more and 20 μm or less.

[0063] The thickness of the third base electrode layer 32c located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 1 μm or more and 20 μm or less. Similarly, the thickness of the fourth base electrode layer 32d located on the second surface 12b in the lamination direction x connecting the first surface 12a and the second surface 12b at the center of the first direction y connecting the third surface 12c and the fourth surface 12d is preferably, for example, 1 μm or more and 20 μm or less.

[0064] (In the case of a conductive resin layer) The conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover a part of the baking layer. In addition, there may be multiple conductive resin layers.

[0065] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0066] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0067] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Alternatively, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0068] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0069] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0070] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0071] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0072] The thickest part of the conductive resin layer is preferably, for example, 5 μm or more and 25 μm or less.

[0073] (In the case of a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0074] The plating layer 34 is positioned to cover the underlying electrode layer 32.

[0075] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0076] The plating layer 34 may be formed from multiple layers. In this case, the plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating. The Ni plating layer is used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer is used to improve the wettability of the solder when mounting the multilayer ceramic capacitor 10, thereby facilitating mounting. The thickness of each layer of the plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0077] Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. Although not shown in the figures, a structure in which the plating layer is provided without the underlayer electrode layer 32 will be described below.

[0078] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, or each of them, may have a plating layer directly formed on the surface of the laminate 12 without providing an underlay electrode layer 32. That is, the multilayer ceramic capacitor 10 may have a structure that includes a plating layer electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. In such a case, the plating layer may be formed after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0079] Furthermore, if the plating layer is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be converted into a lower profile, i.e., a thinner design, or into the thickness of the laminate 12, i.e., the thickness of the capacitance forming section 18, thereby improving the design flexibility of the thin chip.

[0080] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such a metal. Furthermore, the lower plating electrode is preferably formed using Ni, which has solder barrier properties, and the upper plating electrode is preferably formed using Sn or Au, which has good solder wettability.

[0081] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may each consist only of the lower plated electrode. The plating layer may have the upper plated electrode as the outermost layer, or other plated electrodes may be formed on the surface of the upper plated electrode.

[0082] In this case, when the external electrode 30 is formed using only the plating layer without providing the underlayer electrode layer 32, it is preferable that the thickness of each plating layer placed without the underlayer electrode layer 32 is 1 μm or more and 15 μm or less.

[0083] Furthermore, it is preferable that the plating layer does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0084] The dimension of the multilayer ceramic capacitor 10 in the first direction y is denoted as dimension L. Dimension L is between 0.30 mm and 0.70 mm. The dimension of the multilayer ceramic capacitor 10 in the stacking direction x is denoted as dimension T. Dimension T is between 0.10 mm and 0.40 mm. The dimension of the multilayer ceramic capacitor 10 in the second direction z is denoted as dimension W. Dimension W is between 0.10 mm and 0.40 mm.

[0085] Generally, in the process of firing multilayer chips, the multilayer chips are mounted in a sheath, and the firing is performed by passing the sheath through a tunnel firing furnace. However, if the orientation of the multilayer chips on the sheath is random, temperature variations occur within the multilayer chip when it enters the firing furnace, and there is a risk that cracks will occur inside the multilayer chip due to the resulting difference in dimensional shrinkage. In the multilayer ceramic capacitor 10 shown in Figure 1, the Ni content in one first side portion 22a1 is different from the Ni content in the other first side portion 22a2, and the Ni content in one second side portion 22b1 is different from the Ni content in the other second side portion 22b2. Because sintering tends to proceed more easily and the dimensional shrinkage rate is larger on the side with a higher Ni content, by having the side with a lower Ni content enter the firing furnace first, the difference in dimensional shrinkage due to temperature variations can be reduced and structural defects can be suppressed.

[0086] Furthermore, according to the multilayer ceramic capacitor 10 shown in Figure 1, when the brightness value of the other first side portion 22a2 of the first internal electrode layer 16a is set to 1, the brightness value of the other first side portion 22a1 is set to 0.98 or less, and when the brightness value of the other second side portion 22b2 of the first internal electrode layer 16a is set to 1, the brightness value of the other second side portion 22b1 is set to 0.98 or less. This difference in color between the first and second side portions 22a1, 22b1 and the other first and second side portions 22a2, 22b2 makes it possible to align the multilayer chips in a certain direction, and to align them so that the side with a lower Ni content is entered into the firing furnace first.

[0087] 2. Method for Manufacturing a Multilayer Ceramic Capacitor Next, a method for manufacturing a multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0088] First, a dielectric sheet for the dielectric layer and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known substances.

[0089] A conductive paste for the internal electrode layer is printed onto the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer formed on it, and a dielectric sheet with the pattern for the second internal electrode layer formed on it.

[0090] More specifically, a gravure printing plate for forming the first internal electrode layer and the second internal electrode layer can be prepared, and the internal electrode layers can be formed.

[0091] Next, after forming the patterns for the first and second internal electrode layers by gravure printing, Ni powder is sprayed onto one first side and the other first side, for example, by inkjet printing, so that their respective Ni content differs. Similarly, Ni powder is sprayed onto one second side and the other second side, also by inkjet printing, so that their respective Ni content differs. At this time, it is preferable that the particle size of the sprayed Ni powder is 1 / 10 or less of the Ni particle size of the internal electrode layer. This makes it easier to shrink.

[0092] Next, a predetermined number of dielectric sheets without the internal electrode layer pattern printed on them are stacked to form the second outer layer portion 20b on the second surface 12b side. Then, a portion that will become the capacitance forming portion 18 is formed by alternately stacking sheets with the first internal electrode layer printed on them and sheets with the second internal electrode layer printed on them. Then, a predetermined number of dielectric sheets without the internal electrode layer pattern printed on them are stacked on top of the capacitance forming portion to form the first outer layer portion 20a on the first surface 12a side. This completes the production of the laminated sheet.

[0093] Next, the laminated sheets are pressed in the lamination direction using means such as hydrostatic pressing to produce a laminated block.

[0094] Next, the laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0095] Then, the cut laminated chips are fired to produce the laminated body 12 (fired laminated chip process). The firing temperature in the fired laminated chip process depends on the materials of the dielectric layer 14 and the internal electrode layer 16, but is preferably between 900°C and 1400°C.

[0096] The firing process for the laminated chips is carried out as follows: First, the laminated chips are placed on a pallet with the LT surface (the surface containing the first direction y and the stacking direction x) facing outwards. After placing them on the pallet, for example, image analysis using a camera is used to determine the difference in color of the side located on the fifth or sixth surface of the laminated chip. Then, the laminated chips in the pallet are picked up by a mounter and aligned in a sheath so that the direction is aligned by the color of the fifth or sixth surface of the laminated chip.

[0097] The structure obtained by the above manufacturing method has different colorations on the fifth and sixth sides, which allows the laminated chips to be aligned in a specific direction, and enables alignment so that the side with the lower Ni content is entered into the firing furnace first. Since a higher Ni content tends to lead to faster sintering and a larger dimensional shrinkage rate, it is possible to reduce dimensional shrinkage differences due to temperature variations and suppress structural defects.

[0098] (Underlayment electrode layer) Next, a third underlayment electrode layer 32c of the third external electrode 30c is formed on the fifth surface 12e of the laminate 12 obtained by firing, and a fourth underlayment electrode layer 32d of the fourth external electrode 30d is formed on the sixth surface 12f of the laminate 12.

[0099] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the baked layer as the base electrode layer 32. The temperature of the baking process at this time is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed of a baked layer.

[0100] Here, various methods can be used for forming the baked layer. For example, a method can be used in which the orientation of the laminate 12 is aligned using a camera or magnet so that the fifth surface 12e or the sixth surface 12f is facing downwards, and then the laminate 12 is held with a holding jig, and conductive paste is extruded and applied through slits or holes. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the fifth surface 12e and the sixth surface 12f, but also on a part of the first surface 12a and a part of the second surface 12b.

[0101] Next, a first base electrode layer 32a of the first external electrode 30a is formed on the third surface 12c of the laminate 12 obtained by firing, and a second base electrode layer 32b of the second external electrode 30b is formed on the fourth surface 12d of the laminate 12. In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using a dip method so as to extend not only to the third surface 12c and the fourth surface 12d, but also to a part of the first surface 12a, a part of the second surface 12b, a part of the fifth surface 12e, and a part of the sixth surface 12f.

[0102] The baking process may involve baking the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d simultaneously, or the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d separately.

[0103] (Conductive resin layer) When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baked layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baked layer.

[0104] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, in order to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm.

[0105] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, such as a dipping method, a method of applying the conductive resin paste by extruding it through a slit, or a roller transfer method.

[0106] (Thin film layer) When the base electrode layer 32 is formed as a thin film layer, masking can be performed and the base electrode layer 32 can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited.

[0107] (Plating layer) Furthermore, the external electrode 30 may be formed using only the plating layer without providing the underlayer electrode layer 32. In that case, it can be formed by the following method.

[0108] Plating is applied to the third surface 12c and the fourth surface 12d of the laminate 12 to form a lower layer plated electrode on the exposed portion of the second internal electrode layer 16b. Similarly, plating is applied to the fifth surface 12e and the sixth surface 12f of the laminate 12 to form a lower layer plated electrode on the exposed portion of the first internal electrode layer 16a. When performing the plating, either electrolytic plating or electroless plating may be used, but electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred. As for the plating method, barrel plating is preferred. Also, if necessary, the upper layer plated electrode formed on the surface of the lower layer plated electrode may be formed in the same manner.

[0109] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as the lower plating layer, and a Sn plating layer is formed as the upper plating layer. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating requires pretreatment with a catalyst or the like to improve the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0110] As described above, the multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0111] 4. Experimental Example Next, in order to confirm the effect of the multilayer ceramic capacitor according to the present invention described above, a multilayer ceramic capacitor was manufactured as an experimental sample.

[0112] (1) Specifications of the multilayer ceramic capacitors prepared as samples for the experimental examples Multilayer ceramic capacitors, which are the samples for the comparative example and Examples 1 to 5, were prepared using the manufacturing method according to the above embodiment. • Structure of the multilayer ceramic capacitor: 3 terminals (see Figure 1) • Dimensions of the multilayer ceramic capacitor (L): 0.665 mm • Dimensions of the multilayer ceramic capacitor (W): 0.370 mm • Dimensions of the multilayer ceramic capacitor (T): 0.330 mm • Thickness of the dielectric layer located in the capacitance formation area: 0.48 μm • Thickness of the internal electrode layer: 0.38 μm • Number of first internal electrode layers: 155 • Number of second internal electrode layers: 155 • Thickness of the first outer layer: 22 μm • Thickness of the second outer layer: 22 μm • Dimension in the first direction between the capacitance formation area and the third and fourth surfaces: 43 μm • Dimension in the second direction of the first to fourth sides: 39 μm • Structure of the external electrodes: • First external electrode and second external electrode • Underlay electrode layer: Baked layer containing conductive metal (Cu) and glass component • Plating layer Ni plating layer and Sn plating layer (two-layer structure) Third external electrode and fourth external electrode Underlay electrode layer: Baked layer containing conductive metal (Cu) and glass component Plating layer: Ni plating layer and Sn plating layer (two-layer structure)

[0113] In the sample of the example, the Ni content in one first side of the first internal electrode layer was greater than the Ni content in the other first side. Furthermore, the Ni content in one second side was greater than the Ni content in the other second side.

[0114] In the comparative example sample, the Ni content in one first side and the Ni content in the other first side were set to be approximately the same. Furthermore, the Ni content in one second side and the Ni content in the other second side were set to be approximately the same.

[0115] For firing, the laminated chips were aligned in a specific direction, and the first and second sides with lower Ni content were placed into the firing furnace first. The Ni content and brightness values ​​were measured on the fifth or sixth surface (the LT surface, which includes the first direction y and the lamination direction x).

[0116] (2) Evaluation Method Ni content measurement method: The Ni content ratio of each side was measured on the fifth or sixth surface (LT surface, which is the surface containing the first direction y and the stacking direction x) by elemental mapping using WDX analysis (wavelength dispersive X-ray analysis) with an electron microscope. The Ni content measured here was taken as the Ni content of each side. Ni content measuring instrument: Electron microscope JXA-8500F

[0117] Method for measuring luminance values: The amount of light emitted from the surface of the fifth or sixth surface (the LT surface, which includes the first direction y and the stacking direction x) was measured using a luminance meter. The amount of light measured here was defined as the amount of light on each side. Method for confirming internal defect structure: The incidence of horizontal cracks was confirmed for each sample using ultrasonic testing (SAT: Scanning Acoustic Tomography).

[0118] (3) Results Table 1 shows the evaluation results of internal structural defects in each sample of Examples 1 to 5 and the Comparative Examples, with respect to the change in the ratio of Ni content and brightness value of one of the first and second sides, when the other first and second side is set to 1.

[0119]

[0120] In each of the samples from Examples 1 to 5, no internal structural defects were observed because the Ni content of one first and second side differed from that of the other first and second side. Furthermore, when the Ni content of one first and second side was varied while the Ni content of the other first and second side was set to 1, no internal structural defects were observed when the value was at least 1.70 or higher.

[0121] Furthermore, when the luminance values ​​of one of the first and second sides were changed while the luminance values ​​of the other first and second side were set to 1, no internal structural defects were found when the values ​​were at least 0.98 or less.

[0122] On the other hand, in the comparative example sample, since the Ni content in one of the first and second sides was approximately the same as that in the other first and second side, a sample with internal structural defects was generated.

[0123] From these results, it became clear that a higher Ni content tends to facilitate sintering and result in a greater difference in dimensional shrinkage rates, thus reducing dimensional shrinkage differences due to temperature variations and suppressing structural defects. Furthermore, the different coloration of the sides of one and the other makes it possible to align the laminated sample in a certain direction, allowing the side with the lower Ni content to enter the firing furnace first.

[0124] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, without departing from the scope of the technical idea and objectives of the present invention, various modifications can be made to the embodiments described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention.

[0125] 10 Multilayer ceramic capacitor 12 Laminate 12a First surface 12b Second surface 12c Third surface 12d Fourth surface 12e Fifth surface 12f Sixth surface 14 Dielectric layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18 Capacitance forming section 20a First outer layer 20b Second outer layer 22a First side 22b Second side 23a Third side 23b Fourth side 24a, 24b L gap 25a First opposing electrode section 25b Second opposing electrode section 26a First extension section 26b Second extension section 27a First lead section 27b Second lead section 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 30c1 First covering portion 30c2 First folded portion 30c3 Second folded portion 30d1 Second covering portion 30d2 Third folded portion 30d3 Fourth folded portion 32 Underlay electrode layer 32a First underlay electrode layer 32b Second underlay electrode layer 32c Third underlay electrode layer 32d Fourth underlay electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer x Lamination direction y First direction z Second direction L Dimension of the multilayer ceramic capacitor in the first direction W Dimension of the multilayer ceramic capacitor in the second direction T Dimension of the multilayer ceramic capacitor in the lamination direction

Claims

1. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the third surface; a second external electrode disposed on the fourth surface; a third external electrode disposed on the fifth surface; and a fourth external electrode disposed on the sixth surface, wherein the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers, and the first internal electrode layer includes a first opposing electrode portion facing the second internal electrode layer via the dielectric layer, and a first extension portion extending from the first opposing electrode portion and drawn out to the fifth surface, A multilayer ceramic capacitor having: a second extension extending from the first opposing electrode portion and drawn out to the sixth surface, wherein the dielectric layer on which the first internal electrode layer is disposed has: a first side portion located between the fifth surface and the first opposing electrode portion and including the first extension portion; and a second side portion located between the sixth surface and the first opposing electrode portion and including the second extension portion, wherein the size of the multilayer ceramic capacitor in the first direction is 0.30 mm or more and 0.70 mm or less; the size of the multilayer ceramic capacitor in the second direction is 0.10 mm or more and 0.40 mm or less; and the first and second side portions have different Ni content in one and the other, centered on the first and second extension portions.

2. The multilayer ceramic capacitor according to claim 1, wherein when the Ni content of the side with a low Ni content in the first and second sides is set to 1, the Ni content of the side with a high Ni content in the first and second sides is 1.70 or more.

3. The multilayer ceramic capacitor according to claim 1, wherein when the luminance value of the side with a low Ni content on the first and second sides is set to 1, the luminance value of the side with a high Ni content on the first and second sides is 0.98 or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the second internal electrode layer has a second opposing electrode portion that faces the first internal electrode layer via the dielectric layer, and the dielectric layer on which the second internal electrode layer is disposed has a third side portion located between the fifth surface and the second opposing electrode portion, and a fourth side portion located between the sixth surface and the second opposing electrode portion, and the third and fourth side portions of the second internal electrode layer have different Ni content in one and the other, centered on the location where the first and second extensions of the first internal electrode layer are located.

5. A multilayer ceramic capacitor comprising: a laminate including a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, having a first surface and a second surface facing each other in the stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the third surface; a second external electrode disposed on the fourth surface; a third external electrode disposed on the fifth surface; and a fourth external electrode disposed on the sixth surface, wherein the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers, and the first internal electrode layer includes a first opposing electrode portion facing the second internal electrode layer via the dielectric layer, and a first extension portion extending from the first opposing electrode portion and drawn out to the fifth surface, A multilayer ceramic capacitor having: a second extension extending from the first opposing electrode portion and drawn out to the sixth surface, wherein the dielectric layer on which the first internal electrode layer is disposed has: a first side portion located between the fifth surface and the first opposing electrode portion and including the first extension portion; and a second side portion located between the sixth surface and the first opposing electrode portion and including the second extension portion, wherein the size of the multilayer ceramic capacitor in the first direction is 0.30 mm or more and 0.70 mm or less; the size of the multilayer ceramic capacitor in the second direction is 0.10 mm or more and 0.40 mm or less; and the Ni content of the first side portion and the Ni content of the second side portion are different.

6. The multilayer ceramic capacitor according to claim 5, wherein when the Ni content of the first side is 1, the Ni content of the second side is 1.70 or more.

7. The multilayer ceramic capacitor according to claim 6, wherein when the luminance value of the first side is set to 1, the luminance value of the second side is 0.98 or less.

8. The multilayer ceramic capacitor according to claim 7, wherein the second internal electrode layer has a second opposing electrode portion that faces the first internal electrode layer via the dielectric layer, and the dielectric layer on which the second internal electrode layer is disposed has a third side portion located between the fifth surface and the second opposing electrode portion, and a fourth side portion located between the sixth surface and the second opposing electrode portion, wherein the Ni content of the third side portion and the Ni content of the fourth side portion are different.

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