Power converter and power conversion device

Abstract

The power converter according to an embodiment of the present invention is interconnected to a power system and has a number of phase circuits corresponding to the number of phases of the power system. Each phase circuit has an arm, a first reactor and a first current detector, and at least one of a second reactor and a second current detector. In the arm, a plurality of cells, which each comprises a plurality of self-arc-extinguishing semiconductor elements and an electricity storage element, are connected in series. The first reactor and the first current detector are provided on one end side of the arm. At least one of the second reactor and the second current detector is provided on the other end side of the arm.

Description

Power converter and power conversion device

[0001] Embodiments of the present invention relate to a power converter and a power conversion device.

[0002] In recent years, the adoption of renewable energy such as solar power generation or wind power generation has been expanding. Along with the increase in electric power supplied from renewable energy, there is concern that the voltage of the power grid may become unstable. For this reason, demand for static synchronous compensators (STATCOM: STATic synchronous COMpensator) is expanding for stable operation of power grids. A STATCOM compensates reactive power using a self-excited conversion device.

[0003] In addition, in recent years, there have been an increasing number of cases where a modular multilevel converter (MMC: Modular Multilevel Converter) is applied as the circuit topology of a STATCOM. An MMC is a type of power converter, configured by connecting multiple stages of small-capacity converters called cells, and can control the AC-side output voltage in multiple levels according to the number of cell stages, so it has the advantage of eliminating the need for an AC filter that was required conventionally. The MMC is connected to the power grid via an interconnection transformer. The following Patent Documents 1 and 2 disclose an example of a power conversion device including such an MMC.

[0004] In the above-described power conversion device including an MMC, when a short-circuit fault or a ground fault occurs in the wiring between cells or in the wiring between multi-stage connected cells and the interconnection transformer, an excessive fault current is generated. Depending on the fault location, for example, the current increase rate becomes extremely large, causing an excessive current to flow in a short time, or it takes time to detect the fault, causing an excessive current to flow through the cells, which may lead to destruction of the power conversion device.

[0005] Japanese Unexamined Patent Application Publication No. 2023-151956 Japanese Unexamined Patent Application Publication No. 2023-77795

[0006] The problem to be solved by the present invention is to provide a power converter and a power conversion device that can reduce the fault current flowing through cells when a short-circuit fault or a ground fault occurs.

[0007] The power converter of this embodiment is connected to a power system and has a number of phase circuits corresponding to the number of phases in the power system. The phase circuit has an arm, a first reactor and a first current detector, and at least one of a second reactor and a second current detector. The arm is made up of multiple cells connected in series, each cell comprising a plurality of self-extinguishing semiconductor elements and an energy storage element. The first reactor and the first current detector are provided on one end of the arm. At least one of the second reactor and the second current detector is provided on the other end of the arm.

[0008] A block diagram showing the main components of a power converter and power converter according to the first embodiment. A diagram showing an example of the configuration of a cell used in a power converter. A diagram showing another example of the configuration of a cell used in a power converter. A diagram for explaining the fault current that flows when a short-circuit fault or ground fault occurs in the power converter according to the first embodiment. A diagram showing an example of the current detected in the power converter according to the first embodiment. A block diagram showing the main components of a power converter and power converter according to the second embodiment. A block diagram showing the main components of a power converter and power converter according to the third embodiment. A block diagram showing the main components of a power converter and power converter according to the fourth embodiment. A block diagram showing the main components of a power converter and power converter according to the fifth embodiment. A block diagram showing the main components of a power converter and power converter according to the sixth embodiment. A block diagram showing the main components of a power converter and power converter according to the seventh embodiment. A block diagram showing the main components of a power converter and power converter according to the eighth embodiment.

[0009] The power converter and power conversion device of the embodiment will be described below with reference to the drawings.

[0010] (First Embodiment) Figure 1 is a block diagram showing the main components of a power converter and power conversion device according to the first embodiment. The power conversion device 1 shown in Figure 1 is installed (connected) in parallel to the power system and aims to stabilize the AC power of the power system by compensating (adjusting) the reactive power output (supplied) to the power system.

[0011] A power system is, for example, an AC power source or an AC load. A power system is, for example, a three-phase AC system consisting of the first phase (Phase A), the second phase (Phase B), and the third phase (Phase C). Power converter 1 is, for example, a static reactive power compensator (STATCOM). In the following description, the connection point between power converter 1 and the power system is referred to as the interconnection point. Furthermore, in the following description, unless otherwise specified, the three phases will not be distinguished.

[0012] As shown in Figure 1, the power converter 1 comprises a power converter 10 and a control device 20. The power converter 10 stabilizes the grid voltage in the power system by supplying AC power (reactive power) to the interconnection point or consuming the reactive power at the interconnection point, in accordance with the control device 20. The reactive power supplied or consumed by the power converter 10 is either positive-sequence reactive power or negative-sequence reactive power.

[0013] Here, positive phase refers to a situation where, for example, in a power system with three phases (A, B, and C), the phase sequence of the AC current supplied to the interconnection point is shifted by 120° in the order of A, B, and C phases. In contrast, negative phase refers to a situation where the phase sequence of the AC voltage is supplied in a different order from the positive phase, such as A, C, and B phases.

[0014] The power converter 10 comprises, for example, a transformer 11 and a modular multilevel converter (MMC) 12. The transformer 11 may be, for example, a three-phase transformer, or it may be a configuration in which three single-phase transformers, each corresponding to one of the three phases, are connected. In some cases, it may be directly connected to the power grid without a transformer. The power converter 10 outputs an AC voltage from the MMC 12 in response to control from the control device 20, thereby supplying an AC current corresponding to the control from the control device 20.

[0015] The MMC12 is a delta-connected MMC. The MMC12 includes, for example, three phase circuits 12a, 12b, and 12c corresponding to each of the three phases. In the MMC12, the ends of the phase circuits 12a, 12b, and 12c are connected to different phases in the transformer 11, thereby forming a delta-connected circuit in which the three phase circuits 12a, 12b, and 12c are delta-connected.

[0016] Phase circuits 12a, 12b, and 12c have a similar configuration and include a buffer reactor 31 (first reactor), a current detector 32 (first current detector), an arm 33, a current detector 34 (second current detector), and a buffer reactor 35 (second reactor). In the diagram, buffer reactors 31 and 35 are denoted as "BT," and current detectors 32 and 34 are denoted as "CT."

[0017] In each of the phase circuits 12a, 12b, and 12c, the buffer reactor 31, current detector 32, arm 33, current detector 34, and buffer reactor 35 are connected in series in this order. In other words, phase circuits 12a, 12b, and 12c are first phase circuits in which the current detector 32 is provided between the buffer reactor 31 and the arm 33, and the current detector 34 is provided between the buffer reactor 35 and the arm 33.

[0018] The buffer reactor 31 is an impedance element having an impedance component for suppressing changes in the current flowing through the arm 33. One end of the buffer reactor 31 is connected to the transformer 11, and the other end is connected to the current detector 32. The current detector 32 detects the current flowing between the buffer reactor 31 and the arm 33.

[0019] Arm 33 is configured, for example, to have multiple cells CL connected in series. In other words, Arm 33 is composed of multiple stages of cells CL. Each cell CL is a small-capacitance converter. Cell CL comprises multiple self-extinguishing semiconductor elements and an energy storage element. The semiconductor elements are, for example, insulated gate bipolar transistors (IGBTs). The semiconductor elements operate (switching operation) in response to control (switching control) from the control device 20. The energy storage element is, for example, a DC capacitor. However, the energy storage element is not limited to a capacitor; any element with an energy storage function is acceptable. The detailed configuration of cell CL will be described later.

[0020] The current detector 34 detects the current flowing between the buffer reactor 35 and the arm 33. The same current detector 34 as the current detector 32 can be used. The buffer reactor 35, like the buffer reactor 31, is an impedance element that has an impedance component to suppress changes in the current flowing through the arm 33. One end of the buffer reactor 35 is connected to the current detector 34, and the other end is connected to the transformer 11. Note that the phases of the transformer 11 to which one end of the buffer reactor 31 and the other end of the buffer reactor 35 are connected are different.

[0021] Phase circuit 12a is connected, for example, between phase A and phase C of transformer 11; phase circuit 12b is connected, for example, between phase B and phase A of transformer 11; and phase circuit 12c is connected, for example, between phase C and phase B of transformer 11. In other words, one end of the buffer reactor 31 of phase circuit 12a is connected to phase A of transformer 11, and the other end of the buffer reactor 35 of phase circuit 12a is connected to phase C of transformer 11. Also, one end of the buffer reactor 31 of phase circuit 12b is connected to phase B of transformer 11, and the other end of the buffer reactor 35 of phase circuit 12b is connected to phase A of transformer 11. Also, one end of the buffer reactor 31 of phase circuit 12c is connected to phase C of transformer 11, and the other end of the buffer reactor 35 of phase circuit 12c is connected to phase B of transformer 11.

[0022] Furthermore, the detection result of the current detector 32 installed in phase circuit 12a will be denoted as Ia1, and the detection result of the current detector 34 installed in phase circuit 12a will be denoted as Ia2. Similarly, the detection result of the current detector 32 installed in phase circuit 12b will be denoted as Ib1, and the detection result of the current detector 34 installed in phase circuit 12b will be denoted as Ib2. Likewise, the detection result of the current detector 32 installed in phase circuit 12c will be denoted as Ic1, and the detection result of the current detector 34 installed in phase circuit 12c will be denoted as Ic2.

[0023] Figure 2 shows an example of a cell configuration used in a power converter. The cell CL shown in Figure 2 is a configuration that applies a half-bridge. The cell CL comprises, for example, two semiconductor switch units 41a and 41b and one DC capacitor 42 (energy storage element). The semiconductor switch units 41a and 41b may be, for example, semiconductor elements, or a configuration in which semiconductor elements and diodes are connected in parallel with each other.

[0024] The cell CL shown in Figure 2 has a configuration in which a semiconductor switch section 41a and a semiconductor switch section 41b are connected in series, with a DC capacitor 42 connected to both ends. The cell CL has two output terminals. One output terminal of the cell CL is connected to the connection point between the semiconductor switch section 41a and the semiconductor switch section 41b, and the other output terminal of the cell CL is connected to the connection point between the semiconductor switch section 41b and the DC capacitor 42. The output terminals of the cell CL output an output voltage with two voltage levels, which is either positive or negative and has unipolarity.

[0025] Figure 3 shows another example of a cell configuration used in a power converter. The cell CL shown in Figure 3 is a configuration that applies a full bridge. The cell CL comprises, for example, four semiconductor switch sections 41a to 41d and two DC capacitors 42 (energy storage elements). The semiconductor switch sections 41a to 41d may be semiconductor elements, similar to the semiconductor switch sections 41a and 41b shown in Figure 2, or they may be a configuration in which semiconductor elements and diodes are connected in parallel with each other.

[0026] The cell CL shown in Figure 3 has a configuration in which a series circuit in which semiconductor switch section 41a and semiconductor switch section 41b are connected in series, and a series circuit in which semiconductor switch section 41c and semiconductor switch section 41d are connected in series are connected in parallel, with DC capacitors 42 connected to both ends of each series circuit. The cell CL shown in Figure 3 also has two output terminals. One output terminal of the cell CL is connected to the connection point between semiconductor switch section 41a and semiconductor switch section 41b, and the other output terminal of the cell CL is connected to the connection point between semiconductor switch section 41c and semiconductor switch section 41d. The output terminals of the cell CL output an output voltage with three voltage levels, which has both positive and negative polarity.

[0027] Returning to Figure 1, the control device 20 controls the operation of the power converter 10, thereby causing the power converter 10 to output (supply) reactive power to the connection point with the power system. The control device 20 controls the operation of the power converter 10 by performing switching control of each semiconductor switch section (semiconductor switch sections 41a, 41b shown in Figure 2 or semiconductor switch sections 41a to 41d shown in Figure 3) provided in the cell CL within each arm 33 of the MMC 12.

[0028] Specifically, the control device 20 generates a control signal Ca for switching control of each semiconductor switch section provided in the cell CL within the arm 33 in phase circuit 12a. The control device 20 generates a control signal Cb for switching control of each semiconductor switch section provided in the cell CL within the arm 33 in phase circuit 12b. The control device 20 generates a control signal Cc for switching control of each semiconductor switch section provided in the cell CL within the arm 33 in phase circuit 12c.

[0029] The control device 20 outputs the generated control signal Ca to cell CL in phase circuit 12a, the generated control signal Cb to cell CL in phase circuit 12b, and the generated control signal Cc to cell CL in phase circuit 12c. As a result, the power converter 1 outputs an AC voltage from the MMC 12 to the interconnection point side (AC side) in the power converter 10 in accordance with the control from the control device 20, thereby enabling the power converter 10 to output (supply) reactive power to the interconnection point in accordance with the control from the control device 20.

[0030] Furthermore, the control device 20 controls the power converter 10 based on the detection results of the current detectors 32 and 34 provided in the phase circuits 12a to 12c. Specifically, the control device 20 performs protective control to protect the power converter 10 if the detection result of any of the current detectors 32 and 34 provided in the phase circuits 12a to 12c exceeds a predetermined threshold. In other words, the control device 20 performs protective control to prevent the power converter 10 from being destroyed by an excessive fault current flowing through it in the event of a short-circuit or ground fault in the power converter 10 equipped with the MMC 12.

[0031] As part of the above-mentioned protection control, the control device 20 generates and outputs control signals Ca to Cc that turn off the cells CL of the arms 33 provided in the phase circuits 12a to 12c. Alternatively, as part of the above-mentioned protection control, the control device 20 controls the circuit breaker (not shown) connected in series with the cells CL of the arms 33 provided in the phase circuits 12a to 12c to open. The control device 20 may also control the circuit breaker (not shown) connected in series between the interconnection point of the power system and the power converter 10 to open as part of the above-mentioned protection control.

[0032] The circuit breaker connected in series with cell CL is controlled by the control device 20 to be in an open state, thereby interrupting the current flowing to arm 33. The circuit breaker connected in series between the interconnection point of the power system and the power converter 10 is an AC circuit breaker, and is controlled by the control device 20 to be in an open state, thereby disconnecting the power converter 10 from the power system.

[0033] The control device 20 is implemented, for example, by a hardware processor such as a CPU (Central Processing Unit) executing a program (software). Furthermore, part or all of the control device 20 may be implemented by hardware (including circuitry) such as an LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), GPU (Graphics Processing Unit), or SOC (System On Chip), or by the cooperation of software and hardware.

[0034] The program may be stored in advance in a storage device such as an HDD (Hard Disk Drive) or flash memory (a storage device equipped with a non-transient storage medium) provided by the control device 20 or the power converter 1. Alternatively, the program may be stored in a removable storage medium such as a DVD or CD-ROM (a non-transient storage medium), and installed in the HDD or flash memory of the control device 20 or the power converter 1 when the storage medium is mounted in a drive device provided by the control device 20 or the power converter 1.

[0035] Figure 4 is a diagram illustrating the fault currents that flow in a power converter according to the first embodiment when a short-circuit fault or ground fault occurs. When a short-circuit fault or ground fault occurs in the MMC 12 of the power converter 10, for example, as shown in Figure 4, the arms 33 provided in each of the phase circuits 12a, 12b, and 12c are short-circuited and current flows. Then, a loop path is formed between the phase circuits 12a, 12b, and 12c through the current path RT between the phase circuits 12a, 12b, and 12c through which current flows. As a result, for example, fault currents FC11 and FC12 flow in phase circuit 12a, fault currents FC21 and FC22 flow in phase circuit 12b, and fault currents FC31 and FC32 flow in phase circuit 12c.

[0036] Figure 5 shows an example of the current detected in the power converter according to the first embodiment. The upper graph in Figure 5 shows the detection results Ia1 of the current detector 32 provided in phase circuit 12a, Ib1 of the current detector 32 provided in phase circuit 12b, and Ic1 of the current detector 32 provided in phase circuit 12c. The lower graph in Figure 5 shows the detection results Ia2 of the current detector 34 provided in phase circuit 12a, Ib2 of the current detector 34 provided in phase circuit 12b, and Ic2 of the current detector 34 provided in phase circuit 12c.

[0037] In Figure 5, the threshold value TH is set for the detection results of the current detectors 32 and 34 installed in phase circuits 12a, 12b, and 12c. This threshold value TH is used to detect short-circuit or ground faults and is pre-set in the control device 20. In Figure 5, for the sake of simplicity, the threshold values ​​TH set for the detection results of the current detectors 32 and 34 installed in phase circuits 12a, 12b, and 12c are all assumed to be the same, but the threshold values ​​TH set for each detection result may be different. In Figure 5, a short-circuit or ground fault occurs at time t11.

[0038] Until time t11, when a short-circuit or ground fault occurs, the detection results Ia1, Ib1, and Ic1 from the current detectors 32 provided in each of the phase circuits 12a, 12b, and 12c are sinusoidal waves with a phase difference of 120° from each other. Similarly, the detection results Ia2, Ib2, and Ic2 from the current detectors 34 provided in each of the phase circuits 12a, 12b, and 12c are sinusoidal waves with a phase difference of 120° from each other.

[0039] When a short-circuit or ground fault occurs at time t11, a loop path is formed through which current flows via the current path RT between phase circuits 12a, 12b, and 12c, as explained using Figure 4. As a result, for example, fault currents FC11 and FC12 flow in phase circuit 12a, fault currents FC21 and FC22 flow in phase circuit 12b, and fault currents FC31 and FC32 flow in phase circuit 12c. Then, for example, as shown in Figure 5, the magnitudes of the detection results Ia1, Ib1, and Ic1 of the current detectors 32 provided in each of the phase circuits 12a, 12b, and 12c decrease, while the magnitudes of the detection results Ia2, Ib2, and Ic2 of the current detector 34 increase.

[0040] In this embodiment, buffer reactors 31 and 35 are provided in each of the phase circuits 12a, 12b, and 12c. This allows for a gradual change in the fault currents FC11, FC21, and FC31 flowing through the phase circuits 12a, 12b, and 12c, as well as a gradual change in the fault currents FC12, FC22, and FC32 flowing through the phase circuits 12a, 12b, and 12c. As a result, as shown in Figure 5, the rate of change in the magnitudes of the detection results Ia1, Ib1, and Ic1 of the current detector 32 is also gradual, and the rate of change in the magnitudes of the detection results Ia2, Ib2, and Ic2 of the current detector 34 is also gradual.

[0041] Next, let's assume that at time t12 in Figure 5, the control device 20 determines that the magnitude of the detection result Ib2 from the current detector 34 provided in the phase circuit 12b exceeds the threshold TH. In this case, the control device 20 performs protective control to protect the power converter 10. In other words, the control device 20 performs protective control to prevent the power converter 10 from being destroyed by an excessive fault current flowing through it.

[0042] The control device 20, for example, generates and outputs control signals Ca to Cc that turn off the cells CL of the arms 33 provided in the phase circuits 12a to 12c. Alternatively, the control device 20 performs control to open a circuit breaker (not shown) connected in series with the cells CL of the arms 33 provided in the phase circuits 12a to 12c. Alternatively, the control device 20 performs control to open a circuit breaker (not shown) connected in series between the interconnection point of the power system and the power converter 10. By performing such protection control, an excessive fault current can be prevented from flowing through the power converter 10, and damage to the power converter 10 can be prevented.

[0043] Here, consider a case where only the current detector 32 is provided in each of the phase circuits 12a, 12b, and 12c, and no current detector 34 is provided. In other words, consider a case where only the upper detection results Ia1, Ib1, and Ic1 shown in FIG. 5 are input to the control device 20, and the lower detection results Ia2, Ib2, and Ic2 shown in FIG. 5 are not input to the control device 20. In this case, the determination made by the control device 20 at time t12 (the determination that the magnitude of the detection result Ib2 of the current detector 34 provided in the phase circuit 12b exceeds the threshold TH) is not performed.

[0044] Therefore, in FIG. 5, as indicated by the broken line, while the magnitudes of the detection results Ia1, Ib1, and Ic1 of the current detectors 32 provided in each of the phase circuits 12a, 12b, and 12c continue to decrease, the magnitudes of the detection results Ia2, Ib2, and Ic2 of the current detectors 34 continue to increase. Note that, since the case where no current detector 34 is provided in each of the phase circuits 12a, 12b, and 12c is considered here, the detection results Ia2, Ib2, and Ic2 shown in the lower part of FIG. 5 are not actually obtained. In the lower graph of FIG. 5, the detection results Ia2, Ib2, and Ic2 are shown for convenience to facilitate understanding.

[0045] For example, suppose at time t13, the control device 20 determines that the magnitude of the detection result Ia1 from the current detector 32 provided in the phase circuit 12a exceeds the threshold TH. In this case, the control device 20 performs protective control to protect the power converter 10. In other words, the control device 20 performs protective control to prevent the power converter 10 from being destroyed by an excessive fault current flowing through it.

[0046] As described above, when current detectors 32 and 34 are provided in each of the phase circuits 12a, 12b, and 12c, protection control is performed at time t12 in Figure 5. In contrast, when only current detector 32 is provided in each of the phase circuits 12a, 12b, and 12c, and current detector 34 is not provided, protection control may be performed at a later time t13 than time t12 in Figure 5. Therefore, when current detectors 32 and 34 are provided in each of the phase circuits 12a, 12b, and 12c, short-circuit faults or ground faults can be detected and protection control performed in a shorter time than when only current detector 32 is provided in each of the phase circuits 12a, 12b, and 12c, and current detector 34 is not provided.

[0047] Furthermore, consider the case where only buffer reactors 31 are provided in each of the phase circuits 12a, 12b, and 12c, and buffer reactor 35 is not provided. In this case, the changes in the fault currents FC11, FC21, and FC31 flowing through the phase circuits 12a, 12b, and 12c can be slowed down. However, depending on the location of the short-circuit or ground fault, it may not be possible to slow down the changes in the fault currents FC12, FC22, and FC32 flowing through the phase circuits 12a, 12b, and 12c, and the rate of current increase may become extremely large. If the rate of current increase is extremely large, for example, even within the short time period from time t11 to t12 as shown in Figure 5, it is possible that an excessive current may flow.

[0048] As described above, when buffer reactors 31 and 35 are provided in each of the phase circuits 12a, 12b, and 12c, in addition to the fault currents FC11, FC21, and FC31 flowing through the phase circuits 12a, 12b, and 12c, changes in the fault currents FC12, FC22, and FC32 can be moderated. Therefore, excessive fault currents FC11, FC21, and FC31 can be prevented from flowing within a short period of time, and excessive fault currents FC11, FC21, and FC31 can be prevented from flowing within a short period of time.

[0049] As described above, the power converter 10 of the present embodiment is connected to a power system and includes a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. Each of the phase circuits 12a to 12c includes an arm 33, a buffer reactor 31 and a current detector 32, and a current detector 34 and a buffer reactor 35. The arm 33 is formed by connecting in series a plurality of cells CL each including a plurality of semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42. The buffer reactor 31 and the current detector 32 are provided on one end side of the arm 33. The current detector 34 and the buffer reactor 35 are provided on the other end side of the arm 33. This makes it possible to detect the current flowing through one end side of the arm 33 while suppressing changes in said current, and to detect the current flowing through the other end side of the arm 33 while suppressing changes in said current. Accordingly, when a short-circuit fault or a ground fault occurs, the fault current flowing through the cell CL can be reduced.

[0050] (Second Embodiment) Fig. 6 is a block diagram showing the configuration of main parts of a power converter and a power conversion device according to the second embodiment. In Fig. 6, components corresponding to those shown in Fig. 1 are denoted by the same reference numerals. The power conversion device 2 shown in Fig. 6 has a configuration in which the power converter 10 of the power conversion device 1 shown in Fig. 1 is replaced with a power converter 10A.

[0051] The power converter 10A has a configuration that is generally similar to the power converter 10 shown in Figure 1, but the positions of the buffer reactor 31 and current detector 32, as well as the positions of the current detector 34 and buffer reactor 35, are different in each of the three phase circuits 12a, 12b, and 12c. Specifically, in each of the phase circuits 12a, 12b, and 12c, the current detector 32, buffer reactor 31, arm 33, buffer reactor 35, and current detector 34 are connected in series in this order. In other words, phase circuits 12a, 12b, and 12c are second phase circuits in which the buffer reactor 31 is provided between the current detector 32 and the arm 33, and the buffer reactor 35 is provided between the current detector 34 and the arm 33.

[0052] The power converter 10A of this embodiment differs from the power converter 10 shown in Figure 1 only in the positions of the buffer reactor 31 and current detector 32 in each of the three phase circuits 12a, 12b, and 12c, as well as the positions of the current detector 34 and buffer reactor 35. Therefore, in the event of a short-circuit fault or ground fault, protection control similar to that performed by the control device 20 is performed.

[0053] As described above, the power converter 10A of this embodiment is connected to a power system and has phase circuits 12a to 12c corresponding to the number of phases of the power system. Phase circuits 12a to 12c have an arm 33, a current detector 32 and a buffer reactor 31, and a buffer reactor 35 and a current detector 34. Multiple cells CL, each comprising multiple semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The current detector 32 and buffer reactor 31 are provided on one end of the arm 33. The buffer reactor 35 and current detector 34 are provided on the other end of the arm 33. This makes it possible to detect the current while suppressing changes in the current flowing on one end of the arm 33, and to detect the current while suppressing changes in the current flowing on the other end of the arm 33. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0054] (Third Embodiment) Figure 7 is a block diagram showing the main components of a power converter and power conversion device according to the third embodiment. In Figure 7, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 3 shown in Figure 7 is a configuration in which the power converter 10 of the power conversion device 1 shown in Figure 1 is replaced with a power converter 10B.

[0055] The power converter 10B has a configuration that is generally similar to the power converter 10 shown in Figure 1, but the positions of the current detector 34 and buffer reactor 35 in each of the three phase circuits 12a, 12b, and 12c are different. Specifically, in each of the phase circuits 12a, 12b, and 12c, the buffer reactor 31, current detector 32, arm 33, buffer reactor 35, and current detector 34 are connected in series in this order. In other words, phase circuits 12a, 12b, and 12c are third phase circuits in which the current detector 32 is provided between the buffer reactor 31 and the arm 33, and the buffer reactor 35 is provided between the current detector 34 and the arm 33.

[0056] The power converter 10B of this embodiment differs from the power converter 10 shown in Figure 1 only in the positions of the current detectors 34 and buffer reactors 35 in each of the three phase circuits 12a, 12b, and 12c. Therefore, in the event of a short-circuit fault or ground fault, protection control similar to that performed by the control device 20 is performed.

[0057] As described above, the power converter 10B of this embodiment is connected to a power system and has a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. Each phase circuit 12a to 12c has an arm 33, a buffer reactor 31 and a current detector 32, and a buffer reactor 35 and a current detector 34. Multiple cells CL, each comprising a plurality of semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The buffer reactor 31 and current detector 32 are provided on one end of the arm 33. The buffer reactor 35 and current detector 34 are provided on the other end of the arm 33. This makes it possible to detect the current while suppressing changes in the current flowing on one end of the arm 33, and to detect the current while suppressing changes in the current flowing on the other end of the arm 33. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0058] (Fourth Embodiment) Figure 8 is a block diagram showing the main components of a power converter and power conversion device according to the fourth embodiment. In Figure 8, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 4 shown in Figure 8 is a configuration in which the power converter 10 of the power conversion device 1 shown in Figure 1 is replaced with a power converter 10C.

[0059] The power converter 10C has a configuration that is generally similar to the power converter 10 shown in Figure 1, but the positions of the buffer reactor 31 and current detector 32 in each of the three phase circuits 12a, 12b, and 12c are different. Specifically, in each of the phase circuits 12a, 12b, and 12c, the current detector 32, buffer reactor 31, arm 33, current detector 34, and buffer reactor 35 are connected in series in this order. In other words, phase circuits 12a, 12b, and 12c are fourth phase circuits in which the buffer reactor 31 is provided between the current detector 32 and the arm 33, and the current detector 34 is provided between the buffer reactor 35 and the arm 33.

[0060] The power converter 10C of this embodiment differs from the power converter 10 shown in Figure 1 only in the positions of the buffer reactors 31 and current detectors 32 in each of the three phase circuits 12a, 12b, and 12c. Therefore, in the event of a short-circuit fault or ground fault, protection control similar to that performed by the control device 20 is performed.

[0061] As described above, the power converter 10C of this embodiment is connected to a power system and has a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. Each phase circuit 12a to 12c has an arm 33, a current detector 32 and a buffer reactor 31, and a current detector 34 and a buffer reactor 35. Multiple cells CL, each comprising multiple semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The current detector 32 and buffer reactor 31 are provided on one end of the arm 33. The current detector 34 and buffer reactor 35 are provided on the other end of the arm 33. This makes it possible to detect the current while suppressing changes in the current flowing on one end of the arm 33, and to detect the current while suppressing changes in the current flowing on the other end of the arm 33. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0062] (Fifth Embodiment) Figure 9 is a block diagram showing the main components of a power converter and power conversion device according to the fifth embodiment. In Figure 9, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 5 shown in Figure 9 is a configuration in which the power converter 10 of the power conversion device 1 shown in Figure 1 is replaced with a power converter 10D.

[0063] The power converter 10D has a configuration that is generally similar to the power converter 10 shown in Figure 1, but the positions of the buffer reactor 31 and current detector 32, or the positions of the current detector 34 and buffer reactor 35 differ in the three phase circuits 12a, 12b, and 12c. Specifically, in phase circuit 12a, the buffer reactor 31, current detector 32, arm 33, buffer reactor 35, and current detector 34 are connected in series in this order. In phase circuit 12b, the current detector 32, buffer reactor 31, arm 33, current detector 34, and buffer reactor 35 are connected in series in this order. In phase circuit 12c, the buffer reactor 31, current detector 32, arm 33, current detector 34, and buffer reactor 35 are connected in series in this order.

[0064] In other words, phase circuit 12a is a third phase circuit in which a current detector 32 is provided between a buffer reactor 31 and an arm 33, and a buffer reactor 35 is provided between a current detector 34 and an arm 33. Phase circuit 12b is a fourth phase circuit in which a buffer reactor 31 is provided between a current detector 32 and an arm 33, and a current detector 34 is provided between a buffer reactor 35 and an arm 33. Phase circuit 12c is a first phase circuit in which a current detector 32 is provided between a buffer reactor 31 and an arm 33, and a current detector 34 is provided between a buffer reactor 35 and an arm 33.

[0065] In Figure 9, an example is shown where phase circuit 12a is a third-phase circuit, phase circuit 12b is a fourth-phase circuit, and phase circuit 12c is a first-phase circuit, but the example is not limited to this. Phase circuits 12a, 12b, and 12c may also be second-phase circuits. Furthermore, all of phase circuits 12a, 12b, and 12c may be different from each other, or one of phase circuits 12a, 12b, and 12c may be different from the other two. In other words, one of phase circuits 12a, 12b, and 12c (referred to as the "specific phase circuit") may be a first-phase circuit, a second-phase circuit, a third-phase circuit, or a fourth-phase circuit, and the other one of phase circuits 12a, 12b, and 12c may be a different circuit from the specific phase circuit among the first-phase circuit, second-phase circuit, third-phase circuit, and fourth-phase circuit.

[0066] The power converter 10D of this embodiment differs from the power converter 10 shown in Figure 1 in that, in the three phase circuits 12a, 12b, and 12c, the positions of the buffer reactor 31 and current detector 32, or the positions of the current detector 34 and buffer reactor 35, are different. Therefore, in the event of a short-circuit fault or ground fault, protection control similar to that performed by the control device 20 is performed.

[0067] As described above, the power converter 10D of this embodiment is connected to a power system and has a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. The phase circuits 12a to 12c have different positions for the buffer reactor 31 and current detector 32, or the current detector 34 and buffer reactor 35, but each has an arm 33, a current detector 32 and buffer reactor 31, and a current detector 34 and buffer reactor 35. Multiple cells CL, each comprising multiple semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The current detector 32 and buffer reactor 31 are provided on one end of the arm 33. The current detector 34 and buffer reactor 35 are provided on the other end of the arm 33. This makes it possible to detect the current while suppressing changes in the current flowing on one end of the arm 33, and to detect the current while suppressing changes in the current flowing on the other end of the arm 33. This reduces the fault current flowing through cell CL in the event of a short circuit or ground fault.

[0068] (Sixth Embodiment) Figure 10 is a block diagram showing the main components of a power converter and power conversion device according to the sixth embodiment. In Figure 10, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 6 shown in Figure 10 is a configuration in which the power converter 10 of the power conversion device 1 shown in Figure 1 is replaced with a power converter 10E.

[0069] The power converter 10E has a configuration that is generally similar to the power converter 10 shown in Figure 1, but differs in that the current detector 34 on the other end of the arm 33 is omitted in the three phase circuits 12a, 12b, and 12c. In this embodiment, since the current flowing between the buffer reactor 35 and the arm 33 is not detected, the detection results Ia2, Ib2, and Ic2 shown in Figure 1 are not input to the control device 20. Therefore, in this embodiment, the power converter 10E is controlled based on the detection results Ia1, Ib1, and Ic1 shown in Figure 1.

[0070] As described above, the power converter 10E of this embodiment is connected to a power system and has a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. Each phase circuit 12a to 12c has an arm 33, a current detector 32, a buffer reactor 31, and a buffer reactor 35. Multiple cells CL, each comprising multiple semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The current detector 32 and buffer reactor 31 are provided on one end of the arm 33. The buffer reactor 35 is provided on the other end of the arm 33. This makes it possible to detect the current while suppressing changes in the current flowing on one end of the arm 33, and to suppress changes in the current flowing on the other end of the arm 33. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0071] (Seventh Embodiment) Figure 11 is a block diagram showing the main components of a power converter and power conversion device according to the seventh embodiment. In Figure 11, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 7 shown in Figure 11 is a configuration in which the power converter 10 of the power conversion device 1 shown in Figure 1 is replaced with a power converter 10F.

[0072] The power converter 10F has a configuration that is generally similar to the power converter 10 shown in Figure 1, but differs in that the buffer reactor 35 on the other end of the arm 33 is omitted in the three phase circuits 12a, 12b, and 12c. In this embodiment, since the buffer reactor 35 is omitted, it is possible that the current flowing on the other end of the arm 33 may change rapidly in the event of a short circuit or ground fault. However, in this embodiment, a current detector 34 is provided on the other end of the arm 33, so that rapid changes in current can be detected by the current detector 34.

[0073] In this embodiment, unlike the power converter 10E shown in Figure 10, the current flowing between the buffer reactor 31 and the arm 33, and the current flowing between the buffer reactor 35 and the arm 33 are detected. Therefore, in this embodiment, as in the first to fifth embodiments, the power converter 10F is controlled based on the detection results Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2.

[0074] As described above, the power converter 10F of this embodiment is connected to a power system and has a number of phase circuits 12a to 12c corresponding to the number of phases of the power system. Each phase circuit 12a to 12c has an arm 33, a current detector 32 and a buffer reactor 31, and a current detector 34. Multiple cells CL, each comprising multiple semiconductor switch units 41a, 41b or semiconductor switch units 41 to 41d and a DC capacitor 42, are connected in series. The current detector 32 and the buffer reactor 31 are provided on one end of the arm 33. The current detector 34 is provided on the other end of the arm 33. This makes it possible to detect the current flowing on one end of the arm 33 while suppressing changes in the current, and to detect the current flowing on the other end of the arm 33. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0075] (Eighth Embodiment) Figure 12 is a block diagram showing the main components of a power converter and power conversion device according to the eighth embodiment. In Figure 12, components corresponding to the configuration shown in Figure 1 are denoted by the same reference numerals. The power conversion device 8 shown in Figure 12 has a configuration in which control devices 20a, 20b, and 20c are provided for each phase of the AC system instead of the control device 20.

[0076] The power converter 1 shown in Figure 1 controls the three phase circuits 12a, 12b, and 12c corresponding to each of the three phases of the power supply collectively with a control device 20. In contrast, the power converter 8 of this embodiment is equipped with control devices 20a, 20b, and 20c corresponding to the phase circuits 12a, 12b, and 12c, and controls the phase circuits 12a, 12b, and 12c individually. Various information (for example, information indicating the detection result of a short-circuit or ground fault) is exchanged between the phase circuits 12a, 12, and 12c. For this reason, the control devices 20a, 20b, and 20c perform the same control as the control device 20.

[0077] In this embodiment, the current flowing between the buffer reactor 31 and the arm 33, and the current flowing between the buffer reactor 35 and the arm 33 are detected. Therefore, in this embodiment, as in the first to fifth and seventh embodiments, the power converter 10 is controlled based on the detection results Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2.

[0078] As described above, the power converter 8 of this embodiment includes a power converter 10, similar to the power converter 1 shown in Figure 1. This makes it possible to detect the current flowing through one end of the arm 33 while suppressing changes in that current, and to detect the current flowing through the other end of the arm 33 while suppressing that current. This makes it possible to reduce the fault current flowing through the cell CL in the event of a short circuit or ground fault.

[0079] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be carried out in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents.

[0080] The above embodiments may be combined as appropriate. For example, the first to seventh embodiments and the eighth embodiment may be combined, so that the power conversion devices 1 to 7 shown in Figures 1, 6 to 11 are configured to include control devices 20a, 20b, and 20c instead of control device 20.

[0081] With respect to the above embodiments, the following additional notes are disclosed as aspects of the invention and selective features.

[0082] (Note 1) A power converter connected to a power system and having a number of phase circuits corresponding to the number of phases of the power system, wherein the phase circuits include: an arm in which a plurality of cells, each having a plurality of self-extinguishing semiconductor elements and an energy storage element, are connected in series; a first reactor and a first current detector provided on one end of the arm; and at least one of a second reactor and a second current detector provided on the other end of the arm.

[0083] (Note 2) In the power converter described in Note 1, the power system is three-phase, and the three phase circuits corresponding to each phase of the power system may be provided with a delta-connected circuit.

[0084] (Note 3) In the power converter described in Note 1 or Note 2, both the second reactor and the second current detector may be provided.

[0085] (Note 4) In the power converter described in Note 3, the phase circuit may be a first phase circuit in which the first current detector is provided between the first reactor and the arm, and the second current detector is provided between the second reactor and the arm.

[0086] (Note 5) In the power converter described in Note 3, the phase circuit may be a second phase circuit in which the first reactor is provided between the first current detector and the arm, and the second reactor is provided between the second current detector and the arm.

[0087] (Note 6) In the power converter described in Note 3, the phase circuit may be a third phase circuit in which the first current detector is provided between the first reactor and the arm, and the second reactor is provided between the second current detector and the arm.

[0088] (Note 7) In the power converter described in Note 3, the phase circuit may be a fourth phase circuit in which the first reactor is provided between the first current detector and the arm, and the second current detector is provided between the second reactor and the arm.

[0089] (Note 8) In the power converter described in Note 3, any one of the phase circuits is: a first phase circuit in which the first current detector is provided between the first reactor and the arm, and the second current detector is provided between the second reactor and the arm; a second phase circuit in which the first reactor is provided between the first current detector and the arm, and the second reactor is provided between the second current detector and the arm; a third phase circuit in which the first current detector is provided between the first reactor and the arm, and the second reactor is provided between the second current detector and the arm; or a fourth phase circuit in which the first reactor is provided between the first current detector and the arm, and the second current detector is provided between the second reactor and the arm. Any one of the other phase circuits may be a circuit different from any one of the phase circuits among the first phase circuit, the second phase circuit, the third phase circuit, and the fourth phase circuit.

[0090] (Note 9) In the power converter described in any of Notes 1 to 8, the cell may include: a series circuit in which a first semiconductor element and a second semiconductor element are connected in series; an energy storage element connected in parallel to the series circuit; a first output terminal connected to the connection point between the first semiconductor element and the energy storage element; and a second output terminal connected to the connection point between the first semiconductor element and the second semiconductor element.

[0091] In the power converter described in any of the appendices 1 to 8, the cell may include: a first series circuit in which a first semiconductor element and a second semiconductor element are connected in series; a second series circuit in which a third semiconductor element and a fourth semiconductor element are connected in series and connected in parallel to the first series circuit; an energy storage element connected in parallel to the first series circuit and the second series circuit; a first output terminal connected to the connection point between the first semiconductor element and the second semiconductor element; and a second output terminal connected to the connection point between the third semiconductor element and the fourth semiconductor element.

[0092] (Note 11) A power converter comprising: a power converter described in any of Notes 1 to 10; and a control device that controls the power converter based on the detection result of at least one of the first current detector and the second current detector.

[0093] (Note 12) In the power converter described in Note 11, the control device may perform protective control to protect the power converter when the detection result of at least one of the first current detector and the second current detector exceeds a predetermined threshold.

[0094] (Note 13) In the power conversion device described in Note 12, the control device may, as the protective control, perform control to turn off the cell of the arm.

[0095] (Note 14) In the power conversion device described in Note 12, the control device may, as the protective control, perform control to turn off the circuit breaker connected in series with the cell of the arm, or the circuit breaker connected in series between the interconnection point of the power system and the power converter.

[0096] 1-8...Power converter, 10, 10A-10F...Power converter, 12...MMC, 12a, 12b, 12c...Phase circuit, 20, 20a, 20b, 20c...Control device, 31...Buffer reactor, 32...Current detector, 33...Arm, 34...Current detector, 35...Buffer reactor, 41a-41d...Semiconductor switch section, 42...DC capacitor, CL...Cell

Claims

1. A power converter connected to a power system and comprising a number of phase circuits corresponding to the number of phases of the power system, wherein the phase circuits comprise: an arm in which a plurality of cells comprising a plurality of self-extinguishing semiconductor elements and an energy storage element are connected in series; a first reactor and a first current detector provided on one end of the arm; and at least one of a second reactor and a second current detector provided on the other end of the arm.

2. The power converter according to claim 1, wherein the power system is three-phase, and the three phase circuits corresponding to each phase of the power system are delta-connected.

3. The power converter according to claim 1, comprising both the second reactor and the second current detector.

4. The power converter according to claim 3, wherein the phase circuit is a first phase circuit in which the first current detector is provided between the first reactor and the arm, and the second current detector is provided between the second reactor and the arm.

5. The power converter according to claim 3, wherein the phase circuit is a second phase circuit in which the first reactor is provided between the first current detector and the arm, and the second reactor is provided between the second current detector and the arm.

6. The power converter according to claim 3, wherein the phase circuit is a third phase circuit in which the first current detector is provided between the first reactor and the arm, and the second reactor is provided between the second current detector and the arm.

7. The power converter according to claim 3, wherein the phase circuit is a fourth phase circuit in which the first reactor is provided between the first current detector and the arm, and the second current detector is provided between the second reactor and the arm.

8. The power converter according to claim 3, wherein any one of the phase circuits is: a first phase circuit in which the first current detector is provided between the first reactor and the arm, and the second current detector is provided between the second reactor and the arm; a second phase circuit in which the first reactor is provided between the first current detector and the arm, and the second reactor is provided between the second current detector and the arm; a third phase circuit in which the first current detector is provided between the first reactor and the arm, and the second reactor is provided between the second current detector and the arm; or a fourth phase circuit in which the first reactor is provided between the first current detector and the arm, and the second current detector is provided between the second reactor and the arm, and any other one of the phase circuits is a circuit different from any one of the phase circuits among the first phase circuit, the second phase circuit, the third phase circuit, and the fourth phase circuit.

9. The power converter according to claim 1, wherein the cell comprises: a series circuit in which a first semiconductor element and a second semiconductor element are connected in series; an energy storage element connected in parallel to the series circuit; a first output terminal connected to the connection point between the first semiconductor element and the energy storage element; and a second output terminal connected to the connection point between the first semiconductor element and the second semiconductor element.

10. The power converter according to claim 1, wherein the cell comprises: a first series circuit in which a first semiconductor element and a second semiconductor element are connected in series; a second series circuit in which a third semiconductor element and a fourth semiconductor element are connected in series and connected in parallel to the first series circuit; an energy storage element connected in parallel to the first series circuit and the second series circuit; a first output terminal connected to the connection point between the first semiconductor element and the second semiconductor element; and a second output terminal connected to the connection point between the third semiconductor element and the fourth semiconductor element.

11. A power converter comprising: a power converter according to any one of claims 1 to 10; and a control device that controls the power converter based on the detection result of at least one of the first current detector and the second current detector.

12. The power converter according to claim 11, wherein the control device performs protective control to protect the power converter when the detection result of at least one of the first current detector and the second current detector exceeds a predetermined threshold.

13. The power converter according to claim 12, wherein the control device performs a control to turn off the cell of the arm as the protective control.

14. The power converter according to claim 12, wherein the control device performs the protection control by turning off a circuit breaker connected in series with the cell of the arm, or a circuit breaker connected in series between the interconnection point of the power system and the power converter.

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