Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device in which a plurality of gate-all-around transistors are provided on a substrate. Each of the gate-all-around transistors is provided with: a nanosheet laminate in which a plurality of nanosheet layers made of a semiconductor material are laminated; insulating inner spacers sandwiched between the nanosheet layers at both ends of the nanosheet layers; a gate electrode that, between the inner spacers, covers the entire periphery of each of the nanosheet layers with a gate insulating film therebetween, and is provided upright on the upper part of the nanosheet laminate; a source / drain provided upright along the nanosheet laminate at both ends of the nanosheet layers at which the inner spacers are disposed; a contact connected to the source / drain; an insulating spacer sandwiched between the source / drain and the contact, and the gate electrode; and a base spacer disposed between the spacer and the nanosheet laminate and disposed around a portion at which the nanosheet layers and the inner spacers are stacked. The base spacer is formed using an insulating material different from that of the spacer.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Regarding a method for manufacturing a semiconductor device, the following procedure is described in Patent Document 1 below. First, a fin structure is formed on a substrate, and a polysilicon structure is formed on the fin structure. Next, a gate spacer including a first spacer along a sidewall of the polysilicon structure and a second spacer in the fin structure is formed, and epitaxial S / D (source / drain) is formed on the fin structure. Thereafter, the polysilicon structure is replaced with a gate structure.

[0003] US Publication No. 2022 / 0028997

[0004] In the manufacturing method described above, the gate structure formed by replacing the polysilicon structure is insulated from the epitaxial S / D by the gate spacer formed on the sidewalls of the fin structure and the polysilicon structure. When such a manufacturing method is applied to the manufacture of a semiconductor device having a gate-all-around structure, it is necessary to provide a gate spacer on the sidewall of the polysilicon structure before forming the epitaxial S / D, and perform pattern etching on the nanosheet laminate from above the gate spacer. In such pattern etching, since various materials are exposed on the etching surface, level differences are likely to occur. For this reason, it is necessary to increase the film thickness of the polysilicon structure, which results in a process with high difficulty.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device having a gate-all-around structure capable of reducing the difficulty of an etching process, and a method for manufacturing the semiconductor device.

[0006] To achieve this objective, the present invention provides a semiconductor device having a plurality of all-around gate transistors on a substrate, wherein each all-around gate transistor comprises a nanosheet laminate formed by stacking a plurality of nanosheet layers made of a semiconductor material, insulating inner spacers sandwiched between each nanosheet layer at both ends of the nanosheet layer, a gate electrode that covers the entire circumference of each nanosheet layer via a gate insulating film between the inner spacers and is erected on the top of the nanosheet laminate, a source / drain erected along the nanosheet laminate at both ends of the nanosheet layer where the inner spacers are located, a contact connected to the source / drain, an insulating spacer sandwiched between the source / drain and the contact and the gate electrode, and a base spacer disposed between the spacer and the nanosheet laminate and surrounding the stacked portion of the nanosheet layer and the inner spacer, wherein the base spacer is made of an insulating material different from the spacer. The present invention also provides a method for manufacturing such a semiconductor device.

[0007] The present invention provides a semiconductor device with a full-circumference gate structure that reduces the number of manufacturing steps and lowers the difficulty of the etching process, as well as a method for manufacturing a semiconductor device.

[0008] This is a cross-sectional view of the semiconductor device of the first embodiment. This is a manufacturing process diagram (1) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (2) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (3) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (4) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (5) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (6) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (7) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (8) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (9) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (10) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (11) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (12) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (13) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (14) of the semiconductor device of the first embodiment. This is a manufacturing process diagram (15) of the semiconductor device of the first embodiment. This is a cross-sectional view of the semiconductor device of the second embodiment. This is a manufacturing process diagram (1) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (part 2) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 3) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 4) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 5) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 6) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 7) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 8) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 9) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 10) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 12) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 13) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 14) of the semiconductor device according to the second embodiment. This is the manufacturing process diagram (part 15) of the semiconductor device according to the second embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the same reference numerals are used for the same components, and some redundant descriptions will be omitted.

[0010] <First Embodiment> <Semiconductor Device of the First Embodiment> Figure 1 is a cross-sectional view of a semiconductor device 1 of the first embodiment. This semiconductor device 1 has a plurality of full-circumference gate transistors 10 on one main surface side of a semiconductor substrate 100. Figure 1 shows a cross-section in the gate width direction [Wg] and a cross-section in the gate length direction [Lg] at the center of the full-circumference gate transistor 10. Each full-circumference gate transistor 10 shown in Figure 1 is constructed using a nanosheet laminate 103 in which nanosheet layers 102 made of, for example, silicon are laminated on one main surface of the semiconductor substrate 100. The semiconductor substrate 100 has groove-type element isolation 104 formed on one main surface side. This semiconductor device 1 has a plurality of full-circumference gate transistors 10 on a substrate having a semiconductor substrate 100 and groove-type element isolation 104 formed on the semiconductor substrate 100.

[0011] Each nanosheet layer 102 constituting the all-around gate transistor 10 is stacked with a gap between them at both ends in the gate length direction [Lg] via an inner spacer 109. Furthermore, each nanosheet layer 102 has a GAA (Gate All Around) structure in which its entire circumference is surrounded by a gate electrode 115 via a gate insulating film (not shown). The gate electrode 115 may have a multilayer structure of two or more layers.

[0012] Furthermore, the all-around gate transistor 10 has source / drain 110 erected on the semiconductor substrate 100 at both ends of the nanosheet layer 102 in the gate length direction [Lg]. The source / drain 110 is an epitaxial layer grown from the semiconductor substrate 100 and each nanosheet layer 102. A contact 111a is also provided above the source / drain 110 to draw the source / drain 110 to the outside.

[0013] The source / drain 110 and contact 111a described above are kept insulated from the gate electrode 115 by the inner spacer 109, the base spacer S1 positioned on top of the nanosheet laminate 103, and the insulating spacer 114.

[0014] Of these, the base spacer S1 may be made of the same material as the inner spacer 109, but is formed by a different process than the inner spacer 109. Such base spacers S1 are placed at both ends of the nanosheet laminate 103 and insulate the source / drain 110 and the gate electrode 115 at the top of the nanosheet laminate 103. Each base spacer S1 is placed in contact with the top and both sides in the gate width direction of the laminated portion between the nanosheet laminate 103 and the inner spacer 109, as will be explained with reference to Figure 8 in the subsequent semiconductor device manufacturing method, and is positioned to surround the laminated portion between the nanosheet laminate 103 and the inner spacer 109.

[0015] Furthermore, the insulating spacer 114 is positioned on top of the base spacer S1 so as to surround the gate electrode 115, insulating the source / drain 110 and contact 111a from the gate electrode 115.

[0016] Furthermore, the semiconductor device 1 has an embedded insulating film 106 for insulating each full-circumference gate transistor 10 in the gate width direction [Wg].

[0017] <Method of Manufacturing a Semiconductor Device of the First Embodiment> Figures 2 to 16 are process diagrams (1) to (15) showing the method of manufacturing the semiconductor device 1 of the first embodiment. The method of manufacturing the semiconductor device 1 described above and its detailed configuration will be explained below in the order of the manufacturing process shown in Figures 2 to 16. Figures 2 to 16 show plan views of each manufacturing process, as well as A-A and B-B cross-sections in the plan views, and further, A'-A' or A''-A'' cross-sections as needed.

[0018] First, as shown in Figure 2, a nanosheet laminate 103 is formed by stacking nanosheet layers 102 made of a semiconductor material via a sacrificial sheet layer 101 on one main surface of a semiconductor substrate 100 made of single crystal silicon. The sacrificial sheet layer 101 is constructed using a material that allows for selective etching of the nanosheet layers 102 made of semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layers 102, silicon germanium is used as the sacrificial sheet layer 101.

[0019] Next, the nanosheet laminate 103 is separated into a linear shape in one direction (gate width direction: corresponding to the A-A cross section in the figure) by etching using a resist pattern (not shown in the figure) as a mask. At the same time, one main surface side of the semiconductor substrate 100 is etched back to form a groove, and then the groove is filled with an insulating material to form a linear groove-type element separator 104.

[0020] Next, as shown in Figure 3, a sacrificial film 105 is formed on top of the semiconductor substrate 100 so as to cover the nanosheet laminate 103 separated in one direction. This sacrificial film 105 is made of a material that can be selectively etched with respect to the nanosheet layer 102, and it is preferable that it is a material that can be etched in the same process as the sacrificial sheet layer 101. Such a sacrificial film 105 may typically be made of silicon germanium, which is the same material as the sacrificial sheet layer 101. This sacrificial film 105 is formed with a thickness of about 12 nm.

[0021] The formation of the sacrificial film 105 made of silicon germanium can be achieved, for example, by depositing a silicon germanium layer by CVD, followed by heat treatment to crystallize the silicon germanium layer and form the sacrificial film 105. Alternatively, the sacrificial film 105 may be formed by epitaxial growth from a sacrificial sheet layer 101 made of silicon germanium. In this case, the sacrificial film 105 will not be formed on the grooved element separator 104.

[0022] Next, as shown in Figure 4, a step is performed to remove the sacrificial film 105 on the grooved element separator 104. In this case, only the sacrificial film 105 on the grooved element separator 104 is removed by a bottom punch method, in which the sacrificial film material is deposited on the upper part of the nanosheet laminate 103 while etching the sacrificial film 105 at the bottom. As a result, the sacrificial film 105 on the upper part of the nanosheet laminate 103 becomes thicker. Note that if the sacrificial film 105 is a layer epitaxially grown from the sacrificial sheet layer 101, this step is not necessary.

[0023] Next, as shown in Figure 5, an embedded insulating film 106 made of silicon oxide is formed to embed the nanosheet laminate 103 covered with the sacrificial film 105. Then, a hard mask layer 107 is formed on the embedded insulating film 106. Here, for example, an embedded insulating film 106 made of silicon oxide is formed, and a hard mask layer 107 made of silicon nitride is formed on top of it.

[0024] Next, as shown in Figure 6, the hard mask layer 107 is patterned in a line shape approximately perpendicular to the extension direction of the nanosheet laminate 103 (see Figure 5), and the embedded insulating film 106 exposed from the line-shaped hard mask layer 107 is further reduced (A'-A' cross section).

[0025] Next, a resist pattern, not shown in the illustration here, is formed on the hard mask layer 107 and the embedded insulating film 106. This resist pattern is in the shape of lines that overlap the groove-type element separator 104 described with reference to Figure 2, and opens above the nanosheet laminate 103.

[0026] Subsequently, the embedded insulating film 106 is etched using the above-mentioned resist pattern and the patterned hard mask layer 107 as a mask to form an opening 108h in the embedded insulating film 106. Furthermore, the nanosheet laminate 103 exposed at the bottom of the opening 108h is etched to separate the nanosheet laminate 103 into island-like active regions.

[0027] Next, as shown in Figure 7, within the opening 108h, the sacrificial sheet layer 101 and sacrificial film 105 exposed on the side wall of the nanosheet laminate 103 are selectively reduced by isotropic etching (B-B cross section).

[0028] Here, as shown in the A-A cross section that crosses the center of the nanosheet laminate 103, the sacrificial film 105 is formed to cover the nanosheet laminate 103. For this reason, in the region close to the exposed surface of the nanosheet laminate 103, gaps are formed between the nanosheet layers 102, as shown in the A''-A'' cross section, and gaps are also formed between the exposed peripheral wall of the nanosheet laminate 103 and the embedded insulating film 106.

[0029] Next, as shown in Figure 8, insulating inner spacers 109 are formed on the exposed sidewalls of the sacrificial sheet layer 101 to fill the gaps between the nanosheet layers 102. In this step, insulating base spacers S1 are also formed on the exposed sidewalls of the sacrificial film 105 to fill the gaps between the peripheral wall of the nanosheet laminate 103 and the embedded insulating film 106 (A''-A'' cross section).

[0030] In this case, first, an insulating material film made of SiN (silicon nitride), SiON (silicon oxynitride), SiOCN, SiCN, or SiBCN is formed to fill the gaps between the nanosheet layers 102 and the gap between the nanosheet laminate 103 and the embedded insulating film 106. Then, the formed insulating material film is etched back. This leaves the insulating material film only in the gaps between the nanosheet layers 102 and the gap between the nanosheet laminate 103 and the embedded insulating film 106. As a result, the insulating material film left in the gaps between the nanosheet layers 102 is formed as an inner spacer 109. In addition, the insulating material film left in the gap between the nanosheet laminate 103 and the embedded insulating film 106 is formed as a base spacer S1.

[0031] As shown in the A''-A'' cross section, the base spacer S1 formed in this manner is positioned on both exposed surfaces of the nanosheet laminate 103, in contact with the upper part of the laminated portion between the nanosheet laminate 103 and the inner spacer 109 and on both sides in the gate width direction, and is positioned to surround the laminated portion between the nanosheet layer 102 and the inner spacer 109.

[0032] Next, as shown in Figure 9, source / drain 110 made of silicon containing p-type or n-type impurities is formed on the side of the nanosheet laminate 103 by epitaxial growth from the exposed surfaces of the nanosheet layer 102 and the semiconductor substrate 100. This source / drain 110 is connected to each nanosheet layer 102. In the A'-A' section where the nanosheet laminate 103 is not present, the surface height of the embedded insulating film 106 is low (see Figure 6). For this reason, the source / drain 110 formed by epitaxial growth may be formed so as to ride up on top of the embedded insulating film 106.

[0033] Next, as shown in Figure 10, a metal layer 111 is formed over the entire surface of the source / drain 110 and the embedded insulating film 106.

[0034] Next, as shown in Figure 11, the metal layer 111 is patterned to form contacts 111a connected to the source / drain 110. At this time, the metal layer 111 is etched using a resist pattern (not shown here) as a mask. After etching is complete, the resist pattern is removed. At this point, in the B-B cross section, contacts 111a are formed only within the opening 108h.

[0035] Next, as shown in Figure 12, a hard mask layer 112 is formed to fill the opening 108h and cover the contact 111a. First, a hard mask layer 112 made of silicon nitride is formed to a thickness that fills the opening 108h. Then, the hard mask layer 112 and the previously formed hard mask layer 107 (see Figure 11) are CMP polished until the embedded insulating film 106 is exposed. This leaves the hard mask layer 112 in a shape that covers the contact 111a while filling the opening 108h.

[0036] Next, as shown in Figure 13, another opening 113h is formed by pattern etching of the embedded insulating film 106 to expose the upper surface of the sacrificial film 105 covering the nanosheet laminate 103.

[0037] In this case, first, a resist pattern is formed, which is not shown in the illustration here. This resist pattern has a line shape that overlaps with the groove-type element separator 104 explained using Figure 2. Next, using this resist pattern and the hard mask layer 112 as a mask, the embedded insulating film 106 is etched to form another opening 113h that exposes the upper surface of the sacrificial film 105.

[0038] Next, as shown in Figure 14, a spacer 114 is formed on the inner wall of the opening 113h, with a shape that stands upright on the upper surface of the sacrificial film 105. In this case, first, an insulating material film, for example, made of silicon oxide, is deposited to fill the opening 113h. Then, the insulating material film is etched back by anisotropic etching. This leaves an insulating material film on the inner wall of the opening 113h, and the remaining insulating material film is formed as a spacer 114. This spacer 114 is placed on the base spacer S1 and covers the upper part of the source / drain 110, the contact 111a, the hard mask layer 112, and the side wall of the embedded insulating film 106 that are exposed on the side wall of another opening 113.

[0039] Next, as shown in Figure 15, the sacrificial film 105 exposed on the bottom surface of the opening 113h and the sacrificial sheet layer 101 constituting the nanosheet laminate 103 are selectively etched away from the inner spacer 109 and the base spacer S1. This exposes the central part of the silicon nanosheet layer 102 around its entire circumference.

[0040] Next, as shown in Figure 16, a gate electrode 115 is formed on the exposed surface of the nanosheet layer 102 via a gate insulating film (not shown here), and the openings 113h between the nanosheet layers 102 and between the spacers 114 are filled with the gate electrode 115. The gate insulating film is formed using a high dielectric constant film, and the gate electrode 115 is formed using tungsten (W) or titanium nitride (TiN). This results in a full-circumference gate transistor 10 in which the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 115 via the gate insulating film.

[0041] The all-around gate transistor 10 obtained in this way has the configuration described with reference to Figure 1.

[0042] <Effects of First Embodiment> In the manufacturing method according to the first embodiment described above, as explained with reference to FIG. 5, the line-shaped nanosheet stack 103 is buried with the buried insulating film 106 via the sacrificial film 105, and the nanosheet stack 103 is patterned into islands from above the buried insulating film 106. Accordingly, as shown in FIG. 6, when patterning the nanosheet stack 103 into islands, first, in a state where only the buried insulating film 106 and the line-shaped hard mask layer 107 are exposed, the buried insulating film 106 may be etched to expose the nanosheet stack 103. Therefore, the nanosheet stack 103 can be uniformly exposed without forming a step, and the difficulty of the etching process for patterning the nanosheet stack 103 into island-shaped active regions can be reduced.

[0043] Further, in the conventional method of burying the line-shaped nanosheet stack 103 with polysilicon, it was necessary to etch the nanosheet stack 103 after forming base spacers on the sidewalls of the polysilicon structure formed on the nanosheet stack 103. Furthermore, when forming the gate electrode, it was necessary to remove the polysilicon structure. However, according to the manufacturing method of the first embodiment described above, there is no need to perform these steps. Therefore, it is also possible to reduce the total number of manufacturing steps. In addition, the semiconductor device 1 obtained by this manufacturing method includes insulating base spacers S1 arranged so as to surround the stacked portion of the nanosheet layer 102 and the inner spacers 109, and the buried insulating film 106 provided so as to fill the space between the all-around gate transistors 10.

[0044] «Second Embodiment» <Semiconductor device according to Second Embodiment> FIG. 17 is a cross-sectional view of a semiconductor device 2 according to a second embodiment. This semiconductor device 2 has a plurality of all-around gate transistors 20 on one main surface side of a semiconductor substrate 100. FIG. 17 shows a cross-section in the gate width direction [Wg] and a cross-section in the gate length direction [Lg] at the central portion of the all-around gate transistor 20.

[0045] The difference between each full-circumference gate transistor 20 shown in Figure 17 and the full-circumference gate transistor 10 of the semiconductor device 1 of the first embodiment is that each full-circumference gate transistor 20 has an insulating second base spacer S2 between the upper part of the nanosheet laminate 103 and the base spacer S1. The second base spacer S2 is made of a material that can be selectively etched with respect to the sacrificial film material that constitutes the base spacer S1. Such second base spacers S2 are arranged at both ends of the nanosheet laminate 103 and insulate the source / drain 110 and the gate electrode 115' at the upper part of the nanosheet laminate 103. Each second base spacer S2 is arranged at the lower part of the base spacer S1 at the upper part of the nanosheet laminate 103, as will be explained with reference to Figure 29 in the subsequent manufacturing method of the semiconductor device.

[0046] Furthermore, the semiconductor device 2 shown in Figure 17 differs from the semiconductor device 1 of the first embodiment in that the gate electrodes 115' are shared between two full-circumference gate transistors 20 arranged adjacent to each other via a groove-type element separator 104. The other configurations are the same as those of the first embodiment.

[0047] <Method of Manufacturing a Semiconductor Device of the Second Embodiment> Figures 18 to 32 are process diagrams (1) to (15) showing the method of manufacturing the semiconductor device 2 of the second embodiment. The method of manufacturing the semiconductor device 2 described above and its detailed configuration will be explained below in the order of the manufacturing process shown in Figures 18 to 32. Figures 18 to 32 show plan views of each manufacturing process, as well as A-A and B-B cross-sections in the plan views, and further, A'-A' or A''-A'' cross-sections as needed.

[0048] First, as shown in FIG. 18, the steps up to forming a nanosheet stack 103 on one main surface of a semiconductor substrate 100, separating the formed nanosheet stack 103, and further forming a trench-type element isolation 104 are performed by the same procedure as in the first embodiment. Thereafter, an insulating thin film 201 covering the separated nanosheet stack 103 and the trench-type element isolation 104 is formed on the semiconductor substrate 100. This insulating thin film 201 is made of a material that can be selectively etched with respect to the sacrificial sheet layer 101, and when the sacrificial sheet layer 101 is made of silicon germanium, it is made of, for example, silicon oxide.

[0049] Next, as shown in FIG. 19, a sacrificial film 105 is formed on top of the insulating thin film 201. This sacrificial film 105 is constituted by a material that can be selectively etched with respect to the nanosheet layers 102 and the insulating thin film 201, and is preferably a material that can be etched in the same step as the sacrificial sheet layer 101. Such a sacrificial film 105 may typically be constituted of silicon germanium, which is the same material as the sacrificial sheet layer 101. Also, this sacrificial film 105 is formed with a film thickness of about 12 nm.

[0050] The formation of the sacrificial film 105 made of silicon germanium as described above is performed, for example, by forming a silicon germanium layer by a CVD method, then crystallizing the silicon germanium layer by heat treatment to obtain the sacrificial film 105.

[0051] Next, as shown in FIG. 20, a step of removing the sacrificial film 105 and the insulating thin film 201 on the trench-type element isolation 104 is performed. At this time, first, only the sacrificial film 105 on the trench-type element isolation 104 is removed by the same bottom punch method as the procedure described in the first embodiment. Then, by etching the insulating thin film 201 using the sacrificial film 105 as a mask, only the insulating thin film 201 on the trench-type element isolation 104 is removed.

[0052] Next, as shown in Figure 21, an embedded insulating film 106 made of silicon oxide or silicon nitride is formed to embed the nanosheet laminate 103 covered with the sacrificial film 105 and the insulating thin film 201. Then, a hard mask layer 107 is formed on the embedded insulating film 106. Here, for example, an embedded insulating film 106 made of silicon oxide is formed, and a hard mask layer 107 made of silicon nitride is formed on top of it.

[0053] Next, as shown in Figure 22, the hard mask layer 107 is patterned in a line shape substantially perpendicular to the extension direction of the nanosheet laminate 103, and the embedded insulating film 106 exposed from the hard mask layer 107 is further reduced (A'-A' cross section).

[0054] Next, a resist pattern, not shown in the illustration here, is formed on the hard mask layer 107 and the embedded insulating film 106. This resist pattern is in the shape of lines that overlap the groove-type element separator 104 described with reference to Figure 2, and opens above the nanosheet laminate 103.

[0055] Subsequently, the embedded insulating film 106 is etched using the above-mentioned resist pattern and the patterned hard mask layer 107 as a mask to form an opening 108h in the embedded insulating film 106. Furthermore, the nanosheet laminate 103 exposed at the bottom of the opening 108h is etched to separate the nanosheet laminate 103 into island-like active regions.

[0056] Next, as shown in Figure 23, within the opening 108h, the sacrificial sheet layer 101 and sacrificial film 105 exposed on the side wall of the nanosheet laminate 103 are selectively reduced by isotropic etching (B-B cross section).

[0057] Here, as shown in the A-A cross section crossing the center of the nanosheet laminate 103, the sacrificial film 105 is formed to cover the nanosheet laminate 103 via the insulating thin film 201. Therefore, in this process, by reducing the sacrificial film 105 from the exposed surface, gaps are formed between the nanosheet layers 102 in the region close to the exposed surface of the nanosheet laminate 103, as shown in the A''-A'' cross section, and gaps are also formed between the insulating thin film 201 and the embedded insulating film 106.

[0058] Next, as shown in Figure 24, insulating inner spacers 109 are formed on the exposed sidewalls of the sacrificial sheet layer 101 to fill the gaps between the nanosheet layers 102. In this step, insulating base spacers S1 are also formed on the exposed sidewalls of the sacrificial film 105 to fill the gaps between the insulating thin film 201 and the embedded insulating film 106. The procedure for forming the inner spacers 109 and base spacers S1 is the same as the procedure described in the first embodiment.

[0059] The base spacer S1 formed here is positioned on the exposed road-side surface of the nanosheet laminate 103, as shown in the A''-A'' cross section, to surround the laminated portion of the nanosheet layer 102 and the inner spacer 109 via the insulating thin film 201.

[0060] Next, as shown in Figure 25, source / drain 110 made of silicon containing p-type or n-type impurities is formed on the side of the nanosheet laminate 103 by epitaxial growth from the exposed surfaces of the nanosheet layer 102 and the semiconductor substrate 100. This source / drain 110 is connected to each nanosheet layer 102. In the A'-A' section where the nanosheet laminate 103 is not present, the surface height of the embedded insulating film 106 is low (see Figure 22). For this reason, the source / drain 110 formed by epitaxial growth may be formed so as to ride up on top of the embedded insulating film 106.

[0061] Next, as shown in Figure 26, the exposed surfaces of the embedded insulating film 106 and the source / drain 110 are filled and flattened with a hard mask layer 202. First, a hard mask layer 202 made of silicon nitride is formed with a thickness sufficient to fill the opening 108h. Then, the hard mask layer 202 and the previously formed hard mask layer 107 (see Figure 25) are CMP polished until the embedded insulating film 106 is exposed. This leaves the hard mask layer 202 in a state that fills the opening 108h.

[0062] Next, as shown in Figure 27, another opening 106h is formed in the embedded insulating film 106 to expose the sacrificial film 105 on the nanosheet laminate 103. This opening 106h has an opening shape that exposes the sacrificial film 105 on two adjacent nanosheet laminates 103, separated by a groove-type element separator 104, at its bottom. Such an opening 106h is formed by etching the embedded insulating film 106 using a resist pattern (not shown here) as a mask. At this time, the embedded insulating film 106 is left to cover the sidewalls of the source / drain 110 and the hard mask layer 202 above it. The portion of the embedded insulating film 106 that is left to cover the sidewalls of the source / drain 110 and the hard mask layer 202 above it is used as an insulating spacer 106a.

[0063] Next, as shown in Figure 28, the sacrificial film 105 exposed on the bottom surface of the opening 106h is selectively etched away to expose the entire surface of the insulating thin film 201.

[0064] Next, as shown in Figure 29, the insulating thin film 201 exposed on the bottom surface of the opening 106h is selectively etched away from the nanosheet layer 102 and the base spacer S1. Here, the insulating thin film 201 is isotropically etched so as to expose the side walls of the nanosheet laminate 103 and leave the insulating thin film 201 only on the lower part of the base spacer S1. In this case, etching is stopped before the insulating thin film 201 sandwiched between the base spacer S1 and the nanosheet laminate 103 is completely removed by etching from the exposed surface. For this reason, etching is stopped when the side walls of the nanosheet laminate 103 are exposed. As a result, the insulating thin film 201 remaining only on the lower part of the base spacer S1 is formed as the second base spacer S2.

[0065] Next, as shown in Figure 30, a gate electrode 115 is formed on the exposed surface of the nanosheet layer 102 via a gate insulating film (not shown here), and the gate electrode 115 fills the gaps between the nanosheet layers 102 and the openings 106h of the embedded insulating film 106. The gate insulating film is formed using a high dielectric constant film, and the gate electrode 115 is formed using tungsten (W) or titanium nitride (TiN).

[0066] Next, as shown in Figure 31, an opening 202h is formed to expose the source / drain 110. In this case, first, a resist pattern is formed, which is not shown here. This resist pattern is shaped to expose two adjacent source / drain 110s on either side of the groove-type element separator 104. Next, using this resist pattern as a mask, the hard mask layer 202 is etched to form an opening 202h that exposes the two source / drain 110s.

[0067] Next, as shown in Figure 32, a contact 203 is formed to fill the opening 202h and connect the two source / drain 110. First, a metal layer is formed with a thickness that fills the opening 202h. Then, the metal layer is CMP polished until the embedded insulating film 106, the gate electrode 115, and the hard mask layer 202 are exposed. This forms a contact 203 made of the metal layer that fills the opening 202h. This contact 203 and the source / drain 110 are insulated from the gate electrode 115 by a spacer 106a.

[0068] As a result, a full-circumference gate transistor 20 is obtained in which the entire circumference of the nanosheet layer 102 is surrounded by the gate electrode 115 via a gate insulating film. The full-circumference gate transistor 20 obtained in this way has the configuration described with reference to Figure 17.

[0069] <Effects of the Second Embodiment> In the manufacturing method of the second embodiment described above, as explained with reference to Figure 21, a line-shaped nanosheet laminate 103 is embedded with an embedded insulating film 106 via an insulating thin film 201 and a sacrificial film 105, and the nanosheet laminate 103 is patterned in an island shape on top of this embedded insulating film 106. As a result, as shown in Figure 22, when patterning the nanosheet laminate 103 in an island shape, the nanosheet laminate 103 can be exposed uniformly without creating steps, similar to the manufacturing method of the first embodiment. As a result, similar to the manufacturing method of the first embodiment, it is possible to reduce the difficulty of the etching process for patterning the nanosheet laminate 103 into island-shaped active regions.

[0070] Furthermore, similar to the manufacturing method of the first embodiment, it is possible to reduce the total number of manufacturing steps compared to the conventional method of embedding the line-shaped nanosheet laminate 103 with polysilicon. In addition, the semiconductor device 2 obtained by this manufacturing method has a configuration in which a second base spacer S2 is added between the base spacer S1 and the nanosheet laminate 103 compared to the semiconductor device 1 of the first embodiment.

[0071] 1, 2... Semiconductor device 10, 20... Full-circumference gate transistor 100... Semiconductor substrate (substrate) 101... Sacrificial sheet layer 102... Nanosheet layer 103... Nanosheet laminate 104... Groove-type element isolation (substrate) 105... Sacrificial film 106... Embedded insulating film 106h... Aperture (another aperture) 107... Linear hard mask layer 108h... Aperture 109... Inner spacer 110... Source / drain 111a... Contact 113h... Aperture (another aperture) 106a, 114... Spacer 115, 115'... Gate electrode 201... Insulating thin film S1... Underlay spacer S2... Second underlay spacer

Claims

1. A semiconductor device having a plurality of all-around gate transistors on a substrate, wherein each all-around gate transistor comprises: a nanosheet laminate formed by stacking a plurality of nanosheet layers made of a semiconductor material; insulating inner spacers sandwiched between each nanosheet layer at both ends of the nanosheet layer; a gate electrode that covers the entire circumference of each nanosheet layer via a gate insulating film between the inner spacers and is erected on the top of the nanosheet laminate; source / drain erected along the nanosheet laminate at both ends of the nanosheet layer on which the inner spacers are located; contacts connected to the source / drain; insulating spacers sandwiched between the source / drain and the contacts and the gate electrode; and a base spacer disposed between the spacers and the nanosheet laminate, surrounding the stacked portion of the nanosheet layer and the inner spacer, wherein the base spacer is made of an insulating material different from the spacers.

2. The semiconductor device according to claim 1, wherein the spacer is made of silicon oxide.

3. The semiconductor device according to claim 1, further comprising an insulating second base spacer between the upper part of the nanosheet laminate and the base spacer.

4. A method for manufacturing a semiconductor device having a plurality of all-around gate transistors on a substrate, comprising: forming a nanosheet laminate on the substrate by stacking a plurality of nanosheet layers made of a semiconductor material via a sacrificial sheet layer, and patterning the nanosheet laminate in a linear shape; forming a sacrificial film to cover the linear nanosheet laminate with the surface of the substrate exposed; forming an embedded insulating film to embed the nanosheet laminate covered with the sacrificial film; patterning the linear nanosheet laminate and the sacrificial film in an island shape by etching from an opening formed in the embedded insulating film; etching a part of the sacrificial sheet layer and the sacrificial film from the exposed side surface of the island nanosheet laminate, and embedding an insulating material in the etched portion to form an inner spacer between the nanosheet layers and a base spacer surrounding the stacked portion of the nanosheet layer and the inner spacer; forming a source / drain erected along the nanosheet laminate by epitaxial growth from the nanosheet layer in the island nanosheet laminate; and forming a contact connected to the source / drain. A method for manufacturing a semiconductor device, comprising the steps of: forming another opening in the embedded insulating film that reaches the sacrificial film; forming an insulating spacer on the base spacer on the inner wall of the other opening; exposing the entire circumference of the nanosheet layer by etching the sacrificial film and the sacrificial sheet layer from the other opening; and forming a gate electrode that covers the entire circumference of the nanosheet layer via a gate insulating film.

5. The method for manufacturing a semiconductor device according to claim 4, wherein in the step of patterning the nanosheet laminate in an island shape, a line-shaped hard mask layer substantially perpendicular to the line-shaped patterned nanosheet laminate is formed on the embedded insulating film, the embedded insulating film is reduced by etching from the hard mask layer, a resist pattern is formed on the embedded insulating film so as to expose the line-shaped patterned nanosheet laminate, and the embedded insulating film and the nanosheet laminate are etched using the hard mask layer and the resist pattern as a mask.

6. A method for manufacturing a semiconductor device according to claim 4, wherein, after patterning the nanosheet laminate in a linear shape, an insulating thin film is formed to cover the linear nanosheet laminate before forming the sacrificial film, the insulating thin film is etched using the sacrificial film as a mask to expose the surface of the substrate before forming the embedded insulating film, and after forming the other opening, in the step of exposing the entire circumference of the nanosheet layer, the sacrificial film is etched off, then the insulating thin film is etched off while leaving the insulating thin film as a second base spacer below the base spacer, and the entire circumference of the nanosheet layer is exposed by etching the sacrificial sheet layer.

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