Semiconductor device and method for producing semiconductor device

Abstract

A semiconductor device according to an embodiment of the present invention comprises: a first interlayer insulating film; first lower layer wiring provided to the first interlayer insulating film; second lower layer wiring provided to the first interlayer insulating film and adjacent to the first lower layer wiring; a second interlayer insulating film provided on the first interlayer insulating film and having formed therein a via hole communicating with an upper portion of the first lower layer wiring; via wiring provided in the via hole in the second interlayer insulating film and connected to the first lower layer wiring; and an air gap spacer formed between the inner surface of the via hole and at least a side surface of the via wiring, wherein the air gap spacer is positioned at least between the via wiring and an upper portion of the second lower layer wiring.

Description

Semiconductor device and method of manufacturing semiconductor device

[0001] The present embodiment relates to a semiconductor device and a method of manufacturing a semiconductor device.

[0002] In recent years, along with the miniaturization of wiring in semiconductor devices, problems such as excessive via wiring size and overlay shift of via wiring patterns may occur. Due to such structural factors of the semiconductor device, in the structure between a via wiring and an adjacent wiring in the lower layer of the via wiring (a wiring not electrically connected to the via wiring), the distance between the via wiring and the lower-layer wiring becomes short. This may lead to a shortened lifespan of TDDB (Time Dependent Dielectric Breakdown) characteristics and an increase in capacitance between wirings.

[0003] One embodiment aims to provide a semiconductor device and a method of manufacturing a semiconductor device capable of suppressing an increase in capacitance between a via wiring and a lower-layer wiring while suppressing shortening of the lifespan of the TDDB characteristics of the via wiring.

[0004] A semiconductor device according to one embodiment comprises: a first interlayer insulating film; a first lower-layer wiring provided in the first interlayer insulating film; a second lower-layer wiring provided in the first interlayer insulating film and adjacent to the first lower-layer wiring; a second interlayer insulating film provided on the first interlayer insulating film, in which a via hole communicating with an upper portion of the first lower-layer wiring is formed; a via wiring provided in the via hole of the second interlayer insulating film and connected to the first lower-layer wiring; and an air gap spacer formed between an inner surface of the via hole and at least a side surface of the via wiring, wherein the air gap spacer is located at least between the via wiring and an upper portion of the second lower-layer wiring.

[0005] Figure 1 is a cross-sectional view showing an example of a cross-section of the configuration of a semiconductor device according to the first embodiment. Figure 2A is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment shown in Figure 1. Figure 2B is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2A. Figure 2C is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2B. Figure 2D is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2C. Figure 2E is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2D. Figure 2F is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2E. Figure 2G is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the first embodiment, following Figure 2F. Figure 3 is a cross-sectional view showing an example of a cross-section of the configuration of a semiconductor device according to the second embodiment. Figure 4A is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the second embodiment shown in Figure 3. Figure 4B is a cross-sectional view showing an example of the steps of the method for manufacturing a semiconductor device according to the second embodiment, following Figure 4A. Figure 4C is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the second embodiment, following Figure 4B. Figure 4D is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the second embodiment, following Figure 4C. Figure 4E is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the second embodiment, following Figure 4D. Figure 4F is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the second embodiment, following Figure 4E. Figure 5 is a cross-sectional view showing an example of a cross-section of the configuration of a semiconductor device according to the third embodiment. Figure 6A is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment shown in Figure 5. Figure 6B is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6A. Figure 6C is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6B. Figure 6D is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6C. Figure 6E is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6D.Figure 6F is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6E. Figure 6G is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6F. Figure 6H is a cross-sectional view showing an example of the steps for manufacturing a semiconductor device according to the third embodiment, following Figure 6G.

[0006] A semiconductor device and a method for manufacturing a semiconductor device according to the embodiments will be described in detail below with reference to the attached drawings. In the following description, components having substantially equivalent functions and configurations will be denoted by the same reference numerals, and redundant descriptions will be given only when necessary. The present invention is not limited by these embodiments.

[0007] (First Embodiment) Figure 1 is a cross-sectional view showing an example of a cross-sectional view of the configuration of a semiconductor device according to the first embodiment. In Figure 1, an example of the configuration of a semiconductor device is shown focusing on the region connecting the upper layer wiring and the lower layer wiring.

[0008] [Semiconductor device] For example, as shown in Figure 1, the semiconductor device 100 comprises a lower stopper film T1, a first interlayer insulating film S1, a plurality of lower wirings Mxa, Mxb, an upper stopper film T2, a second interlayer insulating film S2, a via wiring V1, an air gap spacer A1, and an upper wiring Mx+1.

[0009] The following describes the various components of this semiconductor device 100.

[0010] [First Interlayer Insulating Film] The first interlayer insulating film S1 is located on the lower stopper film T1, for example, as shown in Figure 1. As will be described later, the first interlayer insulating film S1 has a lower wiring groove G1 that communicates with the lower part of the via hole GV1, and the first lower wiring Mxa is formed in this lower wiring groove G1.

[0011] This first interlayer insulating film S1 is, for example, a Low-k film or a SiOCN film.

[0012] [Underlayer Stopper Film] The underlayer stopper film T1 is located below the first interlayer insulating film S1, as shown in Figure 1, and functions as an etching stopper for dry etching and other processes on the first interlayer insulating film S1.

[0013] [Underlayer Wiring] The first interlayer insulating film S1 is provided with a plurality of underlayer wirings Mxa and Mxb, for example, as shown in Figure 1.

[0014] For example, as shown in Figure 1, the first lower layer wiring Mxa is provided in the first interlayer insulating film S1, and the upper part of this first lower layer wiring Mxa is connected to the lower part of the via wiring V1. In this way, the first interlayer insulating film S1 has a lower layer wiring groove G1 that communicates with the lower part of the via hole GV1, and the first lower layer wiring Mxa is formed in this lower layer wiring groove G1.

[0015] This first lower layer wiring Mxa includes, for example, a lower layer barrier metal film B1, a lower layer adhesion layer H1, a lower layer conductive film K1, and a lower layer cap film C1, as shown in Figure 1.

[0016] The lower barrier metal film B1 is formed on the inner surface of the lower wiring groove G1, for example, as shown in Figure 1.

[0017] The main component of this lower barrier metal film B1 is, for example, TaN.

[0018] Furthermore, the lower adhesion layer H1 is formed in the lower wiring groove G1 via the lower barrier metal film B1, for example, as shown in Figure 1.

[0019] The main component of this lower adhesion layer H1 is, for example, Co or Ru.

[0020] Furthermore, the lower conductive film K1 is formed within the lower wiring groove G1 via the lower barrier metal film B1 and the lower adhesion layer H1, as shown in Figure 1, for example.

[0021] The main component of this underlying conductive film K1 is, for example, Cu, but it may also be W, Mo, or Rh.

[0022] Furthermore, the lower cap film C1 is formed on the lower conductive film K1, for example, as shown in Figure 1. Therefore, the lower conductive film K1 is connected to the lower part of the via wiring V1 via this lower cap film C1.

[0023] The main component of this lower cap film C1 is, for example, Co or Ru.

[0024] The second lower layer wiring Mxb is provided in the first interlayer insulating film S1, as shown in Figure 1, and is adjacent to the first lower layer wiring Mxa. This second lower layer wiring Mxb is not electrically connected to the via wiring V1.

[0025] Furthermore, the second lower layer wiring Mxb has the same configuration as the first lower layer wiring Mxa.

[0026] In the example shown in Figure 1, of the four lower layer wirings provided in the first interlayer insulating film S1, the two lower layer wirings electrically connected to the via wiring V1 are the first lower layer wirings Mxa, and the lower layer wiring adjacent to these two lower layer wirings corresponds to the second lower layer wiring Mxb.

[0027] [Upper Stopper Film] The upper stopper film T2 is located between the lower part of the second interlayer insulating film S2 and the upper part of the first interlayer insulating film S1, as shown in Figure 1, and functions as an etching stopper for the second interlayer insulating film S2.

[0028] [Second Interlayer Insulating Film] The second interlayer insulating film S2 is provided on the first interlayer insulating film S1 via an upper stopper film T2, as shown in Figure 1, and has via holes GV1 that communicate with the upper part of the first lower wiring Mxa, and via wiring V1 is formed in these via holes GV1. In the example of Figure 1, two via holes GV1 are formed.

[0029] In particular, in this embodiment, as shown in Figure 1, for example, the second interlayer insulating film S2 has an upper wiring groove G2 that communicates with the upper parts of two via holes GV1, and the upper wiring Mx+1 is formed in this upper wiring groove G2. For example, the two via holes GV1 and the upper wiring groove G2 are formed by, for example, a dual damascene method.

[0030] This second interlayer insulating film S2 is, for example, a Low-k film or a SiOCN film.

[0031] [Via Wiring] Via wiring V1 is provided in via holes GV1 of the second interlayer insulating film S2, for example, as shown in Figure 1, and is electrically connected to the first lower layer wiring Mxa. In the example of Figure 1, two via wirings V1 are provided, but one or three or more via wirings V1 may be provided.

[0032] The main component of this via wiring V1 is, for example, W, Cu, Mo, or Rh.

[0033] [Air gap spacer] The air gap spacer A1 is formed between the inner surface of the via hole GV1 and at least the side surface of the via wiring V1, as shown in Figure 1, for example.

[0034] In particular, the air gap spacer A1 is continuously formed between the inner surface of the via hole GV1 and the side surface and lower end V1a of the via wiring V1. That is, this air gap spacer A1 is located at least between the via wiring V1 and the upper part of the second lower wiring Mxb.

[0035] Furthermore, at least an upper barrier metal film B2 is provided on the air gap spacer A1, and the upper part of the air gap spacer A1 is sealed by the upper barrier metal film B2. This prevents the air gap spacer A1 from being filled with other materials.

[0036] Here, for example, as shown in region Z of Figure 1, an air gap spacer A1 is present at the shortest distance between via wiring V1 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to via wiring V1, which has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A1 enables a reduction in capacitance between via wiring V1 and lower layer wiring Mxb.

[0037] [Upper Layer Wiring] The upper layer wiring Mx+1 is provided in the second interlayer insulating film S2, for example, as shown in Figure 1, and is connected to the upper part of the two via wirings V1.

[0038] The upper-layer wiring Mx+1 includes, for example, as shown in FIG. 1, an upper-layer barrier metal film B2, an upper-layer adhesion layer H2, an upper-layer conductive film K2, and an upper-layer cap film C2.

[0039] The upper-layer barrier metal film B2 is formed on the inner surface of the upper-layer wiring trench G2, for example, as shown in FIG. 1.

[0040] The upper-layer barrier metal film B2 is provided on at least the via wiring V1 and the air gap spacer A1. The upper-layer barrier metal film B2 covers an upper portion of the air gap spacer A1 and seals the opening. As a result, as described above, the upper portion of the air gap spacer A1 is blocked by the upper-layer barrier metal film B2. This makes it possible to suppress filling of the inside of the air gap spacer A1 from above with another material or the like.

[0041] Note that the main component of this upper-layer barrier metal film B2 is, for example, TaN.

[0042] Furthermore, the upper-layer adhesion layer H2 is formed in the upper-layer wiring trench G2 via the upper-layer barrier metal film B2, for example, as shown in FIG. 1.

[0043] Note that the main component of this upper-layer adhesion layer H2 is, for example, Co or Ru.

[0044] Furthermore, the upper-layer conductive film K2 is formed in the upper-layer wiring trench G2 via the upper-layer barrier metal film B2 and the upper-layer adhesion layer H2, for example, as shown in FIG. 1.

[0045] Note that the main component of this upper-layer conductive film K2 is, for example, Cu, but may also be W, Mo, or Rh.

[0046] Furthermore, the upper-layer cap film C2 is formed on the upper-layer conductive film K2, for example, as shown in FIG. 1.

[0047] Note that the main component of this upper-layer cap film C2 is, for example, Co or Ru.

[0048] As described above, in the semiconductor device 100 according to the present embodiment, the via hole GV1 and the upper wiring trench G2 are formed by a dual damascene method, and the via wiring V1 and the upper-layer wiring Mx+1 constitute a dual damascene structure.

[0049] As described above, in the semiconductor device 100, an air gap spacer A1 is provided at the shortest distance between the via wiring V1 and the second lower-layer wiring Mxb adjacent to the first lower-layer wiring Mxa connected to the via wiring V1, which has the effect of increasing the withstand voltage. For this reason, the TDDB lifetime is prolonged, and the presence of the air gap spacer A1 enables capacitance reduction between the via wiring V1 and the lower-layer wiring Mxb.

[0050] That is, the semiconductor device 100 according to the present embodiment can suppress an increase in capacitance between the via wiring and the lower-layer wiring while suppressing shortening of the lifetime of TDDB characteristics of the via wiring.

[0051] [Method of Manufacturing Semiconductor Device] Next, a method of manufacturing the semiconductor device 100 according to the first embodiment will be described with reference to FIGS. 2A to 2G as described above. FIGS. 2A to 2G are cross-sectional views illustrating an example of each step of the method of manufacturing the semiconductor device according to the first embodiment illustrated in FIG. 1.

[0052] First, as shown in FIG. 2A, using a single damascene method, a lower-layer wiring trench G1 is patterned in the first interlayer insulating film S1 on the lower-layer stopper film T1, and a lower-layer barrier metal film B1 and a lower-layer adhesion layer H1 are formed in the first lower-layer wiring trench G1. After forming the lower-layer barrier metal film B1 and the lower-layer adhesion layer H1, a lower-layer conductive film K1 is formed in the lower-layer wiring trench G1 via the lower-layer barrier metal film B1 and the lower-layer adhesion layer H1. Accordingly, the first lower-layer wiring Mxa and the second lower-layer wiring Mxb adjacent to the first lower-layer wiring are formed in the first interlayer insulating film S1.

[0053] Then, as shown in FIG. 2A, after an upper-layer stopper film T2 is formed on the first interlayer insulating film S1, a second interlayer insulating film S2 is formed on the first interlayer insulating film S1 via the upper-layer stopper film T2.

[0054] Next, as shown in Figure 2B, using a dual damascene method, for example, with a hard mask (not shown) as a mask, a via hole GV1 communicating with the upper part of the first lower wiring Mxa is formed in the second interlayer insulating film S2 by dry etching or the like, and an upper wiring groove G2 communicating with the upper part of the via hole GV1 is formed.

[0055] Ideally, the via hole GV1 should open only above the first lower layer wiring Mxa. However, due to factors such as misalignment of the mask, a portion of the via hole GV1a, GV1a, may shift to the periphery of the upper part of the first lower layer wiring Mxa, as shown in Figure 2B.

[0056] Next, as shown in Figure 2C, a blocking layer IN1 is selectively formed on at least the inner surface of the via hole GV1 (in the example of Figure 2C, the inner surface of the via hole GV1 and the upper wiring groove G2) with a thickness of, for example, about 1 nm to 3 nm, excluding the upper part of the first lower wiring Mxa (i.e., the blocking layer IN1 is not formed on the upper part of the first lower wiring Mxa). For this blocking layer IN1, a dielectric material such as an organic resin material or a polymer resin material is used.

[0057] At this time, a blocking layer IN1 is also formed in a part of via hole GV1, GV1a (around the upper part of the first lower wiring Mxa).

[0058] Next, as shown in Figure 2D, a via wiring V1 is formed in the via hole GV1 of the second interlayer insulating film S2, connected to the upper part of the first lower layer wiring Mxa via a blocking layer IN1. As previously described, this via wiring V1 can be made of, for example, W, Cu, Mo, or Rh. For the deposition of this via wiring V1, deposition processes such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), electroless plating, or electroplating are used.

[0059] Next, as shown in Figure 2E, with the via wiring V1 formed inside the via hole GV1, the blocking layer IN1 is selectively removed. This forms an air gap spacer A1 between the inner surface of the via hole GV1 and at least the side surface of the via wiring V1. In this state, for example, as shown in Figure 2E, the area above the air gap spacer A1 is open.

[0060] The blocking layer IN1 can be removed by ashing, wet treatment, or plasma etching using gases such as H2, N2, NH3, or Ar.

[0061] In particular, the air gap spacer A1 is continuously formed between the inner surface of the via hole GV1 and the side surface and lower end V1a of the via wiring V1. That is, this air gap spacer A1 is located at least between the via wiring V1 and the upper part of the second lower wiring Mxb.

[0062] Next, as shown in Figure 2F, an upper barrier metal film B2 is formed on at least the via wiring V1 and the air gap spacer A1 so as to cover and seal the upper part of the air gap spacer A1. This upper barrier metal film B2 is formed by, for example, PVD (Physical Vector Deposition), ALD, or a combination of both.

[0063] For example, TaN is used to form the upper barrier metal film B2, but it is not limited to this.

[0064] In this way, by providing at least an upper barrier metal film B2 on the air gap spacer A1, the upper part of the air gap spacer A1 is sealed by the upper barrier metal film B2. This prevents the air gap spacer A1 from being filled with other materials.

[0065] As previously described, the presence of the air gap spacer A1 at the shortest distance between via wiring V1 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to via wiring V1 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A1 enables a reduction in capacitance between via wiring V1 and lower layer wiring Mxb.

[0066] Next, as shown in Figure 2G, an upper adhesion layer H2 is formed in the upper wiring groove G2 via the upper barrier metal film B2, and then an upper conductive film K2 is formed in the upper wiring groove G2 via the upper barrier metal film B2 and the upper adhesion layer H2.

[0067] Then, after smoothing the upper surface of the upper conductive film K2 by CMP (Chemical Mechanical Polishing) or the like, the upper cap film C2 is formed on the upper conductive film K2, thereby forming the basic configuration of the semiconductor device according to this embodiment.

[0068] As described above, in the semiconductor device 100 constructed by the semiconductor device manufacturing method according to this embodiment, the via hole GV1 and the upper wiring groove G2 are formed by the dual damascene method, and the via wiring V1 and the upper wiring Mx+1 constitute a dual damascene structure.

[0069] As described above, in the semiconductor device 100 constructed by the semiconductor device manufacturing method according to this embodiment, an air gap spacer A1 is present at the shortest distance between the via wiring V1 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V1, which has the effect of increasing the dielectric strength. As a result, the TDDB life is extended, and the presence of the air gap spacer A1 enables a reduction in capacitance between the via wiring and the lower layer wiring.

[0070] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment, it is possible to suppress the shortening of the lifespan of the TDDB characteristics of the via wiring while suppressing the increase in capacitance between the via wiring and the underlying wiring.

[0071] In the first embodiment described above, in particular, an example of the configuration of a semiconductor device having a dual damascene structure in its wiring and an example of its manufacturing method was explained. However, the configuration of this semiconductor device is not limited to this. Therefore, in the second and third embodiments described below, other examples of semiconductor devices and methods for manufacturing them will be explained.

[0072] (Second Embodiment) Referring to Figure 3, a semiconductor device according to the second embodiment will be described. Figure 3 is a cross-sectional view showing an example of a cross-sectional view of the configuration of a semiconductor device according to the second embodiment. In this Figure 3, an example of the configuration of a semiconductor device is shown focusing on the region connecting the upper and lower wiring.

[0073] [Semiconductor device] For example, as shown in Figure 3, the semiconductor device 200 according to the second embodiment comprises a lower stopper film T1, a first interlayer insulating film S1, a plurality of lower wirings Mxa, Mxb, an upper stopper film T2, a second interlayer insulating film S22, via wiring V12, an air gap spacer A12, an upper barrier metal film B22, and an upper adhesion layer H22.

[0074] The configurations of the semiconductor device 200 will be described below. In the example shown in Figure 3, the configurations of the lower stopper film T1, the first interlayer insulating film S1, the multiple lower wirings Mxa, Mxb, and the upper stopper film T2 are the same as in the first embodiment, so their description will be omitted.

[0075] [Second Interlayer Insulating Film] The second interlayer insulating film S22 is provided on the first interlayer insulating film S1 via an upper stopper film T2, as shown in Figure 3, and has a via hole GV12 that communicates with the upper part of the first lower wiring Mxa, and a via wiring V12 is formed in this via hole GV12. In the example of Figure 3, one via hole GV12 is formed.

[0076] In particular, in this embodiment, for example, one via hole GV12 is formed by the single damascene method.

[0077] This second interlayer insulating film S22 is, for example, a Low-k film or an SiOCN film.

[0078] [Via Wiring] The via wiring V12 is provided, for example, in a via hole GV12 of the second interlayer insulating film S22, as shown in Figure 3, and is electrically connected to the first lower layer wiring Mxa. In the example of Figure 3, one via wiring V12 is provided, but two or more via wiring V12 may be provided.

[0079] As previously described, via holes GV12 are formed by the single damascene method, and via wiring V12 constitutes a single damascene structure.

[0080] The main component of this via wiring V12 is, for example, W, Cu, Mo, or Rh.

[0081] [Upper Barrier Metal Film] The upper barrier metal film B22 is provided continuously on the second interlayer insulating film S22, the via wiring V1, and the air gap spacer A12, for example, as shown in Figure 3. This upper barrier metal film B22 covers and seals the upper part of the air gap spacer A12.

[0082] The main component of this upper barrier metal film B22 is, for example, TaN.

[0083] [Upper Adhesion Layer] The upper adhesion layer H22 is provided on the upper barrier metal film B22, for example, as shown in Figure 3.

[0084] The main component of this upper adhesion layer H22 is, for example, Co or Ru.

[0085] [Air gap spacer] The air gap spacer A12 is formed between the inner surface of the via hole GV12 and at least the side surface of the via wiring V12, as shown in Figure 3, for example.

[0086] In particular, the air gap spacer A12 is continuously formed between the inner surface of the via hole GV12 and the side surface and lower end V12a of the via wiring V12. That is, this air gap spacer A12 is located at least between the via wiring V12 and the upper part of the second lower wiring Mxb.

[0087] Furthermore, at least an upper barrier metal film B22 is provided on the air gap spacer A12, and the upper part of the air gap spacer A12 is sealed by the upper barrier metal film B22. This prevents the air gap spacer A12 from being filled with other materials.

[0088] Here, for example, as shown in region Z2 of Figure 3, an air gap spacer A12 is present at the shortest distance between the via wiring V12 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V12, which has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A12 enables a reduction in capacitance between the via wiring V12 and the lower layer wiring Mxb.

[0089] The other configurations of the semiconductor device 200 according to this embodiment are the same as those of the semiconductor device 100 according to the first embodiment.

[0090] As described above, in the semiconductor device 200 according to this embodiment, the via holes GV12 are formed by the single damascene method, and the via wiring V12 constitutes a single damascene structure.

[0091] As previously described, in the semiconductor device 200, the presence of an air gap spacer A12 at the shortest distance between the via wiring V12 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V12 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A12 enables a reduction in capacitance between the via wiring V12 and the lower layer wiring Mxb.

[0092] In other words, the semiconductor device 200 according to this embodiment can suppress the shortening of the lifespan of the via wiring's TDDB characteristics while suppressing the increase in capacitance between the via wiring and the underlying wiring.

[0093] [Method for Manufacturing a Semiconductor Device] Next, a method for manufacturing a semiconductor device 200 according to the second embodiment will be described with reference to Figures 4A to 4F as previously mentioned. Figures 4A to 4F are cross-sectional views showing an example of each step in the method for manufacturing a semiconductor device according to the second embodiment shown in Figure 3.

[0094] First, as shown in Figure 4A, a lower layer wiring groove G1 is patterned on the first interlayer insulating film S1 on the lower layer stopper film T1 using the single damascene method, and a lower layer barrier metal film B1 and a lower layer adhesion layer H1 are formed within the first lower layer wiring groove G1. Then, after forming the lower layer barrier metal film B1 and the lower layer adhesion layer H1, a lower layer conductive film K1 is formed within the lower layer wiring groove G1 via the lower layer barrier metal film B1 and the lower layer adhesion layer H1. This forms a first lower layer wiring Mxa and a second lower layer wiring Mxb adjacent to the first lower layer wiring in the first interlayer insulating film S1.

[0095] Then, as shown in Figure 4A, an upper stopper film T2 is formed on the first interlayer insulating film S1, and then a second interlayer insulating film S22 is formed on the first interlayer insulating film S1 via the upper stopper film T2.

[0096] Next, as shown in Figure 4B, using a single damascene method, for example, with a hard mask (not shown) as a mask, via holes GV12 communicating with the upper part of the first lower wiring Mxa are formed in the second interlayer insulating film S22 by dry etching or the like.

[0097] Ideally, the via hole GV12 should open only above the first lower layer wiring Mxa. However, due to factors such as misalignment of the mask, a portion of the via hole GV12a, GV12a, may shift to the periphery of the upper part of the first lower layer wiring Mxa, as shown in Figure 4B.

[0098] Next, as shown in Figure 4C, a blocking layer IN12 is selectively formed on at least the inner surface of the via hole GV12 (the inner surface of the via hole GV12 in the example of Figure 4C), with a thickness of, for example, 1 nm to 3 nm, excluding the upper part of the first lower wiring Mxa (i.e., the blocking layer IN12 is not formed on the upper part of the first lower wiring Mxa). For this blocking layer IN12, a dielectric material such as an organic resin material or a polymer resin material is used.

[0099] At this time, a blocking layer IN12 is also formed in a part of via hole GV1, GV12a (around the upper part of the first lower wiring Mxa).

[0100] Next, as shown in Figure 4D, via wiring V12 is formed in the via hole GV12 of the second interlayer insulating film S22, connected to the upper part of the first lower layer wiring Mxa via the blocking layer IN12. As previously described, this via wiring V12 can be made of, for example, W, Cu, Mo, or Rh. A deposition process such as CVD, ALD, chemical reduction plating, or electroplating is used to deposit this via wiring V12.

[0101] Next, as shown in Figure 4E, with the via wiring V12 formed in the via hole GV12, the blocking layer IN12 is selectively removed. This forms an air gap spacer A12 between the inner surface of the via hole GV12 and at least the side surface of the via wiring V12. In this state, for example, as shown in Figure 4E, the area above the air gap spacer A12 is open.

[0102] The blocking layer IN12 can be removed by ashing, wet treatment, or plasma etching using gases such as H2, N2, NH3, or Ar.

[0103] In particular, the air gap spacer A12 is continuously formed between the inner surface of the via hole GV12 and the side surface and lower end V12a of the via wiring V12. That is, this air gap spacer A12 is located at least between the via wiring V12 and the upper part of the second lower wiring Mxb.

[0104] Next, as shown in Figure 4F, an upper barrier metal film B22 is formed on the second interlayer insulating film S22, the via wiring V12, and the air gap spacer A12 so as to cover and seal the upper part of the air gap spacer A12. This upper barrier metal film B22 is formed by, for example, a film deposition method using PVD, ALD, or a combination of both.

[0105] For example, TaN is used to form the upper barrier metal film B22, but it is not limited to this.

[0106] Furthermore, as shown in Figure 4F, an upper adhesion layer H2 is formed via an upper barrier metal film B2.

[0107] In this way, by providing at least an upper barrier metal film B22 on the air gap spacer A12, the upper part of the air gap spacer A12 is sealed by the upper barrier metal film B22. This prevents the air gap spacer A12 from being filled with other materials.

[0108] As previously described, the presence of the air gap spacer A12 at the shortest distance between the via wiring V12 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V12 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A12 enables a reduction in capacitance between the via wiring V12 and the lower layer wiring Mxb.

[0109] As described above, in the semiconductor device 200 constructed by the semiconductor device manufacturing method according to this embodiment, the via holes GV12 are formed by the single damascene method, and the via wiring V12 constitutes a single damascene structure.

[0110] As described above, in the semiconductor device 200 constructed by the semiconductor device manufacturing method according to this embodiment, an air gap spacer A12 is present at the shortest distance between the via wiring V12 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V12, which has the effect of increasing the dielectric strength. As a result, the TDDB life is extended, and the presence of the air gap spacer A12 enables a reduction in capacitance between the via wiring V12 and the lower layer wiring Mxb.

[0111] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device according to the second embodiment, it is possible to suppress the shortening of the lifespan of the TDDB characteristics of the via wiring while suppressing the increase in capacitance between the via wiring and the underlying wiring.

[0112] (Third Embodiment) Next, a semiconductor device according to the third embodiment will be described with reference to Figure 5. Figure 5 is a cross-sectional view showing an example of a cross-sectional view of the configuration of a semiconductor device according to the third embodiment. In this Figure 5, an example of the configuration of a semiconductor device is shown focusing on the region connecting the upper and lower wiring.

[0113] [Semiconductor device] For example, as shown in Figure 5, the semiconductor device 300 according to the third embodiment comprises a lower stopper film T1, a first interlayer insulating film S1, a plurality of lower wirings Mxa, Mxb, an upper stopper film T2, a second interlayer insulating film S23, a via wiring V13, an air gap spacer A13, an upper wiring M2, and a third interlayer insulating film S3.

[0114] The configurations of the semiconductor device 300 will be described below. In the example shown in Figure 5, the configurations of the lower stopper film T1, the first interlayer insulating film S1, the multiple lower wirings Mxa, Mxb, and the upper stopper film T2 are the same as in the second embodiment, so their description will be omitted.

[0115] [Second Interlayer Insulating Film] The second interlayer insulating film S23 is provided on the first interlayer insulating film S1 via an upper stopper film T2, as shown in Figure 5, and has a via hole GV13 that communicates with the upper part of the first lower wiring Mxa, and a via wiring V12 is formed in this via hole GV13. In the example of Figure 3, one via hole GV13 is formed.

[0116] This second interlayer insulating film S23 is, for example, a Low-k film or a SiOCN film.

[0117] [Via Wiring] The via wiring V13 is provided, for example, in a via hole GV13 of the second interlayer insulating film S23, as shown in Figure 5, and is electrically connected to the first lower layer wiring Mxa. In the example of Figure 5, one via wiring V13 is provided, but two or more via wiring V13 may be provided.

[0118] The main component of this via wiring V13 is, for example, W, Cu, Mo, or Rh.

[0119] [Upper layer wiring] The upper layer wiring M2 is provided on the second interlayer insulating film S23, as shown in Figure 5, for example, and is connected to the top of one via wiring V13.

[0120] Furthermore, the main component of this upper layer wiring M2 is the same as that of via wiring V3, for example, W, Cu, Mo, or Rh.

[0121] Furthermore, via wiring V13 and upper layer wiring M2 form a semi-damascene structure.

[0122] [Third Interlayer Insulating Film] The third interlayer insulating film S3 is provided on the second interlayer insulating film S23 and the upper layer wiring M2, for example, as shown in Figure 5.

[0123] [Air gap spacer] The air gap spacer A13 is formed between the inner surface of the via hole GV13 and at least the side surface of the via wiring V13, as shown in Figure 5, for example.

[0124] In particular, the air gap spacer A13 is continuously formed between the inner surface of the via hole GV13 and the side surface and lower end V13a of the via wiring V13. That is, this air gap spacer A13 is located at least between the via wiring V13 and the upper part of the second lower wiring Mxb.

[0125] Furthermore, at least the upper wiring M2 is provided on the air gap spacer A13, and the upper part of the air gap spacer A13 is blocked by the upper wiring M2. This prevents the air gap spacer A13 from being filled with other materials.

[0126] Here, for example, as shown in region Z3 of Figure 5, the presence of an air gap spacer A13 at the shortest distance between the via wiring V13 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V13 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A13 enables a reduction in capacitance between the via wiring V13 and the lower layer wiring Mxb.

[0127] The other configurations of the semiconductor device 300 according to this embodiment are the same as those of the semiconductor device 200 according to the second embodiment.

[0128] As described above, in the semiconductor device 300 according to this embodiment, the via holes GV13 and the upper layer wiring M2 are formed by the semi-damascene method, and the via wiring V13 and the upper layer wiring M2 constitute an s-semi-damascene structure.

[0129] As previously described, in the semiconductor device 300, the presence of an air gap spacer A13 at the shortest distance between the via wiring V13 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V13 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A13 enables a reduction in capacitance between the via wiring V12 and the lower layer wiring Mxb.

[0130] In other words, the semiconductor device 300 according to this embodiment can suppress the shortening of the lifespan of the via wiring's TDDB characteristics while suppressing the increase in capacitance between the via wiring and the underlying wiring.

[0131] [Method for Manufacturing a Semiconductor Device] Next, a method for manufacturing a semiconductor device 200 according to the third embodiment will be described with reference to Figures 6A to 6H as previously mentioned. Figures 6A to 6H are cross-sectional views showing an example of each step in the method for manufacturing a semiconductor device according to the third embodiment shown in Figure 5.

[0132] First, as shown in Figure 6A, a lower layer wiring groove G1 is patterned on the first interlayer insulating film S1 on the lower layer stopper film T1 using the single damascene method, and a lower layer barrier metal film B1 and a lower layer adhesion layer H1 are formed within the first lower layer wiring groove G1. Then, after forming the lower layer barrier metal film B1 and the lower layer adhesion layer H1, a lower layer conductive film K1 is formed within the lower layer wiring groove G1 via the lower layer barrier metal film B1 and the lower layer adhesion layer H1. This forms a first lower layer wiring Mxa and a second lower layer wiring Mxb adjacent to the first lower layer wiring in the first interlayer insulating film S1.

[0133] Then, as shown in Figure 6A, an upper stopper film T2 is formed on the first interlayer insulating film S1, and then a second interlayer insulating film S23 is formed on the first interlayer insulating film S1 via the upper stopper film T2.

[0134] Next, as shown in Figure 6B, using the damascene method, for example, with a hard mask (not shown) as a mask, via holes GV13 communicating with the upper part of the first lower wiring Mxa are formed in the second interlayer insulating film S23 by dry etching or the like.

[0135] Ideally, the via hole GV13 should open only above the first lower layer wiring Mxa. However, due to factors such as misalignment of the mask, a portion of the via hole GV13a, for example, as shown in Figure 6B, may shift to the periphery of the upper part of the first lower layer wiring Mxa.

[0136] Next, as shown in Figure 6C, a blocking layer IN13 is selectively formed on at least the inner surface of the via hole GV13 (the inner surface of the via hole GV13 in the example of Figure 6C), with a thickness of, for example, 1 nm to 3 nm, excluding the upper part of the first lower wiring Mxa (i.e., the blocking layer IN13 is not formed on the upper part of the first lower wiring Mxa). For this blocking layer IN13, a dielectric material such as an organic resin material or a polymer resin material is used.

[0137] At this time, a blocking layer IN13 is also formed in a portion of the via hole GV13 (around the upper part of the first lower wiring Mxa).

[0138] Next, as shown in Figure 6D, via wiring V13 is formed in the via hole GV13 of the second interlayer insulating film S23, connected to the upper part of the first lower layer wiring Mxa via the blocking layer IN13. As previously described, this via wiring V13 can be made of, for example, W, Cu, Mo, or Rh. A deposition process such as CVD, ALD, chemical reduction plating, or electroplating is used to deposit this via wiring V13.

[0139] Next, as shown in Figure 6E, with the via wiring V13 formed in the via hole GV13, the blocking layer IN13 is selectively removed. This forms an air gap spacer A13 between the inner surface of the via hole GV13 and at least the side surface of the via wiring V13. In this state, for example, as shown in Figure 6E, the area above the air gap spacer A13 is open.

[0140] The blocking layer IN13 can be removed by ashing, wet treatment, or plasma etching using gases such as H2, N2, NH3, or Ar.

[0141] In particular, the air gap spacer A13 is continuously formed between the inner surface of the via hole GV13 and the side surface and lower end V13a of the via wiring V13. That is, this air gap spacer A13 is located at least between the via wiring V13 and the upper part of the second lower wiring Mxb.

[0142] Next, as shown in Figure 6F, an upper layer wiring M2 is formed on the second interlayer insulating film S23, on the via wiring V13, and on the air gap spacer A13, so as to cover and seal the upper part of the air gap spacer A13. This upper layer wiring M2 is formed, for example, by PVD. Then, as shown in Figure 6H, a third interlayer insulating film S3 is formed on the second interlayer insulating film S23 and on the upper layer wiring M2.

[0143] In this way, by providing the upper wiring M2 on the air gap spacer A13, the upper part of the air gap spacer A13 is blocked by the upper wiring M2. This prevents the air gap spacer A13 from being filled with other materials.

[0144] As previously described, the presence of the air gap spacer A13 at the shortest distance between the via wiring V13 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V13 has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A13 enables a reduction in capacitance between the via wiring V13 and the lower layer wiring Mxb.

[0145] As described above, in the semiconductor device 300 constructed by the semiconductor device manufacturing method according to this embodiment, the via holes GV13 and upper layer wiring M2 are formed by the semi-damascene method, and the via wiring V1 and upper layer wiring M2 constitute a semi-damascene structure.

[0146] As described above, in the semiconductor device 300 constructed by the semiconductor device manufacturing method according to this embodiment, the air gap spacer A13 is located at the shortest distance between the via wiring V13 and the second lower layer wiring Mxb adjacent to the first lower layer wiring Mxa connected to the via wiring V13, which has the effect of increasing the dielectric strength. As a result, the TDDB lifespan is extended, and the presence of the air gap spacer A13 enables a reduction in capacitance between the via wiring V13 and the lower layer wiring Mxb.

[0147] As described above, according to the semiconductor device and the method for manufacturing the semiconductor device according to the third embodiment, it is possible to suppress the shortening of the lifespan of the TDDB characteristics of the via wiring while suppressing the increase in capacitance between the via wiring and the underlying wiring.

[0148] 100, 200, 300 Semiconductor device T1 Lower stopper film S1 First interlayer insulating film Mxa Lower wiring T2 Upper stopper film S2 Second interlayer insulating film V1 Via wiring A1 Air gap spacer Mx+1 Upper wiring

Claims

1. A semiconductor device comprising: a first interlayer insulating film; a first lower layer wiring provided in the first interlayer insulating film; a second lower layer wiring provided in the first interlayer insulating film and adjacent to the first lower layer wiring; a second interlayer insulating film provided on the first interlayer insulating film and having a via hole formed therein that communicates with the upper part of the first lower layer wiring; a via wiring provided in the via hole of the second interlayer insulating film and connected to the first lower layer wiring; and an air gap spacer formed between the inner surface of the via hole and at least the side surface of the via wiring, wherein the air gap spacer is located at least between the via wiring and the upper part of the second lower layer wiring.

2. The semiconductor device according to claim 1, characterized in that the air gap spacer is continuously formed between the inner surface of the via hole and the side surface and lower end of the via wiring.

3. The semiconductor device according to claim 1, comprising an upper barrier metal film provided on at least the via wiring and the air gap spacer, wherein the upper barrier metal film covers and seals the upper part of the air gap spacer.

4. The semiconductor device according to claim 1, further comprising a lower stopper film located below the first interlayer insulating film and functioning as an etching stopper for the first interlayer insulating film.

5. The semiconductor device according to claim 1, further comprising an upper stopper film located between the lower part of the second interlayer insulating film and the upper part of the first interlayer insulating film, and functioning as an etching stopper for the second interlayer insulating film.

6. The semiconductor device according to claim 1, characterized in that it comprises an upper layer wiring provided in the second interlayer insulating film and connected to the upper part of the via wiring.

7. The semiconductor device according to claim 1, characterized in that the second interlayer insulating film has an upper wiring groove formed thereon that communicates with the upper part of the via hole, and the upper wiring is formed in the upper wiring groove.

8. The semiconductor device according to claim 7, characterized in that the upper wiring comprises an upper barrier metal film formed on the inner surface of the upper wiring groove, an upper adhesion layer formed in the upper wiring groove via the upper barrier metal film, an upper conductive film formed in the upper wiring groove via the upper barrier metal film and the upper adhesion layer, and an upper cap film formed on the upper conductive film K2.

9. The semiconductor device according to claim 8, characterized in that the first interlayer insulating film has a lower wiring groove formed therein that communicates with the lower part of the via hole, and the lower wiring is formed in the lower wiring groove.

10. The semiconductor device according to claim 1, comprising an upper barrier metal film continuously provided on the second interlayer insulating film, the via wiring, and the air gap spacer, wherein the upper barrier metal film covers and lids the upper part of the air gap spacer.

11. The semiconductor device according to claim 10, characterized in that it comprises an upper adhesion layer provided on the upper barrier metal film.

12. The semiconductor device according to claim 1, comprising an upper layer wiring continuously provided on the second interlayer insulating film, the via wiring, and the air gap spacer, and connected to the via wiring, wherein the upper layer wiring covers and lids the upper part of the air gap spacer.

13. The semiconductor device according to claim 9, characterized in that the via wiring and the upper layer wiring constitute a dual damascene structure.

14. The semiconductor device according to claim 10, characterized in that the via wiring constitutes a single damascene structure.

15. The semiconductor device according to claim 12, characterized in that the via wiring and the upper layer wiring constitute a semi-damascene structure.

16. The semiconductor device according to claim 9, characterized in that the first lower wiring comprises a lower barrier metal film formed on the inner surface of the lower wiring groove, a lower adhesion layer formed in the lower wiring groove via the lower barrier metal film, a lower conductive film formed in the lower wiring groove via the lower barrier metal film and the lower adhesion layer, and a lower cap film formed on the lower conductive film.

17. A method for manufacturing a semiconductor device, characterized by: forming a first lower layer wiring and a second lower layer wiring adjacent to the first lower layer wiring in a first interlayer insulating film; forming a second interlayer insulating film on the first interlayer insulating film; forming a via hole in the second interlayer insulating film that communicates with the upper part of the first lower layer wiring and forming an upper layer wiring groove that communicates with the upper part of the via hole using a dual damascene method; selectively forming a blocking layer on at least the inner surface of the via hole, excluding the upper part of the first lower layer wiring; forming a via wiring connected to the first lower layer wiring via the blocking layer within the via hole of the second interlayer insulating film; and selectively removing the blocking layer while the via wiring is formed within the via hole, thereby forming an air gap spacer between the inner surface of the via hole and at least the side surface of the via wiring.

18. The method for manufacturing a semiconductor device according to claim 17, characterized in that an upper barrier metal film is formed on at least the via wiring and on the air gap spacer so as to cover and lid the upper part of the air gap spacer.

19. A method for manufacturing a semiconductor device, comprising: forming a first lower layer wiring and a second lower layer wiring adjacent to the first lower layer wiring in a first interlayer insulating film using a single damascene method; forming a second interlayer insulating film on the first interlayer insulating film; forming a via hole in the second interlayer insulating film that communicates with the upper part of the first lower layer wiring; selectively forming a blocking layer on at least the inner surface of the via hole, excluding the upper part of the first lower layer wiring; forming a via wiring connected to the first lower layer wiring via the blocking layer within the via hole of the second interlayer insulating film; and selectively removing the blocking layer while the via wiring is formed within the via hole, thereby forming an air gap spacer between the inner surface of the via hole and at least the side surface of the via wiring.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that an upper barrier metal film is continuously formed on the second interlayer insulating film, on the via wiring and on the air gap spacer so as to cover and lid the upper part of the air gap spacer.

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