Pattern formation method and semiconductor production device

Abstract

[Problem] To improve roughness performance of a pattern formed through etching using a resist pattern formed by using a metal oxide resist. [Solution] A pattern formation method according to an embodiment of the present invention involves: forming an MOR film containing metal oxide nanoparticles at a first temperature; cooling the formed MOR film to a second temperature lower than the first temperature; heating the cooled MOR film to a third temperature higher than the first temperature; patterning the heated MOR film; and etching a processing target layer by using the patterned MOR film as a mask.

Description

Pattern Formation Method and Semiconductor Manufacturing Apparatus

[0001] The present embodiment relates to a pattern formation method and a semiconductor manufacturing apparatus.

[0002] Metal oxide resists (MOR: Metal Oxide Resist) are expected to be next-generation resists that maximize the performance of next-generation extreme ultraviolet lithography (EUV lithography) and contribute to further miniaturization and cost reduction. This metal oxide resist has the advantages of higher sensitivity and higher uniformity of critical dimension (CD: Critical Dimension) compared to currently mainstream chemically amplified resists (CAR: Chemical Amplified Resist).

[0003] However, the roughness of patterns obtained using MOR resists has not been improved as much as expected compared with CAR resists. Studies by the present inventors have revealed that the cause is that the metal oxide nanoparticles contained in the MOR resist have relatively high mobility, so they are unevenly distributed in the solvent, and variations in height of the metal oxide nanoparticles remain after pre-baking.

[0004] The problem to be solved by the present invention is to improve the roughness performance of a pattern formed by etching using an etching mask formed of a metal oxide resist as a mask. The problem of the present invention is not limited to this, and a problem corresponding to the effect obtained by the configuration of the embodiment described below may be used as the problem of the present invention.

[0005] The pattern formation method according to the present embodiment includes: forming an MOR film containing metal oxide nanoparticles at a first temperature; cooling the formed MOR film to a second temperature lower than the first temperature; heating the cooled MOR film to a third temperature higher than the first temperature; patterning the heated MOR film; and etching a layer to be processed using the patterned MOR film as a mask.

[0006] The semiconductor manufacturing apparatus according to this embodiment includes a MOR supply unit that supplies a metal oxide resist onto a workpiece layer formed on a semiconductor wafer, a cooling unit that cools the MOR film formed on the workpiece layer by the metal oxide resist supplied from the MOR supply unit to a second temperature lower than the first temperature of the MOR film, and a heating unit that heats the cooled MOR film to a third temperature higher than the first temperature.

[0007] This is a flowchart illustrating the pattern formation method according to the first embodiment. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment, following Figure 2A. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment, following Figure 2B. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment, following Figure 2C. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment, following Figure 2D. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the first embodiment, following Figure 2E. This is a schematic cross-sectional diagram corresponding to Figure 2C regarding a pattern formation method according to a comparative example. This is a schematic cross-sectional diagram illustrating the case in the pattern formation method according to the first embodiment in which the MOR film contains a plurality of solvents. This is a plan view showing the schematic configuration of a semiconductor manufacturing apparatus according to the first embodiment. This is a plan view showing the schematic configuration of a semiconductor manufacturing apparatus according to a modified example 1 of the first embodiment. This is a plan view showing the schematic configuration of a semiconductor manufacturing apparatus according to a modified example 2 of the first embodiment. This is a flowchart illustrating the pattern formation method according to the second embodiment. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the second embodiment. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the second embodiment, following Figure 9A. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the second embodiment, following Figure 9B. This is a schematic cross-sectional diagram illustrating the pattern formation method according to the second embodiment, following Figure 9C. This is a plan view showing the schematic configuration of the semiconductor manufacturing apparatus according to the second embodiment. This is a plan view showing the schematic configuration of the semiconductor manufacturing apparatus according to a modified example of the second embodiment.

[0008] Embodiments of the present invention will be described below with reference to the drawings. These embodiments are not limiting to the present invention. The drawings are schematic or conceptual. The same elements are denoted by the same reference numerals in the specification and the drawings.

[0009] (First Embodiment) The pattern formation method according to the first embodiment will be described with reference to the flowchart in Figure 1 and Figures 2A to 2F.

[0010] Step S11: Form an MOR film 20 containing metal oxide nanoparticles 21. Specifically, as shown in Figure 2A, the MOR film 20 is formed by coating a metal oxide resist (MOR) onto a workpiece layer 10 formed on a semiconductor wafer W. Here, metal oxide nanoparticles refer to nanoparticles whose surfaces have been modified with organic compounds from metal oxides such as Sn (tin), Zr (zirconium), Hf (hafnium), Ti (titanium), and Zn (zinc). The MOR film 20 is formed by supplying the metal oxide resist onto the workpiece layer 10 by dropping or the like, and rotating the semiconductor wafer W at high speed.

[0011] The temperature at which the MOR film 20 is formed in step S11 (first temperature) is, for example, 20°C or higher and 22°C or lower. The first temperature is, for example, the ambient temperature when the metal oxide resist is applied (the temperature inside the semiconductor manufacturing apparatus 100 described later).

[0012] The MOR film 20 contains a plurality of metal oxide nanoparticles 21 and a solvent 22 that dissolves the plurality of metal oxide nanoparticles 21. The solvent 22 is, for example, propylene glycol monomethyl ether acetate (PGMEA). As shown in Figure 2A, the metal oxide nanoparticles 21 have a small particle size and a uniform shape, so they have relatively high mobility and are heterogeneously distributed in the solvent 22.

[0013] Step S12: Cool the MOR film 20. Specifically, the MOR film 20 formed in step S11 is cooled to a second temperature lower than the first temperature. The second temperature is, for example, a temperature in the range of -20°C to 22°C, or a temperature in the range of -20°C to 20°C.

[0014] As a result of the cooling in this step, the mobility of the metal oxide nanoparticles 21 in the MOR film 20 decreases, as shown in Figure 2B, causing the metal oxide nanoparticles 21 to move closer together.

[0015] The semiconductor wafer W is, for example, a silicon wafer, but may also be a wafer of other semiconductor materials (silicon carbide, compound semiconductor, etc.). The type of workpiece layer 10 is not particularly limited and may be a semiconductor layer (for example, an n-type or p-type silicon layer), a conductive layer (for example, a polysilicon layer, a metal layer), or an insulating layer (for example, SiO ２ film, Si ３ N ４ It may be a film (or an SiOC film).

[0016] Step S13: Heat the MOR film 20. Specifically, as shown in Figure 2B, the MOR film 20 cooled in step S12 is heated to a third temperature higher than the first temperature. The third temperature is in the range of 80°C to 150°C, or in the range of 80°C to 130°C. This step corresponds to pre-bake (PAB: Post Apply Bake). Heating in this step causes at least a portion of the solvent 22 in the MOR film 20 to evaporate. Note that although Figure 2C shows that all of the solvent 22 has evaporated, in reality, some solvent may remain.

[0017] Step S14: Patterning the MOR film 20. Specifically, the MOR film 20 heated in step S13 is exposed to extreme ultraviolet lithography (EUV lithography) and then developed to form a resist pattern P1 having the desired pattern, as shown in Figure 2D.

[0018] Step S15: The workpiece layer 10 is etched using the MOR film 20 patterned in step S14 as a mask. That is, as shown in Figure 2E, the workpiece layer 10 is etched using the resist pattern P1 formed in step S14 as an etching mask. This forms the desired pattern P shown in Figure 2F.

[0019] As described above, according to the pattern formation method of the first embodiment, after forming the MOR film 20 on the workpiece layer 10, the MOR film 20 is cooled, which separates the multiple metal oxide nanoparticles 21 from the solvent 22, making it easier for the metal oxide nanoparticles 21 to come into contact with each other. As a result, in the MOR film 20, the multiple metal oxide nanoparticles 21 have less variation in height and are in an ordered (regularized) state. Subsequently, the MOR film 20 is heated to evaporate the solvent and patterned to form a resist pattern P1. By etching the workpiece layer 10 using this resist pattern P1 as an etching mask, a pattern P with good roughness can be formed.

[0020] The case where the MOR film 20 is not cooled will be explained. Figure 3 is a schematic diagram showing the arrangement of metal oxide nanoparticles 21 on the workpiece layer 10 when the MOR film 20 is pre-baked without cooling. As shown in this figure, when the MOR film 20 is not cooled, the multiple metal oxide nanoparticles 21 are not ordered, and there are variations in density and height among the metal oxide nanoparticles 21. Therefore, it is not possible to form a resist pattern with good roughness by patterning. As a result, the roughness performance of the pattern formed by etching the workpiece layer 10 is reduced.

[0021] In contrast, the pattern formation method of this embodiment includes a cooling step of the MOR film 20 between the MOR film formation step and the pre-bake step, thereby ordering the molecular arrangement of the multiple metal oxide nanoparticles 21 contained in the MOR film 20. As a result, it becomes possible to pattern the metal oxide nanoparticles 21 in an ordered state, which allows for the formation of a good resist pattern P1 and improves the roughness performance of the pattern P.

[0022] Therefore, according to the first embodiment, the roughness performance of the pattern P formed by etching using the resist pattern P1 can be improved. That is, the roughness performance of the pattern formed by etching using an etching mask formed using a metal oxide resist can be improved.

[0023] The metal oxide resist used to form the MOR film 20 may contain multiple solvents. For example, the MOR 20 film formed in S11 contains solvent 22A (first solvent) and solvent 22B (second solvent) different from solvent 22A, as shown in Figure 3. Solvent 22B is a poor solvent for the metal oxide nanoparticles 21 contained in the MOR film 20. The metal oxide nanoparticles 21 do not dissolve easily in solvent 22B, and the solvent of the MOR film 20 has a two-layer structure of solvent 22A and solvent 22B. In this way, by adding a poor solvent to the metal oxide resist and promoting the separation of the solvents, the cooling temperature (second temperature) of the MOR film 20 can be increased.

[0024] For example, if solvent 22A is PGMEA and solvent 22B is acetic acid, since acetic acid has a low surface energy, the acetic acid in the MOR film 20 formed in step S11 moves to the upper side of the PGMEA. In the subsequent step S12, acetic acid solidifies easily because it has a high freezing point. This allows the temperature at which the MOR film 20 is cooled in step S12 to be increased. As a result, the time required to cool the MOR film 20 can be shortened, and the efficiency of the process can be improved.

[0025] Furthermore, solvent 22B may be a separation solvent that dissolves the metal oxide nanoparticles 21 and separates them from solvent 22A, thereby achieving an effect similar to that of a poor solvent.

[0026] <Semiconductor Manufacturing Apparatus (First Embodiment)> Referring to Figure 5, a semiconductor manufacturing apparatus 100 according to the first embodiment will be described. The semiconductor manufacturing apparatus 100 is configured to apply a metal oxide resist to a semiconductor wafer W brought in from the outside to form a MOR film 20 on the workpiece layer 10, cool the MOR film 20, and then heat the MOR film 20.

[0027] As shown in Figure 5, the semiconductor manufacturing apparatus 100 includes a cooling unit 110, a heating unit 120, transport units 131, 132, 133, and a MOR supply unit 140. Although not shown, the semiconductor manufacturing apparatus 100 may also include a semiconductor wafer W pickup mechanism and a semiconductor wafer W alignment mechanism.

[0028] The cooling unit 110 is transported from the outside by the transport unit 131 and is configured to cool a semiconductor wafer W on which a MOR film 20 has been formed on the workpiece layer 10. The semiconductor wafer W is placed on a plate of the cooling unit 110. As shown in Figure 5, multiple semiconductor wafers W may be placed on the plate and cooled together at once.

[0029] The cooling means of the cooling unit 110 is not particularly limited. In this embodiment, the cooling means is a pipe (refrigerant passage, not shown) through which a refrigerant flows, provided within the plate on which the semiconductor wafer W is placed. By using an antifreeze such as glycol-based antifreeze as the refrigerant, the semiconductor wafer W can be cooled to a temperature below freezing point. Alternatively, the cooling means may be a Peltier element provided on the plate of the cooling unit 110, or a cooling fan that blows cold air toward the semiconductor wafer W on the plate.

[0030] In this manner, the cooling unit 110 cools the MOR film 20 formed on the workpiece layer 10 by the metal oxide resist supplied from the MOR supply unit 140 to a second temperature lower than the first temperature of the MOR film 20. For example, the first temperature is approximately equal to the temperature inside the semiconductor manufacturing apparatus 100 (for example, 20°C to 22°C), and the second temperature is within the range of -20°C to 22°C.

[0031] The heating unit 120 is configured to heat the semiconductor wafer W that has been transported from the cooling unit 110 by the transport unit 132. The semiconductor wafer W is placed on the plate of the heating unit 120. As shown in Figure 5, multiple semiconductor wafers W may be placed on the plate and heated together at once. The heating means may be, for example, a ceramic heater, a resistance wire embedded heater, or a mica heater.

[0032] The heating unit 120 heats the MOR film 20 of the semiconductor wafer W to a third temperature higher than the first temperature. The third temperature is within the range of 80°C to 150°C.

[0033] The transport unit 131 transports the semiconductor wafer W from outside the semiconductor manufacturing apparatus 100 to the cooling unit 110 along the transport direction T1. The transport unit 132 transports the semiconductor wafer W from the cooling unit 110 to the heating unit 120 along the transport direction T2. ​​The transport unit 133 transports the semiconductor wafer W from the heating unit 120 to outside the semiconductor manufacturing apparatus 100 along the transport direction T3. Note that the transport unit is not limited to one transport line, but may have multiple transport lines.

[0034] The MOR supply unit 140 is configured to supply metal oxide resist onto a workpiece layer 10 formed on a semiconductor wafer W. More specifically, the MOR supply unit 140 includes a nozzle 141 for dispensing metal oxide resist and an MOR supply line 142 connected to the nozzle 141 through which the metal oxide resist flows.

[0035] After the metal oxide resist is supplied to the semiconductor wafer W from the MOR supply unit 140, the MOR film 20 is formed on the workpiece layer 10 by spin coating or the like.

[0036] According to the semiconductor manufacturing apparatus 100 described above, the cooling unit 110 cools the MOR film 20 formed on the workpiece layer 10 to a second temperature lower than the first temperature. As a result, as explained with reference to Figure 2B, variations in density and height between the multiple metal oxide nanoparticles 21 in the MOR film 20 can be reduced. Subsequently, the heating unit 120 heats the MOR film 20 to a third temperature higher than the first temperature to evaporate the solvent.

[0037] Subsequently, a good resist pattern P1 is formed by patterning the MOR film 20 using an EUV lithography apparatus (not shown). By etching the workpiece layer 10 using this resist pattern P1 as an etching mask, a pattern P with good roughness can be formed.

[0038] Further, since the semiconductor manufacturing apparatus 100 includes the cooling unit 110 as a dedicated unit for cooling the semiconductor wafer W (the MOR film 20), the semiconductor wafer W can be cooled efficiently, and the process time in the semiconductor manufacturing apparatus 100 can be shortened.

[0039] It should be noted that although the semiconductor manufacturing apparatus 100 is configured as a so-called coater apparatus, the configuration of the semiconductor manufacturing apparatus 100 is not limited to the above. For example, the semiconductor manufacturing apparatus 100 may receive the semiconductor wafer W heated by the heating unit 120 and include a developer unit that patterns the MOR film 20, and may further include an etching unit that etches the layer 10 to be processed using the patterned MOR film 20 as a mask.

[0040] Next, two modified examples of the semiconductor manufacturing apparatus 100 will be described. Effects similar to those described above can be obtained with any of the modified examples.

[0041] <Modified Example 1 of the First Embodiment> A semiconductor manufacturing apparatus 100A according to Modified Example 1 will be described with reference to FIG. 6. One of the differences from the above-described semiconductor manufacturing apparatus 100 is the MOR supply unit. The present modified example will be described below focusing on the differences.

[0042] As shown in FIG. 6, the semiconductor manufacturing apparatus 100A includes a cooling unit 110, a heating unit 120, transfer units 131, 132, 133, and an MOR supply unit 140A. The configuration other than the MOR supply unit 140 is the same as that of the semiconductor manufacturing apparatus 100, so detailed description thereof will be omitted.

[0043] The MOR supply unit 140A is configured to mix a poor solvent for metal oxide nanoparticles contained in a metal oxide resist, or a separation solvent that dissolves the metal oxide nanoparticles and separates them from the solvent (first solvent) of the metal oxide resist, and supply the mixture onto the layer 10 to be processed.

[0044] In detail, the MOR supply unit 140A includes a nozzle 141 that discharges metal oxide resist, a MOR supply line 142, and a solvent addition line 143. The MOR supply line 142 is connected to the nozzle 141, through which the metal oxide resist flows. The solvent addition line 143 is connected to the MOR supply line 142, through which the poor solvent or separation solvent flows.

[0045] In FIG. 6, the solvent addition line 143 is connected to the MOR supply line 142, but it may alternatively be connected to the nozzle 141.

[0046] According to Modification 1, by adding a poor solvent or a separation solvent as a second solvent to the metal oxide resist, the cooling temperature (second temperature) of the MOR film 20 can be increased. Therefore, the time required for the cooling unit 110 to cool the MOR film 20 can be shortened, and the process efficiency can be improved.

[0047] <Modification 2 of the First Embodiment> With reference to FIG. 7, a semiconductor manufacturing apparatus 100B according to Modification 2 will be described. One of the differences from the aforementioned semiconductor manufacturing apparatus 100 is that a cooling unit for cooling a semiconductor wafer W on which the MOR film 20 has been formed and a heating unit for heating the cooled semiconductor wafer W are integrally configured. The modification will be described below focusing on the differences.

[0048] As shown in FIG. 7, the semiconductor manufacturing apparatus 100B includes a cooling and heating unit 125, conveyance units 131 and 132, and a MOR supply unit 140. The configuration other than the cooling and heating unit 125 is substantially the same as that of the semiconductor manufacturing apparatus 100, so a detailed description thereof will be omitted.

[0049] In this modification, the conveyance unit 131 conveys the semiconductor wafer W from the outside of the semiconductor manufacturing apparatus 100B to the cooling and heating unit 125 along the conveyance direction T1. The conveyance unit 132 conveys the semiconductor wafer W from the cooling and heating unit 125 to the outside of the semiconductor manufacturing apparatus 100B along the conveyance direction T2.

[0050] The cooling and heating unit 125 is an integral configuration of the aforementioned cooling unit 110 and heating unit 120. The cooling and heating unit 125 is configured to cool the MOR film 20 formed on the workpiece layer 10 by the metal oxide resist supplied from the MOR supply unit 140 to a second temperature lower than the first temperature of the MOR film 20, and then heat the cooled MOR film 20 to a third temperature higher than the first temperature.

[0051] The cooling and heating unit 125 includes a plate on which a semiconductor wafer W is placed and a Peltier element provided on the plate. The Peltier element is controlled by a control unit 150. The control unit 150 supplies current to the Peltier element in a first direction so that the semiconductor wafer W, which has been transported by the transport unit 131, is cooled. After the semiconductor wafer W has cooled to a second temperature, the control unit 150 supplies current to the Peltier element in a second direction opposite to the first direction so that the semiconductor wafer W is heated. After the semiconductor wafer W has heated to a third temperature, the control unit 150 stops supplying power to the Peltier element.

[0052] The heating and cooling section 125 may include a plate on which the semiconductor wafer W is placed, a heating section for heating the semiconductor wafer W, and a cooling section for cooling the semiconductor wafer W. The heating section may consist of, for example, a ceramic heater, a resistance-wire embedded heater, or a mica heater provided on the plate. The heating section may also be an infrared lamp that heats the semiconductor wafer W by directly irradiating it with infrared rays. The cooling section may consist of, for example, a refrigerant passage provided on the plate through which a refrigerant flows.

[0053] Furthermore, the cooling and heating unit 125 may include a plate on which the semiconductor wafer W is placed, a heating unit provided on the plate, and a cooling fan that blows cold air onto the semiconductor wafer W placed on the plate.

[0054] According to Modification 2, the configuration of the semiconductor manufacturing equipment can be simplified by integrating the cooling and heating sections of the semiconductor wafer W into a single cooling / heating section 125. Furthermore, since the transport path of the semiconductor wafer W is shortened, process efficiency can be improved.

[0055] (Second Embodiment) A pattern forming method according to the second embodiment will be described with reference to the flowchart in Figure 8 and Figures 9A to 9D.

[0056] Step S21: A Directed Self-Assembly (DSA) film 30 is formed as shown in Figure 9A. The DSA film 30 is provided above the workpiece layer 10 and has a self-organized regular pattern. In this embodiment, the DSA film 30 has a pattern in which domains 31 and domains 32 are arranged alternately.

[0057] In step S21, for example, a guide pattern (not shown) is formed on the workpiece layer 10 of the semiconductor wafer W, PS-b-PMMA (a copolymer of polystyrene and polymethyl methacrylate) is applied to the guide pattern, and then heat treatment is applied to form a DSA film 30. In this case, domain 31 is made of polystyrene (PS) and domain 32 is made of polymethyl methacrylate (PMMA). The guide pattern is, for example, a pattern having a pitch slightly larger than the target pitch.

[0058] Step S22: As shown in Figure 9B, a MOR film 20 containing metal oxide nanoparticles is formed on the DSA film 30 formed in step S21 at a first temperature. More specifically, the MOR film 20 is formed by coating the DSA film 30 with metal oxide resist (MOR). The temperature at which the MOR film 20 is formed in step S22 (first temperature) is, for example, 20°C or higher and 22°C or lower. The first temperature is, for example, the ambient temperature when the metal oxide resist is coated (the temperature inside the semiconductor manufacturing apparatus 200 described later).

[0059] Step S23: As shown in Figure 9C, the MOR film 20 formed in step S22 is cooled to a second temperature lower than the first temperature. As a result, due to intermolecular interactions between the metal oxide nanoparticles 21 and substituents of the DSA film 30 (e.g., phenyl groups of polystyrene, methyl groups of PMMA), the metal oxide nanoparticles 21 gather in a specific domain (domain 32 in Figure 9C) of the pattern of the DSA film 30. If the metal oxide nanoparticles 21 contain tin atoms, they are attracted to polar substituents (ester groups) contained in PMMA.

[0060] Step S24: As shown in Figure 9D, the MOR film 20 cooled in step S23 is heated to a third temperature higher than the first temperature. The third temperature is in the range of 80°C to 150°C, or in the range of 80°C to 130°C. This step corresponds to pre-bake (PAB: Post Apply Bake). Heating in this step causes at least a portion of the solvent 22 in the MOR film 20 to evaporate. Note that although Figure 9D shows that all of the solvent 22 has evaporated, in reality, some solvent may remain.

[0061] Step S25: The MOR film 20 and DSA film 30 heated in step S24 are etched. Specifically, the solvent on the domains 31 of the MOR film 20 and the domains 31 of the DSA film 30 are removed. This forms an etching mask.

[0062] Step S26: The workpiece layer is etched using the etching mask formed in step S25 as a mask. This forms the desired pattern, similar to the first embodiment.

[0063] As described above, according to the pattern formation method of the second embodiment, a DSA film 30 having a self-assembled pattern is formed, an MOR film 20 is formed on the formed DSA film 30 at a first temperature, and the formed MOR film 20 is cooled to a second temperature lower than the first temperature. As a result, in the MOR film 20, the multiple metal oxide nanoparticles 21 become ordered (regularized) and gather in specific domains (domains 32) of the pattern of the DSA film 30. After cooling the MOR film 20, the MOR film 20 is heated to evaporate the solvent, and the solvent of the MOR film 20 and the domains 31 on the domains 31 of the DSA film 30 are removed to form a resist pattern. Subsequently, by etching the workpiece layer 10 using the resist pattern as an etching mask, a pattern with good roughness can be formed.

[0064] Therefore, according to the second embodiment, the roughness performance of the pattern formed by etching using an etching mask formed with a metal oxide resist can be improved.

[0065] Furthermore, while the DSA film 30 alone may not have sufficient etching resistance, according to the second embodiment, an etching mask having a two-layer structure of a highly etching-resistant MOR film 20 and a DSA film 30 is formed. Therefore, it is possible to handle high aspect ratio etching, such as when the thickness of the workpiece layer 10 is large.

[0066] In the second embodiment as well, the metal oxide resist used to form the MOR film 20 may contain multiple solvents. As in the first embodiment, one of the multiple solvents may be a poor solvent or a separation solvent.

[0067] <Semiconductor Manufacturing Apparatus (Second Embodiment)> Referring to Figure 10, a semiconductor manufacturing apparatus 200 according to the second embodiment will be described. One of the differences from the semiconductor manufacturing apparatus 100 described in the first embodiment is that the DSA film 30 is formed before the MOR film 20 is formed. The semiconductor manufacturing apparatus 200 according to this embodiment will be described below, focusing on the differences.

[0068] The semiconductor manufacturing apparatus 200 is configured to apply a solution containing a block copolymer (such as PS-b-PMMA) to a semiconductor wafer W brought in from an external source to form a DSA film 30, apply a metal oxide resist on the DSA film 30 to form a MOR film 20, then cool the MOR film 20 to a second temperature, and then heat the MOR film 20 to a third temperature. The solvent for the block copolymer solution is, for example, PGMEA.

[0069] As shown in Figure 10, the semiconductor manufacturing apparatus 200 includes a cooling unit 110, a heating unit 120, transport units 131, 132, and 133, an MOR supply unit 140, and a BCP supply unit 160. Although not shown, the semiconductor manufacturing apparatus 200 may also include a semiconductor wafer W pickup mechanism and a mechanism for aligning the semiconductor wafer W. Also, although not shown, a heating unit (heating plate) for heating the coated block copolymer solution may be provided between the BCP supply unit 160 and the MOR supply unit 140.

[0070] Since the components of the semiconductor manufacturing apparatus 200, excluding the BCP supply unit 160 and the MOR supply unit 140, are almost the same as those of the semiconductor manufacturing apparatus 100 described above, a detailed explanation will be omitted.

[0071] As shown in Figure 10, the BCP supply unit 160 is located upstream of the MOR supply unit 140 in the semiconductor wafer W transport direction T1.

[0072] The BCP supply unit 160 includes a nozzle 161 for discharging a block copolymer solution and a BCP supply line 162 connected to the nozzle 161 through which the block copolymer solution flows.

[0073] The BCP supply unit 160 is configured to supply a block copolymer solution above the workpiece layer 10. The block copolymer is, for example, PS-b-PMMA, which consists of polystyrene (PS) and polymethyl methacrylate (PMMA). After the block copolymer solution is supplied from the BCP supply unit 160 to the semiconductor wafer W, a DSA film 30 is formed by spin coating and heat treatment. In this way, the block copolymer solution supplied from the BCP supply unit 160 is heated by a heating plate (not shown) to form a DSA film 30 in which domains 31 and domains 32 are arranged alternately.

[0074] The MOR supply unit 140 supplies metal oxide resist onto a DSA film 30 having a self-assembled pattern, which is formed by heat-treating a block copolymer solution supplied by the BCP supply unit 160. After the metal oxide resist is supplied from the MOR supply unit 140 to the semiconductor wafer W, the MOR film 20 is formed on the workpiece layer 10 by spin coating or the like.

[0075] As shown in Figure 10, the MOR supply unit 140 has a solvent addition line 143, but it may also be a unit that does not have a solvent addition line 143.

[0076] According to the semiconductor manufacturing apparatus 200 described above, a DSA film 30 in which domains 31 and domains 32 are alternately arranged is formed on a semiconductor wafer W before forming the MOR film 20. Then, the MOR film 20 is formed on the DSA film 30 at a first temperature, and the cooling unit 110 cools the MOR film 20 to a second temperature lower than the first temperature. As a result, as explained in Figure 9C, the multiple metal oxide nanoparticles 21 in the MOR film 20 become ordered (structured) and can be gathered in the domains 32 of the DSA film 30. Then, the heating unit 120 heats the MOR film 20 to a third temperature higher than the first temperature to evaporate the solvent.

[0077] Subsequently, an etching apparatus (not shown) is used to remove the solvent from the MOR film 20 and the domain 31 of the DSA film 30 on the domain 31, thereby forming a good resist pattern. By etching the workpiece layer 10 using this resist pattern as an etching mask, a pattern with good roughness can be formed.

[0078] Although the semiconductor manufacturing apparatus 200 was configured as a so-called coater apparatus, the configuration of the semiconductor manufacturing apparatus 200 is not limited to the above. For example, the semiconductor manufacturing apparatus 200 may include the etching apparatus described above, or it may further include an etching unit that etches the workpiece layer 10 using the resist pattern described above as a mask.

[0079] Next, a modified version of the semiconductor manufacturing apparatus 200 will be described. The same effects as described above can be obtained with this modified version as well.

[0080] <Modified Version of the Second Embodiment> Referring to Figure 11, a modified semiconductor manufacturing apparatus 200A will be described. One of the differences from the semiconductor manufacturing apparatus 200 described above is that the cooling unit for cooling the semiconductor wafer W on which the MOR film 20 is formed and the heating unit for heating the cooled semiconductor wafer W are integrally configured. The modified version will be described below, focusing on the differences.

[0081] As shown in Figure 11, the semiconductor manufacturing apparatus 200A includes a cooling and heating unit 125, transport units 131 and 132, a MOR supply unit 140, and a BCP supply unit 160. The configuration other than the cooling and heating unit 125 is almost the same as that of the semiconductor manufacturing apparatus 200.

[0082] The cooling and heating unit 125 is the same as that described in Modification 2 of the first embodiment, and integrates the cooling unit 110 and the heating unit 120. That is, the cooling and heating unit 125 is configured to cool the MOR film 20 formed on the DSA film 30 with metal oxide resist supplied from the MOR supply unit 140 to a second temperature lower than the first temperature of the MOR film 20, and then heat the cooled MOR film 20 to a third temperature higher than the first temperature.

[0083] According to this modified example, the configuration of the semiconductor manufacturing equipment can be simplified by integrating the cooling and heating sections of the semiconductor wafer W into a single cooling / heating section 125. Furthermore, since the transport path of the semiconductor wafer W is shortened, process efficiency can be improved.

[0084] Based on the above description, those skilled in the art may conceive of additional effects and various modifications of the present invention, but the embodiments of the present invention are not limited to the individual embodiments described above. Components from different embodiments may be combined as appropriate. Various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present invention derived from the claims and their equivalents.

[0085] 10 Layer to be processed 20 MOR film 21 Metal oxide nanoparticles 22, 22A, 22B Solvent 30 DSA film 31, 32 Domains 100, 100A, 100B, 100C, 200, 200A Semiconductor manufacturing equipment 110 Cooling section 120 Heating section 125 Cooling and heating section 131, 132, 133 Transport section 140, 140A MOR supply section 141 Nozzle 142 MOR supply line 143 Solvent addition line 150 Control section 160 BCP supply section 161 Nozzle 162 BCP supply line P Pattern P1 Resist pattern T1, T2, T3 Transport direction W Semiconductor wafer

Claims

1. A pattern forming method comprising: forming a MOR film containing metal oxide nanoparticles at a first temperature; cooling the formed MOR film to a second temperature lower than the first temperature; heating the cooled MOR film to a third temperature higher than the first temperature; patterning the heated MOR film; and etching a workpiece layer using the patterned MOR film as a mask.

2. A pattern forming method comprising: forming a DSA film having a self-assembled pattern; forming a MOR film containing metal oxide nanoparticles on the DSA film at a first temperature; cooling the formed MOR film to a second temperature lower than the first temperature; heating the cooled MOR film to a third temperature higher than the first temperature; etching the heated MOR film and the DSA film to form an etching mask; and etching a workpiece layer using the etching mask as a mask.

3. The pattern forming method according to claim 1 or 2, wherein the second temperature is within the range of -20°C to 22°C.

4. The pattern forming method according to claim 1 or 2, wherein the third temperature is within the range of 80°C to 150°C.

5. The pattern forming method according to claim 1 or 2, wherein the formed MOR film comprises a first solvent and a second solvent different from the first solvent.

6. The pattern forming method according to claim 5, wherein the second solvent is a poor solvent for metal oxide nanoparticles contained in the MOR film, or a separation solvent that dissolves the metal oxide nanoparticles and separates them from the first solvent.

7. The pattern forming method according to claim 5, wherein the first solvent is propylene glycol monomethyl ether acetate (PGMEA) and the second solvent is acetic acid.

8. A semiconductor manufacturing apparatus comprising: a MOR supply unit for supplying a metal oxide resist onto a workpiece layer formed on a semiconductor wafer; a cooling unit for cooling a MOR film formed on the workpiece layer by the metal oxide resist supplied from the MOR supply unit to a second temperature lower than the first temperature of the MOR film; and a heating unit for heating the cooled MOR film to a third temperature higher than the first temperature.

9. The semiconductor manufacturing apparatus according to claim 8, wherein the second temperature is within the range of -20°C to 22°C.

10. The semiconductor manufacturing apparatus according to claim 8, wherein the third temperature is within the range of 80°C to 150°C.

11. The semiconductor manufacturing apparatus according to claim 8, wherein the MOR supply unit comprises a nozzle for discharging the metal oxide resist, and an MOR supply line connected to the nozzle through which the metal oxide resist flows.

12. The semiconductor manufacturing apparatus according to claim 8, wherein the MOR supply unit is configured to mix a poor solvent for metal oxide nanoparticles contained in the metal oxide resist, or a separation solvent for dissolving metal oxide nanoparticles and separating them from the solvent of the metal oxide resist, and supply the mixture onto the workpiece.

13. The semiconductor manufacturing apparatus according to claim 12, wherein the MOR supply unit comprises: a nozzle for discharging the metal oxide resist; an MOR supply line connected to the nozzle through which the metal oxide resist flows; and a solvent addition line connected to the nozzle or the MOR supply line through which a poor solvent or separation solvent for the MOR flows.

14. The semiconductor manufacturing apparatus according to claim 8, wherein the cooling unit and the heating unit are integrally configured as a cooling and heating unit, and the cooling and heating unit cools the MOR film formed on the workpiece layer with metal oxide resist supplied from the MOR supply unit to a second temperature lower than the first temperature of the MOR film, and then heats the cooled MOR film to a third temperature higher than the first temperature.

15. The semiconductor manufacturing apparatus according to claim 8, further comprising a BCP supply unit located upstream of the MOR supply unit in the transport direction of the semiconductor wafer and supplying a block copolymer solution above the layer to be processed, wherein the MOR supply unit supplies a metal oxide resist onto a DSA film having a self-assembled pattern, which is formed by heat-treating the block copolymer solution supplied by the BCP supply unit.

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